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lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_sim_netlist.vhdl | 1 | 157,944 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:25:06 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_to_g8_0_0 -prefix
-- system_rgb888_to_g8_0_0_ system_rgb888_to_g8_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_g8_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0_rgb888_to_g8 is
port (
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb888_to_g8_0_0_rgb888_to_g8;
architecture STRUCTURE of system_rgb888_to_g8_0_0_rgb888_to_g8 is
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal g810_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \g81__120_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_1\ : STD_LOGIC;
signal \g81__120_carry__0_n_2\ : STD_LOGIC;
signal \g81__120_carry__0_n_3\ : STD_LOGIC;
signal \g81__120_carry__0_n_4\ : STD_LOGIC;
signal \g81__120_carry__0_n_5\ : STD_LOGIC;
signal \g81__120_carry__0_n_6\ : STD_LOGIC;
signal \g81__120_carry__0_n_7\ : STD_LOGIC;
signal \g81__120_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_1\ : STD_LOGIC;
signal \g81__120_carry__1_n_2\ : STD_LOGIC;
signal \g81__120_carry__1_n_3\ : STD_LOGIC;
signal \g81__120_carry__1_n_4\ : STD_LOGIC;
signal \g81__120_carry__1_n_5\ : STD_LOGIC;
signal \g81__120_carry__1_n_6\ : STD_LOGIC;
signal \g81__120_carry__1_n_7\ : STD_LOGIC;
signal \g81__120_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_n_1\ : STD_LOGIC;
signal \g81__120_carry__2_n_3\ : STD_LOGIC;
signal \g81__120_carry__2_n_6\ : STD_LOGIC;
signal \g81__120_carry__2_n_7\ : STD_LOGIC;
signal \g81__120_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_1\ : STD_LOGIC;
signal \g81__120_carry_n_2\ : STD_LOGIC;
signal \g81__120_carry_n_3\ : STD_LOGIC;
signal \g81__120_carry_n_4\ : STD_LOGIC;
signal \g81__120_carry_n_5\ : STD_LOGIC;
signal \g81__120_carry_n_6\ : STD_LOGIC;
signal \g81__149_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_1\ : STD_LOGIC;
signal \g81__149_carry__0_n_2\ : STD_LOGIC;
signal \g81__149_carry__0_n_3\ : STD_LOGIC;
signal \g81__149_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_1\ : STD_LOGIC;
signal \g81__149_carry__1_n_2\ : STD_LOGIC;
signal \g81__149_carry__1_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_1\ : STD_LOGIC;
signal \g81__149_carry__2_n_2\ : STD_LOGIC;
signal \g81__149_carry__2_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_n_4\ : STD_LOGIC;
signal \g81__149_carry__2_n_5\ : STD_LOGIC;
signal \g81__149_carry__2_n_6\ : STD_LOGIC;
signal \g81__149_carry__2_n_7\ : STD_LOGIC;
signal \g81__149_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_1\ : STD_LOGIC;
signal \g81__149_carry__3_n_2\ : STD_LOGIC;
signal \g81__149_carry__3_n_3\ : STD_LOGIC;
signal \g81__149_carry__3_n_4\ : STD_LOGIC;
signal \g81__149_carry__3_n_5\ : STD_LOGIC;
signal \g81__149_carry__3_n_6\ : STD_LOGIC;
signal \g81__149_carry__3_n_7\ : STD_LOGIC;
signal \g81__149_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_2\ : STD_LOGIC;
signal \g81__149_carry__4_n_3\ : STD_LOGIC;
signal \g81__149_carry__4_n_5\ : STD_LOGIC;
signal \g81__149_carry__4_n_6\ : STD_LOGIC;
signal \g81__149_carry__4_n_7\ : STD_LOGIC;
signal \g81__149_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_1\ : STD_LOGIC;
signal \g81__149_carry_n_2\ : STD_LOGIC;
signal \g81__149_carry_n_3\ : STD_LOGIC;
signal \g81__206_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_1\ : STD_LOGIC;
signal \g81__206_carry__0_n_2\ : STD_LOGIC;
signal \g81__206_carry__0_n_3\ : STD_LOGIC;
signal \g81__206_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_1\ : STD_LOGIC;
signal \g81__206_carry__1_n_2\ : STD_LOGIC;
signal \g81__206_carry__1_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_1\ : STD_LOGIC;
signal \g81__206_carry__2_n_2\ : STD_LOGIC;
signal \g81__206_carry__2_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_n_4\ : STD_LOGIC;
signal \g81__206_carry__2_n_5\ : STD_LOGIC;
signal \g81__206_carry__2_n_6\ : STD_LOGIC;
signal \g81__206_carry__2_n_7\ : STD_LOGIC;
signal \g81__206_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_1\ : STD_LOGIC;
signal \g81__206_carry__3_n_2\ : STD_LOGIC;
signal \g81__206_carry__3_n_3\ : STD_LOGIC;
signal \g81__206_carry__3_n_4\ : STD_LOGIC;
signal \g81__206_carry__3_n_5\ : STD_LOGIC;
signal \g81__206_carry__3_n_6\ : STD_LOGIC;
signal \g81__206_carry__3_n_7\ : STD_LOGIC;
signal \g81__206_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_2\ : STD_LOGIC;
signal \g81__206_carry__4_n_3\ : STD_LOGIC;
signal \g81__206_carry__4_n_5\ : STD_LOGIC;
signal \g81__206_carry__4_n_6\ : STD_LOGIC;
signal \g81__206_carry__4_n_7\ : STD_LOGIC;
signal \g81__206_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_1\ : STD_LOGIC;
signal \g81__206_carry_n_2\ : STD_LOGIC;
signal \g81__206_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_1\ : STD_LOGIC;
signal \g81__22_carry__0_n_2\ : STD_LOGIC;
signal \g81__22_carry__0_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_n_4\ : STD_LOGIC;
signal \g81__22_carry__0_n_5\ : STD_LOGIC;
signal \g81__22_carry__0_n_6\ : STD_LOGIC;
signal \g81__22_carry__0_n_7\ : STD_LOGIC;
signal \g81__22_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_1\ : STD_LOGIC;
signal \g81__22_carry__1_n_2\ : STD_LOGIC;
signal \g81__22_carry__1_n_3\ : STD_LOGIC;
signal \g81__22_carry__1_n_4\ : STD_LOGIC;
signal \g81__22_carry__1_n_5\ : STD_LOGIC;
signal \g81__22_carry__1_n_6\ : STD_LOGIC;
signal \g81__22_carry__1_n_7\ : STD_LOGIC;
signal \g81__22_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_n_1\ : STD_LOGIC;
signal \g81__22_carry__2_n_3\ : STD_LOGIC;
signal \g81__22_carry__2_n_6\ : STD_LOGIC;
signal \g81__22_carry__2_n_7\ : STD_LOGIC;
signal \g81__22_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_1\ : STD_LOGIC;
signal \g81__22_carry_n_2\ : STD_LOGIC;
signal \g81__22_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry_n_4\ : STD_LOGIC;
signal \g81__22_carry_n_5\ : STD_LOGIC;
signal \g81__22_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_1\ : STD_LOGIC;
signal \g81__261_carry__0_n_2\ : STD_LOGIC;
signal \g81__261_carry__0_n_3\ : STD_LOGIC;
signal \g81__261_carry__0_n_4\ : STD_LOGIC;
signal \g81__261_carry__0_n_5\ : STD_LOGIC;
signal \g81__261_carry__0_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_n_7\ : STD_LOGIC;
signal \g81__261_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_1\ : STD_LOGIC;
signal \g81__261_carry__1_n_2\ : STD_LOGIC;
signal \g81__261_carry__1_n_3\ : STD_LOGIC;
signal \g81__261_carry__1_n_4\ : STD_LOGIC;
signal \g81__261_carry__1_n_5\ : STD_LOGIC;
signal \g81__261_carry__1_n_6\ : STD_LOGIC;
signal \g81__261_carry__1_n_7\ : STD_LOGIC;
signal \g81__261_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_n_1\ : STD_LOGIC;
signal \g81__261_carry__2_n_3\ : STD_LOGIC;
signal \g81__261_carry__2_n_6\ : STD_LOGIC;
signal \g81__261_carry__2_n_7\ : STD_LOGIC;
signal \g81__261_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_1\ : STD_LOGIC;
signal \g81__261_carry_n_2\ : STD_LOGIC;
signal \g81__261_carry_n_3\ : STD_LOGIC;
signal \g81__261_carry_n_4\ : STD_LOGIC;
signal \g81__261_carry_n_5\ : STD_LOGIC;
signal \g81__261_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry_n_7\ : STD_LOGIC;
signal \g81__301_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_1\ : STD_LOGIC;
signal \g81__301_carry__0_n_2\ : STD_LOGIC;
signal \g81__301_carry__0_n_3\ : STD_LOGIC;
signal \g81__301_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_1\ : STD_LOGIC;
signal \g81__301_carry__1_n_2\ : STD_LOGIC;
signal \g81__301_carry__1_n_3\ : STD_LOGIC;
signal \g81__301_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_1\ : STD_LOGIC;
signal \g81__301_carry__2_n_2\ : STD_LOGIC;
signal \g81__301_carry__2_n_3\ : STD_LOGIC;
signal \g81__301_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_1\ : STD_LOGIC;
signal \g81__301_carry__3_n_2\ : STD_LOGIC;
signal \g81__301_carry__3_n_3\ : STD_LOGIC;
signal \g81__301_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_1\ : STD_LOGIC;
signal \g81__301_carry__4_n_2\ : STD_LOGIC;
signal \g81__301_carry__4_n_3\ : STD_LOGIC;
signal \g81__301_carry__5_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_1\ : STD_LOGIC;
signal \g81__301_carry__5_n_2\ : STD_LOGIC;
signal \g81__301_carry__5_n_3\ : STD_LOGIC;
signal \g81__301_carry__6_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_n_1\ : STD_LOGIC;
signal \g81__301_carry__6_n_2\ : STD_LOGIC;
signal \g81__301_carry__6_n_3\ : STD_LOGIC;
signal \g81__301_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_1\ : STD_LOGIC;
signal \g81__301_carry_n_2\ : STD_LOGIC;
signal \g81__301_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_n_1\ : STD_LOGIC;
signal \g81__347_carry__0_n_2\ : STD_LOGIC;
signal \g81__347_carry__0_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_n_4\ : STD_LOGIC;
signal \g81__347_carry__0_n_5\ : STD_LOGIC;
signal \g81__347_carry__0_n_6\ : STD_LOGIC;
signal \g81__347_carry__0_n_7\ : STD_LOGIC;
signal \g81__347_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_1\ : STD_LOGIC;
signal \g81__347_carry_n_2\ : STD_LOGIC;
signal \g81__347_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry_n_4\ : STD_LOGIC;
signal \g81__347_carry_n_5\ : STD_LOGIC;
signal \g81__347_carry_n_6\ : STD_LOGIC;
signal \g81__347_carry_n_7\ : STD_LOGIC;
signal \g81__53_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_1\ : STD_LOGIC;
signal \g81__53_carry__0_n_2\ : STD_LOGIC;
signal \g81__53_carry__0_n_3\ : STD_LOGIC;
signal \g81__53_carry__0_n_4\ : STD_LOGIC;
signal \g81__53_carry__0_n_5\ : STD_LOGIC;
signal \g81__53_carry__0_n_6\ : STD_LOGIC;
signal \g81__53_carry__0_n_7\ : STD_LOGIC;
signal \g81__53_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_1\ : STD_LOGIC;
signal \g81__53_carry__1_n_2\ : STD_LOGIC;
signal \g81__53_carry__1_n_3\ : STD_LOGIC;
signal \g81__53_carry__1_n_4\ : STD_LOGIC;
signal \g81__53_carry__1_n_5\ : STD_LOGIC;
signal \g81__53_carry__1_n_6\ : STD_LOGIC;
signal \g81__53_carry__1_n_7\ : STD_LOGIC;
signal \g81__53_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_n_1\ : STD_LOGIC;
signal \g81__53_carry__2_n_3\ : STD_LOGIC;
signal \g81__53_carry__2_n_6\ : STD_LOGIC;
signal \g81__53_carry__2_n_7\ : STD_LOGIC;
signal \g81__53_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_1\ : STD_LOGIC;
signal \g81__53_carry_n_2\ : STD_LOGIC;
signal \g81__53_carry_n_3\ : STD_LOGIC;
signal \g81__53_carry_n_4\ : STD_LOGIC;
signal \g81__53_carry_n_5\ : STD_LOGIC;
signal \g81__53_carry_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_1\ : STD_LOGIC;
signal \g81__92_carry__0_n_2\ : STD_LOGIC;
signal \g81__92_carry__0_n_3\ : STD_LOGIC;
signal \g81__92_carry__0_n_4\ : STD_LOGIC;
signal \g81__92_carry__0_n_5\ : STD_LOGIC;
signal \g81__92_carry__0_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_n_7\ : STD_LOGIC;
signal \g81__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_1\ : STD_LOGIC;
signal \g81__92_carry__1_n_2\ : STD_LOGIC;
signal \g81__92_carry__1_n_3\ : STD_LOGIC;
signal \g81__92_carry__1_n_4\ : STD_LOGIC;
signal \g81__92_carry__1_n_5\ : STD_LOGIC;
signal \g81__92_carry__1_n_6\ : STD_LOGIC;
signal \g81__92_carry__1_n_7\ : STD_LOGIC;
signal \g81__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_n_1\ : STD_LOGIC;
signal \g81__92_carry__2_n_3\ : STD_LOGIC;
signal \g81__92_carry__2_n_6\ : STD_LOGIC;
signal \g81__92_carry__2_n_7\ : STD_LOGIC;
signal \g81__92_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_1\ : STD_LOGIC;
signal \g81__92_carry_n_2\ : STD_LOGIC;
signal \g81__92_carry_n_3\ : STD_LOGIC;
signal \g81__92_carry_n_4\ : STD_LOGIC;
signal \g81__92_carry_n_5\ : STD_LOGIC;
signal \g81__92_carry_n_6\ : STD_LOGIC;
signal \g81_carry__0_i_10_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_11_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_12_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_13_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_14_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_15_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_1\ : STD_LOGIC;
signal \g81_carry__0_n_2\ : STD_LOGIC;
signal \g81_carry__0_n_3\ : STD_LOGIC;
signal \g81_carry__0_n_4\ : STD_LOGIC;
signal \g81_carry__0_n_5\ : STD_LOGIC;
signal \g81_carry__0_n_6\ : STD_LOGIC;
signal \g81_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_1\ : STD_LOGIC;
signal \g81_carry__1_n_2\ : STD_LOGIC;
signal \g81_carry__1_n_3\ : STD_LOGIC;
signal \g81_carry__1_n_4\ : STD_LOGIC;
signal \g81_carry__1_n_5\ : STD_LOGIC;
signal \g81_carry__1_n_6\ : STD_LOGIC;
signal \g81_carry__1_n_7\ : STD_LOGIC;
signal \g81_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__2_n_1\ : STD_LOGIC;
signal \g81_carry__2_n_3\ : STD_LOGIC;
signal \g81_carry__2_n_6\ : STD_LOGIC;
signal \g81_carry__2_n_7\ : STD_LOGIC;
signal g81_carry_i_1_n_0 : STD_LOGIC;
signal g81_carry_i_2_n_0 : STD_LOGIC;
signal g81_carry_i_3_n_0 : STD_LOGIC;
signal g81_carry_i_4_n_0 : STD_LOGIC;
signal g81_carry_i_5_n_0 : STD_LOGIC;
signal g81_carry_i_6_n_0 : STD_LOGIC;
signal g81_carry_i_7_n_0 : STD_LOGIC;
signal g81_carry_n_0 : STD_LOGIC;
signal g81_carry_n_1 : STD_LOGIC;
signal g81_carry_n_2 : STD_LOGIC;
signal g81_carry_n_3 : STD_LOGIC;
signal g81_carry_n_7 : STD_LOGIC;
signal g83 : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \g83__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_1\ : STD_LOGIC;
signal \g83__0_carry__0_n_2\ : STD_LOGIC;
signal \g83__0_carry__0_n_3\ : STD_LOGIC;
signal \g83__0_carry__0_n_4\ : STD_LOGIC;
signal \g83__0_carry__0_n_5\ : STD_LOGIC;
signal \g83__0_carry__0_n_6\ : STD_LOGIC;
signal \g83__0_carry__0_n_7\ : STD_LOGIC;
signal \g83__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__1_n_2\ : STD_LOGIC;
signal \g83__0_carry__1_n_7\ : STD_LOGIC;
signal \g83__0_carry_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_1\ : STD_LOGIC;
signal \g83__0_carry_n_2\ : STD_LOGIC;
signal \g83__0_carry_n_3\ : STD_LOGIC;
signal \g83__0_carry_n_4\ : STD_LOGIC;
signal \g83__0_carry_n_5\ : STD_LOGIC;
signal \g83__0_carry_n_6\ : STD_LOGIC;
signal \g83__0_carry_n_7\ : STD_LOGIC;
signal g84 : STD_LOGIC;
signal \g84_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g84_carry__0_i_2_n_0\ : STD_LOGIC;
signal g84_carry_i_1_n_0 : STD_LOGIC;
signal g84_carry_i_2_n_0 : STD_LOGIC;
signal g84_carry_i_3_n_0 : STD_LOGIC;
signal g84_carry_i_4_n_0 : STD_LOGIC;
signal g84_carry_i_5_n_0 : STD_LOGIC;
signal g84_carry_i_6_n_0 : STD_LOGIC;
signal g84_carry_i_7_n_0 : STD_LOGIC;
signal g84_carry_i_8_n_0 : STD_LOGIC;
signal g84_carry_n_0 : STD_LOGIC;
signal g84_carry_n_1 : STD_LOGIC;
signal g84_carry_n_2 : STD_LOGIC;
signal g84_carry_n_3 : STD_LOGIC;
signal \NLW__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__120_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__149_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__149_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__206_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__206_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__22_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__22_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__22_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__261_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__261_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__301_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__301_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__347_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__53_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__53_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__53_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__92_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__92_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_g81_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g83__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g83__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_g84_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g84_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g84_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute HLUTNM : string;
attribute HLUTNM of \g81__120_carry__1_i_1\ : label is "lutpair7";
attribute HLUTNM of \g81__149_carry__0_i_1\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_2\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__0_i_5\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__0_i_6\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_7\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__1_i_1\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_2\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_3\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__1_i_4\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__1_i_5\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__1_i_6\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_7\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_8\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__2_i_1\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_2\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_3\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__2_i_4\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__2_i_5\ : label is "lutpair17";
attribute HLUTNM of \g81__149_carry__2_i_6\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_7\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_8\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__3_i_1\ : label is "lutpair17";
attribute HLUTNM of \g81__206_carry__0_i_1\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_2\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__0_i_5\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__0_i_6\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_7\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__1_i_1\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_2\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_3\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__1_i_4\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__1_i_5\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__1_i_6\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_7\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_8\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__2_i_1\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__2_i_4\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__2_i_6\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__3_i_1\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_3\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__3_i_6\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_8\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__4_i_2\ : label is "lutpair26";
attribute HLUTNM of \g81__206_carry__4_i_6\ : label is "lutpair26";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \g81_carry__0_i_10\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_11\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_12\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \g81_carry__0_i_13\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_14\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_15\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__0_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__1_i_9\ : label is "soft_lutpair3";
attribute HLUTNM of \g81_carry__2_i_2\ : label is "lutpair7";
attribute HLUTNM of \g83__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \g83__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_7\ : label is "lutpair0";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(4 downto 1),
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => \_carry_i_5_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_4\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_6\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3 downto 2) => \NLW__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \_carry__1_n_2\,
CO(0) => \NLW__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => g83(9),
S(3 downto 1) => B"001",
S(0) => \_carry__1_i_1_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_2\,
O => \_carry__1_i_1_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
O => \_carry_i_1_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_4\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_6\,
O => \_carry_i_5_n_0\
);
\g81__120_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__120_carry_n_0\,
CO(2) => \g81__120_carry_n_1\,
CO(1) => \g81__120_carry_n_2\,
CO(0) => \g81__120_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__120_carry_i_1_n_0\,
DI(1) => \g81__120_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__120_carry_n_4\,
O(2) => \g81__120_carry_n_5\,
O(1) => \g81__120_carry_n_6\,
O(0) => \NLW_g81__120_carry_O_UNCONNECTED\(0),
S(3) => \g81__120_carry_i_3_n_0\,
S(2) => \g81__120_carry_i_4_n_0\,
S(1) => \g81__120_carry_i_5_n_0\,
S(0) => \g81__120_carry_i_6_n_0\
);
\g81__120_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry_n_0\,
CO(3) => \g81__120_carry__0_n_0\,
CO(2) => \g81__120_carry__0_n_1\,
CO(1) => \g81__120_carry__0_n_2\,
CO(0) => \g81__120_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__120_carry__0_n_4\,
O(2) => \g81__120_carry__0_n_5\,
O(1) => \g81__120_carry__0_n_6\,
O(0) => \g81__120_carry__0_n_7\,
S(3) => \g81__120_carry__0_i_1_n_0\,
S(2) => \g81__120_carry__0_i_2_n_0\,
S(1) => \g81__120_carry__0_i_3_n_0\,
S(0) => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__120_carry__0_i_1_n_0\
);
\g81__120_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__120_carry__0_i_2_n_0\
);
\g81__120_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__120_carry__0_i_3_n_0\
);
\g81__120_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__0_n_0\,
CO(3) => \g81__120_carry__1_n_0\,
CO(2) => \g81__120_carry__1_n_1\,
CO(1) => \g81__120_carry__1_n_2\,
CO(0) => \g81__120_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__120_carry__1_n_4\,
O(2) => \g81__120_carry__1_n_5\,
O(1) => \g81__120_carry__1_n_6\,
O(0) => \g81__120_carry__1_n_7\,
S(3) => \g81__120_carry__1_i_1_n_0\,
S(2) => \g81__120_carry__1_i_2_n_0\,
S(1) => \g81__120_carry__1_i_3_n_0\,
S(0) => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"369C"
)
port map (
I0 => g84,
I1 => \g81_carry__1_i_1_n_0\,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__120_carry__1_i_1_n_0\
);
\g81__120_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_2_n_0\
);
\g81__120_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_3_n_0\
);
\g81__120_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__1_n_0\,
CO(3) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__120_carry__2_n_1\,
CO(1) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__120_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__120_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__120_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__120_carry__2_n_6\,
O(0) => \g81__120_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__120_carry__2_i_1_n_0\
);
\g81__120_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__120_carry_i_1_n_0\
);
\g81__120_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__120_carry_i_2_n_0\
);
\g81__120_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__120_carry_i_3_n_0\
);
\g81__120_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__120_carry_i_4_n_0\
);
\g81__120_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__120_carry_i_5_n_0\
);
\g81__120_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__120_carry_i_6_n_0\
);
\g81__149_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__149_carry_n_0\,
CO(2) => \g81__149_carry_n_1\,
CO(1) => \g81__149_carry_n_2\,
CO(0) => \g81__149_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry_i_1_n_0\,
DI(2) => \g81__149_carry_i_2_n_0\,
DI(1) => \g81__149_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__149_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry_i_4_n_0\,
S(2) => \g81__149_carry_i_5_n_0\,
S(1) => \g81__149_carry_i_6_n_0\,
S(0) => \g81__149_carry_i_7_n_0\
);
\g81__149_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry_n_0\,
CO(3) => \g81__149_carry__0_n_0\,
CO(2) => \g81__149_carry__0_n_1\,
CO(1) => \g81__149_carry__0_n_2\,
CO(0) => \g81__149_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__0_i_1_n_0\,
DI(2) => \g81__149_carry__0_i_2_n_0\,
DI(1) => \g81__149_carry__0_i_3_n_0\,
DI(0) => \g81__149_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__0_i_5_n_0\,
S(2) => \g81__149_carry__0_i_6_n_0\,
S(1) => \g81__149_carry__0_i_7_n_0\,
S(0) => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
O => \g81__149_carry__0_i_1_n_0\
);
\g81__149_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
O => \g81__149_carry__0_i_2_n_0\
);
\g81__149_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_6\,
I1 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_3_n_0\
);
\g81__149_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
O => \g81__149_carry__0_i_4_n_0\
);
\g81__149_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
I3 => \g81__149_carry__0_i_1_n_0\,
O => \g81__149_carry__0_i_5_n_0\
);
\g81__149_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
I3 => \g81__149_carry__0_i_2_n_0\,
O => \g81__149_carry__0_i_6_n_0\
);
\g81__149_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
I2 => \g81_carry__1_n_6\,
I3 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_7_n_0\
);
\g81__149_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
I2 => \g81__22_carry_n_4\,
I3 => \g81_carry__1_n_6\,
O => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__0_n_0\,
CO(3) => \g81__149_carry__1_n_0\,
CO(2) => \g81__149_carry__1_n_1\,
CO(1) => \g81__149_carry__1_n_2\,
CO(0) => \g81__149_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__1_i_1_n_0\,
DI(2) => \g81__149_carry__1_i_2_n_0\,
DI(1) => \g81__149_carry__1_i_3_n_0\,
DI(0) => \g81__149_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__1_i_5_n_0\,
S(2) => \g81__149_carry__1_i_6_n_0\,
S(1) => \g81__149_carry__1_i_7_n_0\,
S(0) => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__1_i_1_n_0\
);
\g81__149_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
O => \g81__149_carry__1_i_2_n_0\
);
\g81__149_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
O => \g81__149_carry__1_i_3_n_0\
);
\g81__149_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
O => \g81__149_carry__1_i_4_n_0\
);
\g81__149_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_1_n_0\,
O => \g81__149_carry__1_i_5_n_0\
);
\g81__149_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_2_n_0\,
O => \g81__149_carry__1_i_6_n_0\
);
\g81__149_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
I3 => \g81__149_carry__1_i_3_n_0\,
O => \g81__149_carry__1_i_7_n_0\
);
\g81__149_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
I3 => \g81__149_carry__1_i_4_n_0\,
O => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__1_n_0\,
CO(3) => \g81__149_carry__2_n_0\,
CO(2) => \g81__149_carry__2_n_1\,
CO(1) => \g81__149_carry__2_n_2\,
CO(0) => \g81__149_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__2_i_1_n_0\,
DI(2) => \g81__149_carry__2_i_2_n_0\,
DI(1) => \g81__149_carry__2_i_3_n_0\,
DI(0) => \g81__149_carry__2_i_4_n_0\,
O(3) => \g81__149_carry__2_n_4\,
O(2) => \g81__149_carry__2_n_5\,
O(1) => \g81__149_carry__2_n_6\,
O(0) => \g81__149_carry__2_n_7\,
S(3) => \g81__149_carry__2_i_5_n_0\,
S(2) => \g81__149_carry__2_i_6_n_0\,
S(1) => \g81__149_carry__2_i_7_n_0\,
S(0) => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_1_n_0\
);
\g81__149_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_2_n_0\
);
\g81__149_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_3_n_0\
);
\g81__149_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_4_n_0\
);
\g81__149_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_1_n_0\,
O => \g81__149_carry__2_i_5_n_0\
);
\g81__149_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_2_n_0\,
O => \g81__149_carry__2_i_6_n_0\
);
\g81__149_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_3_n_0\,
O => \g81__149_carry__2_i_7_n_0\
);
\g81__149_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_4_n_0\,
O => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__2_n_0\,
CO(3) => \g81__149_carry__3_n_0\,
CO(2) => \g81__149_carry__3_n_1\,
CO(1) => \g81__149_carry__3_n_2\,
CO(0) => \g81__149_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__2_i_2_n_0\,
DI(2) => \g81_carry__2_i_2_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81__149_carry__3_i_1_n_0\,
O(3) => \g81__149_carry__3_n_4\,
O(2) => \g81__149_carry__3_n_5\,
O(1) => \g81__149_carry__3_n_6\,
O(0) => \g81__149_carry__3_n_7\,
S(3) => \g81__149_carry__3_i_2_n_0\,
S(2) => \g81__149_carry__3_i_3_n_0\,
S(1) => \g81__149_carry__3_i_4_n_0\,
S(0) => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__3_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__3_i_1_n_0\
);
\g81__149_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_7\,
O => \g81__149_carry__3_i_2_n_0\
);
\g81__149_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_4\,
O => \g81__149_carry__3_i_3_n_0\
);
\g81__149_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_5\,
O => \g81__149_carry__3_i_4_n_0\
);
\g81__149_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__149_carry__3_i_1_n_0\,
I1 => \g81__53_carry__1_n_6\,
O => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__3_n_0\,
CO(3) => \g81__149_carry__4_n_0\,
CO(2) => \NLW_g81__149_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__149_carry__4_n_2\,
CO(0) => \g81__149_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__149_carry__4_i_1_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3) => \NLW_g81__149_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__149_carry__4_n_5\,
O(1) => \g81__149_carry__4_n_6\,
O(0) => \g81__149_carry__4_n_7\,
S(3 downto 2) => B"10",
S(1) => \g81__149_carry__4_i_2_n_0\,
S(0) => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__149_carry__4_i_1_n_0\
);
\g81__149_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_1\,
O => \g81__149_carry__4_i_2_n_0\
);
\g81__149_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_6\,
O => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
O => \g81__149_carry_i_1_n_0\
);
\g81__149_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
O => \g81__149_carry_i_2_n_0\
);
\g81__149_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_3_n_0\
);
\g81__149_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
I2 => \g81__22_carry_n_5\,
I3 => \g81_carry__1_n_7\,
O => \g81__149_carry_i_4_n_0\
);
\g81__149_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__22_carry_n_6\,
I3 => \g81_carry__0_n_4\,
O => \g81__149_carry_i_5_n_0\
);
\g81__149_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g81_carry__0_n_5\,
O => \g81__149_carry_i_6_n_0\
);
\g81__149_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_7_n_0\
);
\g81__206_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__206_carry_n_0\,
CO(2) => \g81__206_carry_n_1\,
CO(1) => \g81__206_carry_n_2\,
CO(0) => \g81__206_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry_i_1_n_0\,
DI(2) => \g81__206_carry_i_2_n_0\,
DI(1) => \g81__206_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__206_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry_i_4_n_0\,
S(2) => \g81__206_carry_i_5_n_0\,
S(1) => \g81__206_carry_i_6_n_0\,
S(0) => \g81__206_carry_i_7_n_0\
);
\g81__206_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry_n_0\,
CO(3) => \g81__206_carry__0_n_0\,
CO(2) => \g81__206_carry__0_n_1\,
CO(1) => \g81__206_carry__0_n_2\,
CO(0) => \g81__206_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__0_i_1_n_0\,
DI(2) => \g81__206_carry__0_i_2_n_0\,
DI(1) => \g81__206_carry__0_i_3_n_0\,
DI(0) => \g81__206_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__0_i_5_n_0\,
S(2) => \g81__206_carry__0_i_6_n_0\,
S(1) => \g81__206_carry__0_i_7_n_0\,
S(0) => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
O => \g81__206_carry__0_i_1_n_0\
);
\g81__206_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
O => \g81__206_carry__0_i_2_n_0\
);
\g81__206_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_4\,
I1 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_3_n_0\
);
\g81__206_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
O => \g81__206_carry__0_i_4_n_0\
);
\g81__206_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
I3 => \g81__206_carry__0_i_1_n_0\,
O => \g81__206_carry__0_i_5_n_0\
);
\g81__206_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
I3 => \g81__206_carry__0_i_2_n_0\,
O => \g81__206_carry__0_i_6_n_0\
);
\g81__206_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
I2 => \g81__92_carry_n_4\,
I3 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_7_n_0\
);
\g81__206_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
I2 => \g81__149_carry__3_n_7\,
I3 => \g81__92_carry_n_4\,
O => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__0_n_0\,
CO(3) => \g81__206_carry__1_n_0\,
CO(2) => \g81__206_carry__1_n_1\,
CO(1) => \g81__206_carry__1_n_2\,
CO(0) => \g81__206_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__1_i_1_n_0\,
DI(2) => \g81__206_carry__1_i_2_n_0\,
DI(1) => \g81__206_carry__1_i_3_n_0\,
DI(0) => \g81__206_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__1_i_5_n_0\,
S(2) => \g81__206_carry__1_i_6_n_0\,
S(1) => \g81__206_carry__1_i_7_n_0\,
S(0) => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
O => \g81__206_carry__1_i_1_n_0\
);
\g81__206_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
O => \g81__206_carry__1_i_2_n_0\
);
\g81__206_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
O => \g81__206_carry__1_i_3_n_0\
);
\g81__206_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
O => \g81__206_carry__1_i_4_n_0\
);
\g81__206_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
I3 => \g81__206_carry__1_i_1_n_0\,
O => \g81__206_carry__1_i_5_n_0\
);
\g81__206_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
I3 => \g81__206_carry__1_i_2_n_0\,
O => \g81__206_carry__1_i_6_n_0\
);
\g81__206_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
I3 => \g81__206_carry__1_i_3_n_0\,
O => \g81__206_carry__1_i_7_n_0\
);
\g81__206_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
I3 => \g81__206_carry__1_i_4_n_0\,
O => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__1_n_0\,
CO(3) => \g81__206_carry__2_n_0\,
CO(2) => \g81__206_carry__2_n_1\,
CO(1) => \g81__206_carry__2_n_2\,
CO(0) => \g81__206_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_i_1_n_0\,
DI(2) => \g81__206_carry__2_i_2_n_0\,
DI(1) => \g81__206_carry__2_i_3_n_0\,
DI(0) => \g81__206_carry__2_i_4_n_0\,
O(3) => \g81__206_carry__2_n_4\,
O(2) => \g81__206_carry__2_n_5\,
O(1) => \g81__206_carry__2_n_6\,
O(0) => \g81__206_carry__2_n_7\,
S(3) => \g81__206_carry__2_i_5_n_0\,
S(2) => \g81__206_carry__2_i_6_n_0\,
S(1) => \g81__206_carry__2_i_7_n_0\,
S(0) => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
O => \g81__206_carry__2_i_1_n_0\
);
\g81__206_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry__2_n_7\,
I1 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_2_n_0\
);
\g81__206_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__0_n_6\,
I3 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_3_n_0\
);
\g81__206_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
O => \g81__206_carry__2_i_4_n_0\
);
\g81__206_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_1_n_0\,
I1 => \g81__120_carry__1_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__2_i_5_n_0\
);
\g81__206_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
I2 => \g81__92_carry__2_n_7\,
I3 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_6_n_0\
);
\g81__206_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"888E77717771888E"
)
port map (
I0 => \g81__92_carry__1_n_4\,
I1 => \g81__120_carry__0_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
I4 => \g81__120_carry__0_n_5\,
I5 => \g81__92_carry__2_n_7\,
O => \g81__206_carry__2_i_7_n_0\
);
\g81__206_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_4_n_0\,
I1 => \g81__120_carry__0_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__2_n_0\,
CO(3) => \g81__206_carry__3_n_0\,
CO(2) => \g81__206_carry__3_n_1\,
CO(1) => \g81__206_carry__3_n_2\,
CO(0) => \g81__206_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_i_1_n_0\,
DI(2) => \g81__206_carry__3_i_2_n_0\,
DI(1) => \g81__206_carry__3_i_3_n_0\,
DI(0) => \g81__206_carry__3_i_4_n_0\,
O(3) => \g81__206_carry__3_n_4\,
O(2) => \g81__206_carry__3_n_5\,
O(1) => \g81__206_carry__3_n_6\,
O(0) => \g81__206_carry__3_n_7\,
S(3) => \g81__206_carry__3_i_5_n_0\,
S(2) => \g81__206_carry__3_i_6_n_0\,
S(1) => \g81__206_carry__3_i_7_n_0\,
S(0) => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_1_n_0\
);
\g81__206_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__3_i_2_n_0\
);
\g81__206_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_3_n_0\
);
\g81__206_carry__3_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__1_n_7\,
I3 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__3_i_4_n_0\
);
\g81__206_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_1_n_0\,
I1 => \g81__120_carry__2_n_7\,
O => \g81__206_carry__3_i_5_n_0\
);
\g81__206_carry__3_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__1_n_4\,
O => \g81__206_carry__3_i_6_n_0\
);
\g81__206_carry__3_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_3_n_0\,
I1 => \g81__120_carry__1_n_5\,
O => \g81__206_carry__3_i_7_n_0\
);
\g81__206_carry__3_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"56AAAAA9"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
I3 => \g81__92_carry__2_n_1\,
I4 => \g81__120_carry__1_n_7\,
O => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__3_n_0\,
CO(3) => \g81__206_carry__4_n_0\,
CO(2) => \NLW_g81__206_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__206_carry__4_n_2\,
CO(0) => \g81__206_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__206_carry__4_i_1_n_0\,
DI(1) => \g81__206_carry__4_i_2_n_0\,
DI(0) => \g81__206_carry__4_i_3_n_0\,
O(3) => \NLW_g81__206_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__206_carry__4_n_5\,
O(1) => \g81__206_carry__4_n_6\,
O(0) => \g81__206_carry__4_n_7\,
S(3) => '1',
S(2) => \g81__206_carry__4_i_4_n_0\,
S(1) => \g81__206_carry__4_i_5_n_0\,
S(0) => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_1_n_0\
);
\g81__206_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__4_i_2_n_0\
);
\g81__206_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_3_n_0\
);
\g81__206_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_4_n_0\
);
\g81__206_carry__4_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__4_i_2_n_0\,
I1 => \g81__120_carry__2_n_1\,
O => \g81__206_carry__4_i_5_n_0\
);
\g81__206_carry__4_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__2_n_6\,
O => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
O => \g81__206_carry_i_1_n_0\
);
\g81__206_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
O => \g81__206_carry_i_2_n_0\
);
\g81__206_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_3_n_0\
);
\g81__206_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
I2 => \g81__149_carry__2_n_4\,
I3 => \g81__92_carry_n_5\,
O => \g81__206_carry_i_4_n_0\
);
\g81__206_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
I2 => \g81__149_carry__2_n_5\,
I3 => \g81__92_carry_n_6\,
O => \g81__206_carry_i_5_n_0\
);
\g81__206_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
I2 => \g81__149_carry__2_n_6\,
I3 => g81_carry_n_7,
O => \g81__206_carry_i_6_n_0\
);
\g81__206_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_7_n_0\
);
\g81__22_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__22_carry_n_0\,
CO(2) => \g81__22_carry_n_1\,
CO(1) => \g81__22_carry_n_2\,
CO(0) => \g81__22_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__22_carry_i_1_n_0\,
DI(1) => \g81__22_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__22_carry_n_4\,
O(2) => \g81__22_carry_n_5\,
O(1) => \g81__22_carry_n_6\,
O(0) => \NLW_g81__22_carry_O_UNCONNECTED\(0),
S(3) => \g81__22_carry_i_3_n_0\,
S(2) => \g81__22_carry_i_4_n_0\,
S(1) => \g81__22_carry_i_5_n_0\,
S(0) => \g81__22_carry_i_6_n_0\
);
\g81__22_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry_n_0\,
CO(3) => \g81__22_carry__0_n_0\,
CO(2) => \g81__22_carry__0_n_1\,
CO(1) => \g81__22_carry__0_n_2\,
CO(0) => \g81__22_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__22_carry__0_n_4\,
O(2) => \g81__22_carry__0_n_5\,
O(1) => \g81__22_carry__0_n_6\,
O(0) => \g81__22_carry__0_n_7\,
S(3) => \g81__22_carry__0_i_1_n_0\,
S(2) => \g81__22_carry__0_i_2_n_0\,
S(1) => \g81__22_carry__0_i_3_n_0\,
S(0) => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__22_carry__0_i_1_n_0\
);
\g81__22_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__22_carry__0_i_2_n_0\
);
\g81__22_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__22_carry__0_i_3_n_0\
);
\g81__22_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__0_n_0\,
CO(3) => \g81__22_carry__1_n_0\,
CO(2) => \g81__22_carry__1_n_1\,
CO(1) => \g81__22_carry__1_n_2\,
CO(0) => \g81__22_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__22_carry__1_n_4\,
O(2) => \g81__22_carry__1_n_5\,
O(1) => \g81__22_carry__1_n_6\,
O(0) => \g81__22_carry__1_n_7\,
S(3) => \g81__22_carry__1_i_1_n_0\,
S(2) => \g81__22_carry__1_i_2_n_0\,
S(1) => \g81__22_carry__1_i_3_n_0\,
S(0) => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__22_carry__1_i_1_n_0\
);
\g81__22_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_2_n_0\
);
\g81__22_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_3_n_0\
);
\g81__22_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__1_n_0\,
CO(3) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__22_carry__2_n_1\,
CO(1) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__22_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__22_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__22_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__22_carry__2_n_6\,
O(0) => \g81__22_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__22_carry__2_i_1_n_0\
);
\g81__22_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__22_carry_i_1_n_0\
);
\g81__22_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__22_carry_i_2_n_0\
);
\g81__22_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__22_carry_i_3_n_0\
);
\g81__22_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__22_carry_i_4_n_0\
);
\g81__22_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__22_carry_i_5_n_0\
);
\g81__22_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__22_carry_i_6_n_0\
);
\g81__261_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__261_carry_n_0\,
CO(2) => \g81__261_carry_n_1\,
CO(1) => \g81__261_carry_n_2\,
CO(0) => \g81__261_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_n_6\,
DI(2) => \g81__206_carry__2_n_7\,
DI(1 downto 0) => B"01",
O(3) => \g81__261_carry_n_4\,
O(2) => \g81__261_carry_n_5\,
O(1) => \g81__261_carry_n_6\,
O(0) => \g81__261_carry_n_7\,
S(3) => \g81__261_carry_i_1_n_0\,
S(2) => \g81__261_carry_i_2_n_0\,
S(1) => \g81__261_carry_i_3_n_0\,
S(0) => \g81__261_carry_i_4_n_0\
);
\g81__261_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry_n_0\,
CO(3) => \g81__261_carry__0_n_0\,
CO(2) => \g81__261_carry__0_n_1\,
CO(1) => \g81__261_carry__0_n_2\,
CO(0) => \g81__261_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_n_6\,
DI(2) => \g81__206_carry__3_n_7\,
DI(1) => \g81__206_carry__2_n_4\,
DI(0) => \g81__206_carry__2_n_5\,
O(3) => \g81__261_carry__0_n_4\,
O(2) => \g81__261_carry__0_n_5\,
O(1) => \g81__261_carry__0_n_6\,
O(0) => \g81__261_carry__0_n_7\,
S(3) => \g81__261_carry__0_i_1_n_0\,
S(2) => \g81__261_carry__0_i_2_n_0\,
S(1) => \g81__261_carry__0_i_3_n_0\,
S(0) => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__206_carry__3_n_4\,
O => \g81__261_carry__0_i_1_n_0\
);
\g81__261_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__206_carry__3_n_5\,
O => \g81__261_carry__0_i_2_n_0\
);
\g81__261_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__206_carry__3_n_6\,
O => \g81__261_carry__0_i_3_n_0\
);
\g81__261_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__206_carry__3_n_7\,
O => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__0_n_0\,
CO(3) => \g81__261_carry__1_n_0\,
CO(2) => \g81__261_carry__1_n_1\,
CO(1) => \g81__261_carry__1_n_2\,
CO(0) => \g81__261_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__4_n_6\,
DI(2) => \g81__206_carry__4_n_7\,
DI(1) => \g81__206_carry__3_n_4\,
DI(0) => \g81__206_carry__3_n_5\,
O(3) => \g81__261_carry__1_n_4\,
O(2) => \g81__261_carry__1_n_5\,
O(1) => \g81__261_carry__1_n_6\,
O(0) => \g81__261_carry__1_n_7\,
S(3) => \g81__261_carry__1_i_1_n_0\,
S(2) => \g81__261_carry__1_i_2_n_0\,
S(1) => \g81__261_carry__1_i_3_n_0\,
S(0) => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_6\,
I1 => \g81__206_carry__4_n_0\,
O => \g81__261_carry__1_i_1_n_0\
);
\g81__261_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_7\,
I1 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__1_i_2_n_0\
);
\g81__261_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__206_carry__4_n_6\,
O => \g81__261_carry__1_i_3_n_0\
);
\g81__261_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__206_carry__4_n_7\,
O => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__1_n_0\,
CO(3) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__261_carry__2_n_1\,
CO(1) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__261_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__206_carry__4_n_0\,
DI(0) => \g81__206_carry__4_n_5\,
O(3 downto 2) => \NLW_g81__261_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__261_carry__2_n_6\,
O(0) => \g81__261_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \g81__261_carry__2_i_1_n_0\,
S(0) => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \g81__206_carry__4_n_0\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__261_carry__2_i_1_n_0\
);
\g81__261_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__206_carry__2_n_4\,
O => \g81__261_carry_i_1_n_0\
);
\g81__261_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__206_carry__2_n_5\,
O => \g81__261_carry_i_2_n_0\
);
\g81__261_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__261_carry_i_3_n_0\
);
\g81__261_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__261_carry_i_4_n_0\
);
\g81__301_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__301_carry_n_0\,
CO(2) => \g81__301_carry_n_1\,
CO(1) => \g81__301_carry_n_2\,
CO(0) => \g81__301_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry_i_1_n_0\,
DI(2) => \g81__301_carry_i_2_n_0\,
DI(1) => \g81__301_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__301_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry_i_4_n_0\,
S(2) => \g81__301_carry_i_5_n_0\,
S(1) => \g81__301_carry_i_6_n_0\,
S(0) => \g81__301_carry_i_7_n_0\
);
\g81__301_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry_n_0\,
CO(3) => \g81__301_carry__0_n_0\,
CO(2) => \g81__301_carry__0_n_1\,
CO(1) => \g81__301_carry__0_n_2\,
CO(0) => \g81__301_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__0_i_1_n_0\,
DI(2) => \g81__301_carry__0_i_2_n_0\,
DI(1) => \g81__301_carry__0_i_3_n_0\,
DI(0) => \g81__301_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__0_i_5_n_0\,
S(2) => \g81__301_carry__0_i_6_n_0\,
S(1) => \g81__301_carry__0_i_7_n_0\,
S(0) => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_5\,
I1 => g84,
I2 => g83(6),
I3 => \g83__0_carry__0_n_5\,
O => \g81__301_carry__0_i_1_n_0\
);
\g81__301_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_6\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
O => \g81__301_carry__0_i_2_n_0\
);
\g81__301_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_7\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
O => \g81__301_carry__0_i_3_n_0\
);
\g81__301_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_4\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
O => \g81__301_carry__0_i_4_n_0\
);
\g81__301_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
I3 => \g81__261_carry__0_n_5\,
I4 => \g81__261_carry__0_n_4\,
I5 => \g81_carry__1_i_9_n_0\,
O => \g81__301_carry__0_i_5_n_0\
);
\g81__301_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
I3 => \g81__261_carry__0_n_6\,
I4 => \g81__261_carry__0_n_5\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__301_carry__0_i_6_n_0\
);
\g81__301_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
I3 => \g81__261_carry__0_n_7\,
I4 => \g81__261_carry__0_n_6\,
I5 => \g81_carry__0_i_14_n_0\,
O => \g81__301_carry__0_i_7_n_0\
);
\g81__301_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => \g81__261_carry_n_4\,
I2 => \g81__261_carry__0_n_7\,
I3 => \g83__0_carry__0_n_7\,
I4 => g83(4),
I5 => g84,
O => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__0_n_0\,
CO(3) => \g81__301_carry__1_n_0\,
CO(2) => \g81__301_carry__1_n_1\,
CO(1) => \g81__301_carry__1_n_2\,
CO(0) => \g81__301_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__1_i_1_n_0\,
DI(2) => \g81__301_carry__1_i_2_n_0\,
DI(1) => \g81__301_carry__1_i_3_n_0\,
DI(0) => \g81__301_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__1_i_5_n_0\,
S(2) => \g81__301_carry__1_i_6_n_0\,
S(1) => \g81__301_carry__1_i_7_n_0\,
S(0) => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__1_i_1_n_0\
);
\g81__301_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_6\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__301_carry__1_i_2_n_0\
);
\g81__301_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_7\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__301_carry__1_i_3_n_0\
);
\g81__301_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_4\,
I1 => g84,
I2 => g83(7),
I3 => \g83__0_carry__0_n_4\,
O => \g81__301_carry__1_i_4_n_0\
);
\g81__301_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \g81__261_carry__1_n_4\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_5_n_0\
);
\g81__301_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"50AF30CF50AFCF30"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => \g81__261_carry__1_n_6\,
I3 => \g81__261_carry__1_n_5\,
I4 => g84,
I5 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_6_n_0\
);
\g81__301_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => g83(8),
I2 => g84,
I3 => \g81__261_carry__1_n_7\,
I4 => \g81__261_carry__1_n_6\,
I5 => \g81__301_carry__1_i_9_n_0\,
O => \g81__301_carry__1_i_7_n_0\
);
\g81__301_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__1_i_9_n_0\,
I1 => \g81__261_carry__0_n_4\,
I2 => \g81__261_carry__1_n_7\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => g84,
O => \g81__301_carry__1_i_9_n_0\
);
\g81__301_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__1_n_0\,
CO(3) => \g81__301_carry__2_n_0\,
CO(2) => \g81__301_carry__2_n_1\,
CO(1) => \g81__301_carry__2_n_2\,
CO(0) => \g81__301_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__2_i_1_n_0\,
DI(2) => \g81__301_carry__2_i_2_n_0\,
DI(1) => \g81__301_carry__2_i_3_n_0\,
DI(0) => \g81__301_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__2_i_5_n_0\,
S(2) => \g81__301_carry__2_i_6_n_0\,
S(1) => \g81__301_carry__2_i_7_n_0\,
S(0) => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__2_i_1_n_0\
);
\g81__301_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_2_n_0\
);
\g81__301_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_3_n_0\
);
\g81__301_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_4_n_0\
);
\g81__301_carry__2_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_5_n_0\
);
\g81__301_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6663"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \g81__261_carry__2_n_1\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_6_n_0\
);
\g81__301_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \g81__261_carry__2_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_7_n_0\
);
\g81__301_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \g81__261_carry__2_n_7\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__2_n_0\,
CO(3) => \g81__301_carry__3_n_0\,
CO(2) => \g81__301_carry__3_n_1\,
CO(1) => \g81__301_carry__3_n_2\,
CO(0) => \g81__301_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__3_i_1_n_0\,
DI(2) => \g81__301_carry__3_i_2_n_0\,
DI(1) => \g81__301_carry__3_i_3_n_0\,
DI(0) => \g81__301_carry__3_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__3_i_5_n_0\,
S(2) => \g81__301_carry__3_i_6_n_0\,
S(1) => \g81__301_carry__3_i_7_n_0\,
S(0) => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_1_n_0\
);
\g81__301_carry__3_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_2_n_0\
);
\g81__301_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_3_n_0\
);
\g81__301_carry__3_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_4_n_0\
);
\g81__301_carry__3_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_5_n_0\
);
\g81__301_carry__3_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_6_n_0\
);
\g81__301_carry__3_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_7_n_0\
);
\g81__301_carry__3_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__3_n_0\,
CO(3) => \g81__301_carry__4_n_0\,
CO(2) => \g81__301_carry__4_n_1\,
CO(1) => \g81__301_carry__4_n_2\,
CO(0) => \g81__301_carry__4_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__4_i_1_n_0\,
DI(2) => \g81__301_carry__4_i_2_n_0\,
DI(1) => \g81__301_carry__4_i_3_n_0\,
DI(0) => \g81__301_carry__4_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__4_i_5_n_0\,
S(2) => \g81__301_carry__4_i_6_n_0\,
S(1) => \g81__301_carry__4_i_7_n_0\,
S(0) => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__4_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_1_n_0\
);
\g81__301_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_2_n_0\
);
\g81__301_carry__4_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_3_n_0\
);
\g81__301_carry__4_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_4_n_0\
);
\g81__301_carry__4_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_5_n_0\
);
\g81__301_carry__4_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_6_n_0\
);
\g81__301_carry__4_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_7_n_0\
);
\g81__301_carry__4_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__4_n_0\,
CO(3) => \g81__301_carry__5_n_0\,
CO(2) => \g81__301_carry__5_n_1\,
CO(1) => \g81__301_carry__5_n_2\,
CO(0) => \g81__301_carry__5_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__5_i_1_n_0\,
DI(2) => \g81__301_carry__5_i_2_n_0\,
DI(1) => \g81__301_carry__5_i_3_n_0\,
DI(0) => \g81__301_carry__5_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__5_i_5_n_0\,
S(2) => \g81__301_carry__5_i_6_n_0\,
S(1) => \g81__301_carry__5_i_7_n_0\,
S(0) => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__5_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_1_n_0\
);
\g81__301_carry__5_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_2_n_0\
);
\g81__301_carry__5_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_3_n_0\
);
\g81__301_carry__5_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_4_n_0\
);
\g81__301_carry__5_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_5_n_0\
);
\g81__301_carry__5_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_6_n_0\
);
\g81__301_carry__5_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_7_n_0\
);
\g81__301_carry__5_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__5_n_0\,
CO(3) => \NLW_g81__301_carry__6_CO_UNCONNECTED\(3),
CO(2) => \g81__301_carry__6_n_1\,
CO(1) => \g81__301_carry__6_n_2\,
CO(0) => \g81__301_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__301_carry__6_i_1_n_0\,
DI(1) => \g81__301_carry__6_i_2_n_0\,
DI(0) => \g81__301_carry__6_i_3_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__6_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \g81__301_carry__6_i_4_n_0\,
S(1) => \g81__301_carry__6_i_5_n_0\,
S(0) => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry__6_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_1_n_0\
);
\g81__301_carry__6_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_2_n_0\
);
\g81__301_carry__6_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_3_n_0\
);
\g81__301_carry__6_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_4_n_0\
);
\g81__301_carry__6_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_5_n_0\
);
\g81__301_carry__6_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_5\,
I1 => g84,
I2 => g83(2),
I3 => \g83__0_carry_n_5\,
O => \g81__301_carry_i_1_n_0\
);
\g81__301_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABEF"
)
port map (
I0 => \g81__261_carry_n_6\,
I1 => g84,
I2 => g83(1),
I3 => \g83__0_carry_n_6\,
O => \g81__301_carry_i_2_n_0\
);
\g81__301_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g81__261_carry_n_7\,
I1 => \g83__0_carry_n_7\,
O => \g81__301_carry_i_3_n_0\
);
\g81__301_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
I3 => \g81__261_carry_n_5\,
I4 => \g81__261_carry_n_4\,
I5 => \g81_carry__0_i_9_n_0\,
O => \g81__301_carry_i_4_n_0\
);
\g81__301_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DD22DD22D2DD2D2"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__261_carry_n_6\,
I2 => \g81__261_carry_n_5\,
I3 => \g83__0_carry_n_5\,
I4 => g83(2),
I5 => g84,
O => \g81__301_carry_i_5_n_0\
);
\g81__301_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22DD22DD2D22D2D"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
I2 => \g81__261_carry_n_6\,
I3 => \g83__0_carry_n_6\,
I4 => g83(1),
I5 => g84,
O => \g81__301_carry_i_6_n_0\
);
\g81__301_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
O => \g81__301_carry_i_7_n_0\
);
\g81__347_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__347_carry_n_0\,
CO(2) => \g81__347_carry_n_1\,
CO(1) => \g81__347_carry_n_2\,
CO(0) => \g81__347_carry_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \g81__347_carry_n_4\,
O(2) => \g81__347_carry_n_5\,
O(1) => \g81__347_carry_n_6\,
O(0) => \g81__347_carry_n_7\,
S(3) => \g81__347_carry_i_1_n_0\,
S(2) => \g81__347_carry_i_2_n_0\,
S(1) => \g81__347_carry_i_3_n_0\,
S(0) => \g81__347_carry_i_4_n_0\
);
\g81__347_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__347_carry_n_0\,
CO(3) => \NLW_g81__347_carry__0_CO_UNCONNECTED\(3),
CO(2) => \g81__347_carry__0_n_1\,
CO(1) => \g81__347_carry__0_n_2\,
CO(0) => \g81__347_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \g81__347_carry__0_n_4\,
O(2) => \g81__347_carry__0_n_5\,
O(1) => \g81__347_carry__0_n_6\,
O(0) => \g81__347_carry__0_n_7\,
S(3) => \g81__347_carry__0_i_1_n_0\,
S(2) => \g81__347_carry__0_i_2_n_0\,
S(1) => \g81__347_carry__0_i_3_n_0\,
S(0) => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_4\,
O => \g81__347_carry__0_i_1_n_0\
);
\g81__347_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_5\,
O => \g81__347_carry__0_i_2_n_0\
);
\g81__347_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_6\,
O => \g81__347_carry__0_i_3_n_0\
);
\g81__347_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_7\,
O => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_4\,
O => \g81__347_carry_i_1_n_0\
);
\g81__347_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_5\,
O => \g81__347_carry_i_2_n_0\
);
\g81__347_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__347_carry_i_3_n_0\
);
\g81__347_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__347_carry_i_4_n_0\
);
\g81__53_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__53_carry_n_0\,
CO(2) => \g81__53_carry_n_1\,
CO(1) => \g81__53_carry_n_2\,
CO(0) => \g81__53_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__53_carry_i_1_n_0\,
DI(1) => \g81__53_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__53_carry_n_4\,
O(2) => \g81__53_carry_n_5\,
O(1) => \g81__53_carry_n_6\,
O(0) => \NLW_g81__53_carry_O_UNCONNECTED\(0),
S(3) => \g81__53_carry_i_3_n_0\,
S(2) => \g81__53_carry_i_4_n_0\,
S(1) => \g81__53_carry_i_5_n_0\,
S(0) => \g81__53_carry_i_6_n_0\
);
\g81__53_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry_n_0\,
CO(3) => \g81__53_carry__0_n_0\,
CO(2) => \g81__53_carry__0_n_1\,
CO(1) => \g81__53_carry__0_n_2\,
CO(0) => \g81__53_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__53_carry__0_n_4\,
O(2) => \g81__53_carry__0_n_5\,
O(1) => \g81__53_carry__0_n_6\,
O(0) => \g81__53_carry__0_n_7\,
S(3) => \g81__53_carry__0_i_1_n_0\,
S(2) => \g81__53_carry__0_i_2_n_0\,
S(1) => \g81__53_carry__0_i_3_n_0\,
S(0) => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__53_carry__0_i_1_n_0\
);
\g81__53_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__53_carry__0_i_2_n_0\
);
\g81__53_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__53_carry__0_i_3_n_0\
);
\g81__53_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__0_n_0\,
CO(3) => \g81__53_carry__1_n_0\,
CO(2) => \g81__53_carry__1_n_1\,
CO(1) => \g81__53_carry__1_n_2\,
CO(0) => \g81__53_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__53_carry__1_n_4\,
O(2) => \g81__53_carry__1_n_5\,
O(1) => \g81__53_carry__1_n_6\,
O(0) => \g81__53_carry__1_n_7\,
S(3) => \g81__53_carry__1_i_1_n_0\,
S(2) => \g81__53_carry__1_i_2_n_0\,
S(1) => \g81__53_carry__1_i_3_n_0\,
S(0) => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__53_carry__1_i_1_n_0\
);
\g81__53_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_2_n_0\
);
\g81__53_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_3_n_0\
);
\g81__53_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__1_n_0\,
CO(3) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__53_carry__2_n_1\,
CO(1) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__53_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__53_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__53_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__53_carry__2_n_6\,
O(0) => \g81__53_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__53_carry__2_i_1_n_0\
);
\g81__53_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__53_carry_i_1_n_0\
);
\g81__53_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__53_carry_i_2_n_0\
);
\g81__53_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__53_carry_i_3_n_0\
);
\g81__53_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__53_carry_i_4_n_0\
);
\g81__53_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__53_carry_i_5_n_0\
);
\g81__53_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__53_carry_i_6_n_0\
);
\g81__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__92_carry_n_0\,
CO(2) => \g81__92_carry_n_1\,
CO(1) => \g81__92_carry_n_2\,
CO(0) => \g81__92_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__92_carry_i_1_n_0\,
DI(1) => \g81__92_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__92_carry_n_4\,
O(2) => \g81__92_carry_n_5\,
O(1) => \g81__92_carry_n_6\,
O(0) => \NLW_g81__92_carry_O_UNCONNECTED\(0),
S(3) => \g81__92_carry_i_3_n_0\,
S(2) => \g81__92_carry_i_4_n_0\,
S(1) => \g81__92_carry_i_5_n_0\,
S(0) => \g81__92_carry_i_6_n_0\
);
\g81__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry_n_0\,
CO(3) => \g81__92_carry__0_n_0\,
CO(2) => \g81__92_carry__0_n_1\,
CO(1) => \g81__92_carry__0_n_2\,
CO(0) => \g81__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__92_carry__0_n_4\,
O(2) => \g81__92_carry__0_n_5\,
O(1) => \g81__92_carry__0_n_6\,
O(0) => \g81__92_carry__0_n_7\,
S(3) => \g81__92_carry__0_i_1_n_0\,
S(2) => \g81__92_carry__0_i_2_n_0\,
S(1) => \g81__92_carry__0_i_3_n_0\,
S(0) => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__92_carry__0_i_1_n_0\
);
\g81__92_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__92_carry__0_i_2_n_0\
);
\g81__92_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__92_carry__0_i_3_n_0\
);
\g81__92_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__0_n_0\,
CO(3) => \g81__92_carry__1_n_0\,
CO(2) => \g81__92_carry__1_n_1\,
CO(1) => \g81__92_carry__1_n_2\,
CO(0) => \g81__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__92_carry__1_n_4\,
O(2) => \g81__92_carry__1_n_5\,
O(1) => \g81__92_carry__1_n_6\,
O(0) => \g81__92_carry__1_n_7\,
S(3) => \g81__92_carry__1_i_1_n_0\,
S(2) => \g81__92_carry__1_i_2_n_0\,
S(1) => \g81__92_carry__1_i_3_n_0\,
S(0) => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__92_carry__1_i_1_n_0\
);
\g81__92_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_2_n_0\
);
\g81__92_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_3_n_0\
);
\g81__92_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__1_n_0\,
CO(3) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__92_carry__2_n_1\,
CO(1) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__92_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__92_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__92_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__92_carry__2_n_6\,
O(0) => \g81__92_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__92_carry__2_i_1_n_0\
);
\g81__92_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__92_carry_i_1_n_0\
);
\g81__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__92_carry_i_2_n_0\
);
\g81__92_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__92_carry_i_3_n_0\
);
\g81__92_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__92_carry_i_4_n_0\
);
\g81__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__92_carry_i_5_n_0\
);
\g81__92_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__92_carry_i_6_n_0\
);
g81_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g81_carry_n_0,
CO(2) => g81_carry_n_1,
CO(1) => g81_carry_n_2,
CO(0) => g81_carry_n_3,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => g81_carry_i_2_n_0,
DI(1) => g81_carry_i_3_n_0,
DI(0) => '0',
O(3 downto 1) => NLW_g81_carry_O_UNCONNECTED(3 downto 1),
O(0) => g81_carry_n_7,
S(3) => g81_carry_i_4_n_0,
S(2) => g81_carry_i_5_n_0,
S(1) => g81_carry_i_6_n_0,
S(0) => g81_carry_i_7_n_0
);
\g81_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g81_carry_n_0,
CO(3) => \g81_carry__0_n_0\,
CO(2) => \g81_carry__0_n_1\,
CO(1) => \g81_carry__0_n_2\,
CO(0) => \g81_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81_carry__0_n_4\,
O(2) => \g81_carry__0_n_5\,
O(1) => \g81_carry__0_n_6\,
O(0) => \NLW_g81_carry__0_O_UNCONNECTED\(0),
S(3) => \g81_carry__0_i_5_n_0\,
S(2) => \g81_carry__0_i_6_n_0\,
S(1) => \g81_carry__0_i_7_n_0\,
S(0) => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
I4 => g83(7),
I5 => \g83__0_carry__0_n_4\,
O => \g81_carry__0_i_1_n_0\
);
\g81_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81_carry__0_i_10_n_0\
);
\g81_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81_carry__0_i_11_n_0\
);
\g81_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
O => \g81_carry__0_i_12_n_0\
);
\g81_carry__0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
O => \g81_carry__0_i_13_n_0\
);
\g81_carry__0_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
O => \g81_carry__0_i_14_n_0\
);
\g81_carry__0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81_carry__0_i_15_n_0\
);
\g81_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_10_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => g83(6),
I5 => \g83__0_carry__0_n_5\,
O => \g81_carry__0_i_2_n_0\
);
\g81_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
I4 => g83(5),
I5 => \g83__0_carry__0_n_6\,
O => \g81_carry__0_i_3_n_0\
);
\g81_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C33CC33CA5A55A5A"
)
port map (
I0 => g83(5),
I1 => \g83__0_carry__0_n_6\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g83__0_carry_n_4\,
I4 => g83(3),
I5 => g84,
O => \g81_carry__0_i_4_n_0\
);
\g81_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81_carry__0_i_5_n_0\
);
\g81_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81_carry__0_i_6_n_0\
);
\g81_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81_carry__0_i_7_n_0\
);
\g81_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81_carry__0_i_9_n_0\
);
\g81_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__0_n_0\,
CO(3) => \g81_carry__1_n_0\,
CO(2) => \g81_carry__1_n_1\,
CO(1) => \g81_carry__1_n_2\,
CO(0) => \g81_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81_carry__1_n_4\,
O(2) => \g81_carry__1_n_5\,
O(1) => \g81_carry__1_n_6\,
O(0) => \g81_carry__1_n_7\,
S(3) => \g81_carry__1_i_5_n_0\,
S(2) => \g81_carry__1_i_6_n_0\,
S(1) => \g81_carry__1_i_7_n_0\,
S(0) => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(7),
I1 => \g83__0_carry__0_n_4\,
I2 => g84,
I3 => g83(9),
I4 => \g83__0_carry__1_n_2\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_1_n_0\
);
\g81_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(6),
I1 => \g83__0_carry__0_n_5\,
I2 => g84,
I3 => g83(8),
I4 => \g83__0_carry__1_n_7\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_2_n_0\
);
\g81_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(5),
I2 => \g83__0_carry__0_n_6\,
I3 => \g81_carry__1_i_9_n_0\,
I4 => g83(9),
I5 => \g83__0_carry__1_n_2\,
O => \g81_carry__1_i_3_n_0\
);
\g81_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(4),
I2 => \g83__0_carry__0_n_7\,
I3 => \g81_carry__0_i_12_n_0\,
I4 => g83(8),
I5 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_4_n_0\
);
\g81_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_5_n_0\
);
\g81_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_6_n_0\
);
\g81_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_7_n_0\
);
\g81_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_4\,
I1 => g83(7),
I2 => g84,
O => \g81_carry__1_i_9_n_0\
);
\g81_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__1_n_0\,
CO(3) => \NLW_g81_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81_carry__2_n_1\,
CO(1) => \NLW_g81_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81_carry__2_n_6\,
O(0) => \g81_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81_carry__2_i_3_n_0\
);
\g81_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_1_n_0\
);
\g81_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_2_n_0\
);
\g81_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81_carry__2_i_3_n_0\
);
g81_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_1_n_0
);
g81_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => g81_carry_i_2_n_0
);
g81_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => g81_carry_i_3_n_0
);
g81_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => g81_carry_i_4_n_0
);
g81_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => g81_carry_i_5_n_0
);
g81_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_6_n_0
);
g81_carry_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => g81_carry_i_7_n_0
);
\g83__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g83__0_carry_n_0\,
CO(2) => \g83__0_carry_n_1\,
CO(1) => \g83__0_carry_n_2\,
CO(0) => \g83__0_carry_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry_i_1_n_0\,
DI(2) => \g83__0_carry_i_2_n_0\,
DI(1) => \g83__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \g83__0_carry_n_4\,
O(2) => \g83__0_carry_n_5\,
O(1) => \g83__0_carry_n_6\,
O(0) => \g83__0_carry_n_7\,
S(3) => \g83__0_carry_i_4_n_0\,
S(2) => \g83__0_carry_i_5_n_0\,
S(1) => \g83__0_carry_i_6_n_0\,
S(0) => \g83__0_carry_i_7_n_0\
);
\g83__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry_n_0\,
CO(3) => \g83__0_carry__0_n_0\,
CO(2) => \g83__0_carry__0_n_1\,
CO(1) => \g83__0_carry__0_n_2\,
CO(0) => \g83__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry__0_i_1_n_0\,
DI(2) => \g83__0_carry__0_i_2_n_0\,
DI(1) => \g83__0_carry__0_i_3_n_0\,
DI(0) => \g83__0_carry__0_i_4_n_0\,
O(3) => \g83__0_carry__0_n_4\,
O(2) => \g83__0_carry__0_n_5\,
O(1) => \g83__0_carry__0_n_6\,
O(0) => \g83__0_carry__0_n_7\,
S(3) => \g83__0_carry__0_i_5_n_0\,
S(2) => \g83__0_carry__0_i_6_n_0\,
S(1) => \g83__0_carry__0_i_7_n_0\,
S(0) => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
O => \g83__0_carry__0_i_1_n_0\
);
\g83__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
O => \g83__0_carry__0_i_2_n_0\
);
\g83__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
O => \g83__0_carry__0_i_3_n_0\
);
\g83__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
O => \g83__0_carry__0_i_4_n_0\
);
\g83__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry__0_i_1_n_0\,
I1 => rgb888(7),
I2 => rgb888(15),
I3 => rgb888(23),
O => \g83__0_carry__0_i_5_n_0\
);
\g83__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
I3 => \g83__0_carry__0_i_2_n_0\,
O => \g83__0_carry__0_i_6_n_0\
);
\g83__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
I3 => \g83__0_carry__0_i_3_n_0\,
O => \g83__0_carry__0_i_7_n_0\
);
\g83__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
I3 => \g83__0_carry__0_i_4_n_0\,
O => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry__0_n_0\,
CO(3 downto 2) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \g83__0_carry__1_n_2\,
CO(0) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_g83__0_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \g83__0_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(15),
I1 => rgb888(7),
I2 => rgb888(23),
O => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
O => \g83__0_carry_i_1_n_0\
);
\g83__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
O => \g83__0_carry_i_2_n_0\
);
\g83__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_3_n_0\
);
\g83__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
I3 => \g83__0_carry_i_1_n_0\,
O => \g83__0_carry_i_4_n_0\
);
\g83__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
I3 => \g83__0_carry_i_2_n_0\,
O => \g83__0_carry_i_5_n_0\
);
\g83__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
I3 => \g83__0_carry_i_3_n_0\,
O => \g83__0_carry_i_6_n_0\
);
\g83__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_7_n_0\
);
g84_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g84_carry_n_0,
CO(2) => g84_carry_n_1,
CO(1) => g84_carry_n_2,
CO(0) => g84_carry_n_3,
CYINIT => '1',
DI(3) => g84_carry_i_1_n_0,
DI(2) => g84_carry_i_2_n_0,
DI(1) => g84_carry_i_3_n_0,
DI(0) => g84_carry_i_4_n_0,
O(3 downto 0) => NLW_g84_carry_O_UNCONNECTED(3 downto 0),
S(3) => g84_carry_i_5_n_0,
S(2) => g84_carry_i_6_n_0,
S(1) => g84_carry_i_7_n_0,
S(0) => g84_carry_i_8_n_0
);
\g84_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g84_carry_n_0,
CO(3 downto 1) => \NLW_g84_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => g84,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \g84_carry__0_i_1_n_0\,
O(3 downto 0) => \NLW_g84_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \g84_carry__0_i_2_n_0\
);
\g84_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_1_n_0\
);
\g84_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_2_n_0\
);
g84_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_1_n_0
);
g84_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_2_n_0
);
g84_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_3_n_0
);
g84_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_4_n_0
);
g84_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_5_n_0
);
g84_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_6_n_0
);
g84_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_7_n_0
);
g84_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_8_n_0
);
\g8[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_7\,
O => g810_in(0)
);
\g8[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_6\,
O => g810_in(1)
);
\g8[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_5\,
O => g810_in(2)
);
\g8[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_4\,
O => g810_in(3)
);
\g8[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_7\,
O => g810_in(4)
);
\g8[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_6\,
O => g810_in(5)
);
\g8[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_5\,
O => g810_in(6)
);
\g8[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_4\,
O => g810_in(7)
);
\g8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(0),
Q => g8(0),
R => '0'
);
\g8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(1),
Q => g8(1),
R => '0'
);
\g8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(2),
Q => g8(2),
R => '0'
);
\g8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(3),
Q => g8(3),
R => '0'
);
\g8_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(4),
Q => g8(4),
R => '0'
);
\g8_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(5),
Q => g8(5),
R => '0'
);
\g8_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(6),
Q => g8(6),
R => '0'
);
\g8_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(7),
Q => g8(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_g8_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_g8_0_0 : entity is "system_rgb888_to_g8_0_0,rgb888_to_g8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_g8_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_g8_0_0 : entity is "rgb888_to_g8,Vivado 2016.4";
end system_rgb888_to_g8_0_0;
architecture STRUCTURE of system_rgb888_to_g8_0_0 is
begin
U0: entity work.system_rgb888_to_g8_0_0_rgb888_to_g8
port map (
clk => clk,
g8(7 downto 0) => g8(7 downto 0),
rgb888(23 downto 0) => rgb888(23 downto 0)
);
end STRUCTURE;
| mit | ccb78f0dae6a49fff2089d7953b7b8c7 | 0.49156 | 2.24905 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_1/sim/system_vga_buffer_1_1.vhd | 1 | 4,004 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_1_1 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_1_1;
ARCHITECTURE system_vga_buffer_1_1_arch OF system_vga_buffer_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 12
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_1_1_arch;
| mit | 5695b9e7dba273e108b6c35d3f60db85 | 0.697303 | 3.663312 | false | false | false | false |
loa-org/loa-hdl | modules/uart/hdl/uart.vhd | 1 | 2,621 | -------------------------------------------------------------------------------
-- Title : UART receiver/transmitter
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
entity uart is
generic (
RESET_IMPL : reset_type := none
);
port (
txd_p : out std_logic;
rxd_p : in std_logic;
din_p : in std_logic_vector(7 downto 0);
empty_p : in std_logic;
re_p : out std_logic;
dout_p : out std_logic_vector(7 downto 0);
we_p : out std_logic;
error_p : out std_logic;
full_p : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
clk : in std_logic);
end uart;
-------------------------------------------------------------------------------
architecture behavioural of uart is
signal busy : std_logic := '0';
signal clk_tx_en : std_logic := '0';
begin
-- 1/5 clock divider for generating the transmission clock
divider : process (clk)
variable counter : integer range 0 to 5 := 0;
begin
if rising_edge(clk) then
if clk_en = '1' then
counter := counter + 1;
if counter = 5 then
counter := 0;
clk_tx_en <= '1';
end if;
else
clk_tx_en <= '0';
end if;
end if;
end process;
-- Receiver
rx : uart_rx
generic map ( RESET_IMPL => RESET_IMPL )
port map (
rxd_p => rxd_p,
disable_p => busy,
data_p => dout_p,
we_p => we_p,
error_p => error_p,
full_p => full_p,
clk_rx_en => clk_en,
reset => reset,
clk => clk);
-- Transmitter
tx : uart_tx
generic map ( RESET_IMPL => RESET_IMPL )
port map (
txd_p => txd_p,
busy_p => busy,
data_p => din_p,
empty_p => empty_p,
re_p => re_p,
clk_tx_en => clk_tx_en,
reset => reset,
clk => clk);
end behavioural;
| bsd-3-clause | 4b6b3eccfad7ad12f7bfff116608db2d | 0.38306 | 4.213826 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl | 3 | 10,113 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
active : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_0_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal \data_pair[15]_i_1_n_0\ : STD_LOGIC;
signal \data_pair[7]_i_1_n_0\ : STD_LOGIC;
signal \data_pair_reg_n_0_[0]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[10]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[11]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[12]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[13]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[14]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[15]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[1]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[2]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[3]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[4]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[5]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[6]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[7]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[8]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[9]\ : STD_LOGIC;
signal rgb_regn_0_0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => \data_pair[7]_i_1_n_0\,
Q => cycle,
R => '0'
);
\data_pair[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle,
I1 => active,
O => \data_pair[15]_i_1_n_0\
);
\data_pair[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => active,
I1 => cycle,
O => \data_pair[7]_i_1_n_0\
);
\data_pair_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[0]\,
R => '0'
);
\data_pair_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[10]\,
R => '0'
);
\data_pair_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[11]\,
R => '0'
);
\data_pair_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[12]\,
R => '0'
);
\data_pair_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[13]\,
R => '0'
);
\data_pair_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[14]\,
R => '0'
);
\data_pair_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[15]\,
R => '0'
);
\data_pair_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[1]\,
R => '0'
);
\data_pair_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[2]\,
R => '0'
);
\data_pair_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[3]\,
R => '0'
);
\data_pair_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[4]\,
R => '0'
);
\data_pair_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[5]\,
R => '0'
);
\data_pair_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[6]\,
R => '0'
);
\data_pair_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[7]\,
R => '0'
);
\data_pair_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[8]\,
R => '0'
);
\data_pair_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[9]\,
R => '0'
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[0]\,
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[10]\,
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[11]\,
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[12]\,
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[13]\,
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[14]\,
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[15]\,
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[1]\,
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[2]\,
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[3]\,
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[4]\,
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[5]\,
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[6]\,
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[7]\,
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[8]\,
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[9]\,
Q => rgb(9),
R => '0'
);
rgb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_x2,
O => rgb_regn_0_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_0_0;
architecture STRUCTURE of system_ov7670_vga_0_0 is
begin
U0: entity work.system_ov7670_vga_0_0_ov7670_vga
port map (
active => active,
clk_x2 => clk_x2,
data(7 downto 0) => data(7 downto 0),
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | 37a3cf7a2e5a5f4521d14893948bbf6a | 0.506279 | 2.78595 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 1 | 7,616 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz : entity is "system_clk_wiz_0_0_clk_wiz";
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 36.500000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
| mit | ed17a56b66d06f2d27c0e94bb987a7d0 | 0.637999 | 3.279931 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/goertzel_control_unit.vhd | 2 | 6,316 | -------------------------------------------------------------------------------
-- Title : Goertzel Pipelined Control Unit
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Control Unit (a state machine) that controls the muxes and the
-- pipeline of the pipelined goertzel algorithm.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
entity goertzel_control_unit is
generic (
SAMPLES : positive := 250;
FREQUENCIES : positive;
CHANNELS : positive := 12);
port (
start_p : in std_logic; -- start the FSM when new ADC values arrived
ready_p : out std_logic := '0'; -- inform STM about new data
bram_addr_p : out std_logic_vector(7 downto 0) := (others => '0'); -- address where to read/write
bram_we_p : out std_logic; -- write to the Block RAM
mux_delay1_p : out std_logic; -- select delay1 from BRAM
mux_delay2_p : out std_logic; -- select delay2 from BRAM
mux_coef_p : out natural range FREQUENCIES-1 downto 0;
mux_input_p : out natural range CHANNELS-1 downto 0;
clk : in std_logic);
end entity goertzel_control_unit;
architecture behavourial of goertzel_control_unit is
type cu_state_type is (
IDLE, -- do nothing, wait for start signal
READ1, -- reads data from BRAM
CALC1, -- first RTL
CALC2, -- second RTL
WRITE1 -- write the result back to BRAM
);
type cu_type is record
state : cu_state_type;
ready : std_logic;
mux_coef : natural range FREQUENCIES-1 downto 0;
mux_input : natural range CHANNELS-1 downto 0;
bram_addr : unsigned(7 downto 0);
bram_we : std_logic;
samples : natural range SAMPLES-1 downto 0;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : cu_type := (state => IDLE,
ready => '0',
mux_coef => 0,
mux_input => 0,
bram_addr => (others => '0'),
bram_we => '0',
samples => 0);
----------------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------------
-- None here, if any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
ready_p <= r.ready;
mux_coef_p <= r.mux_coef;
mux_input_p <= r.mux_input;
bram_we_p <= r.bram_we;
bram_addr_p <= std_logic_vector(r.bram_addr);
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(r, r.bram_addr, r.mux_coef, r.mux_input, r.state,
start_p)
variable v : cu_type;
begin
v := r;
case r.state is
when IDLE =>
v.ready := '0';
if (start_p = '1') then
v.state := READ1;
-- select coef and input
v.bram_addr := (others => '0');
v.mux_coef := 0;
v.mux_input := 0;
-- bram_addr
end if;
when READ1 =>
v.state := CALC1;
when CALC1 =>
v.state := CALC2;
when CALC2 =>
v.state := WRITE1;
v.bram_we := '1';
when WRITE1 =>
v.state := READ1;
v.bram_we := '0';
-- Three nested loops:
-- inner: channel
-- frequency
-- outer: sample
v.bram_addr := r.bram_addr + 1;
if r.mux_input = CHANNELS-1 then
v.mux_input := 0;
if r.mux_coef = FREQUENCIES-1 then
v.mux_coef := 0;
v.bram_addr := (others => '0');
v.state := IDLE;
if r.samples = SAMPLES-1 then
v.samples := 0;
v.ready := '1';
else
v.samples := r.samples + 1;
end if;
else
v.mux_coef := r.mux_coef + 1;
end if;
else
v.mux_input := r.mux_input + 1;
end if;
end case;
rin <= v;
end process comb_proc;
-- For the first sample ignore the value in the BRAM and overwrite it
-- with zero. No special erase cycle is needed. At the end of the first
-- sample the old data is overwritten in the BRAM.
mux_delay1_p <= '0' when (r.samples = 0) else '1';
mux_delay2_p <= '0' when (r.samples = 0) else '1';
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- none
end architecture behavourial;
| bsd-3-clause | a2aaca2fc2c71114e2b80579885f1fe9 | 0.382996 | 4.938233 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_buffer/vga_buffer.srcs/sources_1/new/vga_buffer.vhd | 6 | 1,583 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0)
);
end vga_buffer;
architecture Behavioral of vga_buffer is
type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0);
signal data : DATA_BUFFER;
signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0);
signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0);
begin
process(clk_w)
begin
if rising_edge(clk_w) then
if wen = '1' then
c_addr_w(9 downto 0) <= x_addr_w;
c_addr_w(19 downto 10) <= y_addr_w;
addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0);
data(to_integer(unsigned(addr_w))) <= data_w;
end if;
end if;
end process;
process(clk_r)
begin
if rising_edge(clk_r) then
c_addr_r(9 downto 0) <= x_addr_r;
c_addr_r(19 downto 10) <= y_addr_r;
addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0);
data_r <= data(to_integer(unsigned(addr_r)));
end if;
end process;
end Behavioral;
| mit | bc4afc4d0fbf408a6fcdb03aa4a6598a | 0.550221 | 3.122288 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/div_pipe-rtl.vhdl | 1 | 1,612 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of div_pipe is
begin
div : entity work.div_pipe_inferred(rtl)
generic map (
stages => stages,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
dbz => dbz,
overflow => overflow,
result => result
);
end;
| apache-2.0 | d188b0472dd971722523ee39544e8b9f | 0.476427 | 5.11746 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 5,732 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon May 22 02:50:48 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
resend : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
signal Net : STD_LOGIC;
signal clk_100_1 : STD_LOGIC;
signal resend_1 : STD_LOGIC;
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_pll_0_clk_50 : STD_LOGIC;
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_vga_pll_0_clk_12_5_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
resend_1 <= resend;
vdd: component system_xlconstant_0_0
port map (
dout(0) => vdd_dout(0)
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => vga_pll_0_clk_25,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => NLW_vga_pll_0_clk_12_5_UNCONNECTED,
clk_25 => vga_pll_0_clk_25,
clk_50 => vga_pll_0_clk_50,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk => vga_pll_0_clk_25,
hsync => vga_sync_0_hsync,
rst => vdd_dout(0),
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_0_active,
clk => vga_pll_0_clk_25,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_50,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_0_hsync,
rgb888(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
vsync => vga_sync_0_vsync
);
end STRUCTURE;
| mit | 68de810cdd7431656ebf38928cd36656 | 0.620726 | 3.004193 | false | false | false | false |
loa-org/loa-hdl | modules/uart/tb/uart_tx_tb.vhd | 2 | 2,517 | -------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_tx_tb is
end entity uart_tx_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tx_tb is
-- component ports
signal txd : std_logic;
signal busy : std_logic;
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_tx
port map (
txd_p => txd,
busy_p => busy,
data_p => data,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
| bsd-3-clause | 1f9f635edce46bc0a645f42b7ac7fc4a | 0.397298 | 4.669759 | false | false | false | false |
loa-org/loa-hdl | modules/uss_tx/hdl/uss_tx_module.vhd | 1 | 6,529 | -------------------------------------------------------------------------------
-- Title : Transmitter for ultrasonic beacons
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Register description
--
-- offset | Meaning
-- -------+---------
-- 0x00 | Fractional Clock Divider MUL value
-- 0x01 | Fractional Clock Divider DIV value
-- 0x02 | Bit pattern 0
-- 0x03 | Bit pattern 1
-- 0x04 | Bit pattern 2
-- 0x05 | Bit pattern 3
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012, 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all; -- for half_bridge_type
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity uss_tx_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF# -- Base address at the internal data bus
);
port (
-- Ports to the ultrasonic transmitters
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
-- Output of the clock enable signal
clk_uss_enable_p : out std_logic;
-- signals to and from the internal parallel bus
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end uss_tx_module;
-------------------------------------------------------------------------------
architecture behavioral of uss_tx_module is
-- types for states
-- none
-- record for internal states
-- none
-----------------------------------------------------------------------------
-- internal signals
-----------------------------------------------------------------------------
-- access to the internal register
constant REG_ADDR_BIT : natural := 3; -- 2**3 = 8 registers for mul and div value
constant BITPATTERN_WIDTH : positive := 64; -- Width of the bit pattern to send
signal reg_o : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal reg_i : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal clk_mul : std_logic_vector(15 downto 0);
signal clk_div : std_logic_vector(15 downto 0);
signal pattern : std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
signal bitstream : std_logic;
signal clk_bit : std_logic;
signal modulation : std_logic_vector(2 downto 0); -- Modulation of the US carrier
signal clk_uss_enable : std_logic := '0';
signal clk_uss : std_logic := '0'; -- Clock signal with 50% duty cycle
signal clk_uss_n : std_logic;
signal uss_tx_high : std_logic; -- With deadtime, for H-bridges
signal uss_tx_low : std_logic; -- With deadtime, for H-bridges
begin -- behavioral
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- register for access to and from STM
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT
)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
reset => '0',
clk => clk
);
-- Serialise the bit pattern to a bit stream
serialiser : entity work.serialiser
generic map (
BITPATTERN_WIDTH => BITPATTERN_WIDTH)
port map (
pattern_in_p => pattern,
bitstream_out_p => bitstream,
clk_bit => clk_bit,
clk => clk);
-- Bit clock (2000 bps)
-- 50 MHz / 25000 = 2000
clock_divider : entity work.clock_divider
generic map (
DIV => 25000)
port map (
clk_out_p => clk_bit,
clk => clk);
-- clock generation of clk_uss_tx (carrier)
fractional_clock_divider_variable_1 : fractional_clock_divider_variable
generic map (
WIDTH => 16)
port map (
div => clk_div,
mul => clk_mul,
clk_out_p => clk_uss_enable,
clk => clk);
-- generate a signal with a 50% duty-cycle from the enable signal
process (clk, clk_uss_enable)
begin
if rising_edge(clk) then
if clk_uss_enable = '1' then
clk_uss <= not clk_uss;
end if;
end if;
end process;
-- generate clocks with deadtime
clk_uss_n <= not clk_uss;
-- output to the H-bridges
deadtime_on : deadtime
generic map (
T_DEAD => 250) -- 5000ns
port map (
in_p => clk_uss_n,
out_p => uss_tx_low,
clk => clk);
deadtime_off : deadtime
generic map (
T_DEAD => 250) -- 5000ns
port map (
in_p => clk_uss,
out_p => uss_tx_high,
clk => clk);
-----------------------------------------------------------------------------
-- Mapping of signals between components and module ports
-----------------------------------------------------------------------------
clk_mul <= reg_o(0);
clk_div <= reg_o(1);
pattern(15 downto 0) <= reg_o(2);
pattern(31 downto 16) <= reg_o(3);
pattern(47 downto 32) <= reg_o(4);
pattern(63 downto 48) <= reg_o(5);
-- enable readback of configurations
reg_i <= reg_o;
clk_uss_enable_p <= clk_uss_enable;
-----------------------------------------------------------------------------
-- Drive Ultrasonic transmitters
-----------------------------------------------------------------------------
modulation(0) <= bitstream;
modulation(1) <= bitstream;
modulation(2) <= bitstream;
uss_tx0_out_p.high <= uss_tx_high and modulation(0);
uss_tx1_out_p.high <= uss_tx_high and modulation(1);
uss_tx2_out_p.high <= uss_tx_high and modulation(2);
uss_tx0_out_p.low <= uss_tx_low and modulation(0);
uss_tx1_out_p.low <= uss_tx_low and modulation(1);
uss_tx2_out_p.low <= uss_tx_low and modulation(2);
end behavioral;
| bsd-3-clause | d62d571b546dd5de3b46fc7717d974af | 0.470516 | 4.161249 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl | 1 | 70,096 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:42:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_0_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_0_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_0_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_0_0 : entity is "system_vga_sync_ref_0_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_0_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_0_0;
architecture STRUCTURE of system_vga_sync_ref_0_0 is
begin
U0: entity work.system_vga_sync_ref_0_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 9cdac5480815463bbf63bd6f75cec70e | 0.486148 | 2.524799 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 3,084 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:54:53 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync_0 : in STD_LOGIC;
hsync_1 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
ready : out STD_LOGIC_VECTOR ( 0 to 0 );
reset : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
ready : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc_0 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync_0 : in STD_LOGIC;
vsync_0 : in STD_LOGIC;
reset : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_1 : inout STD_LOGIC;
vsync_1 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync_1 : in STD_LOGIC;
xclk_1 : out STD_LOGIC;
xclk_0 : out STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
data_0(7 downto 0) => data_0(7 downto 0),
data_1(7 downto 0) => data_1(7 downto 0),
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync_0 => hsync_0,
hsync_1 => hsync_1,
pclk_0 => pclk_0,
pclk_1 => pclk_1,
ready(0) => ready(0),
reset => reset,
sioc_0 => sioc_0,
sioc_1 => sioc_1,
siod_0 => siod_0,
siod_1 => siod_1,
vsync_0 => vsync_0,
vsync_1 => vsync_1,
xclk_0 => xclk_0,
xclk_1 => xclk_1
);
end STRUCTURE;
| mit | 63e8eafcbf2dc9845039419b019ae30d | 0.558042 | 3.209157 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/hdl/affine_block.vhd | 2 | 7,875 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 20 13:51:56 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target affine_block.bd
--Design : affine_block
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block is
port (
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of affine_block : entity is "affine_block,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=affine_block,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=10,numReposBlks=10,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of affine_block : entity is "affine_block.hwdef";
end affine_block;
architecture STRUCTURE of affine_block is
component affine_block_uint_to_ieee754_fp_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_uint_to_ieee754_fp_0_0;
component affine_block_uint_to_ieee754_fp_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_uint_to_ieee754_fp_0_1;
component affine_block_ieee754_fp_multiplier_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_0_0;
component affine_block_ieee754_fp_multiplier_1_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_0;
component affine_block_ieee754_fp_multiplier_1_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_1;
component affine_block_ieee754_fp_multiplier_1_2 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_2;
component affine_block_ieee754_fp_adder_subtractor_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_adder_subtractor_0_0;
component affine_block_ieee754_fp_adder_subtractor_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_adder_subtractor_0_1;
component affine_block_ieee754_fp_to_uint_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block_ieee754_fp_to_uint_0_0;
component affine_block_ieee754_fp_to_uint_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block_ieee754_fp_to_uint_0_1;
signal ieee754_fp_adder_subtractor_0_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_adder_subtractor_1_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_0_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_1_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_2_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_3_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_to_uint_0_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal ieee754_fp_to_uint_1_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal uint_to_ieee754_fp_0_y : STD_LOGIC_VECTOR ( 31 downto 0 );
signal uint_to_ieee754_fp_1_y : STD_LOGIC_VECTOR ( 31 downto 0 );
signal x_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal x_2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal y_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_4 : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
x_1(9 downto 0) <= x_in(9 downto 0);
x_2(9 downto 0) <= y_in(9 downto 0);
x_out(9 downto 0) <= ieee754_fp_to_uint_0_y(9 downto 0);
y_1(31 downto 0) <= a00(31 downto 0);
y_2(31 downto 0) <= a01(31 downto 0);
y_3(31 downto 0) <= a10(31 downto 0);
y_4(31 downto 0) <= a11(31 downto 0);
y_out(9 downto 0) <= ieee754_fp_to_uint_1_y(9 downto 0);
ieee754_fp_adder_subtractor_0: component affine_block_ieee754_fp_adder_subtractor_0_0
port map (
x(31 downto 0) => ieee754_fp_multiplier_0_z(31 downto 0),
y(31 downto 0) => ieee754_fp_multiplier_1_z(31 downto 0),
z(31 downto 0) => ieee754_fp_adder_subtractor_0_z(31 downto 0)
);
ieee754_fp_adder_subtractor_1: component affine_block_ieee754_fp_adder_subtractor_0_1
port map (
x(31 downto 0) => ieee754_fp_multiplier_2_z(31 downto 0),
y(31 downto 0) => ieee754_fp_multiplier_3_z(31 downto 0),
z(31 downto 0) => ieee754_fp_adder_subtractor_1_z(31 downto 0)
);
ieee754_fp_multiplier_0: component affine_block_ieee754_fp_multiplier_0_0
port map (
x(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0),
y(31 downto 0) => y_1(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_0_z(31 downto 0)
);
ieee754_fp_multiplier_1: component affine_block_ieee754_fp_multiplier_1_0
port map (
x(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0),
y(31 downto 0) => y_2(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_1_z(31 downto 0)
);
ieee754_fp_multiplier_2: component affine_block_ieee754_fp_multiplier_1_1
port map (
x(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0),
y(31 downto 0) => y_3(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_2_z(31 downto 0)
);
ieee754_fp_multiplier_3: component affine_block_ieee754_fp_multiplier_1_2
port map (
x(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0),
y(31 downto 0) => y_4(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_3_z(31 downto 0)
);
ieee754_fp_to_uint_0: component affine_block_ieee754_fp_to_uint_0_0
port map (
x(31 downto 0) => ieee754_fp_adder_subtractor_0_z(31 downto 0),
y(9 downto 0) => ieee754_fp_to_uint_0_y(9 downto 0)
);
ieee754_fp_to_uint_1: component affine_block_ieee754_fp_to_uint_0_1
port map (
x(31 downto 0) => ieee754_fp_adder_subtractor_1_z(31 downto 0),
y(9 downto 0) => ieee754_fp_to_uint_1_y(9 downto 0)
);
uint_to_ieee754_fp_0: component affine_block_uint_to_ieee754_fp_0_0
port map (
x(9 downto 0) => x_1(9 downto 0),
y(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0)
);
uint_to_ieee754_fp_1: component affine_block_uint_to_ieee754_fp_0_1
port map (
x(9 downto 0) => x_2(9 downto 0),
y(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0)
);
end STRUCTURE;
| mit | 86277be9bb294e82a6f251d3209ef712 | 0.645206 | 2.93953 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_rgb888_mux_2_0_0/system_rgb888_mux_2_0_0_sim_netlist.vhdl | 1 | 13,017 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:25:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_mux_2_0_0 -prefix
-- system_rgb888_mux_2_0_0_ system_rgb888_mux_2_0_0_sim_netlist.vhdl
-- Design : system_rgb888_mux_2_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_mux_2_0_0_rgb888_mux_2 is
port (
rgb888 : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
sel : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_rgb888_mux_2_0_0_rgb888_mux_2;
architecture STRUCTURE of system_rgb888_mux_2_0_0_rgb888_mux_2 is
signal p_0_in : STD_LOGIC_VECTOR ( 23 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb888[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb888[10]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb888[11]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb888[12]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb888[13]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb888[14]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb888[15]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb888[16]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb888[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb888[18]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb888[19]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb888[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb888[20]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb888[21]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb888[22]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rgb888[23]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rgb888[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb888[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb888[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb888[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb888[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb888[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb888[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb888[9]_i_1\ : label is "soft_lutpair4";
begin
\rgb888[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(0),
I1 => rgb888_0(0),
I2 => sel,
O => p_0_in(0)
);
\rgb888[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(10),
I1 => rgb888_0(10),
I2 => sel,
O => p_0_in(10)
);
\rgb888[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(11),
I1 => rgb888_0(11),
I2 => sel,
O => p_0_in(11)
);
\rgb888[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(12),
I1 => rgb888_0(12),
I2 => sel,
O => p_0_in(12)
);
\rgb888[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(13),
I1 => rgb888_0(13),
I2 => sel,
O => p_0_in(13)
);
\rgb888[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(14),
I1 => rgb888_0(14),
I2 => sel,
O => p_0_in(14)
);
\rgb888[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(15),
I1 => rgb888_0(15),
I2 => sel,
O => p_0_in(15)
);
\rgb888[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(16),
I1 => rgb888_0(16),
I2 => sel,
O => p_0_in(16)
);
\rgb888[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(17),
I1 => rgb888_0(17),
I2 => sel,
O => p_0_in(17)
);
\rgb888[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(18),
I1 => rgb888_0(18),
I2 => sel,
O => p_0_in(18)
);
\rgb888[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(19),
I1 => rgb888_0(19),
I2 => sel,
O => p_0_in(19)
);
\rgb888[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(1),
I1 => rgb888_0(1),
I2 => sel,
O => p_0_in(1)
);
\rgb888[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(20),
I1 => rgb888_0(20),
I2 => sel,
O => p_0_in(20)
);
\rgb888[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(21),
I1 => rgb888_0(21),
I2 => sel,
O => p_0_in(21)
);
\rgb888[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(22),
I1 => rgb888_0(22),
I2 => sel,
O => p_0_in(22)
);
\rgb888[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(23),
I1 => rgb888_0(23),
I2 => sel,
O => p_0_in(23)
);
\rgb888[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(2),
I1 => rgb888_0(2),
I2 => sel,
O => p_0_in(2)
);
\rgb888[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(3),
I1 => rgb888_0(3),
I2 => sel,
O => p_0_in(3)
);
\rgb888[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(4),
I1 => rgb888_0(4),
I2 => sel,
O => p_0_in(4)
);
\rgb888[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(5),
I1 => rgb888_0(5),
I2 => sel,
O => p_0_in(5)
);
\rgb888[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(6),
I1 => rgb888_0(6),
I2 => sel,
O => p_0_in(6)
);
\rgb888[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(7),
I1 => rgb888_0(7),
I2 => sel,
O => p_0_in(7)
);
\rgb888[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(8),
I1 => rgb888_0(8),
I2 => sel,
O => p_0_in(8)
);
\rgb888[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb888_1(9),
I1 => rgb888_0(9),
I2 => sel,
O => p_0_in(9)
);
\rgb888_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(0),
Q => rgb888(0),
R => '0'
);
\rgb888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(10),
Q => rgb888(10),
R => '0'
);
\rgb888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(11),
Q => rgb888(11),
R => '0'
);
\rgb888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(12),
Q => rgb888(12),
R => '0'
);
\rgb888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(13),
Q => rgb888(13),
R => '0'
);
\rgb888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(14),
Q => rgb888(14),
R => '0'
);
\rgb888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(15),
Q => rgb888(15),
R => '0'
);
\rgb888_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(16),
Q => rgb888(16),
R => '0'
);
\rgb888_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(17),
Q => rgb888(17),
R => '0'
);
\rgb888_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(18),
Q => rgb888(18),
R => '0'
);
\rgb888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(19),
Q => rgb888(19),
R => '0'
);
\rgb888_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(1),
Q => rgb888(1),
R => '0'
);
\rgb888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(20),
Q => rgb888(20),
R => '0'
);
\rgb888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(21),
Q => rgb888(21),
R => '0'
);
\rgb888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(22),
Q => rgb888(22),
R => '0'
);
\rgb888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(23),
Q => rgb888(23),
R => '0'
);
\rgb888_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(2),
Q => rgb888(2),
R => '0'
);
\rgb888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(3),
Q => rgb888(3),
R => '0'
);
\rgb888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(4),
Q => rgb888(4),
R => '0'
);
\rgb888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(5),
Q => rgb888(5),
R => '0'
);
\rgb888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(6),
Q => rgb888(6),
R => '0'
);
\rgb888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(7),
Q => rgb888(7),
R => '0'
);
\rgb888_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(8),
Q => rgb888(8),
R => '0'
);
\rgb888_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => p_0_in(9),
Q => rgb888(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_mux_2_0_0 is
port (
clk : in STD_LOGIC;
sel : in STD_LOGIC;
rgb888_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_mux_2_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_mux_2_0_0 : entity is "system_rgb888_mux_2_0_0,rgb888_mux_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_mux_2_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_mux_2_0_0 : entity is "rgb888_mux_2,Vivado 2016.4";
end system_rgb888_mux_2_0_0;
architecture STRUCTURE of system_rgb888_mux_2_0_0 is
begin
U0: entity work.system_rgb888_mux_2_0_0_rgb888_mux_2
port map (
clk => clk,
rgb888(23 downto 0) => rgb888(23 downto 0),
rgb888_0(23 downto 0) => rgb888_0(23 downto 0),
rgb888_1(23 downto 0) => rgb888_1(23 downto 0),
sel => sel
);
end STRUCTURE;
| mit | 2a4d36da0b4fdd05ff90cce67d7e1099 | 0.50242 | 2.854605 | false | false | false | false |
loa-org/loa-hdl | template/template_fsm.vhd | 1 | 2,635 | -------------------------------------------------------------------------------
-- Title : xyz
-- Project : LOA Project - HDL Part
-------------------------------------------------------------------------------
-- File : template_fsm.vhd
-- Author :
-- Company :
-- Created : 2015-mm-dd
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a Template for FSMs in 2-process description style.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.reset_pkg.all;
entity xyz is
generic (
RESET_IMPL : reset_type := none);
port (
reset : in std_logic_1164;
clk : in std_logic);
end entity xyz;
-------------------------------------------------------------------------------
architecture behavioural of xyz is
type xyz_state_type is (IDLE, START);
type xyz_type is record
state : xyz_state_type;
somesignal : std_logic;
end record;
constant xyz_rx_type_initial : xyz_type := (
state => IDLE,
somesignal => '0');
signal r, rin : xyz_type := xyz_type_initial;
begin
bus_o.data <= r.dout;
-----------------------------------------------------------------------------
-- Combinatorial part of FSM
-----------------------------------------------------------------------------
comb_proc : process(r, reset)
variable v : xyz_rx_type;
begin
v := r;
case r.state is
when IDLE =>
end case;
-- sync reset
if RESET_IMPL = sync then
if reset = '1' then
v := xyz_type_initial;
end if;
end if;
rin <= v;
end process comb_proc;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
reset_async : if RESET_IMPL = async generate
seq_proc : process(clk, reset)
begin
if reset = '1' then
r <= xyz_type_initial; -- async reset
elsif rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
end generate reset_async;
reset_sync : if not (RESET_IMPL = async) generate
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
end generate reset_sync;
end architecture xyz;
| bsd-3-clause | de3cabdf51eaacfe7ed34c43e7e0f089 | 0.41556 | 4.69697 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/synth/system_vga_pll_0_0.vhd | 3 | 3,802 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_pll:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_pll_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END system_vga_pll_0_0;
ARCHITECTURE system_vga_pll_0_0_arch OF system_vga_pll_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_pll_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_pll IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END COMPONENT vga_pll;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_pll_0_0_arch: ARCHITECTURE IS "vga_pll,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_pll_0_0_arch : ARCHITECTURE IS "system_vga_pll_0_0,vga_pll,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_pll_0_0_arch: ARCHITECTURE IS "system_vga_pll_0_0,vga_pll,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_pll,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : vga_pll
PORT MAP (
clk_100 => clk_100,
clk_50 => clk_50,
clk_25 => clk_25,
clk_12_5 => clk_12_5,
clk_6_25 => clk_6_25
);
END system_vga_pll_0_0_arch;
| mit | ccebaf8408dfd35427c1d109c5a70d1d | 0.725145 | 3.712891 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/xbip_utils_v3_0_vh_rfs.vhd | 13 | 163,693 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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`protect end_protected
| mit | e1b5f5e8abacbb928e36c41fb2d07b95 | 0.953969 | 1.814115 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_axi_dma_0_0/synth/system_axi_dma_0_0.vhd | 1 | 31,671 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_12;
USE axi_dma_v7_1_12.axi_dma;
ENTITY system_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_axi_dma_0_0;
ARCHITECTURE system_axi_dma_0_0_arch OF system_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_dma_0_0_arch : ARCHITECTURE IS "system_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_dma_0_0_arch: ARCHITECTURE IS "system_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=12,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=1,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_A" &
"XIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END system_axi_dma_0_0_arch;
| mit | 7d427c13e5092c6d24b38b18fdb76537 | 0.681886 | 2.755917 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_sim_netlist.vhdl | 1 | 5,435 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 15:55:33 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_1_0 -prefix
-- system_clk_wiz_1_0_ system_clk_wiz_1_0_sim_netlist.vhdl
-- Design : system_clk_wiz_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
signal clk_in1_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_1_0 : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_1_0,
O => clkfbout_buf_system_clk_wiz_1_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_1_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_1_0,
O => clk_out1
);
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 10,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 5,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_1_0,
CLKFBOUT => clkfbout_system_clk_wiz_1_0,
CLKIN1 => clk_in1_system_clk_wiz_1_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKOUT0 => clk_out1_system_clk_wiz_1_0,
CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_plle2_adv_inst_LOCKED_UNCONNECTED,
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0 is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_1_0 : entity is true;
end system_clk_wiz_1_0;
architecture STRUCTURE of system_clk_wiz_1_0 is
begin
inst: entity work.system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;
| mit | 86ea9436f0dd127605c8fff99646738c | 0.632015 | 3.264264 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_sim_netlist.vhdl | 1 | 158,108 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_g8_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0_rgb888_to_g8 is
port (
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rgb888_to_g8_0_0_rgb888_to_g8 : entity is "rgb888_to_g8";
end system_rgb888_to_g8_0_0_rgb888_to_g8;
architecture STRUCTURE of system_rgb888_to_g8_0_0_rgb888_to_g8 is
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal g810_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \g81__120_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_1\ : STD_LOGIC;
signal \g81__120_carry__0_n_2\ : STD_LOGIC;
signal \g81__120_carry__0_n_3\ : STD_LOGIC;
signal \g81__120_carry__0_n_4\ : STD_LOGIC;
signal \g81__120_carry__0_n_5\ : STD_LOGIC;
signal \g81__120_carry__0_n_6\ : STD_LOGIC;
signal \g81__120_carry__0_n_7\ : STD_LOGIC;
signal \g81__120_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_1\ : STD_LOGIC;
signal \g81__120_carry__1_n_2\ : STD_LOGIC;
signal \g81__120_carry__1_n_3\ : STD_LOGIC;
signal \g81__120_carry__1_n_4\ : STD_LOGIC;
signal \g81__120_carry__1_n_5\ : STD_LOGIC;
signal \g81__120_carry__1_n_6\ : STD_LOGIC;
signal \g81__120_carry__1_n_7\ : STD_LOGIC;
signal \g81__120_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_n_1\ : STD_LOGIC;
signal \g81__120_carry__2_n_3\ : STD_LOGIC;
signal \g81__120_carry__2_n_6\ : STD_LOGIC;
signal \g81__120_carry__2_n_7\ : STD_LOGIC;
signal \g81__120_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_1\ : STD_LOGIC;
signal \g81__120_carry_n_2\ : STD_LOGIC;
signal \g81__120_carry_n_3\ : STD_LOGIC;
signal \g81__120_carry_n_4\ : STD_LOGIC;
signal \g81__120_carry_n_5\ : STD_LOGIC;
signal \g81__120_carry_n_6\ : STD_LOGIC;
signal \g81__149_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_1\ : STD_LOGIC;
signal \g81__149_carry__0_n_2\ : STD_LOGIC;
signal \g81__149_carry__0_n_3\ : STD_LOGIC;
signal \g81__149_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_1\ : STD_LOGIC;
signal \g81__149_carry__1_n_2\ : STD_LOGIC;
signal \g81__149_carry__1_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_1\ : STD_LOGIC;
signal \g81__149_carry__2_n_2\ : STD_LOGIC;
signal \g81__149_carry__2_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_n_4\ : STD_LOGIC;
signal \g81__149_carry__2_n_5\ : STD_LOGIC;
signal \g81__149_carry__2_n_6\ : STD_LOGIC;
signal \g81__149_carry__2_n_7\ : STD_LOGIC;
signal \g81__149_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_1\ : STD_LOGIC;
signal \g81__149_carry__3_n_2\ : STD_LOGIC;
signal \g81__149_carry__3_n_3\ : STD_LOGIC;
signal \g81__149_carry__3_n_4\ : STD_LOGIC;
signal \g81__149_carry__3_n_5\ : STD_LOGIC;
signal \g81__149_carry__3_n_6\ : STD_LOGIC;
signal \g81__149_carry__3_n_7\ : STD_LOGIC;
signal \g81__149_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_2\ : STD_LOGIC;
signal \g81__149_carry__4_n_3\ : STD_LOGIC;
signal \g81__149_carry__4_n_5\ : STD_LOGIC;
signal \g81__149_carry__4_n_6\ : STD_LOGIC;
signal \g81__149_carry__4_n_7\ : STD_LOGIC;
signal \g81__149_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_1\ : STD_LOGIC;
signal \g81__149_carry_n_2\ : STD_LOGIC;
signal \g81__149_carry_n_3\ : STD_LOGIC;
signal \g81__206_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_1\ : STD_LOGIC;
signal \g81__206_carry__0_n_2\ : STD_LOGIC;
signal \g81__206_carry__0_n_3\ : STD_LOGIC;
signal \g81__206_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_1\ : STD_LOGIC;
signal \g81__206_carry__1_n_2\ : STD_LOGIC;
signal \g81__206_carry__1_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_1\ : STD_LOGIC;
signal \g81__206_carry__2_n_2\ : STD_LOGIC;
signal \g81__206_carry__2_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_n_4\ : STD_LOGIC;
signal \g81__206_carry__2_n_5\ : STD_LOGIC;
signal \g81__206_carry__2_n_6\ : STD_LOGIC;
signal \g81__206_carry__2_n_7\ : STD_LOGIC;
signal \g81__206_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_1\ : STD_LOGIC;
signal \g81__206_carry__3_n_2\ : STD_LOGIC;
signal \g81__206_carry__3_n_3\ : STD_LOGIC;
signal \g81__206_carry__3_n_4\ : STD_LOGIC;
signal \g81__206_carry__3_n_5\ : STD_LOGIC;
signal \g81__206_carry__3_n_6\ : STD_LOGIC;
signal \g81__206_carry__3_n_7\ : STD_LOGIC;
signal \g81__206_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_2\ : STD_LOGIC;
signal \g81__206_carry__4_n_3\ : STD_LOGIC;
signal \g81__206_carry__4_n_5\ : STD_LOGIC;
signal \g81__206_carry__4_n_6\ : STD_LOGIC;
signal \g81__206_carry__4_n_7\ : STD_LOGIC;
signal \g81__206_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_1\ : STD_LOGIC;
signal \g81__206_carry_n_2\ : STD_LOGIC;
signal \g81__206_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_1\ : STD_LOGIC;
signal \g81__22_carry__0_n_2\ : STD_LOGIC;
signal \g81__22_carry__0_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_n_4\ : STD_LOGIC;
signal \g81__22_carry__0_n_5\ : STD_LOGIC;
signal \g81__22_carry__0_n_6\ : STD_LOGIC;
signal \g81__22_carry__0_n_7\ : STD_LOGIC;
signal \g81__22_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_1\ : STD_LOGIC;
signal \g81__22_carry__1_n_2\ : STD_LOGIC;
signal \g81__22_carry__1_n_3\ : STD_LOGIC;
signal \g81__22_carry__1_n_4\ : STD_LOGIC;
signal \g81__22_carry__1_n_5\ : STD_LOGIC;
signal \g81__22_carry__1_n_6\ : STD_LOGIC;
signal \g81__22_carry__1_n_7\ : STD_LOGIC;
signal \g81__22_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_n_1\ : STD_LOGIC;
signal \g81__22_carry__2_n_3\ : STD_LOGIC;
signal \g81__22_carry__2_n_6\ : STD_LOGIC;
signal \g81__22_carry__2_n_7\ : STD_LOGIC;
signal \g81__22_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_1\ : STD_LOGIC;
signal \g81__22_carry_n_2\ : STD_LOGIC;
signal \g81__22_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry_n_4\ : STD_LOGIC;
signal \g81__22_carry_n_5\ : STD_LOGIC;
signal \g81__22_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_1\ : STD_LOGIC;
signal \g81__261_carry__0_n_2\ : STD_LOGIC;
signal \g81__261_carry__0_n_3\ : STD_LOGIC;
signal \g81__261_carry__0_n_4\ : STD_LOGIC;
signal \g81__261_carry__0_n_5\ : STD_LOGIC;
signal \g81__261_carry__0_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_n_7\ : STD_LOGIC;
signal \g81__261_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_1\ : STD_LOGIC;
signal \g81__261_carry__1_n_2\ : STD_LOGIC;
signal \g81__261_carry__1_n_3\ : STD_LOGIC;
signal \g81__261_carry__1_n_4\ : STD_LOGIC;
signal \g81__261_carry__1_n_5\ : STD_LOGIC;
signal \g81__261_carry__1_n_6\ : STD_LOGIC;
signal \g81__261_carry__1_n_7\ : STD_LOGIC;
signal \g81__261_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_n_1\ : STD_LOGIC;
signal \g81__261_carry__2_n_3\ : STD_LOGIC;
signal \g81__261_carry__2_n_6\ : STD_LOGIC;
signal \g81__261_carry__2_n_7\ : STD_LOGIC;
signal \g81__261_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_1\ : STD_LOGIC;
signal \g81__261_carry_n_2\ : STD_LOGIC;
signal \g81__261_carry_n_3\ : STD_LOGIC;
signal \g81__261_carry_n_4\ : STD_LOGIC;
signal \g81__261_carry_n_5\ : STD_LOGIC;
signal \g81__261_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry_n_7\ : STD_LOGIC;
signal \g81__301_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_1\ : STD_LOGIC;
signal \g81__301_carry__0_n_2\ : STD_LOGIC;
signal \g81__301_carry__0_n_3\ : STD_LOGIC;
signal \g81__301_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_1\ : STD_LOGIC;
signal \g81__301_carry__1_n_2\ : STD_LOGIC;
signal \g81__301_carry__1_n_3\ : STD_LOGIC;
signal \g81__301_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_1\ : STD_LOGIC;
signal \g81__301_carry__2_n_2\ : STD_LOGIC;
signal \g81__301_carry__2_n_3\ : STD_LOGIC;
signal \g81__301_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_1\ : STD_LOGIC;
signal \g81__301_carry__3_n_2\ : STD_LOGIC;
signal \g81__301_carry__3_n_3\ : STD_LOGIC;
signal \g81__301_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_1\ : STD_LOGIC;
signal \g81__301_carry__4_n_2\ : STD_LOGIC;
signal \g81__301_carry__4_n_3\ : STD_LOGIC;
signal \g81__301_carry__5_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_1\ : STD_LOGIC;
signal \g81__301_carry__5_n_2\ : STD_LOGIC;
signal \g81__301_carry__5_n_3\ : STD_LOGIC;
signal \g81__301_carry__6_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_n_1\ : STD_LOGIC;
signal \g81__301_carry__6_n_2\ : STD_LOGIC;
signal \g81__301_carry__6_n_3\ : STD_LOGIC;
signal \g81__301_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_1\ : STD_LOGIC;
signal \g81__301_carry_n_2\ : STD_LOGIC;
signal \g81__301_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_n_1\ : STD_LOGIC;
signal \g81__347_carry__0_n_2\ : STD_LOGIC;
signal \g81__347_carry__0_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_n_4\ : STD_LOGIC;
signal \g81__347_carry__0_n_5\ : STD_LOGIC;
signal \g81__347_carry__0_n_6\ : STD_LOGIC;
signal \g81__347_carry__0_n_7\ : STD_LOGIC;
signal \g81__347_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_1\ : STD_LOGIC;
signal \g81__347_carry_n_2\ : STD_LOGIC;
signal \g81__347_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry_n_4\ : STD_LOGIC;
signal \g81__347_carry_n_5\ : STD_LOGIC;
signal \g81__347_carry_n_6\ : STD_LOGIC;
signal \g81__347_carry_n_7\ : STD_LOGIC;
signal \g81__53_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_1\ : STD_LOGIC;
signal \g81__53_carry__0_n_2\ : STD_LOGIC;
signal \g81__53_carry__0_n_3\ : STD_LOGIC;
signal \g81__53_carry__0_n_4\ : STD_LOGIC;
signal \g81__53_carry__0_n_5\ : STD_LOGIC;
signal \g81__53_carry__0_n_6\ : STD_LOGIC;
signal \g81__53_carry__0_n_7\ : STD_LOGIC;
signal \g81__53_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_1\ : STD_LOGIC;
signal \g81__53_carry__1_n_2\ : STD_LOGIC;
signal \g81__53_carry__1_n_3\ : STD_LOGIC;
signal \g81__53_carry__1_n_4\ : STD_LOGIC;
signal \g81__53_carry__1_n_5\ : STD_LOGIC;
signal \g81__53_carry__1_n_6\ : STD_LOGIC;
signal \g81__53_carry__1_n_7\ : STD_LOGIC;
signal \g81__53_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_n_1\ : STD_LOGIC;
signal \g81__53_carry__2_n_3\ : STD_LOGIC;
signal \g81__53_carry__2_n_6\ : STD_LOGIC;
signal \g81__53_carry__2_n_7\ : STD_LOGIC;
signal \g81__53_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_1\ : STD_LOGIC;
signal \g81__53_carry_n_2\ : STD_LOGIC;
signal \g81__53_carry_n_3\ : STD_LOGIC;
signal \g81__53_carry_n_4\ : STD_LOGIC;
signal \g81__53_carry_n_5\ : STD_LOGIC;
signal \g81__53_carry_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_1\ : STD_LOGIC;
signal \g81__92_carry__0_n_2\ : STD_LOGIC;
signal \g81__92_carry__0_n_3\ : STD_LOGIC;
signal \g81__92_carry__0_n_4\ : STD_LOGIC;
signal \g81__92_carry__0_n_5\ : STD_LOGIC;
signal \g81__92_carry__0_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_n_7\ : STD_LOGIC;
signal \g81__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_1\ : STD_LOGIC;
signal \g81__92_carry__1_n_2\ : STD_LOGIC;
signal \g81__92_carry__1_n_3\ : STD_LOGIC;
signal \g81__92_carry__1_n_4\ : STD_LOGIC;
signal \g81__92_carry__1_n_5\ : STD_LOGIC;
signal \g81__92_carry__1_n_6\ : STD_LOGIC;
signal \g81__92_carry__1_n_7\ : STD_LOGIC;
signal \g81__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_n_1\ : STD_LOGIC;
signal \g81__92_carry__2_n_3\ : STD_LOGIC;
signal \g81__92_carry__2_n_6\ : STD_LOGIC;
signal \g81__92_carry__2_n_7\ : STD_LOGIC;
signal \g81__92_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_1\ : STD_LOGIC;
signal \g81__92_carry_n_2\ : STD_LOGIC;
signal \g81__92_carry_n_3\ : STD_LOGIC;
signal \g81__92_carry_n_4\ : STD_LOGIC;
signal \g81__92_carry_n_5\ : STD_LOGIC;
signal \g81__92_carry_n_6\ : STD_LOGIC;
signal \g81_carry__0_i_10_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_11_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_12_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_13_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_14_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_15_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_1\ : STD_LOGIC;
signal \g81_carry__0_n_2\ : STD_LOGIC;
signal \g81_carry__0_n_3\ : STD_LOGIC;
signal \g81_carry__0_n_4\ : STD_LOGIC;
signal \g81_carry__0_n_5\ : STD_LOGIC;
signal \g81_carry__0_n_6\ : STD_LOGIC;
signal \g81_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_1\ : STD_LOGIC;
signal \g81_carry__1_n_2\ : STD_LOGIC;
signal \g81_carry__1_n_3\ : STD_LOGIC;
signal \g81_carry__1_n_4\ : STD_LOGIC;
signal \g81_carry__1_n_5\ : STD_LOGIC;
signal \g81_carry__1_n_6\ : STD_LOGIC;
signal \g81_carry__1_n_7\ : STD_LOGIC;
signal \g81_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__2_n_1\ : STD_LOGIC;
signal \g81_carry__2_n_3\ : STD_LOGIC;
signal \g81_carry__2_n_6\ : STD_LOGIC;
signal \g81_carry__2_n_7\ : STD_LOGIC;
signal g81_carry_i_1_n_0 : STD_LOGIC;
signal g81_carry_i_2_n_0 : STD_LOGIC;
signal g81_carry_i_3_n_0 : STD_LOGIC;
signal g81_carry_i_4_n_0 : STD_LOGIC;
signal g81_carry_i_5_n_0 : STD_LOGIC;
signal g81_carry_i_6_n_0 : STD_LOGIC;
signal g81_carry_i_7_n_0 : STD_LOGIC;
signal g81_carry_n_0 : STD_LOGIC;
signal g81_carry_n_1 : STD_LOGIC;
signal g81_carry_n_2 : STD_LOGIC;
signal g81_carry_n_3 : STD_LOGIC;
signal g81_carry_n_7 : STD_LOGIC;
signal g83 : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \g83__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_1\ : STD_LOGIC;
signal \g83__0_carry__0_n_2\ : STD_LOGIC;
signal \g83__0_carry__0_n_3\ : STD_LOGIC;
signal \g83__0_carry__0_n_4\ : STD_LOGIC;
signal \g83__0_carry__0_n_5\ : STD_LOGIC;
signal \g83__0_carry__0_n_6\ : STD_LOGIC;
signal \g83__0_carry__0_n_7\ : STD_LOGIC;
signal \g83__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__1_n_2\ : STD_LOGIC;
signal \g83__0_carry__1_n_7\ : STD_LOGIC;
signal \g83__0_carry_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_1\ : STD_LOGIC;
signal \g83__0_carry_n_2\ : STD_LOGIC;
signal \g83__0_carry_n_3\ : STD_LOGIC;
signal \g83__0_carry_n_4\ : STD_LOGIC;
signal \g83__0_carry_n_5\ : STD_LOGIC;
signal \g83__0_carry_n_6\ : STD_LOGIC;
signal \g83__0_carry_n_7\ : STD_LOGIC;
signal g84 : STD_LOGIC;
signal \g84_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g84_carry__0_i_2_n_0\ : STD_LOGIC;
signal g84_carry_i_1_n_0 : STD_LOGIC;
signal g84_carry_i_2_n_0 : STD_LOGIC;
signal g84_carry_i_3_n_0 : STD_LOGIC;
signal g84_carry_i_4_n_0 : STD_LOGIC;
signal g84_carry_i_5_n_0 : STD_LOGIC;
signal g84_carry_i_6_n_0 : STD_LOGIC;
signal g84_carry_i_7_n_0 : STD_LOGIC;
signal g84_carry_i_8_n_0 : STD_LOGIC;
signal g84_carry_n_0 : STD_LOGIC;
signal g84_carry_n_1 : STD_LOGIC;
signal g84_carry_n_2 : STD_LOGIC;
signal g84_carry_n_3 : STD_LOGIC;
signal \NLW__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__120_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__149_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__149_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__206_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__206_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__22_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__22_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__22_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__261_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__261_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__301_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__301_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__347_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__53_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__53_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__53_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__92_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__92_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_g81_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g83__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g83__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_g84_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g84_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g84_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute HLUTNM : string;
attribute HLUTNM of \g81__120_carry__1_i_1\ : label is "lutpair7";
attribute HLUTNM of \g81__149_carry__0_i_1\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_2\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__0_i_5\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__0_i_6\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_7\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__1_i_1\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_2\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_3\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__1_i_4\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__1_i_5\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__1_i_6\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_7\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_8\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__2_i_1\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_2\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_3\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__2_i_4\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__2_i_5\ : label is "lutpair17";
attribute HLUTNM of \g81__149_carry__2_i_6\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_7\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_8\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__3_i_1\ : label is "lutpair17";
attribute HLUTNM of \g81__206_carry__0_i_1\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_2\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__0_i_5\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__0_i_6\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_7\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__1_i_1\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_2\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_3\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__1_i_4\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__1_i_5\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__1_i_6\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_7\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_8\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__2_i_1\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__2_i_4\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__2_i_6\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__3_i_1\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_3\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__3_i_6\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_8\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__4_i_2\ : label is "lutpair26";
attribute HLUTNM of \g81__206_carry__4_i_6\ : label is "lutpair26";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \g81_carry__0_i_10\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_11\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_12\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \g81_carry__0_i_13\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_14\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_15\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__0_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__1_i_9\ : label is "soft_lutpair3";
attribute HLUTNM of \g81_carry__2_i_2\ : label is "lutpair7";
attribute HLUTNM of \g83__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \g83__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_7\ : label is "lutpair0";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(4 downto 1),
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => \_carry_i_5_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_4\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_6\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3 downto 2) => \NLW__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \_carry__1_n_2\,
CO(0) => \NLW__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => g83(9),
S(3 downto 1) => B"001",
S(0) => \_carry__1_i_1_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_2\,
O => \_carry__1_i_1_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
O => \_carry_i_1_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_4\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_6\,
O => \_carry_i_5_n_0\
);
\g81__120_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__120_carry_n_0\,
CO(2) => \g81__120_carry_n_1\,
CO(1) => \g81__120_carry_n_2\,
CO(0) => \g81__120_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__120_carry_i_1_n_0\,
DI(1) => \g81__120_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__120_carry_n_4\,
O(2) => \g81__120_carry_n_5\,
O(1) => \g81__120_carry_n_6\,
O(0) => \NLW_g81__120_carry_O_UNCONNECTED\(0),
S(3) => \g81__120_carry_i_3_n_0\,
S(2) => \g81__120_carry_i_4_n_0\,
S(1) => \g81__120_carry_i_5_n_0\,
S(0) => \g81__120_carry_i_6_n_0\
);
\g81__120_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry_n_0\,
CO(3) => \g81__120_carry__0_n_0\,
CO(2) => \g81__120_carry__0_n_1\,
CO(1) => \g81__120_carry__0_n_2\,
CO(0) => \g81__120_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__120_carry__0_n_4\,
O(2) => \g81__120_carry__0_n_5\,
O(1) => \g81__120_carry__0_n_6\,
O(0) => \g81__120_carry__0_n_7\,
S(3) => \g81__120_carry__0_i_1_n_0\,
S(2) => \g81__120_carry__0_i_2_n_0\,
S(1) => \g81__120_carry__0_i_3_n_0\,
S(0) => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__120_carry__0_i_1_n_0\
);
\g81__120_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__120_carry__0_i_2_n_0\
);
\g81__120_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__120_carry__0_i_3_n_0\
);
\g81__120_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__0_n_0\,
CO(3) => \g81__120_carry__1_n_0\,
CO(2) => \g81__120_carry__1_n_1\,
CO(1) => \g81__120_carry__1_n_2\,
CO(0) => \g81__120_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__120_carry__1_n_4\,
O(2) => \g81__120_carry__1_n_5\,
O(1) => \g81__120_carry__1_n_6\,
O(0) => \g81__120_carry__1_n_7\,
S(3) => \g81__120_carry__1_i_1_n_0\,
S(2) => \g81__120_carry__1_i_2_n_0\,
S(1) => \g81__120_carry__1_i_3_n_0\,
S(0) => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"369C"
)
port map (
I0 => g84,
I1 => \g81_carry__1_i_1_n_0\,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__120_carry__1_i_1_n_0\
);
\g81__120_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_2_n_0\
);
\g81__120_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_3_n_0\
);
\g81__120_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__1_n_0\,
CO(3) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__120_carry__2_n_1\,
CO(1) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__120_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__120_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__120_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__120_carry__2_n_6\,
O(0) => \g81__120_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__120_carry__2_i_1_n_0\
);
\g81__120_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__120_carry_i_1_n_0\
);
\g81__120_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__120_carry_i_2_n_0\
);
\g81__120_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__120_carry_i_3_n_0\
);
\g81__120_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__120_carry_i_4_n_0\
);
\g81__120_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__120_carry_i_5_n_0\
);
\g81__120_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__120_carry_i_6_n_0\
);
\g81__149_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__149_carry_n_0\,
CO(2) => \g81__149_carry_n_1\,
CO(1) => \g81__149_carry_n_2\,
CO(0) => \g81__149_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry_i_1_n_0\,
DI(2) => \g81__149_carry_i_2_n_0\,
DI(1) => \g81__149_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__149_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry_i_4_n_0\,
S(2) => \g81__149_carry_i_5_n_0\,
S(1) => \g81__149_carry_i_6_n_0\,
S(0) => \g81__149_carry_i_7_n_0\
);
\g81__149_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry_n_0\,
CO(3) => \g81__149_carry__0_n_0\,
CO(2) => \g81__149_carry__0_n_1\,
CO(1) => \g81__149_carry__0_n_2\,
CO(0) => \g81__149_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__0_i_1_n_0\,
DI(2) => \g81__149_carry__0_i_2_n_0\,
DI(1) => \g81__149_carry__0_i_3_n_0\,
DI(0) => \g81__149_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__0_i_5_n_0\,
S(2) => \g81__149_carry__0_i_6_n_0\,
S(1) => \g81__149_carry__0_i_7_n_0\,
S(0) => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
O => \g81__149_carry__0_i_1_n_0\
);
\g81__149_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
O => \g81__149_carry__0_i_2_n_0\
);
\g81__149_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_6\,
I1 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_3_n_0\
);
\g81__149_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
O => \g81__149_carry__0_i_4_n_0\
);
\g81__149_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
I3 => \g81__149_carry__0_i_1_n_0\,
O => \g81__149_carry__0_i_5_n_0\
);
\g81__149_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
I3 => \g81__149_carry__0_i_2_n_0\,
O => \g81__149_carry__0_i_6_n_0\
);
\g81__149_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
I2 => \g81_carry__1_n_6\,
I3 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_7_n_0\
);
\g81__149_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
I2 => \g81__22_carry_n_4\,
I3 => \g81_carry__1_n_6\,
O => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__0_n_0\,
CO(3) => \g81__149_carry__1_n_0\,
CO(2) => \g81__149_carry__1_n_1\,
CO(1) => \g81__149_carry__1_n_2\,
CO(0) => \g81__149_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__1_i_1_n_0\,
DI(2) => \g81__149_carry__1_i_2_n_0\,
DI(1) => \g81__149_carry__1_i_3_n_0\,
DI(0) => \g81__149_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__1_i_5_n_0\,
S(2) => \g81__149_carry__1_i_6_n_0\,
S(1) => \g81__149_carry__1_i_7_n_0\,
S(0) => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__1_i_1_n_0\
);
\g81__149_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
O => \g81__149_carry__1_i_2_n_0\
);
\g81__149_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
O => \g81__149_carry__1_i_3_n_0\
);
\g81__149_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
O => \g81__149_carry__1_i_4_n_0\
);
\g81__149_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_1_n_0\,
O => \g81__149_carry__1_i_5_n_0\
);
\g81__149_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_2_n_0\,
O => \g81__149_carry__1_i_6_n_0\
);
\g81__149_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
I3 => \g81__149_carry__1_i_3_n_0\,
O => \g81__149_carry__1_i_7_n_0\
);
\g81__149_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
I3 => \g81__149_carry__1_i_4_n_0\,
O => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__1_n_0\,
CO(3) => \g81__149_carry__2_n_0\,
CO(2) => \g81__149_carry__2_n_1\,
CO(1) => \g81__149_carry__2_n_2\,
CO(0) => \g81__149_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__2_i_1_n_0\,
DI(2) => \g81__149_carry__2_i_2_n_0\,
DI(1) => \g81__149_carry__2_i_3_n_0\,
DI(0) => \g81__149_carry__2_i_4_n_0\,
O(3) => \g81__149_carry__2_n_4\,
O(2) => \g81__149_carry__2_n_5\,
O(1) => \g81__149_carry__2_n_6\,
O(0) => \g81__149_carry__2_n_7\,
S(3) => \g81__149_carry__2_i_5_n_0\,
S(2) => \g81__149_carry__2_i_6_n_0\,
S(1) => \g81__149_carry__2_i_7_n_0\,
S(0) => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_1_n_0\
);
\g81__149_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_2_n_0\
);
\g81__149_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_3_n_0\
);
\g81__149_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_4_n_0\
);
\g81__149_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_1_n_0\,
O => \g81__149_carry__2_i_5_n_0\
);
\g81__149_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_2_n_0\,
O => \g81__149_carry__2_i_6_n_0\
);
\g81__149_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_3_n_0\,
O => \g81__149_carry__2_i_7_n_0\
);
\g81__149_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_4_n_0\,
O => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__2_n_0\,
CO(3) => \g81__149_carry__3_n_0\,
CO(2) => \g81__149_carry__3_n_1\,
CO(1) => \g81__149_carry__3_n_2\,
CO(0) => \g81__149_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__2_i_2_n_0\,
DI(2) => \g81_carry__2_i_2_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81__149_carry__3_i_1_n_0\,
O(3) => \g81__149_carry__3_n_4\,
O(2) => \g81__149_carry__3_n_5\,
O(1) => \g81__149_carry__3_n_6\,
O(0) => \g81__149_carry__3_n_7\,
S(3) => \g81__149_carry__3_i_2_n_0\,
S(2) => \g81__149_carry__3_i_3_n_0\,
S(1) => \g81__149_carry__3_i_4_n_0\,
S(0) => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__3_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__3_i_1_n_0\
);
\g81__149_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_7\,
O => \g81__149_carry__3_i_2_n_0\
);
\g81__149_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_4\,
O => \g81__149_carry__3_i_3_n_0\
);
\g81__149_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_5\,
O => \g81__149_carry__3_i_4_n_0\
);
\g81__149_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__149_carry__3_i_1_n_0\,
I1 => \g81__53_carry__1_n_6\,
O => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__3_n_0\,
CO(3) => \g81__149_carry__4_n_0\,
CO(2) => \NLW_g81__149_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__149_carry__4_n_2\,
CO(0) => \g81__149_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__149_carry__4_i_1_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3) => \NLW_g81__149_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__149_carry__4_n_5\,
O(1) => \g81__149_carry__4_n_6\,
O(0) => \g81__149_carry__4_n_7\,
S(3 downto 2) => B"10",
S(1) => \g81__149_carry__4_i_2_n_0\,
S(0) => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__149_carry__4_i_1_n_0\
);
\g81__149_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_1\,
O => \g81__149_carry__4_i_2_n_0\
);
\g81__149_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_6\,
O => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
O => \g81__149_carry_i_1_n_0\
);
\g81__149_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
O => \g81__149_carry_i_2_n_0\
);
\g81__149_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_3_n_0\
);
\g81__149_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
I2 => \g81__22_carry_n_5\,
I3 => \g81_carry__1_n_7\,
O => \g81__149_carry_i_4_n_0\
);
\g81__149_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__22_carry_n_6\,
I3 => \g81_carry__0_n_4\,
O => \g81__149_carry_i_5_n_0\
);
\g81__149_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g81_carry__0_n_5\,
O => \g81__149_carry_i_6_n_0\
);
\g81__149_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_7_n_0\
);
\g81__206_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__206_carry_n_0\,
CO(2) => \g81__206_carry_n_1\,
CO(1) => \g81__206_carry_n_2\,
CO(0) => \g81__206_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry_i_1_n_0\,
DI(2) => \g81__206_carry_i_2_n_0\,
DI(1) => \g81__206_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__206_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry_i_4_n_0\,
S(2) => \g81__206_carry_i_5_n_0\,
S(1) => \g81__206_carry_i_6_n_0\,
S(0) => \g81__206_carry_i_7_n_0\
);
\g81__206_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry_n_0\,
CO(3) => \g81__206_carry__0_n_0\,
CO(2) => \g81__206_carry__0_n_1\,
CO(1) => \g81__206_carry__0_n_2\,
CO(0) => \g81__206_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__0_i_1_n_0\,
DI(2) => \g81__206_carry__0_i_2_n_0\,
DI(1) => \g81__206_carry__0_i_3_n_0\,
DI(0) => \g81__206_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__0_i_5_n_0\,
S(2) => \g81__206_carry__0_i_6_n_0\,
S(1) => \g81__206_carry__0_i_7_n_0\,
S(0) => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
O => \g81__206_carry__0_i_1_n_0\
);
\g81__206_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
O => \g81__206_carry__0_i_2_n_0\
);
\g81__206_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_4\,
I1 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_3_n_0\
);
\g81__206_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
O => \g81__206_carry__0_i_4_n_0\
);
\g81__206_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
I3 => \g81__206_carry__0_i_1_n_0\,
O => \g81__206_carry__0_i_5_n_0\
);
\g81__206_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
I3 => \g81__206_carry__0_i_2_n_0\,
O => \g81__206_carry__0_i_6_n_0\
);
\g81__206_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
I2 => \g81__92_carry_n_4\,
I3 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_7_n_0\
);
\g81__206_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
I2 => \g81__149_carry__3_n_7\,
I3 => \g81__92_carry_n_4\,
O => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__0_n_0\,
CO(3) => \g81__206_carry__1_n_0\,
CO(2) => \g81__206_carry__1_n_1\,
CO(1) => \g81__206_carry__1_n_2\,
CO(0) => \g81__206_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__1_i_1_n_0\,
DI(2) => \g81__206_carry__1_i_2_n_0\,
DI(1) => \g81__206_carry__1_i_3_n_0\,
DI(0) => \g81__206_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__1_i_5_n_0\,
S(2) => \g81__206_carry__1_i_6_n_0\,
S(1) => \g81__206_carry__1_i_7_n_0\,
S(0) => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
O => \g81__206_carry__1_i_1_n_0\
);
\g81__206_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
O => \g81__206_carry__1_i_2_n_0\
);
\g81__206_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
O => \g81__206_carry__1_i_3_n_0\
);
\g81__206_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
O => \g81__206_carry__1_i_4_n_0\
);
\g81__206_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
I3 => \g81__206_carry__1_i_1_n_0\,
O => \g81__206_carry__1_i_5_n_0\
);
\g81__206_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
I3 => \g81__206_carry__1_i_2_n_0\,
O => \g81__206_carry__1_i_6_n_0\
);
\g81__206_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
I3 => \g81__206_carry__1_i_3_n_0\,
O => \g81__206_carry__1_i_7_n_0\
);
\g81__206_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
I3 => \g81__206_carry__1_i_4_n_0\,
O => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__1_n_0\,
CO(3) => \g81__206_carry__2_n_0\,
CO(2) => \g81__206_carry__2_n_1\,
CO(1) => \g81__206_carry__2_n_2\,
CO(0) => \g81__206_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_i_1_n_0\,
DI(2) => \g81__206_carry__2_i_2_n_0\,
DI(1) => \g81__206_carry__2_i_3_n_0\,
DI(0) => \g81__206_carry__2_i_4_n_0\,
O(3) => \g81__206_carry__2_n_4\,
O(2) => \g81__206_carry__2_n_5\,
O(1) => \g81__206_carry__2_n_6\,
O(0) => \g81__206_carry__2_n_7\,
S(3) => \g81__206_carry__2_i_5_n_0\,
S(2) => \g81__206_carry__2_i_6_n_0\,
S(1) => \g81__206_carry__2_i_7_n_0\,
S(0) => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
O => \g81__206_carry__2_i_1_n_0\
);
\g81__206_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry__2_n_7\,
I1 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_2_n_0\
);
\g81__206_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__0_n_6\,
I3 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_3_n_0\
);
\g81__206_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
O => \g81__206_carry__2_i_4_n_0\
);
\g81__206_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_1_n_0\,
I1 => \g81__120_carry__1_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__2_i_5_n_0\
);
\g81__206_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
I2 => \g81__92_carry__2_n_7\,
I3 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_6_n_0\
);
\g81__206_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"888E77717771888E"
)
port map (
I0 => \g81__92_carry__1_n_4\,
I1 => \g81__120_carry__0_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
I4 => \g81__120_carry__0_n_5\,
I5 => \g81__92_carry__2_n_7\,
O => \g81__206_carry__2_i_7_n_0\
);
\g81__206_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_4_n_0\,
I1 => \g81__120_carry__0_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__2_n_0\,
CO(3) => \g81__206_carry__3_n_0\,
CO(2) => \g81__206_carry__3_n_1\,
CO(1) => \g81__206_carry__3_n_2\,
CO(0) => \g81__206_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_i_1_n_0\,
DI(2) => \g81__206_carry__3_i_2_n_0\,
DI(1) => \g81__206_carry__3_i_3_n_0\,
DI(0) => \g81__206_carry__3_i_4_n_0\,
O(3) => \g81__206_carry__3_n_4\,
O(2) => \g81__206_carry__3_n_5\,
O(1) => \g81__206_carry__3_n_6\,
O(0) => \g81__206_carry__3_n_7\,
S(3) => \g81__206_carry__3_i_5_n_0\,
S(2) => \g81__206_carry__3_i_6_n_0\,
S(1) => \g81__206_carry__3_i_7_n_0\,
S(0) => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_1_n_0\
);
\g81__206_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__3_i_2_n_0\
);
\g81__206_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_3_n_0\
);
\g81__206_carry__3_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__1_n_7\,
I3 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__3_i_4_n_0\
);
\g81__206_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_1_n_0\,
I1 => \g81__120_carry__2_n_7\,
O => \g81__206_carry__3_i_5_n_0\
);
\g81__206_carry__3_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__1_n_4\,
O => \g81__206_carry__3_i_6_n_0\
);
\g81__206_carry__3_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_3_n_0\,
I1 => \g81__120_carry__1_n_5\,
O => \g81__206_carry__3_i_7_n_0\
);
\g81__206_carry__3_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"56AAAAA9"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
I3 => \g81__92_carry__2_n_1\,
I4 => \g81__120_carry__1_n_7\,
O => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__3_n_0\,
CO(3) => \g81__206_carry__4_n_0\,
CO(2) => \NLW_g81__206_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__206_carry__4_n_2\,
CO(0) => \g81__206_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__206_carry__4_i_1_n_0\,
DI(1) => \g81__206_carry__4_i_2_n_0\,
DI(0) => \g81__206_carry__4_i_3_n_0\,
O(3) => \NLW_g81__206_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__206_carry__4_n_5\,
O(1) => \g81__206_carry__4_n_6\,
O(0) => \g81__206_carry__4_n_7\,
S(3) => '1',
S(2) => \g81__206_carry__4_i_4_n_0\,
S(1) => \g81__206_carry__4_i_5_n_0\,
S(0) => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_1_n_0\
);
\g81__206_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__4_i_2_n_0\
);
\g81__206_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_3_n_0\
);
\g81__206_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_4_n_0\
);
\g81__206_carry__4_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__4_i_2_n_0\,
I1 => \g81__120_carry__2_n_1\,
O => \g81__206_carry__4_i_5_n_0\
);
\g81__206_carry__4_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__2_n_6\,
O => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
O => \g81__206_carry_i_1_n_0\
);
\g81__206_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
O => \g81__206_carry_i_2_n_0\
);
\g81__206_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_3_n_0\
);
\g81__206_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
I2 => \g81__149_carry__2_n_4\,
I3 => \g81__92_carry_n_5\,
O => \g81__206_carry_i_4_n_0\
);
\g81__206_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
I2 => \g81__149_carry__2_n_5\,
I3 => \g81__92_carry_n_6\,
O => \g81__206_carry_i_5_n_0\
);
\g81__206_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
I2 => \g81__149_carry__2_n_6\,
I3 => g81_carry_n_7,
O => \g81__206_carry_i_6_n_0\
);
\g81__206_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_7_n_0\
);
\g81__22_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__22_carry_n_0\,
CO(2) => \g81__22_carry_n_1\,
CO(1) => \g81__22_carry_n_2\,
CO(0) => \g81__22_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__22_carry_i_1_n_0\,
DI(1) => \g81__22_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__22_carry_n_4\,
O(2) => \g81__22_carry_n_5\,
O(1) => \g81__22_carry_n_6\,
O(0) => \NLW_g81__22_carry_O_UNCONNECTED\(0),
S(3) => \g81__22_carry_i_3_n_0\,
S(2) => \g81__22_carry_i_4_n_0\,
S(1) => \g81__22_carry_i_5_n_0\,
S(0) => \g81__22_carry_i_6_n_0\
);
\g81__22_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry_n_0\,
CO(3) => \g81__22_carry__0_n_0\,
CO(2) => \g81__22_carry__0_n_1\,
CO(1) => \g81__22_carry__0_n_2\,
CO(0) => \g81__22_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__22_carry__0_n_4\,
O(2) => \g81__22_carry__0_n_5\,
O(1) => \g81__22_carry__0_n_6\,
O(0) => \g81__22_carry__0_n_7\,
S(3) => \g81__22_carry__0_i_1_n_0\,
S(2) => \g81__22_carry__0_i_2_n_0\,
S(1) => \g81__22_carry__0_i_3_n_0\,
S(0) => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__22_carry__0_i_1_n_0\
);
\g81__22_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__22_carry__0_i_2_n_0\
);
\g81__22_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__22_carry__0_i_3_n_0\
);
\g81__22_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__0_n_0\,
CO(3) => \g81__22_carry__1_n_0\,
CO(2) => \g81__22_carry__1_n_1\,
CO(1) => \g81__22_carry__1_n_2\,
CO(0) => \g81__22_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__22_carry__1_n_4\,
O(2) => \g81__22_carry__1_n_5\,
O(1) => \g81__22_carry__1_n_6\,
O(0) => \g81__22_carry__1_n_7\,
S(3) => \g81__22_carry__1_i_1_n_0\,
S(2) => \g81__22_carry__1_i_2_n_0\,
S(1) => \g81__22_carry__1_i_3_n_0\,
S(0) => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__22_carry__1_i_1_n_0\
);
\g81__22_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_2_n_0\
);
\g81__22_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_3_n_0\
);
\g81__22_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__1_n_0\,
CO(3) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__22_carry__2_n_1\,
CO(1) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__22_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__22_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__22_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__22_carry__2_n_6\,
O(0) => \g81__22_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__22_carry__2_i_1_n_0\
);
\g81__22_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__22_carry_i_1_n_0\
);
\g81__22_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__22_carry_i_2_n_0\
);
\g81__22_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__22_carry_i_3_n_0\
);
\g81__22_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__22_carry_i_4_n_0\
);
\g81__22_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__22_carry_i_5_n_0\
);
\g81__22_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__22_carry_i_6_n_0\
);
\g81__261_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__261_carry_n_0\,
CO(2) => \g81__261_carry_n_1\,
CO(1) => \g81__261_carry_n_2\,
CO(0) => \g81__261_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_n_6\,
DI(2) => \g81__206_carry__2_n_7\,
DI(1 downto 0) => B"01",
O(3) => \g81__261_carry_n_4\,
O(2) => \g81__261_carry_n_5\,
O(1) => \g81__261_carry_n_6\,
O(0) => \g81__261_carry_n_7\,
S(3) => \g81__261_carry_i_1_n_0\,
S(2) => \g81__261_carry_i_2_n_0\,
S(1) => \g81__261_carry_i_3_n_0\,
S(0) => \g81__261_carry_i_4_n_0\
);
\g81__261_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry_n_0\,
CO(3) => \g81__261_carry__0_n_0\,
CO(2) => \g81__261_carry__0_n_1\,
CO(1) => \g81__261_carry__0_n_2\,
CO(0) => \g81__261_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_n_6\,
DI(2) => \g81__206_carry__3_n_7\,
DI(1) => \g81__206_carry__2_n_4\,
DI(0) => \g81__206_carry__2_n_5\,
O(3) => \g81__261_carry__0_n_4\,
O(2) => \g81__261_carry__0_n_5\,
O(1) => \g81__261_carry__0_n_6\,
O(0) => \g81__261_carry__0_n_7\,
S(3) => \g81__261_carry__0_i_1_n_0\,
S(2) => \g81__261_carry__0_i_2_n_0\,
S(1) => \g81__261_carry__0_i_3_n_0\,
S(0) => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__206_carry__3_n_4\,
O => \g81__261_carry__0_i_1_n_0\
);
\g81__261_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__206_carry__3_n_5\,
O => \g81__261_carry__0_i_2_n_0\
);
\g81__261_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__206_carry__3_n_6\,
O => \g81__261_carry__0_i_3_n_0\
);
\g81__261_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__206_carry__3_n_7\,
O => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__0_n_0\,
CO(3) => \g81__261_carry__1_n_0\,
CO(2) => \g81__261_carry__1_n_1\,
CO(1) => \g81__261_carry__1_n_2\,
CO(0) => \g81__261_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__4_n_6\,
DI(2) => \g81__206_carry__4_n_7\,
DI(1) => \g81__206_carry__3_n_4\,
DI(0) => \g81__206_carry__3_n_5\,
O(3) => \g81__261_carry__1_n_4\,
O(2) => \g81__261_carry__1_n_5\,
O(1) => \g81__261_carry__1_n_6\,
O(0) => \g81__261_carry__1_n_7\,
S(3) => \g81__261_carry__1_i_1_n_0\,
S(2) => \g81__261_carry__1_i_2_n_0\,
S(1) => \g81__261_carry__1_i_3_n_0\,
S(0) => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_6\,
I1 => \g81__206_carry__4_n_0\,
O => \g81__261_carry__1_i_1_n_0\
);
\g81__261_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_7\,
I1 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__1_i_2_n_0\
);
\g81__261_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__206_carry__4_n_6\,
O => \g81__261_carry__1_i_3_n_0\
);
\g81__261_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__206_carry__4_n_7\,
O => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__1_n_0\,
CO(3) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__261_carry__2_n_1\,
CO(1) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__261_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__206_carry__4_n_0\,
DI(0) => \g81__206_carry__4_n_5\,
O(3 downto 2) => \NLW_g81__261_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__261_carry__2_n_6\,
O(0) => \g81__261_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \g81__261_carry__2_i_1_n_0\,
S(0) => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \g81__206_carry__4_n_0\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__261_carry__2_i_1_n_0\
);
\g81__261_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__206_carry__2_n_4\,
O => \g81__261_carry_i_1_n_0\
);
\g81__261_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__206_carry__2_n_5\,
O => \g81__261_carry_i_2_n_0\
);
\g81__261_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__261_carry_i_3_n_0\
);
\g81__261_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__261_carry_i_4_n_0\
);
\g81__301_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__301_carry_n_0\,
CO(2) => \g81__301_carry_n_1\,
CO(1) => \g81__301_carry_n_2\,
CO(0) => \g81__301_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry_i_1_n_0\,
DI(2) => \g81__301_carry_i_2_n_0\,
DI(1) => \g81__301_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__301_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry_i_4_n_0\,
S(2) => \g81__301_carry_i_5_n_0\,
S(1) => \g81__301_carry_i_6_n_0\,
S(0) => \g81__301_carry_i_7_n_0\
);
\g81__301_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry_n_0\,
CO(3) => \g81__301_carry__0_n_0\,
CO(2) => \g81__301_carry__0_n_1\,
CO(1) => \g81__301_carry__0_n_2\,
CO(0) => \g81__301_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__0_i_1_n_0\,
DI(2) => \g81__301_carry__0_i_2_n_0\,
DI(1) => \g81__301_carry__0_i_3_n_0\,
DI(0) => \g81__301_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__0_i_5_n_0\,
S(2) => \g81__301_carry__0_i_6_n_0\,
S(1) => \g81__301_carry__0_i_7_n_0\,
S(0) => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_5\,
I1 => g84,
I2 => g83(6),
I3 => \g83__0_carry__0_n_5\,
O => \g81__301_carry__0_i_1_n_0\
);
\g81__301_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_6\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
O => \g81__301_carry__0_i_2_n_0\
);
\g81__301_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_7\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
O => \g81__301_carry__0_i_3_n_0\
);
\g81__301_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_4\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
O => \g81__301_carry__0_i_4_n_0\
);
\g81__301_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
I3 => \g81__261_carry__0_n_5\,
I4 => \g81__261_carry__0_n_4\,
I5 => \g81_carry__1_i_9_n_0\,
O => \g81__301_carry__0_i_5_n_0\
);
\g81__301_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
I3 => \g81__261_carry__0_n_6\,
I4 => \g81__261_carry__0_n_5\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__301_carry__0_i_6_n_0\
);
\g81__301_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
I3 => \g81__261_carry__0_n_7\,
I4 => \g81__261_carry__0_n_6\,
I5 => \g81_carry__0_i_14_n_0\,
O => \g81__301_carry__0_i_7_n_0\
);
\g81__301_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => \g81__261_carry_n_4\,
I2 => \g81__261_carry__0_n_7\,
I3 => \g83__0_carry__0_n_7\,
I4 => g83(4),
I5 => g84,
O => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__0_n_0\,
CO(3) => \g81__301_carry__1_n_0\,
CO(2) => \g81__301_carry__1_n_1\,
CO(1) => \g81__301_carry__1_n_2\,
CO(0) => \g81__301_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__1_i_1_n_0\,
DI(2) => \g81__301_carry__1_i_2_n_0\,
DI(1) => \g81__301_carry__1_i_3_n_0\,
DI(0) => \g81__301_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__1_i_5_n_0\,
S(2) => \g81__301_carry__1_i_6_n_0\,
S(1) => \g81__301_carry__1_i_7_n_0\,
S(0) => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__1_i_1_n_0\
);
\g81__301_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_6\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__301_carry__1_i_2_n_0\
);
\g81__301_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_7\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__301_carry__1_i_3_n_0\
);
\g81__301_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_4\,
I1 => g84,
I2 => g83(7),
I3 => \g83__0_carry__0_n_4\,
O => \g81__301_carry__1_i_4_n_0\
);
\g81__301_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \g81__261_carry__1_n_4\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_5_n_0\
);
\g81__301_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"50AF30CF50AFCF30"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => \g81__261_carry__1_n_6\,
I3 => \g81__261_carry__1_n_5\,
I4 => g84,
I5 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_6_n_0\
);
\g81__301_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => g83(8),
I2 => g84,
I3 => \g81__261_carry__1_n_7\,
I4 => \g81__261_carry__1_n_6\,
I5 => \g81__301_carry__1_i_9_n_0\,
O => \g81__301_carry__1_i_7_n_0\
);
\g81__301_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__1_i_9_n_0\,
I1 => \g81__261_carry__0_n_4\,
I2 => \g81__261_carry__1_n_7\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => g84,
O => \g81__301_carry__1_i_9_n_0\
);
\g81__301_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__1_n_0\,
CO(3) => \g81__301_carry__2_n_0\,
CO(2) => \g81__301_carry__2_n_1\,
CO(1) => \g81__301_carry__2_n_2\,
CO(0) => \g81__301_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__2_i_1_n_0\,
DI(2) => \g81__301_carry__2_i_2_n_0\,
DI(1) => \g81__301_carry__2_i_3_n_0\,
DI(0) => \g81__301_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__2_i_5_n_0\,
S(2) => \g81__301_carry__2_i_6_n_0\,
S(1) => \g81__301_carry__2_i_7_n_0\,
S(0) => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__2_i_1_n_0\
);
\g81__301_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_2_n_0\
);
\g81__301_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_3_n_0\
);
\g81__301_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_4_n_0\
);
\g81__301_carry__2_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_5_n_0\
);
\g81__301_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6663"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \g81__261_carry__2_n_1\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_6_n_0\
);
\g81__301_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \g81__261_carry__2_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_7_n_0\
);
\g81__301_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \g81__261_carry__2_n_7\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__2_n_0\,
CO(3) => \g81__301_carry__3_n_0\,
CO(2) => \g81__301_carry__3_n_1\,
CO(1) => \g81__301_carry__3_n_2\,
CO(0) => \g81__301_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__3_i_1_n_0\,
DI(2) => \g81__301_carry__3_i_2_n_0\,
DI(1) => \g81__301_carry__3_i_3_n_0\,
DI(0) => \g81__301_carry__3_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__3_i_5_n_0\,
S(2) => \g81__301_carry__3_i_6_n_0\,
S(1) => \g81__301_carry__3_i_7_n_0\,
S(0) => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_1_n_0\
);
\g81__301_carry__3_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_2_n_0\
);
\g81__301_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_3_n_0\
);
\g81__301_carry__3_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_4_n_0\
);
\g81__301_carry__3_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_5_n_0\
);
\g81__301_carry__3_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_6_n_0\
);
\g81__301_carry__3_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_7_n_0\
);
\g81__301_carry__3_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__3_n_0\,
CO(3) => \g81__301_carry__4_n_0\,
CO(2) => \g81__301_carry__4_n_1\,
CO(1) => \g81__301_carry__4_n_2\,
CO(0) => \g81__301_carry__4_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__4_i_1_n_0\,
DI(2) => \g81__301_carry__4_i_2_n_0\,
DI(1) => \g81__301_carry__4_i_3_n_0\,
DI(0) => \g81__301_carry__4_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__4_i_5_n_0\,
S(2) => \g81__301_carry__4_i_6_n_0\,
S(1) => \g81__301_carry__4_i_7_n_0\,
S(0) => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__4_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_1_n_0\
);
\g81__301_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_2_n_0\
);
\g81__301_carry__4_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_3_n_0\
);
\g81__301_carry__4_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_4_n_0\
);
\g81__301_carry__4_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_5_n_0\
);
\g81__301_carry__4_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_6_n_0\
);
\g81__301_carry__4_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_7_n_0\
);
\g81__301_carry__4_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__4_n_0\,
CO(3) => \g81__301_carry__5_n_0\,
CO(2) => \g81__301_carry__5_n_1\,
CO(1) => \g81__301_carry__5_n_2\,
CO(0) => \g81__301_carry__5_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__5_i_1_n_0\,
DI(2) => \g81__301_carry__5_i_2_n_0\,
DI(1) => \g81__301_carry__5_i_3_n_0\,
DI(0) => \g81__301_carry__5_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__5_i_5_n_0\,
S(2) => \g81__301_carry__5_i_6_n_0\,
S(1) => \g81__301_carry__5_i_7_n_0\,
S(0) => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__5_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_1_n_0\
);
\g81__301_carry__5_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_2_n_0\
);
\g81__301_carry__5_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_3_n_0\
);
\g81__301_carry__5_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_4_n_0\
);
\g81__301_carry__5_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_5_n_0\
);
\g81__301_carry__5_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_6_n_0\
);
\g81__301_carry__5_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_7_n_0\
);
\g81__301_carry__5_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__5_n_0\,
CO(3) => \NLW_g81__301_carry__6_CO_UNCONNECTED\(3),
CO(2) => \g81__301_carry__6_n_1\,
CO(1) => \g81__301_carry__6_n_2\,
CO(0) => \g81__301_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__301_carry__6_i_1_n_0\,
DI(1) => \g81__301_carry__6_i_2_n_0\,
DI(0) => \g81__301_carry__6_i_3_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__6_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \g81__301_carry__6_i_4_n_0\,
S(1) => \g81__301_carry__6_i_5_n_0\,
S(0) => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry__6_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_1_n_0\
);
\g81__301_carry__6_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_2_n_0\
);
\g81__301_carry__6_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_3_n_0\
);
\g81__301_carry__6_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_4_n_0\
);
\g81__301_carry__6_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_5_n_0\
);
\g81__301_carry__6_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_5\,
I1 => g84,
I2 => g83(2),
I3 => \g83__0_carry_n_5\,
O => \g81__301_carry_i_1_n_0\
);
\g81__301_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABEF"
)
port map (
I0 => \g81__261_carry_n_6\,
I1 => g84,
I2 => g83(1),
I3 => \g83__0_carry_n_6\,
O => \g81__301_carry_i_2_n_0\
);
\g81__301_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g81__261_carry_n_7\,
I1 => \g83__0_carry_n_7\,
O => \g81__301_carry_i_3_n_0\
);
\g81__301_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
I3 => \g81__261_carry_n_5\,
I4 => \g81__261_carry_n_4\,
I5 => \g81_carry__0_i_9_n_0\,
O => \g81__301_carry_i_4_n_0\
);
\g81__301_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DD22DD22D2DD2D2"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__261_carry_n_6\,
I2 => \g81__261_carry_n_5\,
I3 => \g83__0_carry_n_5\,
I4 => g83(2),
I5 => g84,
O => \g81__301_carry_i_5_n_0\
);
\g81__301_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22DD22DD2D22D2D"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
I2 => \g81__261_carry_n_6\,
I3 => \g83__0_carry_n_6\,
I4 => g83(1),
I5 => g84,
O => \g81__301_carry_i_6_n_0\
);
\g81__301_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
O => \g81__301_carry_i_7_n_0\
);
\g81__347_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__347_carry_n_0\,
CO(2) => \g81__347_carry_n_1\,
CO(1) => \g81__347_carry_n_2\,
CO(0) => \g81__347_carry_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \g81__347_carry_n_4\,
O(2) => \g81__347_carry_n_5\,
O(1) => \g81__347_carry_n_6\,
O(0) => \g81__347_carry_n_7\,
S(3) => \g81__347_carry_i_1_n_0\,
S(2) => \g81__347_carry_i_2_n_0\,
S(1) => \g81__347_carry_i_3_n_0\,
S(0) => \g81__347_carry_i_4_n_0\
);
\g81__347_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__347_carry_n_0\,
CO(3) => \NLW_g81__347_carry__0_CO_UNCONNECTED\(3),
CO(2) => \g81__347_carry__0_n_1\,
CO(1) => \g81__347_carry__0_n_2\,
CO(0) => \g81__347_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \g81__347_carry__0_n_4\,
O(2) => \g81__347_carry__0_n_5\,
O(1) => \g81__347_carry__0_n_6\,
O(0) => \g81__347_carry__0_n_7\,
S(3) => \g81__347_carry__0_i_1_n_0\,
S(2) => \g81__347_carry__0_i_2_n_0\,
S(1) => \g81__347_carry__0_i_3_n_0\,
S(0) => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_4\,
O => \g81__347_carry__0_i_1_n_0\
);
\g81__347_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_5\,
O => \g81__347_carry__0_i_2_n_0\
);
\g81__347_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_6\,
O => \g81__347_carry__0_i_3_n_0\
);
\g81__347_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_7\,
O => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_4\,
O => \g81__347_carry_i_1_n_0\
);
\g81__347_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_5\,
O => \g81__347_carry_i_2_n_0\
);
\g81__347_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__347_carry_i_3_n_0\
);
\g81__347_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__347_carry_i_4_n_0\
);
\g81__53_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__53_carry_n_0\,
CO(2) => \g81__53_carry_n_1\,
CO(1) => \g81__53_carry_n_2\,
CO(0) => \g81__53_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__53_carry_i_1_n_0\,
DI(1) => \g81__53_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__53_carry_n_4\,
O(2) => \g81__53_carry_n_5\,
O(1) => \g81__53_carry_n_6\,
O(0) => \NLW_g81__53_carry_O_UNCONNECTED\(0),
S(3) => \g81__53_carry_i_3_n_0\,
S(2) => \g81__53_carry_i_4_n_0\,
S(1) => \g81__53_carry_i_5_n_0\,
S(0) => \g81__53_carry_i_6_n_0\
);
\g81__53_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry_n_0\,
CO(3) => \g81__53_carry__0_n_0\,
CO(2) => \g81__53_carry__0_n_1\,
CO(1) => \g81__53_carry__0_n_2\,
CO(0) => \g81__53_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__53_carry__0_n_4\,
O(2) => \g81__53_carry__0_n_5\,
O(1) => \g81__53_carry__0_n_6\,
O(0) => \g81__53_carry__0_n_7\,
S(3) => \g81__53_carry__0_i_1_n_0\,
S(2) => \g81__53_carry__0_i_2_n_0\,
S(1) => \g81__53_carry__0_i_3_n_0\,
S(0) => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__53_carry__0_i_1_n_0\
);
\g81__53_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__53_carry__0_i_2_n_0\
);
\g81__53_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__53_carry__0_i_3_n_0\
);
\g81__53_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__0_n_0\,
CO(3) => \g81__53_carry__1_n_0\,
CO(2) => \g81__53_carry__1_n_1\,
CO(1) => \g81__53_carry__1_n_2\,
CO(0) => \g81__53_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__53_carry__1_n_4\,
O(2) => \g81__53_carry__1_n_5\,
O(1) => \g81__53_carry__1_n_6\,
O(0) => \g81__53_carry__1_n_7\,
S(3) => \g81__53_carry__1_i_1_n_0\,
S(2) => \g81__53_carry__1_i_2_n_0\,
S(1) => \g81__53_carry__1_i_3_n_0\,
S(0) => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__53_carry__1_i_1_n_0\
);
\g81__53_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_2_n_0\
);
\g81__53_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_3_n_0\
);
\g81__53_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__1_n_0\,
CO(3) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__53_carry__2_n_1\,
CO(1) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__53_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__53_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__53_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__53_carry__2_n_6\,
O(0) => \g81__53_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__53_carry__2_i_1_n_0\
);
\g81__53_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__53_carry_i_1_n_0\
);
\g81__53_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__53_carry_i_2_n_0\
);
\g81__53_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__53_carry_i_3_n_0\
);
\g81__53_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__53_carry_i_4_n_0\
);
\g81__53_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__53_carry_i_5_n_0\
);
\g81__53_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__53_carry_i_6_n_0\
);
\g81__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__92_carry_n_0\,
CO(2) => \g81__92_carry_n_1\,
CO(1) => \g81__92_carry_n_2\,
CO(0) => \g81__92_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__92_carry_i_1_n_0\,
DI(1) => \g81__92_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__92_carry_n_4\,
O(2) => \g81__92_carry_n_5\,
O(1) => \g81__92_carry_n_6\,
O(0) => \NLW_g81__92_carry_O_UNCONNECTED\(0),
S(3) => \g81__92_carry_i_3_n_0\,
S(2) => \g81__92_carry_i_4_n_0\,
S(1) => \g81__92_carry_i_5_n_0\,
S(0) => \g81__92_carry_i_6_n_0\
);
\g81__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry_n_0\,
CO(3) => \g81__92_carry__0_n_0\,
CO(2) => \g81__92_carry__0_n_1\,
CO(1) => \g81__92_carry__0_n_2\,
CO(0) => \g81__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__92_carry__0_n_4\,
O(2) => \g81__92_carry__0_n_5\,
O(1) => \g81__92_carry__0_n_6\,
O(0) => \g81__92_carry__0_n_7\,
S(3) => \g81__92_carry__0_i_1_n_0\,
S(2) => \g81__92_carry__0_i_2_n_0\,
S(1) => \g81__92_carry__0_i_3_n_0\,
S(0) => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__92_carry__0_i_1_n_0\
);
\g81__92_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__92_carry__0_i_2_n_0\
);
\g81__92_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__92_carry__0_i_3_n_0\
);
\g81__92_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__0_n_0\,
CO(3) => \g81__92_carry__1_n_0\,
CO(2) => \g81__92_carry__1_n_1\,
CO(1) => \g81__92_carry__1_n_2\,
CO(0) => \g81__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__92_carry__1_n_4\,
O(2) => \g81__92_carry__1_n_5\,
O(1) => \g81__92_carry__1_n_6\,
O(0) => \g81__92_carry__1_n_7\,
S(3) => \g81__92_carry__1_i_1_n_0\,
S(2) => \g81__92_carry__1_i_2_n_0\,
S(1) => \g81__92_carry__1_i_3_n_0\,
S(0) => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__92_carry__1_i_1_n_0\
);
\g81__92_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_2_n_0\
);
\g81__92_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_3_n_0\
);
\g81__92_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__1_n_0\,
CO(3) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__92_carry__2_n_1\,
CO(1) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__92_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__92_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__92_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__92_carry__2_n_6\,
O(0) => \g81__92_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__92_carry__2_i_1_n_0\
);
\g81__92_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__92_carry_i_1_n_0\
);
\g81__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__92_carry_i_2_n_0\
);
\g81__92_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__92_carry_i_3_n_0\
);
\g81__92_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__92_carry_i_4_n_0\
);
\g81__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__92_carry_i_5_n_0\
);
\g81__92_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__92_carry_i_6_n_0\
);
g81_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g81_carry_n_0,
CO(2) => g81_carry_n_1,
CO(1) => g81_carry_n_2,
CO(0) => g81_carry_n_3,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => g81_carry_i_2_n_0,
DI(1) => g81_carry_i_3_n_0,
DI(0) => '0',
O(3 downto 1) => NLW_g81_carry_O_UNCONNECTED(3 downto 1),
O(0) => g81_carry_n_7,
S(3) => g81_carry_i_4_n_0,
S(2) => g81_carry_i_5_n_0,
S(1) => g81_carry_i_6_n_0,
S(0) => g81_carry_i_7_n_0
);
\g81_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g81_carry_n_0,
CO(3) => \g81_carry__0_n_0\,
CO(2) => \g81_carry__0_n_1\,
CO(1) => \g81_carry__0_n_2\,
CO(0) => \g81_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81_carry__0_n_4\,
O(2) => \g81_carry__0_n_5\,
O(1) => \g81_carry__0_n_6\,
O(0) => \NLW_g81_carry__0_O_UNCONNECTED\(0),
S(3) => \g81_carry__0_i_5_n_0\,
S(2) => \g81_carry__0_i_6_n_0\,
S(1) => \g81_carry__0_i_7_n_0\,
S(0) => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
I4 => g83(7),
I5 => \g83__0_carry__0_n_4\,
O => \g81_carry__0_i_1_n_0\
);
\g81_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81_carry__0_i_10_n_0\
);
\g81_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81_carry__0_i_11_n_0\
);
\g81_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
O => \g81_carry__0_i_12_n_0\
);
\g81_carry__0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
O => \g81_carry__0_i_13_n_0\
);
\g81_carry__0_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
O => \g81_carry__0_i_14_n_0\
);
\g81_carry__0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81_carry__0_i_15_n_0\
);
\g81_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_10_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => g83(6),
I5 => \g83__0_carry__0_n_5\,
O => \g81_carry__0_i_2_n_0\
);
\g81_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
I4 => g83(5),
I5 => \g83__0_carry__0_n_6\,
O => \g81_carry__0_i_3_n_0\
);
\g81_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C33CC33CA5A55A5A"
)
port map (
I0 => g83(5),
I1 => \g83__0_carry__0_n_6\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g83__0_carry_n_4\,
I4 => g83(3),
I5 => g84,
O => \g81_carry__0_i_4_n_0\
);
\g81_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81_carry__0_i_5_n_0\
);
\g81_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81_carry__0_i_6_n_0\
);
\g81_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81_carry__0_i_7_n_0\
);
\g81_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81_carry__0_i_9_n_0\
);
\g81_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__0_n_0\,
CO(3) => \g81_carry__1_n_0\,
CO(2) => \g81_carry__1_n_1\,
CO(1) => \g81_carry__1_n_2\,
CO(0) => \g81_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81_carry__1_n_4\,
O(2) => \g81_carry__1_n_5\,
O(1) => \g81_carry__1_n_6\,
O(0) => \g81_carry__1_n_7\,
S(3) => \g81_carry__1_i_5_n_0\,
S(2) => \g81_carry__1_i_6_n_0\,
S(1) => \g81_carry__1_i_7_n_0\,
S(0) => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(7),
I1 => \g83__0_carry__0_n_4\,
I2 => g84,
I3 => g83(9),
I4 => \g83__0_carry__1_n_2\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_1_n_0\
);
\g81_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(6),
I1 => \g83__0_carry__0_n_5\,
I2 => g84,
I3 => g83(8),
I4 => \g83__0_carry__1_n_7\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_2_n_0\
);
\g81_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(5),
I2 => \g83__0_carry__0_n_6\,
I3 => \g81_carry__1_i_9_n_0\,
I4 => g83(9),
I5 => \g83__0_carry__1_n_2\,
O => \g81_carry__1_i_3_n_0\
);
\g81_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(4),
I2 => \g83__0_carry__0_n_7\,
I3 => \g81_carry__0_i_12_n_0\,
I4 => g83(8),
I5 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_4_n_0\
);
\g81_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_5_n_0\
);
\g81_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_6_n_0\
);
\g81_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_7_n_0\
);
\g81_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_4\,
I1 => g83(7),
I2 => g84,
O => \g81_carry__1_i_9_n_0\
);
\g81_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__1_n_0\,
CO(3) => \NLW_g81_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81_carry__2_n_1\,
CO(1) => \NLW_g81_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81_carry__2_n_6\,
O(0) => \g81_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81_carry__2_i_3_n_0\
);
\g81_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_1_n_0\
);
\g81_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_2_n_0\
);
\g81_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81_carry__2_i_3_n_0\
);
g81_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_1_n_0
);
g81_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => g81_carry_i_2_n_0
);
g81_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => g81_carry_i_3_n_0
);
g81_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => g81_carry_i_4_n_0
);
g81_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => g81_carry_i_5_n_0
);
g81_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_6_n_0
);
g81_carry_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => g81_carry_i_7_n_0
);
\g83__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g83__0_carry_n_0\,
CO(2) => \g83__0_carry_n_1\,
CO(1) => \g83__0_carry_n_2\,
CO(0) => \g83__0_carry_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry_i_1_n_0\,
DI(2) => \g83__0_carry_i_2_n_0\,
DI(1) => \g83__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \g83__0_carry_n_4\,
O(2) => \g83__0_carry_n_5\,
O(1) => \g83__0_carry_n_6\,
O(0) => \g83__0_carry_n_7\,
S(3) => \g83__0_carry_i_4_n_0\,
S(2) => \g83__0_carry_i_5_n_0\,
S(1) => \g83__0_carry_i_6_n_0\,
S(0) => \g83__0_carry_i_7_n_0\
);
\g83__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry_n_0\,
CO(3) => \g83__0_carry__0_n_0\,
CO(2) => \g83__0_carry__0_n_1\,
CO(1) => \g83__0_carry__0_n_2\,
CO(0) => \g83__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry__0_i_1_n_0\,
DI(2) => \g83__0_carry__0_i_2_n_0\,
DI(1) => \g83__0_carry__0_i_3_n_0\,
DI(0) => \g83__0_carry__0_i_4_n_0\,
O(3) => \g83__0_carry__0_n_4\,
O(2) => \g83__0_carry__0_n_5\,
O(1) => \g83__0_carry__0_n_6\,
O(0) => \g83__0_carry__0_n_7\,
S(3) => \g83__0_carry__0_i_5_n_0\,
S(2) => \g83__0_carry__0_i_6_n_0\,
S(1) => \g83__0_carry__0_i_7_n_0\,
S(0) => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
O => \g83__0_carry__0_i_1_n_0\
);
\g83__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
O => \g83__0_carry__0_i_2_n_0\
);
\g83__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
O => \g83__0_carry__0_i_3_n_0\
);
\g83__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
O => \g83__0_carry__0_i_4_n_0\
);
\g83__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry__0_i_1_n_0\,
I1 => rgb888(7),
I2 => rgb888(15),
I3 => rgb888(23),
O => \g83__0_carry__0_i_5_n_0\
);
\g83__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
I3 => \g83__0_carry__0_i_2_n_0\,
O => \g83__0_carry__0_i_6_n_0\
);
\g83__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
I3 => \g83__0_carry__0_i_3_n_0\,
O => \g83__0_carry__0_i_7_n_0\
);
\g83__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
I3 => \g83__0_carry__0_i_4_n_0\,
O => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry__0_n_0\,
CO(3 downto 2) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \g83__0_carry__1_n_2\,
CO(0) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_g83__0_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \g83__0_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(15),
I1 => rgb888(7),
I2 => rgb888(23),
O => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
O => \g83__0_carry_i_1_n_0\
);
\g83__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
O => \g83__0_carry_i_2_n_0\
);
\g83__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_3_n_0\
);
\g83__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
I3 => \g83__0_carry_i_1_n_0\,
O => \g83__0_carry_i_4_n_0\
);
\g83__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
I3 => \g83__0_carry_i_2_n_0\,
O => \g83__0_carry_i_5_n_0\
);
\g83__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
I3 => \g83__0_carry_i_3_n_0\,
O => \g83__0_carry_i_6_n_0\
);
\g83__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_7_n_0\
);
g84_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g84_carry_n_0,
CO(2) => g84_carry_n_1,
CO(1) => g84_carry_n_2,
CO(0) => g84_carry_n_3,
CYINIT => '1',
DI(3) => g84_carry_i_1_n_0,
DI(2) => g84_carry_i_2_n_0,
DI(1) => g84_carry_i_3_n_0,
DI(0) => g84_carry_i_4_n_0,
O(3 downto 0) => NLW_g84_carry_O_UNCONNECTED(3 downto 0),
S(3) => g84_carry_i_5_n_0,
S(2) => g84_carry_i_6_n_0,
S(1) => g84_carry_i_7_n_0,
S(0) => g84_carry_i_8_n_0
);
\g84_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g84_carry_n_0,
CO(3 downto 1) => \NLW_g84_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => g84,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \g84_carry__0_i_1_n_0\,
O(3 downto 0) => \NLW_g84_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \g84_carry__0_i_2_n_0\
);
\g84_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_1_n_0\
);
\g84_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_2_n_0\
);
g84_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_1_n_0
);
g84_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_2_n_0
);
g84_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_3_n_0
);
g84_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_4_n_0
);
g84_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_5_n_0
);
g84_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_6_n_0
);
g84_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_7_n_0
);
g84_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_8_n_0
);
\g8[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_7\,
O => g810_in(0)
);
\g8[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_6\,
O => g810_in(1)
);
\g8[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_5\,
O => g810_in(2)
);
\g8[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_4\,
O => g810_in(3)
);
\g8[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_7\,
O => g810_in(4)
);
\g8[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_6\,
O => g810_in(5)
);
\g8[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_5\,
O => g810_in(6)
);
\g8[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_4\,
O => g810_in(7)
);
\g8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(0),
Q => g8(0),
R => '0'
);
\g8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(1),
Q => g8(1),
R => '0'
);
\g8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(2),
Q => g8(2),
R => '0'
);
\g8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(3),
Q => g8(3),
R => '0'
);
\g8_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(4),
Q => g8(4),
R => '0'
);
\g8_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(5),
Q => g8(5),
R => '0'
);
\g8_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(6),
Q => g8(6),
R => '0'
);
\g8_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(7),
Q => g8(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_g8_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_g8_0_0 : entity is "system_rgb888_to_g8_0_0,rgb888_to_g8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_g8_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_g8_0_0 : entity is "rgb888_to_g8,Vivado 2016.4";
end system_rgb888_to_g8_0_0;
architecture STRUCTURE of system_rgb888_to_g8_0_0 is
begin
U0: entity work.system_rgb888_to_g8_0_0_rgb888_to_g8
port map (
clk => clk,
g8(7 downto 0) => g8(7 downto 0),
rgb888(23 downto 0) => rgb888(23 downto 0)
);
end STRUCTURE;
| mit | 410fb5034152669e18f57bec3ba46ded | 0.491835 | 2.249335 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/hdl/hall_sensor_decoder.vhd | 2 | 5,081 | -------------------------------------------------------------------------------
-- Title : Hall Sensor Decoder
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Company : Roboterclub Aachen e. V.
-------------------------------------------------------------------------------
-- Description:
--
-- _____ _______ _____
-- A ___| |_____| |_____|
-- _____ ___ _______
-- B _____| |_____| |_____|
-- _____ _______
-- C _______| |___________| |_
--
-- step_p 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
-- dir_p 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
package hall_sensor_decoder_pkg is
component hall_sensor_decoder
port (
hall_sensor_p : in hall_sensor_type;
step_p : out std_logic;
dir_p : out std_logic;
error_p : out std_logic;
clk : in std_logic);
end component;
end hall_sensor_decoder_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
entity hall_sensor_decoder is
port (
hall_sensor_p : in hall_sensor_type;
step_p : out std_logic; -- detected step_p ('1' for one clock cycle)
dir_p : out std_logic; -- count direction (1 = up, 0 = down)
error_p : out std_logic; -- illegal transition (two or more bits change at the same time)
clk : in std_logic -- system clock
);
end hall_sensor_decoder;
architecture behavioral of hall_sensor_decoder is
signal a_buf : std_logic_vector(1 downto 0) := (others => '0');
signal b_buf : std_logic_vector(1 downto 0) := (others => '0');
signal c_buf : std_logic_vector(1 downto 0) := (others => '0');
begin
-- edge detection
process
begin
wait until rising_edge(clk);
a_buf <= a_buf(0) & hall_sensor_p.a;
b_buf <= b_buf(0) & hall_sensor_p.b;
c_buf <= c_buf(0) & hall_sensor_p.c;
end process;
-- signal decoding
comb : process(a_buf, b_buf, c_buf)
variable state : std_logic_vector(5 downto 0);
begin
state := a_buf(0) & b_buf(0) & c_buf(0) & a_buf(1) & b_buf(1) & c_buf(1);
case state is
-- new -> old
-- unchanged valid codes
when "101" & "101" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "100" & "100" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "110" & "110" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "010" & "010" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "011" & "011" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "001" & "001" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
-- CW
when "101" & "100" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "100" & "110" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "110" & "010" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "010" & "011" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "011" & "001" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
when "001" & "101" => step_p <= '1'; dir_p <= '0'; error_p <= '0';
-- CCW
when "101" & "001" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "001" & "011" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "011" & "010" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "010" & "110" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "110" & "100" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
when "100" & "101" => step_p <= '1'; dir_p <= '1'; error_p <= '0';
-- From invalid to any valid
when "101" & "000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "101" & "111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "100" & "000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "100" & "111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "110" & "000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "110" & "111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "010" & "000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "010" & "111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "011" & "000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "011" & "111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "001" & "000" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
when "001" & "111" => step_p <= '0'; dir_p <= '0'; error_p <= '0';
-- All other invalid
when others => step_p <= '0'; dir_p <= '0'; error_p <= '1';
end case;
end process;
end behavioral;
| bsd-3-clause | 9bde75f9e86082460dd4fc1aefe47421 | 0.407991 | 3.031623 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zybo_hdmi/zybo_hdmi.srcs/sources_1/new/zybo_hdmi.vhd | 6 | 2,777 | ----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; | mit | 590ebdb767663a1486d06da689b6bf98 | 0.46381 | 3.798906 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/sim/system_rst_ps7_0_100M_0.vhd | 1 | 5,839 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY system_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_ps7_0_100M_0;
ARCHITECTURE system_rst_ps7_0_100M_0_arch OF system_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_ps7_0_100M_0_arch;
| mit | 29dbeafad3173f401c614a7176220056 | 0.706114 | 3.560366 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dotcmul.vhd | 2 | 16,584 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
use work.Bit_Manipulation.all;
-------------------------------------------------------------------------------
entity dotcmul is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
length_kern_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((sig_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end dotcmul;
--=----------------------------------------------------------------------------
architecture archi_dotcmul of dotcmul is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_addr_pipe_depth : integer := 11;
constant c_ind_width : integer := cmdreg_width - 2;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_dotcmul_state is (st_init, st_startpipe, st_performop, st_copy);
type t_datastate is (st_data_y1, st_data_y2);
signal s_state : t_dotcmul_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_data_y1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_y2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_u2 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u1_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u2_r : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y1 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_y2 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u1 : std_logic_vector((sig_width - 1) downto 0);
signal s_out_u2 : std_logic_vector((sig_width - 1) downto 0);
signal s_datastate : t_datastate;
signal s_datastate_n1 : t_datastate;
type t_addr_pipe is array(0 to c_addr_pipe_depth - 1) of unsigned((cmdreg_width - 1) downto 0);
type t_wr_pipe is array(0 to c_addr_pipe_depth - 1) of std_logic;
signal s_addr_pipe : t_addr_pipe;
signal s_wr_pipe : t_wr_pipe;
signal s_next_index : unsigned((c_ind_width - 1) downto 0);
signal s_next_group : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index_rev : unsigned((c_ind_width - 1) downto 0);
signal s_addr_r_m0_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r_m1_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_imag_part : std_logic;
-- signal s_module : integer;
signal s_mask_reg : unsigned((cmdreg_width - 1) downto 0);
signal s_length_kern : unsigned((cmdreg_width - 1) downto 0);
begin -- archs_dotcmul
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_dotcmul : process (clk)
begin -- process p_dotcmul
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
-- s_dsp_bus.addr_r_m0 <= (others => '0');
-- s_dsp_bus.addr_w_m0 <= (others => '0');
-- s_dsp_bus.wr_en_m0 <= '0';
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m2 <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
-- s_count <= 0;
if s_dsp_bus.op_done = '0' then
s_state <= st_performop;
end if;
when st_performop =>
-- In this state : reading, complex multiplication and writting
-- are done concurently
if s_sample_index = s_length then
--s_dsp_bus.wr_en_m1 <= '1';
s_state <= st_copy;
end if;
when st_copy =>
-- write last words to memory
-- s_count <= s_count + 1;
-- if(s_count = 10) then
if(s_dsp_bus.wr_en_m0 = '0') then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
end if;
when others => null;
end case;
end if;
end if;
end process p_dotcmul;
-------------------------------------------------------------------------------
-- Data states
-------------------------------------------------------------------------------
p_data : process (clk)
begin -- process p_data
if rising_edge(clk) then -- rising clock edge
if s_state = st_init then
-- initial state is calculated as a function of pipeline depth
-- s_datastate <= st_data_y1;
s_datastate <= st_data_y2;
s_dsp_bus.alu_select <= alu_mul;
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
else
case s_datastate is
when st_data_y1 =>
s_datastate <= st_data_y2;
when others => -- st_data_y2
s_datastate <= st_data_y1;
s_dsp_bus.alu_select <= alu_cmul_conj;
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
end case;
end if;
end if;
end process p_data;
-------------------------------------------------------------------------------
-- load data from memory
-------------------------------------------------------------------------------
p_dataload : process (clk)
begin -- process p_dataload
if rising_edge(clk) then -- rising clock edge
case s_datastate is
when st_data_y1 =>
s_data_u1_r <= data_in_m1;
s_data_y1_r <= data_in_m0;
when others => -- st_data_y2
dispsig("sigcmul", to_integer(s_sample_index) + 1, to_integer(signed(s_data_y1_r)));
s_data_y1 <= s_data_y1_r;
s_data_y2 <= data_in_m0;
s_data_u2 <= data_in_m1;
s_data_u1 <= s_data_u1_r;
end case;
end if;
end process p_dataload;
-------------------------------------------------------------------------------
-- store data to memory
-------------------------------------------------------------------------------
p_datastore : process (clk)
begin -- process p_datastore
if rising_edge(clk) then -- rising clock edge
s_datastate_n1 <= s_datastate;
case s_datastate_n1 is
when st_data_y1 =>
-- states y1, y2 inverted for writing because pipe length is odd
s_dsp_bus.data_out_m0 <= s_out_y1;
s_out_y2_r <= s_out_y2;
when others => -- st_data_y1
s_dsp_bus.data_out_m0 <= s_out_y2_r;
s_out_y1 <= result1;
s_out_y2 <= result2;
end case;
end if;
end process p_datastore;
-------------------------------------------------------------------------------
-- Compute address of reading words
-------------------------------------------------------------------------------
p_addr_comput : process (clk)
begin -- process p_addr_comput
if rising_edge(clk) then -- rising clock edge
if s_state = st_init then
s_sample_index <= to_unsigned(0, c_ind_width);
s_imag_part <= '0';
else
-- the real datastate is shifted of 2 stages because of pipeline delay
if (s_datastate = st_data_y2) then
-- y1 being read, compute index of y2
s_imag_part <= '1';
-- else compute index of next sample
-- elsif (s_next_index < s_length) then
else
-- increment index
s_sample_index <= s_next_index((c_ind_width - 1) downto 0);
s_imag_part <= '0';
end if;
end if;
end if;
end process p_addr_comput;
s_next_index <= s_sample_index + 1;
-------------------------------------------------------------------------------
-- address pipe : output is writting address
-------------------------------------------------------------------------------
p_addr_pipe : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_addr_pipe(0) <= s_addr_r_m0_tmp;
if(s_state = st_performop) then
s_wr_pipe(0) <= '1';
else
s_wr_pipe(0) <= '0';
end if;
for i in 0 to c_addr_pipe_depth - 2 loop
s_addr_pipe(i + 1) <= s_addr_pipe(i);
s_wr_pipe(i + 1) <= s_wr_pipe(i);
end loop;
end if;
end process p_addr_pipe;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
-- alu inputs
s_dsp_bus.mul_in_a1 <= s_data_y1;
s_dsp_bus.mul_in_a2 <= s_data_y2;
s_dsp_bus.mul_in_b1 <= s_data_u1;
s_dsp_bus.mul_in_b2 <= s_data_u2;
-- Writing and reading address of the memory
s_sample_index_rev <= bit_reverse(s_sample_index);
s_addr_r_m0_tmp((cmdreg_width - 1) downto (c_ind_width + 1)) <= (others => '0');
s_addr_r_m1_tmp((cmdreg_width - 1) downto (c_ind_width + 1)) <= (others => '0');
s_addr_r_m1_tmp((c_ind_width) downto 1) <= s_sample_index;
-- index with bit reverse if needed
s_addr_r_m0_tmp((c_ind_width) downto 1) <= s_sample_index when opflag_select(opflagbit_bitrev) = '0' else
s_sample_index((c_ind_width - 1) downto 4) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 4))
when length_kern_reg(4) = '1' else
s_sample_index((c_ind_width - 1) downto 5) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 5))
when length_kern_reg(5) = '1' else
s_sample_index((c_ind_width - 1) downto 6) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 6))
when length_kern_reg(6) = '1' else
s_sample_index((c_ind_width - 1) downto 7) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 7))
when length_kern_reg(7) = '1' else
s_sample_index((c_ind_width - 1) downto 8) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 8))
when length_kern_reg(8) = '1' else
s_sample_index((c_ind_width - 1) downto 9) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 9))
when length_kern_reg(9) = '1' else
s_sample_index((c_ind_width - 1) downto 10) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 10))
when length_kern_reg(10) = '1' else
s_sample_index((c_ind_width - 1) downto 11) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 11))
when length_kern_reg(11) = '1' else
s_sample_index((c_ind_width - 1) downto 12) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 12))
when length_kern_reg(12) = '1' else
s_sample_index((c_ind_width - 1) downto 13) &
s_sample_index_rev((c_ind_width - 1) downto (c_ind_width - 13))
when length_kern_reg(13) = '1' else
s_sample_index_rev;
s_addr_r_m0_tmp(0) <= s_imag_part;
s_addr_r_m1_tmp(0) <= s_imag_part;
p_addr_delay : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_dsp_bus.addr_r_m0 <= s_addr_r_m0_tmp;
s_dsp_bus.addr_m1 <= unsigned(bitbit_and(std_logic_vector(s_addr_r_m1_tmp),
std_logic_vector(s_mask_reg)));
end if;
end process p_addr_delay;
s_dsp_bus.addr_w_m0 <= s_addr_pipe(c_addr_pipe_depth - 1);
s_dsp_bus.wr_en_m0 <= s_wr_pipe(c_addr_pipe_depth - 1);
-- specific index relations
s_length <= unsigned(length_reg);
-- left shift because real length is double (complex values)
s_length_kern <= unsigned(length_kern_reg((cmdreg_data_width - 2) downto 0) & '0');
s_mask_reg <= s_length_kern - 1;
-- s_module <= module(signed(s_data_y1), signed(s_data_y2));
end archi_dotcmul;
| gpl-3.0 | 2bb583468db56fdc0d22e505c7609d9e | 0.440666 | 3.687792 | false | false | false | false |
loa-org/loa-hdl | modules/spw_node/tb/spw_node_tb.vhd | 1 | 3,842 | -------------------------------------------------------------------------------
-- Title : Testbench for SpW Node
-------------------------------------------------------------------------------
-- Author : Carl Treudler
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.spw_node_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity spw_node_tb is
end entity spw_node_tb;
-------------------------------------------------------------------------------
architecture behavourial of spw_node_tb is
constant BASE_ADDRESS : integer := 16#0100#;
signal do_p : std_logic;
signal so_p : std_logic;
signal di_p : std_logic;
signal si_p : std_logic;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
-- component ports
signal clk, reset : std_logic := '0';
begin
-- loop back
si_p <= so_p;
di_p <= do_p;
spw_node_1 : entity work.spw_node
generic map (
BASE_ADDRESS => BASE_ADDRESS,
RESET_IMPL => sync)
port map (
do_p => do_p,
so_p => so_p,
di_p => di_p,
si_p => si_p,
bus_o => bus_o,
bus_i => bus_i,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate reset signal
process
begin
wait until rising_edge(clk);
reset <= '1';
wait until rising_edge(clk);
reset <= '0';
wait for 500 ms;
end process;
-- waveform generation
process
begin
wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk);
readWord(addr => BASE_ADDRESS+1, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS+2, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS+2, data => 16#0203#, bus_i => bus_i, clk => clk);
wait for 10 us;
readWord(addr => BASE_ADDRESS+1, bus_i => bus_i, clk => clk);
wait for 10 us;
readWord(addr => BASE_ADDRESS+1, bus_i => bus_i, clk => clk);
wait for 10 us;
readWord(addr => BASE_ADDRESS+1, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS, data => 16#0055#, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS, data => 16#0056#, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS, data => 16#0057#, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS, data => 16#0058#, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS, data => 16#0059#, bus_i => bus_i, clk => clk);
wait for 10 us;
readWord(addr => BASE_ADDRESS+1, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
wait for 100 us;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
wait for 100 us;
end process;
end architecture behavourial;
| bsd-3-clause | 170c1e3c0b8b4430e21fbde3c9e8c49d | 0.503123 | 3.537753 | false | false | false | false |
loa-org/loa-hdl | modules/servo/hdl/servo_sequencer.vhd | 2 | 5,041 | -------------------------------------------------------------------------------
-- Title : Servo Sequencer
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Generates eight periode begin signals shifted by 2.5ms
-- (8 x 2.5ms = 20ms). An additional helper signal is generated ~0.85 ms after
-- the periode begin signal.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package servo_sequencer_pkg is
component servo_sequencer is
port (
load_p : out std_logic_vector(7 downto 0);
enable_p : out std_logic_vector(7 downto 0);
counter_p : out std_logic_vector(15 downto 0);
reset : in std_logic;
clk : in std_logic);
end component servo_sequencer;
end package servo_sequencer_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity servo_sequencer is
port (
load_p : out std_logic_vector(7 downto 0);
enable_p : out std_logic_vector(7 downto 0);
-- Servo periode counter. The channel compare this value to their own value
-- and keep their output set to one as long as the counter is smaller then
-- the compare value.
counter_p : out std_logic_vector(15 downto 0);
reset : in std_logic; -- Output disable (if set to '1')
clk : in std_logic -- must be 50 MHz or the constants have
-- to be adapted.
);
end servo_sequencer;
-------------------------------------------------------------------------------
architecture behavioral of servo_sequencer is
constant CLK_FREQENCY : real := real(50e6); -- 50 MHz
-- 2.5ms
constant PERIODE_SLICE_TICKS : integer :=
integer((CLK_FREQENCY * 2.5e-3) - 1.0);
-- ~0.85ms
constant PERIODE_SIGNAL_TICKS : integer :=
integer((1.5e-3 - (real(2**16) / CLK_FREQENCY / 2.0)) * CLK_FREQENCY - 1.0);
type servo_sequencer_state_type is (STATE_IDLE, STATE_LOAD, STATE_WAIT, STATE_SIGNAL);
type servo_sequencer_type is record
state : servo_sequencer_state_type;
periode_counter : integer range 0 to PERIODE_SLICE_TICKS;
signal_counter : integer range 0 to 2**16;
index : integer range 0 to 8;
load : std_logic_vector(7 downto 0);
enable : std_logic_vector(7 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : servo_sequencer_type := (
state => STATE_LOAD,
periode_counter => 0,
signal_counter => 0,
index => 0,
load => (others => '0'),
enable => (others => '0'));
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(r, r.enable, r.index, r.load, r.periode_counter,
r.signal_counter, r.state, reset)
variable v : servo_sequencer_type;
begin
v := r;
-- set default values
v.enable := (others => '0');
v.load := (others => '0');
v.periode_counter := r.periode_counter + 1;
if v.periode_counter = PERIODE_SLICE_TICKS then
v.periode_counter := 0;
v.index := (r.index + 1) mod 8;
v.state := STATE_LOAD;
elsif v.periode_counter = PERIODE_SIGNAL_TICKS then
v.state := STATE_SIGNAL;
end if;
case r.state is
when STATE_LOAD =>
v.load(r.index) := '1';
v.state := STATE_WAIT;
when STATE_WAIT =>
v.signal_counter := 0;
v.enable(r.index) := '1';
when STATE_SIGNAL =>
v.signal_counter := r.signal_counter + 1;
if v.signal_counter = 2**16 then
v.signal_counter := 0;
v.state := STATE_IDLE;
else
v.enable(r.index) := '1';
end if;
when others => null;
end case;
if reset = '1' then
v.state := STATE_LOAD;
v.signal_counter := 0;
v.periode_counter := 0;
v.index := 0;
v.load := (others => '0');
v.enable := (others => '0');
end if;
-- register outputs
counter_p <= std_logic_vector(to_unsigned(r.signal_counter, counter_p'length));
load_p <= r.load;
enable_p <= r.enable;
rin <= v;
end process comb_proc;
end behavioral;
| bsd-3-clause | 087b7ff5396a787d37f72ca8c576bf98 | 0.478675 | 4.118464 | false | false | false | false |
ashikpoojari/Hardware-Security | PUF Lab/Students_PUFS/puf_lab_mos283_ad3572/Hex2SevenSegConverter.vhd | 2 | 895 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Hex2LED is
Port ( CLK: in STD_LOGIC; X : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end Hex2LED;
architecture Behavioral of Hex2LED is
begin
process (CLK, X)
begin
case X is
when "0000" => Y <= "11000000";
when "0001" => Y <= "11111001";
when "0010" => Y <= "10100100";
when "0011" => Y <= "10110000";
when "0100" => Y <= "10011001";
when "0101" => Y <= "10010010";
when "0110" => Y <= "10000010";
when "0111" => Y <= "11111000";
when "1000" => Y <= "10000000";
when "1001" => Y <= "10010000";
when "1010" => Y <= "10001000";
when "1011" => Y <= "10000011";
when "1100" => Y <= "11000110";
when "1101" => Y <= "10100001";
when "1110" => Y <= "10000110";
when others => Y <= "10001110";
end case;
end process;
end Behavioral;
| mit | 7c729d25b3ad4c972eee6a0ae1a6b75d | 0.603352 | 2.905844 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/txt_util.vhd | 2 | 15,745 | -- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- The package provides a means to output text and
-- manipulate strings.
--
-- The basic usage is like this: >> print(s); <<
-- (where s is any string)
-- To print something which is not a string it has to be converted
-- into a string first. For this purpose the package contains
-- conversion functions called >> str(...) <<.
-- For example a std_logic_vector slv would be printed like this:
-- >> print(str(slv)); <<. To print several items on one line the
-- items have to concatenated as strings with the "&" operator eg:
-- >> print("The value of slv is "& str(slv)); <<
-- The string functions can also be used in assert statements as shown
-- in the example below:
-- >> assert DIN = "0101" <<
-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
-- >> severity Error; <<
--
--
--
-- -------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| mit | 6c3bc17a32b8139f94a2859e175acd51 | 0.478247 | 3.839307 | false | false | false | false |
loa-org/loa-hdl | modules/utils/hdl/text_pkg.vhd | 2 | 15,220 | -- from http://www.stefanvhdl.com/vhdl/vhdl/txt_util.vhd
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package text_pkg is
-- prints a message to the screen
procedure print(text : string);
-- prints the message when active
-- useful for debug switches
procedure print(active : boolean; text : string);
-- converts std_logic into a character
function chr(sl : std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv : std_logic_vector) return string;
-- converts boolean into a string
function str(b : boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int : integer) return character;
-- converts integer into string using specified base
function str(int : integer; base : integer) return string;
-- converts integer to string, using base 10
function str(int : integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv : std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c : character) return character;
-- convert a character to lower case
function to_lower(c : character) return character;
-- convert a string to upper case
function to_upper(s : string) return string;
-- convert a string to lower case
function to_lower(s : string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c : character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string);
-- print string to a file and start new line
procedure print(file out_file : text;
new_string : in string);
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character);
procedure str_write(file out_file : text;
new_string : in string);
end text_pkg;
package body text_pkg is
-- prints text to the screen
procedure print(text : string) is
variable msg_line : line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active : boolean; text : string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl : std_logic) return character is
variable c : character;
begin
case sl is
when 'U' => c := 'U';
when 'X' => c := 'X';
when '0' => c := '0';
when '1' => c := '1';
when 'Z' => c := 'Z';
when 'W' => c := 'W';
when 'L' => c := 'L';
when 'H' => c := 'H';
when '-' => c := '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl : std_logic) return string is
variable s : string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv : std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b : boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int : integer) return character is
variable c : character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int : integer; base : integer) return string is
variable temp : string(1 to 10);
variable num : integer;
variable abs_int : integer;
variable len : integer := 1;
variable power : integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int : integer) return string is
begin
return str(int, 10);
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv : std_logic_vector) return string is
variable hexlen : integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'LEFT+1)/4;
if (slv'LEFT+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'LEFT downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
----------------------------------------------------------------------------
-- functions to manipulate strings
-- convert a character to upper case
function to_upper(c : character) return character is
variable u : character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c : character) return character is
variable l : character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s : string) return string is
variable uppercase : string (s'range);
begin
for i in s'range loop
uppercase(i) := to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s : string) return string is
variable lowercase : string (s'range);
begin
for i in s'range loop
lowercase(i) := to_lower(s(i));
end loop;
return lowercase;
end to_lower;
----------------------------------------------------------------------------
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c : character) return std_logic is
variable sl : std_logic;
begin
case c is
when 'U' => sl := 'U';
when 'X' => sl := 'X';
when '0' => sl := '0';
when '1' => sl := '1';
when 'Z' => sl := 'Z';
when 'W' => sl := 'W';
when 'L' => sl := 'L';
when 'H' => sl := 'H';
when '-' => sl := '-';
when others => sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s : string) return std_logic_vector is
variable slv : std_logic_vector(s'high-s'low downto 0);
variable k : integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------------------------------------------------------------------
-- file I/O
----------------------------------------------------------------------------
-- read variable length string from input file
procedure str_read(file in_file : text;
res_string : out string) is
variable l : line;
variable c : character;
variable is_string : boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file : text;
new_string : in string) is
variable l : line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file : text;
char : in character) is
variable l : line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file : text;
new_string : in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end text_pkg;
| bsd-3-clause | f9dc590c8609f8b26f90f594070855a2 | 0.456965 | 3.883644 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/synth/system_debounce_0_0.vhd | 4 | 3,776 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:debounce:1.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_debounce_0_0 IS
PORT (
clk : IN STD_LOGIC;
signal_in : IN STD_LOGIC;
signal_out : OUT STD_LOGIC
);
END system_debounce_0_0;
ARCHITECTURE system_debounce_0_0_arch OF system_debounce_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_debounce_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT debounce IS
PORT (
clk : IN STD_LOGIC;
signal_in : IN STD_LOGIC;
signal_out : OUT STD_LOGIC
);
END COMPONENT debounce;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_debounce_0_0_arch: ARCHITECTURE IS "debounce,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_debounce_0_0_arch : ARCHITECTURE IS "system_debounce_0_0,debounce,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_debounce_0_0_arch: ARCHITECTURE IS "system_debounce_0_0,debounce,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=debounce,x_ipVersion=1.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : debounce
PORT MAP (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
END system_debounce_0_0_arch;
| mit | 048632816da22cbc2978e1ce5c4ce01d | 0.744174 | 4.012752 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_0/affine_block_uint_to_ieee754_fp_0_0_sim_netlist.vhdl | 1 | 30,710 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_0/affine_block_uint_to_ieee754_fp_0_0_sim_netlist.vhdl
-- Design : affine_block_uint_to_ieee754_fp_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_0_uint_to_ieee754_fp is
port (
\y[13]\ : out STD_LOGIC;
\y[23]\ : out STD_LOGIC;
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y[22]\ : out STD_LOGIC;
\y[20]\ : out STD_LOGIC;
\y[18]\ : out STD_LOGIC;
\y[22]_0\ : out STD_LOGIC;
\y[22]_1\ : out STD_LOGIC;
\y[21]\ : out STD_LOGIC;
\y[20]_0\ : out STD_LOGIC;
\x_9__s_port_]\ : in STD_LOGIC;
\x[9]_0\ : in STD_LOGIC;
\x[9]_1\ : in STD_LOGIC;
\x[9]_2\ : in STD_LOGIC;
\x[9]_3\ : in STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
\x[9]_4\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_out : in STD_LOGIC_VECTOR ( 0 to 0 );
\x[9]_5\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_uint_to_ieee754_fp_0_0_uint_to_ieee754_fp : entity is "uint_to_ieee754_fp";
end affine_block_uint_to_ieee754_fp_0_0_uint_to_ieee754_fp;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_0_uint_to_ieee754_fp is
signal mantissa2_carry_i_1_n_0 : STD_LOGIC;
signal mantissa2_carry_i_2_n_0 : STD_LOGIC;
signal mantissa2_carry_i_3_n_0 : STD_LOGIC;
signal mantissa2_carry_i_4_n_0 : STD_LOGIC;
signal mantissa2_carry_n_2 : STD_LOGIC;
signal mantissa2_carry_n_3 : STD_LOGIC;
signal \x_9__s_net_1\ : STD_LOGIC;
signal \^y[13]\ : STD_LOGIC;
signal \y[13]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^y[18]\ : STD_LOGIC;
signal \y[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \^y[20]\ : STD_LOGIC;
signal \^y[20]_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \^y[21]\ : STD_LOGIC;
signal \y[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \^y[22]\ : STD_LOGIC;
signal \^y[22]_0\ : STD_LOGIC;
signal \^y[22]_1\ : STD_LOGIC;
signal \^y[23]\ : STD_LOGIC;
signal \y[23]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[27]_INST_0_i_4_n_0\ : STD_LOGIC;
signal NLW_mantissa2_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_mantissa2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[14]_INST_0_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[14]_INST_0_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[15]_INST_0_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[16]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_6\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[23]_INST_0_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[30]_INST_0_i_2\ : label is "soft_lutpair1";
begin
\x_9__s_net_1\ <= \x_9__s_port_]\;
\y[13]\ <= \^y[13]\;
\y[18]\ <= \^y[18]\;
\y[20]\ <= \^y[20]\;
\y[20]_0\ <= \^y[20]_0\;
\y[21]\ <= \^y[21]\;
\y[22]\ <= \^y[22]\;
\y[22]_0\ <= \^y[22]_0\;
\y[22]_1\ <= \^y[22]_1\;
\y[23]\ <= \^y[23]\;
mantissa2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => NLW_mantissa2_carry_CO_UNCONNECTED(3 downto 2),
CO(1) => mantissa2_carry_n_2,
CO(0) => mantissa2_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1) => mantissa2_carry_i_1_n_0,
DI(0) => mantissa2_carry_i_2_n_0,
O(3 downto 0) => NLW_mantissa2_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => mantissa2_carry_i_3_n_0,
S(0) => mantissa2_carry_i_4_n_0
);
mantissa2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^y[22]\,
I1 => \^y[20]\,
O => mantissa2_carry_i_1_n_0
);
mantissa2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^y[13]\,
I1 => \^y[23]\,
O => mantissa2_carry_i_2_n_0
);
mantissa2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^y[20]\,
I1 => \^y[22]\,
O => mantissa2_carry_i_3_n_0
);
mantissa2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^y[23]\,
I1 => \^y[13]\,
O => mantissa2_carry_i_4_n_0
);
\y[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888C888888BF"
)
port map (
I0 => \y[14]_INST_0_i_3_n_0\,
I1 => \^y[23]\,
I2 => \y[13]_INST_0_i_1_n_0\,
I3 => \y[14]_INST_0_i_1_n_0\,
I4 => \x[9]_4\,
I5 => \y[14]_INST_0_i_2_n_0\,
O => y(0)
);
\y[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[13]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(6),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[13]_INST_0_i_1_n_0\
);
\y[13]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(4),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(8),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(0),
O => \y[13]_INST_0_i_2_n_0\
);
\y[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFFAB00ABFFABFF"
)
port map (
I0 => \y[15]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_1_n_0\,
I2 => \y[14]_INST_0_i_2_n_0\,
I3 => \^y[23]\,
I4 => \y[14]_INST_0_i_3_n_0\,
I5 => \y[15]_INST_0_i_1_n_0\,
O => y(1)
);
\y[14]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mantissa2_carry_n_2,
I1 => CO(0),
O => \y[14]_INST_0_i_1_n_0\
);
\y[14]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[14]_INST_0_i_4_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(7),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[14]_INST_0_i_2_n_0\
);
\y[14]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(0),
I3 => \^y[22]\,
O => \y[14]_INST_0_i_3_n_0\
);
\y[14]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(5),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(1),
O => \y[14]_INST_0_i_4_n_0\
);
\y[14]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => O(0),
I2 => mantissa2_carry_n_2,
O => \y[14]_INST_0_i_5_n_0\
);
\y[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[16]_INST_0_i_2_n_0\,
I3 => \y[15]_INST_0_i_1_n_0\,
I4 => \y[16]_INST_0_i_1_n_0\,
I5 => \y[15]_INST_0_i_2_n_0\,
O => y(2)
);
\y[15]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[15]_INST_0_i_3_n_0\,
I1 => \y[17]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[15]_INST_0_i_1_n_0\
);
\y[15]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(1),
I3 => \^y[22]\,
O => \y[15]_INST_0_i_2_n_0\
);
\y[15]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(6),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[15]_INST_0_i_3_n_0\
);
\y[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[17]_INST_0_i_2_n_0\,
I3 => \y[16]_INST_0_i_1_n_0\,
I4 => \y[17]_INST_0_i_1_n_0\,
I5 => \y[16]_INST_0_i_2_n_0\,
O => y(3)
);
\y[16]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[16]_INST_0_i_3_n_0\,
I1 => \y[18]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_1_n_0\
);
\y[16]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(0),
I1 => \^y[22]\,
I2 => x(2),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_2_n_0\
);
\y[16]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(7),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[16]_INST_0_i_3_n_0\
);
\y[16]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_4_n_0\
);
\y[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[18]_INST_0_i_2_n_0\,
I3 => \y[17]_INST_0_i_1_n_0\,
I4 => \y[18]_INST_0_i_1_n_0\,
I5 => \y[17]_INST_0_i_2_n_0\,
O => y(4)
);
\y[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0000FFFBFFFB"
)
port map (
I0 => \y[20]_INST_0_i_4_n_0\,
I1 => x(6),
I2 => \y[21]_INST_0_i_4_n_0\,
I3 => \y[20]_INST_0_i_3_n_0\,
I4 => \y[17]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[17]_INST_0_i_1_n_0\
);
\y[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(1),
I1 => \^y[22]\,
I2 => x(3),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[17]_INST_0_i_2_n_0\
);
\y[17]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(8),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(4),
O => \y[17]_INST_0_i_3_n_0\
);
\y[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0BFBFBF"
)
port map (
I0 => \y[19]_INST_0_i_2_n_0\,
I1 => \y[18]_INST_0_i_1_n_0\,
I2 => \^y[23]\,
I3 => \y[18]_INST_0_i_2_n_0\,
I4 => \y[19]_INST_0_i_1_n_0\,
O => y(5)
);
\y[18]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEF0000FFEFFFEF"
)
port map (
I0 => \y[20]_INST_0_i_3_n_0\,
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(7),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => \y[18]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[18]_INST_0_i_1_n_0\
);
\y[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00BFBFFFFFFFFF"
)
port map (
I0 => \^y[22]\,
I1 => x(2),
I2 => \^y[20]\,
I3 => \x[9]_2\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[18]_INST_0_i_2_n_0\
);
\y[18]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(9),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(5),
O => \y[18]_INST_0_i_3_n_0\
);
\y[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[20]_INST_0_i_2_n_0\,
I3 => \y[19]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_1_n_0\,
I5 => \y[19]_INST_0_i_2_n_0\,
O => y(6)
);
\y[19]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(6),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(8),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[19]_INST_0_i_1_n_0\
);
\y[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF404000000000"
)
port map (
I0 => \^y[22]\,
I1 => x(3),
I2 => \^y[20]\,
I3 => \x[9]_0\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[19]_INST_0_i_2_n_0\
);
\y[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[21]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_1_n_0\,
O => y(7)
);
\y[20]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(7),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(9),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[20]_INST_0_i_1_n_0\
);
\y[20]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_2\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_3\,
O => \y[20]_INST_0_i_2_n_0\
);
\y[20]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[20]_INST_0_i_3_n_0\
);
\y[20]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
O => \y[20]_INST_0_i_4_n_0\
);
\y[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAFFEA00EAFFEAFF"
)
port map (
I0 => \y[21]_INST_0_i_1_n_0\,
I1 => \x_9__s_net_1\,
I2 => mantissa2_carry_n_2,
I3 => \^y[23]\,
I4 => \y[21]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_3_n_0\,
O => y(8)
);
\y[21]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400044400000000"
)
port map (
I0 => \y[21]_INST_0_i_4_n_0\,
I1 => x(8),
I2 => \^y[22]\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[21]_INST_0_i_1_n_0\
);
\y[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000202020"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => \y[21]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \^y[22]\,
I4 => mantissa2_carry_n_2,
I5 => O(1),
O => \y[21]_INST_0_i_2_n_0\
);
\y[21]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_0\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_1\,
O => \y[21]_INST_0_i_3_n_0\
);
\y[21]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55A9FFFF55A90000"
)
port map (
I0 => p_1_out(0),
I1 => \^y[23]\,
I2 => \^y[18]\,
I3 => \^y[22]_0\,
I4 => mantissa2_carry_n_2,
I5 => O(2),
O => \y[21]_INST_0_i_4_n_0\
);
\y[21]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[21]_INST_0_i_6_n_0\
);
\y[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE222E200000000"
)
port map (
I0 => \x_9__s_net_1\,
I1 => \^y[23]\,
I2 => \x[9]_1\,
I3 => \^y[13]\,
I4 => \x[9]_5\,
I5 => mantissa2_carry_n_2,
O => y(9)
);
\y[22]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
O => \^y[13]\
);
\y[22]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
O => \^y[22]\
);
\y[22]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => \^y[20]_0\,
I3 => \^y[21]\,
I4 => x(8),
I5 => x(9),
O => \^y[20]\
);
\y[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00005504"
)
port map (
I0 => x(3),
I1 => x(0),
I2 => x(1),
I3 => x(2),
I4 => \y[23]_INST_0_i_1_n_0\,
I5 => \y[23]_INST_0_i_2_n_0\,
O => \^y[23]\
);
\y[23]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => x(5),
I1 => x(9),
I2 => x(7),
O => \y[23]_INST_0_i_1_n_0\
);
\y[23]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0FFF0F4"
)
port map (
I0 => x(5),
I1 => x(4),
I2 => x(8),
I3 => x(7),
I4 => x(6),
I5 => x(9),
O => \y[23]_INST_0_i_2_n_0\
);
\y[25]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888888888A"
)
port map (
I0 => \^y[22]_1\,
I1 => \^y[21]\,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => \^y[22]_0\
);
\y[27]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF01"
)
port map (
I0 => \y[27]_INST_0_i_4_n_0\,
I1 => x(7),
I2 => x(6),
I3 => x(9),
I4 => x(8),
O => \^y[18]\
);
\y[27]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(6),
I3 => x(7),
O => \^y[21]\
);
\y[27]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(1),
I1 => x(0),
I2 => x(2),
I3 => x(3),
O => \^y[20]_0\
);
\y[27]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1110111011101111"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(3),
I3 => x(2),
I4 => x(0),
I5 => x(1),
O => \y[27]_INST_0_i_4_n_0\
);
\y[30]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => x(8),
I1 => x(9),
O => \^y[22]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_uint_to_ieee754_fp_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_uint_to_ieee754_fp_0_0 : entity is "affine_block_uint_to_ieee754_fp_0_0,uint_to_ieee754_fp,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_uint_to_ieee754_fp_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_uint_to_ieee754_fp_0_0 : entity is "uint_to_ieee754_fp,Vivado 2016.4";
end affine_block_uint_to_ieee754_fp_0_0;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_0 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^y\ : STD_LOGIC_VECTOR ( 30 downto 13 );
signal \y[20]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[21]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[20]_INST_0_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_5\ : label is "soft_lutpair8";
begin
y(31) <= \<const0>\;
y(30) <= \^y\(30);
y(29) <= \^y\(27);
y(28) <= \^y\(27);
y(27 downto 13) <= \^y\(27 downto 13);
y(12) <= \<const0>\;
y(11) <= \<const0>\;
y(10) <= \<const0>\;
y(9) <= \<const0>\;
y(8) <= \<const0>\;
y(7) <= \<const0>\;
y(6) <= \<const0>\;
y(5) <= \<const0>\;
y(4) <= \<const0>\;
y(3) <= \<const0>\;
y(2) <= \<const0>\;
y(1) <= \<const0>\;
y(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.affine_block_uint_to_ieee754_fp_0_0_uint_to_ieee754_fp
port map (
CO(0) => \y[21]_INST_0_i_5_n_0\,
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
p_1_out(0) => p_1_out(3),
x(9 downto 0) => x(9 downto 0),
\x[9]_0\ => \y[21]_INST_0_i_7_n_0\,
\x[9]_1\ => \y[22]_INST_0_i_2_n_0\,
\x[9]_2\ => \y[20]_INST_0_i_5_n_0\,
\x[9]_3\ => \y[20]_INST_0_i_6_n_0\,
\x[9]_4\ => \y[30]_INST_0_i_1_n_0\,
\x[9]_5\ => \y[22]_INST_0_i_4_n_0\,
\x_9__s_port_]\ => \y[22]_INST_0_i_1_n_0\,
y(9 downto 0) => \^y\(22 downto 13),
\y[13]\ => U0_n_0,
\y[18]\ => U0_n_14,
\y[20]\ => U0_n_13,
\y[20]_0\ => U0_n_18,
\y[21]\ => U0_n_17,
\y[22]\ => U0_n_12,
\y[22]_0\ => U0_n_15,
\y[22]_1\ => U0_n_16,
\y[23]\ => \^y\(23)
);
\y[20]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(0),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(4),
O => \y[20]_INST_0_i_5_n_0\
);
\y[20]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => x(2),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(6),
O => \y[20]_INST_0_i_6_n_0\
);
\y[21]_INST_0_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \y[21]_INST_0_i_10_n_0\
);
\y[21]_INST_0_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y\(23),
I1 => U0_n_14,
O => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[21]_INST_0_i_5_n_0\,
CO(2) => \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\(2),
CO(1) => \y[21]_INST_0_i_5_n_2\,
CO(0) => \y[21]_INST_0_i_5_n_3\,
CYINIT => \^y\(23),
DI(3 downto 0) => B"0000",
O(3) => \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\(3),
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
S(3) => '1',
S(2) => \y[21]_INST_0_i_9_n_0\,
S(1) => \y[21]_INST_0_i_10_n_0\,
S(0) => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(1),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(5),
O => \y[21]_INST_0_i_7_n_0\
);
\y[21]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => U0_n_16,
I1 => U0_n_17,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => p_1_out(3)
);
\y[21]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_18,
I3 => U0_n_17,
I4 => x(8),
I5 => x(9),
O => \y[21]_INST_0_i_9_n_0\
);
\y[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[22]_INST_0_i_5_n_0\,
I1 => U0_n_0,
I2 => x(2),
I3 => U0_n_12,
I4 => U0_n_13,
I5 => x(6),
O => \y[22]_INST_0_i_1_n_0\
);
\y[22]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"C888"
)
port map (
I0 => x(7),
I1 => U0_n_13,
I2 => x(3),
I3 => U0_n_12,
O => \y[22]_INST_0_i_2_n_0\
);
\y[22]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(5),
I1 => U0_n_12,
I2 => x(9),
I3 => U0_n_13,
I4 => x(1),
O => \y[22]_INST_0_i_4_n_0\
);
\y[22]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(4),
I1 => U0_n_12,
I2 => x(8),
I3 => U0_n_13,
I4 => x(0),
O => \y[22]_INST_0_i_5_n_0\
);
\y[24]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(23),
I2 => U0_n_14,
O => \^y\(24)
);
\y[25]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_15,
I3 => \y[30]_INST_0_i_1_n_0\,
O => \^y\(25)
);
\y[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => x(9),
I1 => \^y\(27),
O => \^y\(26)
);
\y[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => x(9),
I3 => x(8),
I4 => U0_n_17,
I5 => U0_n_18,
O => \^y\(27)
);
\y[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(27),
O => \^y\(30)
);
\y[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => U0_n_17,
I1 => x(1),
I2 => x(0),
I3 => x(2),
I4 => x(3),
I5 => U0_n_16,
O => \y[30]_INST_0_i_1_n_0\
);
end STRUCTURE;
| mit | fd62c857bf14d7a54b476ebf444c9872 | 0.472745 | 2.339275 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/fp.vhd | 2 | 1,101 | library ieee;
use ieee.std_logic_1164.all;
entity fp is port
(
l,r : in std_logic_vector(1 to 32);
pt : out std_logic_vector(1 to 64)
);
end fp;
architecture behaviour of fp is
begin
pt(1)<=r(8); pt(2)<=l(8); pt(3)<=r(16);pt(4)<=l(16);pt(5)<=r(24);pt(6)<=l(24); pt(7)<=r(32);pt(8)<=l(32);
pt(9)<=r(7); pt(10)<=l(7);pt(11)<=r(15); pt(12)<=l(15); pt(13)<=r(23); pt(14)<=l(23); pt(15)<=r(31); pt(16)<=l(31);
pt(17)<=r(6);pt(18)<=l(6);pt(19)<=r(14); pt(20)<=l(14); pt(21)<=r(22); pt(22)<=l(22); pt(23)<=r(30); pt(24)<=l(30);
pt(25)<=r(5);pt(26)<=l(5);pt(27)<=r(13); pt(28)<=l(13); pt(29)<=r(21); pt(30)<=l(21); pt(31)<=r(29); pt(32)<=l(29);
pt(33)<=r(4);pt(34)<=l(4);pt(35)<=r(12); pt(36)<=l(12); pt(37)<=r(20); pt(38)<=l(20);pt(39)<=r(28); pt(40)<=l(28);
pt(41)<=r(3);pt(42)<=l(3);pt(43)<=r(11); pt(44)<=l(11); pt(45)<=r(19); pt(46)<=l(19); pt(47)<=r(27); pt(48)<=l(27);
pt(49)<=r(2);pt(50)<=l(2);pt(51)<=r(10); pt(52)<=l(10); pt(53)<=r(18); pt(54)<=l(18); pt(55)<=r(26); pt(56)<=l(26);
pt(57)<=r(1);pt(58)<=l(1);pt(59)<=r(9);pt(60)<=l(9);pt(61)<=r(17); pt(62)<=l(17); pt(63)<=r(25); pt(64)<=l(25);
end;
| mit | 79c285c461883512c8af6419a3b9b34f | 0.504087 | 1.866102 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/sim/system_ov7670_controller_1_0.vhd | 2 | 3,747 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
| mit | cc78e8e07c24d60297c11660e82d4b5e | 0.721911 | 4.037716 | false | false | false | false |
loa-org/loa-hdl | modules/ir_rx/hdl/ir_rx_module.vhd | 2 | 13,620 | -------------------------------------------------------------------------------
-- Title : Module for Receiver for infrared beacons
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Two functions:
-- a) Extract sync from IR signal
-- b) Measure frequency component of opponent beacons (with Goertzel algorithm)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity ir_rx_module is
-- Memory maps
--
-- Coefficient Register at BASE_ADDRESS_COEFS
-- ------------------------------------------
--
-- Lower 16 bits of 18-bit-wide Goertzel Coefficient in fixed point format
--
-- offset | R/W | Description
-- -------+-------------------------------------------------
-- +00 | W | Goertzel Coefficient Frequency 0
-- +01 | W | Goertzel Coefficient Frequency 1
--
--
-- Timestamp Register at BASE_ADDRESS_TIMESTAMP
-- --------------------------------------------
--
-- offset | R/W | Description
-- -------+-------------------------------------------------
-- +00 | R | Bits 15 downto 0 of timestamp
-- +01 | R | Bits 31 downto 16 of timestamp
-- +02 | R | Bits 47 downto 32 of timestamp
--
--
-- Result Register at BASE_ADDRESS_RESULTS
-- ---------------------------------------
--
-- Upper 16 bits of 18-bit-wide Goertzel Result
--
-- offset | R/W | Description
-- -------+-----+-------------------------------------------
-- +00 | R | Goertzel Result 0, Channel 0, Frequency 0
-- +01 | R | Goertzel Result 1, Channel 0, Frequency 0
-- +02 | R | Goertzel Result 0, Channel 1, Frequency 0
-- +03 | R | Goertzel Result 1, Channel 1, Frequency 0
-- +04 | R | Goertzel Result 0, Channel 2, Frequency 0
-- +05 | R | Goertzel Result 1, Channel 2, Frequency 0
-- +06 | R | Goertzel Result 0, Channel 3, Frequency 0
-- +07 | R | Goertzel Result 1, Channel 3, Frequency 0
-- +08 | R | Goertzel Result 0, Channel 4, Frequency 0
-- +09 | R | Goertzel Result 1, Channel 4, Frequency 0
-- +0A | R | Goertzel Result 0, Channel 5, Frequency 0
-- +0B | R | Goertzel Result 1, Channel 5, Frequency 0
-- +0C | R | Goertzel Result 0, Channel 6, Frequency 0
-- +0D | R | Goertzel Result 1, Channel 6, Frequency 0
-- +0E | R | Goertzel Result 0, Channel 7, Frequency 0
-- +0F | R | Goertzel Result 1, Channel 7, Frequency 0
-- +10 | R | Goertzel Result 0, Channel 8, Frequency 0
-- +11 | R | Goertzel Result 1, Channel 8, Frequency 0
-- +12 | R | Goertzel Result 0, Channel 9, Frequency 0
-- +13 | R | Goertzel Result 1, Channel 9, Frequency 0
-- +14 | R | Goertzel Result 0, Channel 10, Frequency 0
-- +15 | R | Goertzel Result 1, Channel 10, Frequency 0
-- +16 | R | Goertzel Result 0, Channel 11, Frequency 0
-- +17 | R | Goertzel Result 1, Channel 11, Frequency 0
-- ---------------------------------------------------------
-- +18 | R | Goertzel Result 0, Channel 0, Frequency 1
-- +19 | R | Goertzel Result 1, Channel 0, Frequency 1
-- +1A | R | Goertzel Result 0, Channel 1, Frequency 1
-- +1B | R | Goertzel Result 1, Channel 1, Frequency 1
-- +1C | R | Goertzel Result 0, Channel 2, Frequency 1
-- +1D | R | Goertzel Result 1, Channel 2, Frequency 1
-- +1E | R | Goertzel Result 0, Channel 3, Frequency 1
-- +1F | R | Goertzel Result 1, Channel 3, Frequency 1
-- +20 | R | Goertzel Result 0, Channel 4, Frequency 1
-- +21 | R | Goertzel Result 1, Channel 4, Frequency 1
-- +22 | R | Goertzel Result 0, Channel 5, Frequency 1
-- +23 | R | Goertzel Result 1, Channel 5, Frequency 1
-- +24 | R | Goertzel Result 0, Channel 6, Frequency 1
-- +25 | R | Goertzel Result 1, Channel 6, Frequency 1
-- +26 | R | Goertzel Result 0, Channel 7, Frequency 1
-- +27 | R | Goertzel Result 1, Channel 7, Frequency 1
-- +28 | R | Goertzel Result 0, Channel 8, Frequency 1
-- +29 | R | Goertzel Result 1, Channel 8, Frequency 1
-- +2A | R | Goertzel Result 0, Channel 9, Frequency 1
-- +2B | R | Goertzel Result 1, Channel 9, Frequency 1
-- +2C | R | Goertzel Result 0, Channel 10, Frequency 1
-- +2D | R | Goertzel Result 1, Channel 10, Frequency 1
-- +2E | R | Goertzel Result 0, Channel 11, Frequency 1
-- +2F | R | Goertzel Result 1, Channel 11, Frequency 1
--
-- +000 to +03f = 6 Bits = 2^6 = 64 words
--
-- The Block RAM is bigger and other working sets up to
-- Channels * Frequencies <= 256 are possible.
--
-- Mind the execution time for big datasets:
-- 4 cycles per channel and frequency + 4 cycles to fill the pipeline
--
-- E.g.: 12 channels, 5 frequencies, f_clk = 50 MHz, f_sample = 250 kHz
--
-- 1/f_clk = 20 ns
-- 1/f_sample = 4 us
-- 12 * 5 * 4 = 240 * 20 ns = 4.8 us > 4.0 us (clash!)
--
generic (
-- Base address at the internal data bus of the register for the coefficients
BASE_ADDRESS_COEFS : integer range 0 to 16#7FFF#;
-- Base address at the internal data bus of the dual port block RAM register for
-- the results
BASE_ADDRESS_RESULTS : integer range 0 to 16#7FFF#;
-- Base address at the internal data bus of the register with the
-- timestamp of the last sample.
BASE_ADDRESS_TIMESTAMP : integer range 0 to 16#7FFF#;
-- How many samples should make a set of goertzel values
SAMPLES : natural := 500
);
port (
-- Ports to two ADCs
-- signals to and from real hardware
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
-- Raw values of last ADC conversions (two ADCs with six channels each)
adc_values_o_p : out adc_ltc2351_values_type(11 downto 0);
-- Extracted sync signal
sync_o_p : out std_logic;
-- signals to and from the internal parallel bus
bus_o_p : out busdevice_out_type;
bus_i_p : in busdevice_in_type;
-- Handshake interface to STM when new data is available
done_o_p : out std_logic;
ack_i_p : in std_logic;
-- Sampling clock enable (expected to be 250 kHz or less)
-- starts a new ADC conversion and starts processing with goertzel algorithm.
clk_sample_en_i_p : in std_logic;
-- Timestamp input from the timestamp module
timestamp_i_p : in timestamp_type;
clk : in std_logic
);
end ir_rx_module;
architecture structural of ir_rx_module is
----------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------
constant Q : natural := 13;
constant CHANNELS : natural := 12;
constant FREQUENCIES : natural := 2;
----------------------------------------------------------------------------
-- Internal signal declaration
----------------------------------------------------------------------------
-- twelve ADC channels
signal adc_values_s : adc_ltc2351_values_type(CHANNELS-1 downto 0) := (others => (others => '0'));
-- conversion to signed values
signal adc_values_signed_s : goertzel_inputs_type(CHANNELS-1 downto 0) := (others => (others => '0'));
signal adc_values_signed_clipped_s : goertzel_inputs_type(CHANNELS-1 downto 0) := (others => (others => '0'));
-- Goertzel coefficients, one for each frequency
signal coefs_s : goertzel_coefs_type(FREQUENCIES-1 downto 0) := (others => (others => '0'));
signal results_s : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0) := (others => (others => (others => (others => '0'))));
signal module_done_s : std_logic := '0';
-- Merge internal bus
signal bus_coefs_s : busdevice_out_type;
signal bus_results_s : busdevice_out_type;
signal bus_timestamp_s : busdevice_out_type;
-- Connection between bram and pipelined
signal bram_data_i : std_logic_vector(35 downto 0);
signal bram_data_o : std_logic_vector(35 downto 0);
signal bram_addr_s : std_logic_vector(7 downto 0);
signal bram_we_s : std_logic;
signal adc_start_s : std_logic := '0';
signal adc_done_s : std_logic := '0';
signal reg_coefs_s : reg_file_type(FREQUENCIES-1 downto 0) := (others => (others => '0'));
signal goertzel_done_s : std_logic;
signal ack_s : std_logic;
signal bank_x_s : std_logic;
signal bank_y_s : std_logic;
begin -- structural
----------------------------------------------------------------------------
-- Connect components
----------------------------------------------------------------------------
bus_o_p.data <= bus_coefs_s.data or bus_results_s.data or bus_timestamp_s.data;
adc_values_o_p <= adc_values_s;
done_o_p <= module_done_s;
ack_s <= ack_i_p;
-- convert std_logic_vector to goertzel coefficients
coef_loop : for ii in 0 to FREQUENCIES-1 generate
coefs_s(ii) <= "00" & signed(reg_coefs_s(ii));
end generate coef_loop;
----------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------
-- Register file for the goertzel coefficients,
-- write only
reg_file_coefs_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS_COEFS,
REG_ADDR_BIT => log2(FREQUENCIES) -- 2**n = FREQUENCIES registers of 16 bits for goertzel coefficients
)
port map (
bus_o => bus_coefs_s,
bus_i => bus_i_p,
reg_o => reg_coefs_s,
reg_i => reg_coefs_s,
clk => clk
);
-- Block RAM with double buffering for the results
-- read only
reg_file_results_1 : entity work.reg_file_bram_double_buffered
generic map (
BASE_ADDRESS => BASE_ADDRESS_RESULTS)
port map (
bus_o => bus_results_s,
bus_i => bus_i_p,
bram_data_i => bram_data_i, -- in
bram_data_o => bram_data_o, -- out
bram_addr_i => bram_addr_s, -- in
bram_we_p => bram_we_s, -- in
irq_o => module_done_s,
ack_i => ack_s,
ready_i => goertzel_done_s,
enable_o => open,
bank_x_o => bank_x_s,
bank_y_o => bank_y_s,
clk => clk);
------------------------------------------------------------------------------
-- ADCs
------------------------------------------------------------------------------
ir_rx_adcs_1 : ir_rx_adcs
generic map (
CHANNELS => CHANNELS)
port map (
clk_sample_en_i_p => clk_sample_en_i_p,
adc_o_p => adc_o_p,
adc_i_p => adc_i_p,
adc_values_o_p => adc_values_s,
adc_done_o_p => adc_done_s,
clk => clk);
-- translate raw ADC values to signed
-- 14-bit ADC value, 0x0000 to 0x3fff, 0x2000 on average
adc_values_loop : for ch in CHANNELS-1 downto 0 generate
adc_values_signed_s(ch) <= signed(adc_values_s(ch)) - to_signed(16#2000#, 16)(INPUT_WIDTH-1 downto 0);
end generate adc_values_loop;
adc_values_clip_loop : for ch in CHANNELS-1 downto 0 generate
adc_values_signed_clipped_s(ch) <= to_signed(-200, INPUT_WIDTH) when adc_values_signed_s(ch) < -200 else
to_signed(+200, INPUT_WIDTH) when adc_values_signed_s(ch) > +200 else
adc_values_signed_s(ch);
end generate adc_values_clip_loop;
goertzel_pipelined_v2_1 : entity work.goertzel_pipelined_v2
generic map (
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS,
SAMPLES => SAMPLES,
Q => Q)
port map (
start_p => adc_done_s, -- whenever ADC is done process a new sample
bram_addr_p => bram_addr_s,
bram_data_i => bram_data_o,
bram_data_o => bram_data_i,
bram_we_p => bram_we_s,
ready_p => goertzel_done_s,
enable_p => '1', -- not used yet
coefs_p => coefs_s,
inputs_p => adc_values_signed_clipped_s, -- adc_values_signed_s,
clk => clk);
timestamp_taker_1 : timestamp_taker
generic map (
BASE_ADDRESS => BASE_ADDRESS_TIMESTAMP)
port map (
timestamp_i_p => timestamp_i_p,
trigger_i_p => goertzel_done_s,
bank_x_i_p => bank_x_s,
bank_y_i_p => bank_y_s,
bus_o => bus_timestamp_s,
bus_i => bus_i_p,
clk => clk);
-- Sync extraction
-- TODO
sync_o_p <= '0';
end structural;
| bsd-3-clause | ae93b3af070b446a5db581bfc781fee7 | 0.506902 | 3.705114 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_axi_mem_buffer/vga_axi_mem_buffer_1.0/hdl/vga_axi_mem_buffer_v1_0.vhd | 1 | 7,817 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_axi_mem_buffer_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6;
C_S_AXI_AWUSER_WIDTH : integer := 0;
C_S_AXI_ARUSER_WIDTH : integer := 0;
C_S_AXI_WUSER_WIDTH : integer := 0;
C_S_AXI_RUSER_WIDTH : integer := 0;
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awqos : in std_logic_vector(3 downto 0);
s_axi_awregion : in std_logic_vector(3 downto 0);
s_axi_awuser : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wuser : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_buser : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arqos : in std_logic_vector(3 downto 0);
s_axi_arregion : in std_logic_vector(3 downto 0);
s_axi_aruser : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_ruser : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end vga_axi_mem_buffer_v1_0;
architecture arch_imp of vga_axi_mem_buffer_v1_0 is
-- component declaration
component vga_axi_mem_buffer_v1_0_S_AXI is
generic (
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6;
C_S_AXI_AWUSER_WIDTH : integer := 0;
C_S_AXI_ARUSER_WIDTH : integer := 0;
C_S_AXI_WUSER_WIDTH : integer := 0;
C_S_AXI_RUSER_WIDTH : integer := 0;
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component vga_axi_mem_buffer_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
vga_axi_mem_buffer_v1_0_S_AXI_inst : vga_axi_mem_buffer_v1_0_S_AXI
generic map (
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_AWUSER_WIDTH => C_S_AXI_AWUSER_WIDTH,
C_S_AXI_ARUSER_WIDTH => C_S_AXI_ARUSER_WIDTH,
C_S_AXI_WUSER_WIDTH => C_S_AXI_WUSER_WIDTH,
C_S_AXI_RUSER_WIDTH => C_S_AXI_RUSER_WIDTH,
C_S_AXI_BUSER_WIDTH => C_S_AXI_BUSER_WIDTH
)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWID => s_axi_awid,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWLOCK => s_axi_awlock,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWQOS => s_axi_awqos,
S_AXI_AWREGION => s_axi_awregion,
S_AXI_AWUSER => s_axi_awuser,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WUSER => s_axi_wuser,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BUSER => s_axi_buser,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARLOCK => s_axi_arlock,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARQOS => s_axi_arqos,
S_AXI_ARREGION => s_axi_arregion,
S_AXI_ARUSER => s_axi_aruser,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RUSER => s_axi_ruser,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| mit | 48bc410147091141a9afd9b14c6b44ab | 0.661251 | 2.299794 | false | false | false | false |
pgavin/carpe | hdl/util/numeric_pkg.vhdl | 1 | 3,191 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package numeric_pkg is
pure function log2(n : natural) return natural;
pure function log2ceil(n : natural) return natural;
pure function is_pow2(n : natural) return boolean;
pure function integer_minimum(x1, x2 : integer) return integer;
pure function integer_maximum(x1, x2 : integer) return integer;
pure function factorial(n : natural) return natural;
pure function bitsize(n : natural) return natural;
end package;
package body numeric_pkg is
pure function log2(n : natural) return natural is
variable m, r : natural;
begin
m := n;
r := 0;
while m > 1 loop
r := r + 1;
m := m / 2;
end loop;
return r;
end function;
pure function log2ceil(n : natural) return natural is
variable m, r : natural;
begin
m := 1;
r := 0;
while m < n loop
r := r + 1;
m := m * 2;
end loop;
return r;
end function;
pure function is_pow2(n : natural) return boolean is
variable m : natural;
begin
if (n < 1) then
return false;
else
m := 1;
while (m < n) loop
m := m * 2;
end loop;
return m = n;
end if;
end function;
pure function integer_minimum(x1, x2 : integer) return integer is
begin
if x1 < x2 then
return x1;
else
return x2;
end if;
end function;
pure function integer_maximum(x1, x2 : integer) return integer is
begin
if x1 > x2 then
return x1;
else
return x2;
end if;
end function;
pure function factorial(n : natural) return natural is
variable ret : natural;
variable m : natural;
begin
m := n;
ret := 1;
while m > 0 loop
ret := ret * n;
m := m - 1;
end loop;
return ret;
end function;
pure function bitsize(n : natural) return natural is
begin
if n = 0 then
return 0;
else
return log2(n) + 1;
end if;
end function;
end package body;
| apache-2.0 | 2401c5239519b6632cc58a16942a8cd4 | 0.548731 | 4.176702 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl | 1 | 17,575 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 23:35:07 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync";
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active0 : STD_LOGIC;
signal active_i_3_n_0 : STD_LOGIC;
signal clear : STD_LOGIC;
signal \h_count_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \^vsync\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_3 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of hsync_i_2 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair0";
begin
vsync <= \^vsync\;
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0022002A"
)
port map (
I0 => active_i_3_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^yaddr\(9),
I4 => \^xaddr\(8),
O => active0
);
active_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => clear
);
active_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
O => active_i_3_n_0
);
active_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => clear,
D => active0,
Q => active
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => p_0_in(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
O => p_0_in(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => p_0_in(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
O => p_0_in(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
O => p_0_in(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33332333CCCCCCCC"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
O => p_0_in(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFFFFF7C0000000"
)
port map (
I0 => \^xaddr\(9),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(7),
I4 => \^xaddr\(6),
I5 => \^xaddr\(8),
O => \h_count_reg[8]_i_1_n_0\
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F80EF00FF00FF00"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
I3 => \^xaddr\(4),
I4 => \^xaddr\(3),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(4),
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => \h_count_reg[8]_i_1_n_0\,
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(9),
Q => \^xaddr\(9)
);
hsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFBFBFBFBFFF"
)
port map (
I0 => \^xaddr\(8),
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => hsync_i_2_n_0,
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(3),
I3 => \^xaddr\(1),
I4 => \^xaddr\(0),
O => hsync_i_2_n_0
);
hsync_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
PRE => clear,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => \p_0_in__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \p_0_in__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55AA55AA45AA55AA"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => \p_0_in__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFAA0045FFAA00"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => \p_0_in__0\(3)
);
\v_count_reg[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \v_count_reg[3]_i_2_n_0\
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \p_0_in__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => \p_0_in__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_5_n_0\,
I2 => \^yaddr\(5),
O => \v_count_reg[6]_i_1_n_0\
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(6),
O => \p_0_in__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(5),
I4 => \^yaddr\(7),
O => \p_0_in__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"D0D00DD0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => active_i_3_n_0,
O => \p_0_in__0\(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(7),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
I4 => \^yaddr\(4),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \v_count_reg[6]_i_1_n_0\,
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(9),
Q => \^yaddr\(9)
);
vsync_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E0EE"
)
port map (
I0 => \^vsync\,
I1 => rst,
I2 => active_i_3_n_0,
I3 => vsync_i_2_n_0,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(2),
I2 => \^yaddr\(4),
I3 => \^yaddr\(9),
I4 => rst,
I5 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => \^vsync\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | a46086c496517052883f7eb514ef5d3f | 0.484381 | 2.7769 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/synth/system_vga_sync_ref_0_0.vhd | 5 | 4,637 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_ref:1.0
-- IP Revision: 65
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_ref_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_ref_0_0;
ARCHITECTURE system_vga_sync_ref_0_0_arch OF system_vga_sync_ref_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_ref IS
GENERIC (
H_SIZE : INTEGER;
H_SYNC_SIZE : INTEGER;
V_SIZE : INTEGER;
DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_ref;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "vga_sync_ref,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_ref_0_0_arch : ARCHITECTURE IS "system_vga_sync_ref_0_0,vga_sync_ref,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_ref_0_0_arch: ARCHITECTURE IS "system_vga_sync_ref_0_0,vga_sync_ref,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync_ref,x_ipVersion=1.0,x_ipCoreRevision=65,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_SYNC_SIZE=144,V_SIZE=480,DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_ref
GENERIC MAP (
H_SIZE => 640,
H_SYNC_SIZE => 144,
V_SIZE => 480,
DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
hsync => hsync,
vsync => vsync,
start => start,
active => active,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_ref_0_0_arch;
| mit | fd9ba860446e912ad020f6df6094e946 | 0.70757 | 3.703674 | false | false | false | false |
pgavin/carpe | hdl/cpu/btb/cache/cpu_btb_cache-rtl.vhdl | 1 | 9,668 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_types_pkg.all;
use work.cpu_btb_cache_pkg.all;
use work.cpu_btb_cache_config_pkg.all;
use work.cpu_btb_cache_replace_pkg.all;
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
use util.numeric_pkg.all;
library mem;
library tech;
architecture rtl of cpu_btb_cache is
constant state_way_lsb : natural := cpu_btb_cache_assoc + cpu_btb_cache_replace_state_bits;
constant state_replace_way_lsb : natural := cpu_btb_cache_replace_state_bits;
constant state_replace_state_lsb : natural := 0;
type way_tags_type is array (cpu_btb_cache_assoc-1 downto 0) of std_ulogic_vector(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
type comb_type is record
wstate_way : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
wstate_replace_way : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
wstate_replace_state : cpu_btb_cache_replace_state_type;
rway_tags : way_tags_type;
rway_unpri : std_ulogic_vector(cpu_btb_cache_assoc downto 0);
rway_pri : std_ulogic_vector(cpu_btb_cache_assoc downto 0);
rway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
rhit : std_ulogic;
rtarget : cpu_ivaddr_type;
whit : std_ulogic;
cache_we : std_ulogic;
cache_wway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
cache_wtagen : std_ulogic;
cache_wdataen : std_ulogic;
cache_windex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
cache_wtag : std_ulogic_vector(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
cache_wdata : std_ulogic_vector(cpu_ivaddr_bits-1 downto 0);
cache_re : std_ulogic;
cache_rway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
cache_rtagen : std_ulogic;
cache_rdataen : std_ulogic;
cache_rindex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
cache_rtag : std_ulogic_vector2(cpu_btb_cache_assoc-1 downto 0, cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
cache_rdata : std_ulogic_vector2(cpu_btb_cache_assoc-1 downto 0, cpu_ivaddr_bits-1 downto 0);
replace_re : std_ulogic;
replace_rindex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
replace_rway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
replace_rstate : cpu_btb_cache_replace_state_type;
replace_we : std_ulogic;
replace_windex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
replace_wway : std_ulogic_vector(cpu_btb_cache_assoc-1 downto 0);
replace_wstate : cpu_btb_cache_replace_state_type;
rtag_write : std_ulogic;
cpu_btb_cache_replace_ctrl_in : cpu_btb_cache_replace_ctrl_in_type;
cpu_btb_cache_replace_dp_in : cpu_btb_cache_replace_dp_in_type;
cpu_btb_cache_replace_dp_out : cpu_btb_cache_replace_dp_out_type;
end record;
type reg_type is record
rrequested : std_ulogic;
rtag : std_ulogic_vector(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
end record;
constant reg_init : reg_type := (
rrequested => '0',
rtag => (others => 'X')
);
constant reg_x : reg_type := (
rrequested => 'X',
rtag => (others => 'X')
);
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.wstate_way <= cpu_btb_cache_dp_in.wstate(state_way_lsb+cpu_btb_cache_assoc-1 downto
state_way_lsb);
c.wstate_replace_way <= cpu_btb_cache_dp_in.wstate(state_replace_way_lsb+cpu_btb_cache_assoc-1 downto
state_replace_way_lsb);
c.wstate_replace_state <= cpu_btb_cache_dp_in.wstate(state_replace_state_lsb+cpu_btb_cache_replace_state_bits-1 downto
state_replace_state_lsb);
c.whit <= reduce_or(c.wstate_way);
c.cache_we <= cpu_btb_cache_ctrl_in.wen and not c.whit;
c.cache_wway <= c.wstate_replace_way;
c.cache_wtagen <= cpu_btb_cache_ctrl_in.wen;
c.cache_wdataen <= cpu_btb_cache_ctrl_in.wen;
c.cache_windex <= cpu_btb_cache_dp_in.waddr(cpu_btb_cache_index_bits-1 downto 0);
c.cache_wtag <= cpu_btb_cache_dp_in.waddr(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits);
c.cache_wdata <= cpu_btb_cache_dp_in.wtarget;
c.replace_we <= cpu_btb_cache_ctrl_in.wen;
c.replace_windex <= cpu_btb_cache_dp_in.waddr(cpu_btb_cache_index_bits-1 downto 0);
with c.whit select
c.replace_wway <= c.wstate_replace_way when '0',
c.wstate_way when '1',
(others => 'X') when others;
c.replace_wstate <= c.wstate_replace_state;
c.cache_re <= cpu_btb_cache_ctrl_in.ren;
c.cache_rway <= (others => '1');
c.cache_rtagen <= cpu_btb_cache_ctrl_in.ren;
c.cache_rdataen <= cpu_btb_cache_ctrl_in.ren;
c.cache_rindex <= cpu_btb_cache_dp_in.raddr(cpu_btb_cache_index_bits-1 downto 0);
c.replace_re <= cpu_btb_cache_ctrl_in.ren;
c.replace_rindex <= cpu_btb_cache_dp_in.raddr(cpu_btb_cache_index_bits-1 downto 0);
r_next.rrequested <= c.cache_re;
c.rtag_write <= c.cache_re;
with c.rtag_write select
r_next.rtag <= cpu_btb_cache_dp_in.raddr(cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits) when '1',
r.rtag when '0',
(others => 'X') when others;
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
way_loop : for n in cpu_btb_cache_assoc-1 downto 0 generate
ivaddr_bit_loop : for m in cpu_ivaddr_bits-1 downto cpu_btb_cache_index_bits generate
c.rway_tags(n)(m) <= c.cache_rtag(n, m);
end generate;
c.rway_unpri(n) <= logic_eq(c.rway_tags(n), r.rtag);
end generate;
-- need to prioritize because we might get multiple hits, since we don't keep valid bits
c.rway_unpri(cpu_btb_cache_assoc) <= '1';
c.rway_pri <= prioritize_least(c.rway_unpri);
c.rway <= c.rway_pri(cpu_btb_cache_assoc-1 downto 0);
c.rhit <= any_ones(c.rway);
c.replace_rway <= c.cpu_btb_cache_replace_dp_out.rway;
c.replace_rstate <= c.cpu_btb_cache_replace_dp_out.rstate;
c.cpu_btb_cache_replace_ctrl_in <= (
re => c.replace_re,
we => c.replace_we
);
c.cpu_btb_cache_replace_dp_in <= (
rindex => c.replace_rindex,
windex => c.replace_windex,
wway => c.replace_wway,
wstate => c.replace_wstate
);
cpu_btb_cache_ctrl_out <= (
rvalid => c.rhit
);
cpu_btb_cache_dp_out.rstate <= (
c.rway &
c.replace_rway &
c.replace_rstate
);
rtarget_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_ivaddr_bits,
sel_bits => cpu_btb_cache_assoc
)
port map (
din => c.cache_rdata,
sel => c.rway,
dout => cpu_btb_cache_dp_out.rtarget
);
replace : entity work.cpu_btb_cache_replace(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_btb_cache_replace_ctrl_in => c.cpu_btb_cache_replace_ctrl_in,
cpu_btb_cache_replace_dp_in => c.cpu_btb_cache_replace_dp_in,
cpu_btb_cache_replace_dp_out => c.cpu_btb_cache_replace_dp_out
);
cache : entity mem.cache_core_1r1w(rtl)
generic map (
log2_assoc => cpu_btb_cache_log2_assoc,
word_bits => cpu_ivaddr_bits,
index_bits => cpu_btb_cache_index_bits,
offset_bits => 0,
tag_bits => cpu_ivaddr_bits - cpu_btb_cache_index_bits,
write_first => true
)
port map (
clk => clk,
rstn => rstn,
we => c.cache_we,
wway => c.cache_wway,
wtagen => c.cache_wtagen,
wdataen => c.cache_wdataen,
windex => c.cache_windex,
woffset => "",
wtag => c.cache_wtag,
wdata => c.cache_wdata,
re => c.cache_re,
rway => c.cache_rway,
rtagen => c.cache_rtagen,
rdataen => c.cache_rdataen,
rindex => c.cache_rindex,
roffset => "",
rtag => c.cache_rtag,
rdata => c.cache_rdata
);
end;
| apache-2.0 | 95f69c24aecaa0781839281358775e71 | 0.5753 | 3.215165 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_0_0/synth/system_util_ds_buf_0_0.vhd | 1 | 6,451 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_ds_buf:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_ds_buf_v2_01_a;
USE util_ds_buf_v2_01_a.util_ds_buf;
ENTITY system_util_ds_buf_0_0 IS
PORT (
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_ds_buf_0_0;
ARCHITECTURE system_util_ds_buf_0_0_arch OF system_util_ds_buf_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_ds_buf IS
GENERIC (
C_BUF_TYPE : STRING;
C_SIZE : INTEGER
);
PORT (
IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_ds_buf;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "util_ds_buf,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_ds_buf_0_0_arch : ARCHITECTURE IS "system_util_ds_buf_0_0,util_ds_buf,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "system_util_ds_buf_0_0,util_ds_buf,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_ds_buf,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_BUF_TYPE=BUFG,C_SIZE=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK";
ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK";
BEGIN
U0 : util_ds_buf
GENERIC MAP (
C_BUF_TYPE => "BUFG",
C_SIZE => 1
)
PORT MAP (
IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_I => BUFG_I,
BUFG_O => BUFG_O,
BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3))
);
END system_util_ds_buf_0_0_arch;
| mit | fc4afe16ccf5b85037906219d8e33d07 | 0.687955 | 3.299744 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/inst/cache/cpu_l1mem_inst_cache_ctrl-rtl.vhdl | 1 | 66,695 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
-- pragma translate_off
use util.names_pkg.all;
library sim;
use sim.options_pkg.all;
use sim.monitor_pkg.all;
-- pragma translate_on
use work.cpu_l1mem_inst_types_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_mmu_inst_types_pkg.all;
use work.cpu_types_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_ctrl is
type request_type is record
code : cpu_l1mem_inst_request_code_type;
direction : cpu_l1mem_inst_fetch_direction_type;
cacheen : std_ulogic;
mmuen : std_ulogic;
priv : std_ulogic;
alloc : std_ulogic;
end record;
constant request_x : request_type := (
code => (others => 'X'),
direction => (others => 'X'),
cacheen => 'X',
mmuen => 'X',
priv => 'X',
alloc => 'X'
);
constant request_init : request_type := (
code => cpu_l1mem_inst_request_code_none,
direction => (others => 'X'),
cacheen => 'X',
mmuen => 'X',
priv => 'X',
alloc => 'X'
);
type request_state_index_type is (
request_state_index_none,
request_state_index_uncached_fetch_mmu_access,
request_state_index_uncached_fetch_bus_op,
request_state_index_cached_fetch_l1_access,
request_state_index_cached_fetch_fill,
request_state_index_invalidate_sync,
request_state_index_invalidate_l1_access,
request_state_index_sync
);
type request_state_type is
array (request_state_index_type range
request_state_index_type'high downto
request_state_index_type'low) of std_ulogic;
constant request_state_none : request_state_type := "00000001";
constant request_state_uncached_fetch_mmu_access : request_state_type := "00000010";
constant request_state_uncached_fetch_bus_op : request_state_type := "00000100";
constant request_state_cached_fetch_l1_access : request_state_type := "00001000";
constant request_state_cached_fetch_fill : request_state_type := "00010000";
constant request_state_invalidate_sync : request_state_type := "00100000";
constant request_state_invalidate_l1_access : request_state_type := "01000000";
constant request_state_sync : request_state_type := "10000000";
type bus_op_code_index_type is (
bus_op_code_index_none,
bus_op_code_index_fetch,
bus_op_code_index_fill
);
type bus_op_code_type is
array (bus_op_code_index_type range
bus_op_code_index_type'high downto
bus_op_code_index_type'low) of std_ulogic;
constant bus_op_code_none : bus_op_code_type := "001";
constant bus_op_code_fetch : bus_op_code_type := "010";
constant bus_op_code_fill : bus_op_code_type := "100";
type bus_op_state_index_type is (
bus_op_state_index_none,
bus_op_state_index_fetch,
bus_op_state_index_fill_first,
bus_op_state_index_fill,
bus_op_state_index_fill_last
);
type bus_op_state_type is
array (bus_op_state_index_type range
bus_op_state_index_type'high downto
bus_op_state_index_type'low) of std_ulogic;
constant bus_op_state_none : bus_op_state_type := "00001";
constant bus_op_state_fetch : bus_op_state_type := "00010";
constant bus_op_state_fill_first : bus_op_state_type := "00100";
constant bus_op_state_fill : bus_op_state_type := "01000";
constant bus_op_state_fill_last : bus_op_state_type := "10000";
type bus_op_type is record
code : bus_op_code_type;
way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
priv : std_ulogic;
end record;
constant bus_op_x : bus_op_type := (
code => (others => 'X'),
way => (others => 'X'),
priv => 'X'
);
constant bus_op_init : bus_op_type := (
code => bus_op_code_none,
way => (others => 'X'),
priv => 'X'
);
type reg_type is record
b_cache_owner : cpu_l1mem_inst_cache_owner_type;
b_bus_op_owner : cpu_l1mem_inst_cache_owner_type;
b_request_granted : std_ulogic;
b_request_state : request_state_type;
b_request : request_type;
b_request_tagless : std_ulogic;
b_request_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_mmu_accessed : std_ulogic;
b_bus_op_granted : std_ulogic;
b_bus_op_state : bus_op_state_type;
b_bus_op_cacheable : std_ulogic;
b_bus_op_priv : std_ulogic;
b_bus_op_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_bus_op_block_inst : std_ulogic_vector(cpu_l1mem_inst_cache_block_insts-1 downto 0);
b_bus_op_requested : std_ulogic;
end record;
constant reg_x : reg_type := (
b_cache_owner => (others => 'X'),
b_bus_op_owner => (others => 'X'),
b_request_granted => 'X',
b_request_state => (others => 'X'),
b_request => request_x,
b_request_tagless => 'X',
b_request_way => (others => 'X'),
b_request_mmu_accessed => 'X',
b_bus_op_granted => 'X',
b_bus_op_state => (others => 'X'),
b_bus_op_cacheable => 'X',
b_bus_op_priv => 'X',
b_bus_op_way => (others => 'X'),
b_bus_op_block_inst => (others => 'X'),
b_bus_op_requested => 'X'
);
constant reg_init : reg_type := (
b_cache_owner => cpu_l1mem_inst_cache_owner_none,
b_bus_op_owner => cpu_l1mem_inst_cache_owner_none,
b_request_granted => 'X',
b_request_state => request_state_none,
b_request => request_init,
b_request_tagless => 'X',
b_request_way => (others => 'X'),
b_request_mmu_accessed => 'X',
b_bus_op_granted => 'X',
b_bus_op_state => bus_op_state_none,
b_bus_op_cacheable => 'X',
b_bus_op_priv => 'X',
b_bus_op_way => (others => 'X'),
b_bus_op_block_inst => (others => 'X'),
b_bus_op_requested => 'X'
);
type comb_type is record
b_vram_rdata : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_vram_rdata_all_ones : std_ulogic;
b_vram_rdata_first_free : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_replace_rway : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_replace_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_bus_op_error : std_ulogic;
b_bus_op_cycle_complete : std_ulogic;
b_bus_op_fill_fetch_data_ready : std_ulogic;
b_bus_op_fill_complete : std_ulogic;
b_bus_op_complete : std_ulogic;
b_bus_op_state_next_fill_first : bus_op_state_type;
b_bus_op_state_next_fill : bus_op_state_type;
b_bus_op_state_next_fill_last : bus_op_state_type;
b_bus_op_state_next_no_error : bus_op_state_type;
b_bus_op_state_next : bus_op_state_type;
b_bus_op_block_inst_advance : std_ulogic;
b_bus_op_block_inst_next : std_ulogic_vector(cpu_l1mem_inst_cache_block_insts-1 downto 0);
b_bus_op_vram_we : std_ulogic;
b_bus_op_vram_wdata : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_bus_op_replace_we : std_ulogic;
b_bus_op_replace_wway : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_sync : std_ulogic;
b_request_mmu_result_ready : std_ulogic;
b_request_mmu_result_valid : std_ulogic;
b_request_mmu_error : std_ulogic;
b_request_cache_way_hit : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_cache_hit : std_ulogic;
b_request_cache_miss : std_ulogic;
b_request_complete_uncached_fetch_mmu_access : std_ulogic;
b_request_complete_uncached_fetch_bus_op : std_ulogic;
b_request_complete_cached_fetch_l1_access : std_ulogic;
b_request_complete_cached_fetch_fill : std_ulogic;
b_request_complete_invalidate_l1_access : std_ulogic;
b_request_complete_sync : std_ulogic;
b_request_complete_no_error : std_ulogic;
b_request_complete : std_ulogic;
b_request_way_next_sel : std_ulogic_vector(2 downto 0);
b_request_way_next : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_tagless_seq_next : std_ulogic;
b_request_state_next_uncached_fetch_mmu_access : request_state_type;
b_request_state_next_cached_fetch_l1_access : request_state_type;
b_request_state_next_invalidate_sync : request_state_type;
b_request_state_next_no_error : request_state_type;
b_request_state_next : request_state_type;
b_request_cache_accessed_next : std_ulogic;
b_request_replace_we : std_ulogic;
b_request_replace_wway : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_vram_we : std_ulogic;
b_request_vram_wdata : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_cache_read_data_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_result_ready : std_ulogic;
b_result_code_mmu_access : cpu_l1mem_inst_result_code_type;
b_result_code_no_error : cpu_l1mem_inst_result_code_type;
b_result_code : cpu_l1mem_inst_result_code_type;
b_result_inst_sel : cpu_l1mem_inst_cache_b_result_inst_sel_type;
b_replace_we_no_error : std_ulogic;
b_replace_we : std_ulogic;
b_replace_wway : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_vram_we_no_error : std_ulogic;
b_vram_we : std_ulogic;
b_vram_wdata : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_cache_owner_next_request : cpu_l1mem_inst_cache_owner_type;
b_cache_owner_next_bus_op_request : cpu_l1mem_inst_cache_owner_type;
b_cache_owner_next_bus_op_bus_op : cpu_l1mem_inst_cache_owner_type;
b_cache_owner_next_bus_op : cpu_l1mem_inst_cache_owner_type;
b_cache_owner_next_no_error : cpu_l1mem_inst_cache_owner_type;
b_cache_owner_next : cpu_l1mem_inst_cache_owner_type;
b_bus_op_owner_next_request : cpu_l1mem_inst_cache_owner_type;
b_bus_op_owner_next_bus_op : cpu_l1mem_inst_cache_owner_type;
b_bus_op_owner_next_no_error : cpu_l1mem_inst_cache_owner_type;
b_bus_op_owner_next : cpu_l1mem_inst_cache_owner_type;
a_new_request : request_type;
a_new_request_fill_forward : std_ulogic;
a_new_request_state_fetch : request_state_type;
a_new_request_state : request_state_type;
a_request : request_type;
a_request_fill_forward : std_ulogic;
a_request_state : request_state_type;
a_request_tagless : std_ulogic;
a_request_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_request_cache_accessed : std_ulogic;
a_request_mmu_accessed : std_ulogic;
a_request_want_cache : std_ulogic;
a_request_want_bus_op : std_ulogic;
a_request_can_own_cache : std_ulogic;
a_request_can_own_bus_op : std_ulogic;
a_request_granted : std_ulogic;
a_request_bus_op_code : bus_op_code_type;
a_request_vram_re : std_ulogic;
a_request_tram_en : std_ulogic;
a_request_tram_we : std_ulogic;
a_request_tram_banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_request_dram_en : std_ulogic;
a_request_dram_banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_request_replace_re : std_ulogic;
a_request_mmu_accessed_next : std_ulogic;
a_new_bus_op_owner : cpu_l1mem_inst_cache_owner_type;
a_new_bus_op_code : bus_op_code_type;
a_new_bus_op_state : bus_op_state_type;
a_new_bus_op_cacheable : std_ulogic;
a_new_bus_op_priv : std_ulogic;
a_new_bus_op_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_new_bus_op_block_inst : std_ulogic_vector(cpu_l1mem_inst_cache_block_insts-1 downto 0);
a_bus_op_owner : cpu_l1mem_inst_cache_owner_type;
a_bus_op_state : bus_op_state_type;
a_bus_op_priv : std_ulogic;
a_bus_op_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_bus_op_cacheable : std_ulogic;
a_bus_op_block_inst : std_ulogic_vector(cpu_l1mem_inst_cache_block_insts-1 downto 0);
a_bus_op_requested : std_ulogic;
a_bus_op_paddr_tag_sel : cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_type;
a_bus_op_paddr_index_sel : cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_type;
a_bus_op_paddr_offset_sel : cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_type;
a_bus_op_cache_paddr_sel_old : std_ulogic;
a_bus_op_want_cache : std_ulogic;
a_bus_op_vram_re : std_ulogic;
a_bus_op_tram_en : std_ulogic;
a_bus_op_tram_we : std_ulogic;
a_bus_op_tram_banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_bus_op_dram_en : std_ulogic;
a_bus_op_dram_we : std_ulogic;
a_bus_op_dram_banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_bus_op_replace_re : std_ulogic;
a_bus_op_can_own_cache : std_ulogic;
a_bus_op_granted : std_ulogic;
a_new_cache_owner : cpu_l1mem_inst_cache_owner_type;
a_cache_owner : cpu_l1mem_inst_cache_owner_type;
a_vram_re : std_ulogic;
a_tram_en : std_ulogic;
a_tram_we : std_ulogic;
a_tram_banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_dram_en : std_ulogic;
a_dram_we : std_ulogic;
a_dram_banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
a_replace_re : std_ulogic;
a_mmu_request : std_ulogic;
a_sys_request : std_ulogic;
a_sys_be : std_ulogic;
a_sys_write : std_ulogic;
a_sys_cacheable : std_ulogic;
a_sys_priv : std_ulogic;
a_sys_burst : std_ulogic;
a_sys_bcycles : sys_burst_cycles_type;
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.b_vram_rdata <= cpu_l1mem_inst_cache_ctrl_in_vram.rdata;
c.b_vram_rdata_all_ones <= all_ones(c.b_vram_rdata);
c.b_vram_rdata_first_free <= prioritize(not c.b_vram_rdata);
c.b_replace_rway <= cpu_l1mem_inst_cache_replace_ctrl_out.rway;
with c.b_vram_rdata_all_ones select
c.b_replace_way <= c.b_replace_rway when '1',
c.b_vram_rdata_first_free when '0',
(others => 'X') when others;
c.b_bus_op_error <= (
r.b_bus_op_requested and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error
);
c.b_bus_op_cycle_complete <= (
r.b_bus_op_requested and
sys_slave_ctrl_out.ready
);
with r.b_bus_op_state select
c.b_bus_op_fill_fetch_data_ready <= c.b_bus_op_cycle_complete when bus_op_state_fill_first,
sys_slave_ctrl_out.ready when bus_op_state_fill |
bus_op_state_fill_last,
'X' when others;
c.b_bus_op_fill_complete <= (
r.b_bus_op_state(bus_op_state_index_fill_last)
);
with r.b_bus_op_state select
c.b_bus_op_complete <= '1' when bus_op_state_none |
bus_op_state_fill_last,
c.b_bus_op_cycle_complete when bus_op_state_fetch,
'0' when bus_op_state_fill_first |
bus_op_state_fill,
'X' when others;
b_bus_op_state_next_block_insts_eq_1_gen : if cpu_l1mem_inst_cache_block_insts = 1 generate
c.b_bus_op_state_next_fill_first <= (
bus_op_state_index_fill_first => (
not c.b_bus_op_cycle_complete
),
bus_op_state_index_fill_last => (
c.b_bus_op_cycle_complete
),
others => '0'
);
end generate;
b_bus_op_state_next_block_insts_gt_1_gen : if cpu_l1mem_inst_cache_block_insts > 1 generate
c.b_bus_op_state_next_fill_first <= (
bus_op_state_index_fill_first => (
not r.b_bus_op_granted
),
bus_op_state_index_fill => (
r.b_bus_op_granted
),
others => '0'
);
c.b_bus_op_state_next_fill <= (
bus_op_state_index_fill => (
not c.b_bus_op_cycle_complete or
not r.b_bus_op_block_inst(cpu_l1mem_inst_cache_block_insts-1)
),
bus_op_state_index_fill_last => (
c.b_bus_op_cycle_complete and
r.b_bus_op_block_inst(cpu_l1mem_inst_cache_block_insts-1)
),
others => '0'
);
end generate;
with r.b_bus_op_state select
c.b_bus_op_state_next_no_error <= bus_op_state_fetch when bus_op_state_fetch,
c.b_bus_op_state_next_fill_first when bus_op_state_fill_first,
c.b_bus_op_state_next_fill when bus_op_state_fill,
bus_op_state_fill_last when bus_op_state_fill_last,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_bus_op_state_next <= c.b_bus_op_state_next_no_error when '0',
bus_op_state_none when '1',
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_block_inst_advance <= sys_slave_ctrl_out.ready when bus_op_state_fill_first |
bus_op_state_fill,
'0' when bus_op_state_fetch,
'X' when others;
with c.b_bus_op_block_inst_advance select
c.b_bus_op_block_inst_next <= r.b_bus_op_block_inst when '0',
(r.b_bus_op_block_inst(cpu_l1mem_inst_cache_block_insts-2 downto 0) &
r.b_bus_op_block_inst(cpu_l1mem_inst_cache_block_insts-1)
) when '1',
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_vram_we <= '0' when bus_op_state_fill,
sys_slave_ctrl_out.ready and r.b_bus_op_block_inst(0) when bus_op_state_fill_first,
'1' when bus_op_state_fill_last,
'X' when others;
with r.b_bus_op_state select
c.b_bus_op_vram_wdata <= c.b_vram_rdata and not r.b_bus_op_way when bus_op_state_fill_first,
c.b_vram_rdata or r.b_bus_op_way when bus_op_state_fill_last,
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_replace_we <= '0' when bus_op_state_fill_first |
bus_op_state_fill,
'1' when bus_op_state_fill_last,
'X' when others;
c.b_bus_op_replace_wway <= r.b_bus_op_way;
---- request post-phase
c.b_request_sync <= (
r.b_cache_owner(cpu_l1mem_inst_cache_owner_index_none) and
r.b_bus_op_owner(cpu_l1mem_inst_cache_owner_index_none)
);
c.b_request_mmu_result_ready <= (
r.b_request_mmu_accessed and
cpu_mmu_inst_ctrl_out.ready
);
c.b_request_mmu_result_valid <= (
r.b_request_mmu_accessed and
cpu_mmu_inst_ctrl_out.ready and
cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_valid)
);
c.b_request_mmu_error <= (
r.b_request_mmu_accessed and
cpu_mmu_inst_ctrl_out.ready and
not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_valid)
);
-- check for cache hit
c.b_request_cache_way_hit <= (c.b_vram_rdata and
cpu_l1mem_inst_cache_dp_out_ctrl.b_request_cache_tag_match);
c.b_request_cache_hit <= reduce_or(c.b_request_cache_way_hit);
c.b_request_cache_miss <= not c.b_request_cache_hit;
-- request completion
c.b_request_complete_uncached_fetch_mmu_access <= (
c.b_request_mmu_error
);
c.b_request_complete_uncached_fetch_bus_op <= (
r.b_request_granted and
c.b_bus_op_cycle_complete
);
c.b_request_complete_cached_fetch_l1_access <= (
(c.b_request_mmu_result_valid and
((r.b_request_granted and
(r.b_request_tagless or
c.b_request_cache_hit))
)
) or
c.b_request_mmu_error
);
c.b_request_complete_cached_fetch_fill <= (
r.b_request_granted and
c.b_bus_op_fill_fetch_data_ready
);
c.b_request_complete_invalidate_l1_access <= (
r.b_request_granted
);
c.b_request_complete_sync <= (
c.b_request_sync
);
with r.b_request_state select
c.b_request_complete_no_error <= '1' when request_state_none,
c.b_request_complete_uncached_fetch_mmu_access when request_state_uncached_fetch_mmu_access,
c.b_request_complete_uncached_fetch_bus_op when request_state_uncached_fetch_bus_op,
c.b_request_complete_cached_fetch_l1_access when request_state_cached_fetch_l1_access,
c.b_request_complete_cached_fetch_fill when request_state_cached_fetch_fill,
c.b_request_complete_sync when request_state_sync,
c.b_request_complete_invalidate_l1_access when request_state_invalidate_l1_access,
'0' when request_state_invalidate_sync,
'X' when others;
c.b_request_complete <= c.b_request_complete_no_error or c.b_bus_op_error;
c.b_request_way_next_sel <= (
0 => (
r.b_request_state(request_state_index_none) or
r.b_request_state(request_state_index_cached_fetch_fill) or
(r.b_request_state(request_state_index_cached_fetch_l1_access) and
r.b_request_tagless)
),
1 => (
r.b_request_state(request_state_index_cached_fetch_l1_access) and
not r.b_request_tagless and
c.b_request_cache_hit
),
2 => (
r.b_request_state(request_state_index_cached_fetch_l1_access) and
not r.b_request_tagless and
not c.b_request_cache_hit
)
);
with c.b_request_way_next_sel select
c.b_request_way_next <= r.b_request_way when "001",
c.b_request_cache_way_hit when "010",
c.b_replace_way when "100",
(others => 'X') when others;
with r.b_request_state select
c.b_request_tagless_seq_next <= r.b_request_tagless when request_state_none,
not cpu_l1mem_inst_cache_dp_out_ctrl.b_request_last_in_block
when request_state_cached_fetch_l1_access |
request_state_cached_fetch_fill,
'0' when request_state_uncached_fetch_mmu_access |
request_state_uncached_fetch_bus_op |
request_state_invalidate_sync |
request_state_invalidate_l1_access |
request_state_sync,
'X' when others;
c.b_request_state_next_uncached_fetch_mmu_access <= (
request_state_index_uncached_fetch_mmu_access => (
not c.b_request_mmu_result_ready
),
request_state_index_uncached_fetch_bus_op => (
c.b_request_mmu_result_ready
),
others => '0'
);
c.b_request_state_next_cached_fetch_l1_access <= (
request_state_index_cached_fetch_l1_access => (
not r.b_request_granted or
not c.b_request_mmu_result_ready
),
request_state_index_cached_fetch_fill => (
r.b_request_granted and
r.b_request.alloc and
c.b_request_mmu_result_ready
),
request_state_index_uncached_fetch_bus_op => (
r.b_request_granted and
not r.b_request.alloc
),
others => '0'
);
c.b_request_state_next_invalidate_sync <= (
request_state_index_invalidate_sync => (
not c.b_request_sync
),
request_state_index_invalidate_l1_access => (
c.b_request_sync
),
others => '0'
);
with r.b_request_state select
c.b_request_state_next_no_error <= r.b_request_state when request_state_none |
request_state_uncached_fetch_bus_op |
request_state_invalidate_l1_access |
request_state_sync,
c.b_request_state_next_uncached_fetch_mmu_access when request_state_uncached_fetch_mmu_access,
c.b_request_state_next_cached_fetch_l1_access when request_state_cached_fetch_l1_access,
request_state_cached_fetch_fill when request_state_cached_fetch_fill,
c.b_request_state_next_invalidate_sync when request_state_invalidate_sync,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_request_state_next <= c.b_request_state_next_no_error when '0',
request_state_none when '1',
(others => 'X') when others;
with r.b_request_state select
c.b_request_cache_accessed_next <= r.b_request_granted when request_state_cached_fetch_l1_access |
request_state_invalidate_l1_access,
'0' when request_state_none |
request_state_invalidate_sync,
'X' when others;
with r.b_request_state select
c.b_request_replace_we <= (c.b_request_mmu_result_valid and
(c.b_request_cache_hit or
r.b_request_tagless)
) when request_state_cached_fetch_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with r.b_request_state select
c.b_request_replace_wway <= logic_if(r.b_request_tagless,
r.b_request_way,
c.b_request_cache_way_hit) when request_state_cached_fetch_l1_access,
(others => 'X') when others;
with r.b_request_state select
c.b_request_vram_we <= '1' when request_state_invalidate_l1_access,
'0' when request_state_cached_fetch_l1_access,
'X' when others;
with r.b_request_state select
c.b_request_vram_wdata <= (others => '0') when request_state_invalidate_l1_access,
(others => 'X') when others;
with r.b_cache_owner select
c.b_cache_read_data_way <= r.b_bus_op_way when cpu_l1mem_inst_cache_owner_bus_op,
logic_if(r.b_request_tagless,
r.b_request_way,
c.b_request_cache_way_hit) when cpu_l1mem_inst_cache_owner_request,
(others => 'X') when others;
-- request result processing
c.b_result_ready <= c.b_request_complete;
c.b_result_code_mmu_access <= (
cpu_l1mem_inst_result_code_index_valid => (
not r.b_request.mmuen or
cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_valid)
),
cpu_l1mem_inst_result_code_index_error => (
r.b_request.mmuen and
cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_error)
),
cpu_l1mem_inst_result_code_index_tlbmiss => (
r.b_request.mmuen and
cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_tlbmiss)
),
cpu_l1mem_inst_result_code_index_pf => (
r.b_request.mmuen and
cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_pf)
)
);
with r.b_request_state select
c.b_result_code_no_error <= c.b_result_code_mmu_access when request_state_uncached_fetch_mmu_access |
request_state_cached_fetch_l1_access,
cpu_l1mem_inst_result_code_valid when request_state_none |
request_state_sync |
request_state_uncached_fetch_bus_op |
request_state_cached_fetch_fill |
request_state_invalidate_l1_access,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_result_code <= c.b_result_code_no_error when '0',
cpu_l1mem_inst_result_code_error when '1',
(others => 'X') when others;
with r.b_request_state select
c.b_result_inst_sel <= cpu_l1mem_inst_cache_b_result_inst_sel_b_cache when request_state_cached_fetch_l1_access,
cpu_l1mem_inst_cache_b_result_inst_sel_b_bus when request_state_uncached_fetch_bus_op |
request_state_cached_fetch_fill,
(others => 'X') when others;
-- write vram, replace
with r.b_cache_owner select
c.b_replace_we_no_error <= c.b_request_replace_we when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_replace_we when cpu_l1mem_inst_cache_owner_bus_op,
'0' when cpu_l1mem_inst_cache_owner_none,
'X' when others;
c.b_replace_we <= c.b_replace_we_no_error and not c.b_bus_op_error;
with r.b_cache_owner select
c.b_replace_wway <= c.b_request_replace_wway when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_replace_wway when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with r.b_cache_owner select
c.b_vram_we_no_error <= c.b_request_vram_we when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_vram_we when cpu_l1mem_inst_cache_owner_bus_op,
'0' when cpu_l1mem_inst_cache_owner_none,
'X' when others;
c.b_vram_we <= c.b_vram_we_no_error and not c.b_bus_op_error;
with r.b_cache_owner select
c.b_vram_wdata <= c.b_request_vram_wdata when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_vram_wdata when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with r.b_request_state select
c.b_cache_owner_next_request <=
(cpu_l1mem_inst_cache_owner_index_none => (
c.b_request_mmu_result_ready
),
cpu_l1mem_inst_cache_owner_index_request => (
not c.b_request_mmu_result_ready
),
others => '0'
) when request_state_cached_fetch_l1_access,
cpu_l1mem_inst_cache_owner_none when request_state_invalidate_l1_access,
(others => 'X') when others;
with r.b_request_state select
c.b_cache_owner_next_bus_op_request <=
(cpu_l1mem_inst_cache_owner_index_none => (
c.b_bus_op_fill_complete or
c.b_bus_op_error
),
cpu_l1mem_inst_cache_owner_index_bus_op => (
not c.b_bus_op_fill_complete and
not c.b_bus_op_error
),
others => '0'
) when request_state_cached_fetch_fill,
(others => 'X') when others;
with r.b_bus_op_state select
c.b_cache_owner_next_bus_op_bus_op <=
cpu_l1mem_inst_cache_owner_bus_op when bus_op_state_fill_first |
bus_op_state_fill,
cpu_l1mem_inst_cache_owner_none when bus_op_state_fill_last,
(others => 'X') when others;
with r.b_bus_op_owner select
c.b_cache_owner_next_bus_op <= cpu_l1mem_inst_cache_owner_none when cpu_l1mem_inst_cache_owner_none,
c.b_cache_owner_next_bus_op_request when cpu_l1mem_inst_cache_owner_request,
c.b_cache_owner_next_bus_op_bus_op when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
-- Choose the next cache vram & tram owner
with r.b_cache_owner select
c.b_cache_owner_next_no_error <= c.b_cache_owner_next_request when cpu_l1mem_inst_cache_owner_request,
c.b_cache_owner_next_bus_op when cpu_l1mem_inst_cache_owner_bus_op,
cpu_l1mem_inst_cache_owner_none when cpu_l1mem_inst_cache_owner_none,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_cache_owner_next <= c.b_cache_owner_next_no_error when '0',
cpu_l1mem_inst_cache_owner_none when '1',
(others => 'X') when others;
with r.b_request_state select
c.b_bus_op_owner_next_request <=
(cpu_l1mem_inst_cache_owner_index_none => c.b_bus_op_cycle_complete,
cpu_l1mem_inst_cache_owner_index_request => not c.b_bus_op_cycle_complete,
others => '0'
) when request_state_uncached_fetch_bus_op,
(cpu_l1mem_inst_cache_owner_index_none => c.b_bus_op_fill_complete or c.b_bus_op_error,
cpu_l1mem_inst_cache_owner_index_bus_op => c.b_bus_op_fill_fetch_data_ready and not c.b_bus_op_fill_complete and not c.b_bus_op_error,
cpu_l1mem_inst_cache_owner_index_request => not c.b_bus_op_fill_fetch_data_ready and not c.b_bus_op_error,
others => '0'
) when request_state_cached_fetch_fill,
(others => 'X'
) when others;
with r.b_bus_op_state select
c.b_bus_op_owner_next_bus_op <=
cpu_l1mem_inst_cache_owner_bus_op when bus_op_state_fill,
cpu_l1mem_inst_cache_owner_none when bus_op_state_fill_last,
(others => 'X') when others;
with r.b_bus_op_owner select
c.b_bus_op_owner_next_no_error <= cpu_l1mem_inst_cache_owner_none when cpu_l1mem_inst_cache_owner_none,
c.b_bus_op_owner_next_request when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_owner_next_bus_op when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_bus_op_owner_next <= c.b_bus_op_owner_next_no_error when '0',
cpu_l1mem_inst_cache_owner_none when '1',
(others => 'X') when others;
-- new request selection, declare wants
c.a_new_request <= (code => cpu_l1mem_inst_cache_ctrl_in.request,
direction => cpu_l1mem_inst_cache_ctrl_in.direction,
cacheen => cpu_l1mem_inst_cache_ctrl_in.cacheen,
mmuen => cpu_l1mem_inst_cache_ctrl_in.mmuen,
priv => cpu_l1mem_inst_cache_ctrl_in.priv,
alloc => cpu_l1mem_inst_cache_ctrl_in.alloc
);
c.a_new_request_fill_forward <= (
c.a_new_request.code(cpu_l1mem_inst_request_code_index_fetch) and
r.b_request_state(request_state_index_cached_fetch_fill) and
c.a_new_request.direction(cpu_l1mem_inst_fetch_direction_index_seq) and
not cpu_l1mem_inst_cache_dp_out_ctrl.b_request_last_in_block and
not (c.a_new_request.mmuen xor r.b_request.mmuen)
);
c.a_new_request_state_fetch <= (
request_state_index_uncached_fetch_mmu_access => (
not c.a_request.cacheen
),
request_state_index_cached_fetch_l1_access => (
c.a_request.cacheen and
not c.a_new_request_fill_forward
),
request_state_index_cached_fetch_fill => (
c.a_request.cacheen and
c.a_new_request_fill_forward
),
others => '0'
);
with c.a_request.code select
c.a_new_request_state <= request_state_none when cpu_l1mem_inst_request_code_none,
c.a_new_request_state_fetch when cpu_l1mem_inst_request_code_fetch,
request_state_invalidate_sync when cpu_l1mem_inst_request_code_invalidate,
request_state_sync when cpu_l1mem_inst_request_code_sync,
(others => 'X') when others;
with c.b_request_complete select
c.a_request <= c.a_new_request when '1',
r.b_request when '0',
request_x when others;
c.a_request_fill_forward <= c.b_request_complete and c.a_new_request_fill_forward;
with c.b_request_complete select
c.a_request_state <= c.a_new_request_state when '1',
c.b_request_state_next when '0',
(others => 'X') when others;
with c.b_request_complete select
c.a_request_tagless <= (c.b_request_tagless_seq_next and
c.a_request.direction(cpu_l1mem_inst_fetch_direction_index_seq)
) when '1',
r.b_request_tagless when '0',
'X' when others;
c.a_request_way <= c.b_request_way_next;
c.a_request_cache_accessed <= c.b_request_cache_accessed_next and not c.b_request_complete;
c.a_request_mmu_accessed <= r.b_request_mmu_accessed and not c.b_request_complete;
with c.a_request_state select
c.a_request_want_cache <= '0' when request_state_none |
request_state_uncached_fetch_mmu_access |
request_state_uncached_fetch_bus_op |
request_state_cached_fetch_fill |
request_state_invalidate_sync,
'1' when request_state_cached_fetch_l1_access |
request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_want_bus_op <= '0' when request_state_none |
request_state_uncached_fetch_mmu_access |
request_state_cached_fetch_l1_access |
request_state_invalidate_sync |
request_state_invalidate_l1_access,
'1' when request_state_uncached_fetch_bus_op |
request_state_cached_fetch_fill,
'X' when others;
with c.b_bus_op_owner_next select
c.a_request_can_own_bus_op <= '1' when cpu_l1mem_inst_cache_owner_request |
cpu_l1mem_inst_cache_owner_none,
'0' when cpu_l1mem_inst_cache_owner_bus_op,
'X' when others;
with c.b_cache_owner_next select
c.a_request_can_own_cache <= '1' when cpu_l1mem_inst_cache_owner_request |
cpu_l1mem_inst_cache_owner_none,
'0' when cpu_l1mem_inst_cache_owner_bus_op,
'X' when others;
c.a_request_granted <= (
(not (c.a_request_want_cache and
not c.a_request_can_own_cache
) and
not (c.a_request_want_bus_op and
not c.a_request_can_own_bus_op
)
) or
c.a_request_fill_forward
);
with c.a_request_state select
c.a_request_bus_op_code <= bus_op_code_fetch when request_state_uncached_fetch_bus_op,
bus_op_code_fill when request_state_cached_fetch_fill,
(others => 'X') when others;
with c.a_request_state select
c.a_request_vram_re <= (not c.a_request_cache_accessed and
not c.a_request_tagless) when request_state_cached_fetch_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_tram_en <= (not c.a_request_cache_accessed and
not c.a_request_tagless) when request_state_cached_fetch_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_tram_we <= '0' when request_state_cached_fetch_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_tram_banken <= (others => '1') when request_state_cached_fetch_l1_access,
(others => 'X') when others;
with c.a_request_state select
c.a_request_dram_en <= not c.a_request_cache_accessed when request_state_cached_fetch_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_dram_banken <= ((cpu_l1mem_inst_cache_assoc-1 downto 0 => not c.a_request_tagless) or
c.a_request_way) when request_state_cached_fetch_l1_access,
(others => 'X') when others;
with c.a_request_state select
c.a_request_replace_re <= not c.a_request_cache_accessed when request_state_cached_fetch_l1_access |
request_state_invalidate_l1_access,
'X' when others;
c.a_request_mmu_accessed_next <= c.a_request_mmu_accessed or cpu_mmu_inst_ctrl_out.ready;
---
c.a_new_bus_op_owner <= (
cpu_l1mem_inst_cache_owner_index_none => (
not (c.a_request_granted and c.a_request_want_bus_op)
),
cpu_l1mem_inst_cache_owner_index_request => (
c.a_request_granted and c.a_request_want_bus_op
),
cpu_l1mem_inst_cache_owner_index_bus_op => '0'
);
with c.a_new_bus_op_owner select
c.a_new_bus_op_code <= c.a_request_bus_op_code when cpu_l1mem_inst_cache_owner_request,
bus_op_code_none when cpu_l1mem_inst_cache_owner_none,
(others => 'X') when others;
with c.a_new_bus_op_code select
c.a_new_bus_op_state <= bus_op_state_none when bus_op_code_none,
bus_op_state_fetch when bus_op_code_fetch,
bus_op_state_fill_first when bus_op_code_fill,
(others => 'X') when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_cacheable <= c.a_request.cacheen when cpu_l1mem_inst_cache_owner_request,
'X' when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_priv <= c.a_request.priv when cpu_l1mem_inst_cache_owner_request,
'X' when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_way <= c.a_request_way when cpu_l1mem_inst_cache_owner_request,
(others => 'X') when others;
c.a_new_bus_op_block_inst <= (0 => '1', others => '0');
with c.b_bus_op_owner_next(cpu_l1mem_inst_cache_owner_index_none) select
c.a_bus_op_owner <= c.b_bus_op_owner_next when '0',
c.a_new_bus_op_owner when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_state <= c.b_bus_op_state_next when '0',
c.a_new_bus_op_state when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_cacheable <= r.b_bus_op_cacheable when '0',
c.a_new_bus_op_cacheable when '1',
'X' when others;
with c.b_bus_op_complete select
c.a_bus_op_priv <= r.b_bus_op_priv when '0',
c.a_new_bus_op_priv when '1',
'X' when others;
with c.b_bus_op_complete select
c.a_bus_op_way <= r.b_bus_op_way when '0',
c.a_new_bus_op_way when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_block_inst <= c.b_bus_op_block_inst_next when '0',
c.a_new_bus_op_block_inst when '1',
(others => 'X') when others;
c.a_bus_op_requested <= (
(r.b_bus_op_requested and
not c.b_bus_op_complete) or
sys_slave_ctrl_out.ready
);
with c.b_bus_op_complete select
c.a_bus_op_paddr_tag_sel <= cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_old when '0',
cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_request when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_paddr_index_sel <= cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_old when '0',
cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_request when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_paddr_offset_sel <= (cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_old =>
not c.b_bus_op_block_inst_advance,
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_next =>
c.b_bus_op_block_inst_advance,
others => '0'
) when '0',
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_request when '1',
(others => 'X') when others;
with c.a_bus_op_state select
c.a_bus_op_cache_paddr_sel_old <= '1' when bus_op_state_fill |
bus_op_state_fill_last,
'0' when bus_op_state_fill_first,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_want_cache <= '0' when bus_op_state_none |
bus_op_state_fetch,
'1' when bus_op_state_fill_first,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_vram_re <= '1' when bus_op_state_fill_first | -- clear valid bit
bus_op_state_fill_last, -- set valid bit
'0' when bus_op_state_fill,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_tram_en <= '1' when bus_op_state_fill_last, -- write tag for fill
'0' when bus_op_state_fill_first |
bus_op_state_fill,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_tram_we <= '1' when bus_op_state_fill_last, -- write tag for fill
'X' when others;
c.a_bus_op_tram_banken <= c.a_bus_op_way;
with c.a_bus_op_state select
c.a_bus_op_dram_en <= sys_slave_ctrl_out.ready when bus_op_state_fill |
bus_op_state_fill_last,
'0' when bus_op_state_fill_first,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_dram_we <= '1' when bus_op_state_fill |
bus_op_state_fill_last,
'X' when others;
c.a_bus_op_dram_banken <= c.a_bus_op_way;
with c.a_bus_op_state select
c.a_bus_op_replace_re <= '1' when bus_op_state_fill_last,
'0' when bus_op_state_fill_first |
bus_op_state_fill,
'X' when others;
with c.b_cache_owner_next select
c.a_bus_op_can_own_cache <= '1' when cpu_l1mem_inst_cache_owner_bus_op |
cpu_l1mem_inst_cache_owner_none,
'0' when cpu_l1mem_inst_cache_owner_request,
'X' when others;
c.a_bus_op_granted <= (
not (c.a_bus_op_want_cache and
(not c.a_bus_op_can_own_cache or
(c.a_request_granted and c.a_request_want_cache)
)
)
);
c.a_new_cache_owner <= (
cpu_l1mem_inst_cache_owner_index_none => (
not (c.a_request_granted and c.a_request_want_cache) and
not (c.a_bus_op_granted and c.a_bus_op_want_cache)
),
cpu_l1mem_inst_cache_owner_index_request => (
c.a_request_granted and c.a_request_want_cache
),
cpu_l1mem_inst_cache_owner_index_bus_op => (
c.a_bus_op_granted and c.a_bus_op_want_cache
)
);
with c.b_cache_owner_next select
c.a_cache_owner <= c.a_new_cache_owner when cpu_l1mem_inst_cache_owner_none,
c.b_cache_owner_next when cpu_l1mem_inst_cache_owner_request |
cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
-- choose cache component inputs
with c.a_cache_owner select
c.a_vram_re <= c.a_request_vram_re when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_vram_re when cpu_l1mem_inst_cache_owner_bus_op,
'0' when cpu_l1mem_inst_cache_owner_none,
'X' when others;
with c.a_cache_owner select
c.a_tram_en <= c.a_request_tram_en when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_tram_en when cpu_l1mem_inst_cache_owner_bus_op,
'0' when cpu_l1mem_inst_cache_owner_none,
'X' when others;
with c.a_cache_owner select
c.a_tram_we <= c.a_request_tram_we when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_tram_we when cpu_l1mem_inst_cache_owner_bus_op,
'X' when others;
with c.a_cache_owner select
c.a_tram_banken <= c.a_request_tram_banken when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_tram_banken when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with c.a_cache_owner select
c.a_dram_en <= c.a_request_dram_en when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_dram_en when cpu_l1mem_inst_cache_owner_bus_op,
'0' when cpu_l1mem_inst_cache_owner_none,
'X' when others;
with c.a_cache_owner select
c.a_dram_we <= '0' when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_dram_we when cpu_l1mem_inst_cache_owner_bus_op,
'X' when others;
with c.a_cache_owner select
c.a_replace_re <= c.a_request_replace_re when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_replace_re when cpu_l1mem_inst_cache_owner_bus_op,
'0' when cpu_l1mem_inst_cache_owner_none,
'X' when others;
with c.a_cache_owner select
c.a_dram_banken <= c.a_request_dram_banken when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_dram_banken when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with c.a_request_state select
c.a_mmu_request <= '0' when request_state_none |
request_state_uncached_fetch_bus_op |
request_state_cached_fetch_fill |
request_state_invalidate_sync |
request_state_sync,
'1' when request_state_uncached_fetch_mmu_access |
request_state_cached_fetch_l1_access |
request_state_invalidate_l1_access,
'X' when others;
with c.a_bus_op_state select
c.a_sys_request <= '1' when bus_op_state_fetch |
bus_op_state_fill_first |
bus_op_state_fill,
'0' when bus_op_state_none |
bus_op_state_fill_last,
'X' when others;
a_sys_be_0 : if cpu_inst_endianness = little_endian generate
c.a_sys_be <= '0';
end generate;
a_sys_be_1 : if cpu_inst_endianness = big_endian generate
c.a_sys_be <= '1';
end generate;
with c.a_bus_op_state select
c.a_sys_write <= '0' when bus_op_state_fetch |
bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_fill_last,
'X' when others;
with c.a_bus_op_state select
c.a_sys_cacheable <= '0' when bus_op_state_fetch,
'1' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_fill_last,
'X' when others;
c.a_sys_priv <= c.a_bus_op_priv;
a_sys_burst_gen_bursts : if sys_max_burst_cycles > 1 generate
with c.a_bus_op_state select
c.a_sys_burst <=
not c.a_bus_op_block_inst(cpu_l1mem_inst_cache_block_insts-1) when bus_op_state_fill_first |
bus_op_state_fill,
'0' when bus_op_state_fetch,
'X' when others;
c.a_sys_bcycles <= std_ulogic_vector(to_unsigned(cpu_l1mem_inst_cache_offset_bits-cpu_log2_word_bytes, sys_burst_cycles_bits));
end generate;
a_sys_burst_gen_no_bursts : if sys_max_burst_cycles <= 1 generate
c.a_sys_burst <= '0';
c.a_sys_bcycles <= (others => 'X');
end generate;
r_next <= (
b_cache_owner => c.a_cache_owner,
b_bus_op_owner => c.a_bus_op_owner,
b_request_granted => c.a_request_granted,
b_request_state => c.a_request_state,
b_request => c.a_request,
b_request_tagless => c.a_request_tagless,
b_request_way => c.a_request_way,
b_request_mmu_accessed => c.a_request_mmu_accessed_next,
b_bus_op_granted => c.a_bus_op_granted,
b_bus_op_state => c.a_bus_op_state,
b_bus_op_cacheable => c.a_bus_op_cacheable,
b_bus_op_priv => c.a_bus_op_priv,
b_bus_op_way => c.a_bus_op_way,
b_bus_op_block_inst => c.a_bus_op_block_inst,
b_bus_op_requested => c.a_bus_op_requested
);
cpu_l1mem_inst_cache_ctrl_out <= (
ready => c.b_result_ready,
result => c.b_result_code
);
sys_master_ctrl_out <= (request => c.a_sys_request,
be => c.a_sys_be,
write => c.a_sys_write,
cacheable => c.a_sys_cacheable,
priv => c.a_sys_priv,
inst => '0',
burst => c.a_sys_burst,
bwrap => '1',
bcycles => c.a_sys_bcycles
);
cpu_l1mem_inst_cache_ctrl_out_vram <= (re => c.a_vram_re,
we => c.b_vram_we,
wdata => c.b_vram_wdata
);
cpu_l1mem_inst_cache_ctrl_out_tram <= (en => c.a_tram_en,
we => c.a_tram_we,
banken => c.a_tram_banken
);
cpu_l1mem_inst_cache_ctrl_out_dram <= (en => c.a_dram_en,
we => c.a_dram_we,
banken => c.a_dram_banken
);
cpu_l1mem_inst_cache_dp_in_ctrl <= (
a_cache_owner => c.a_cache_owner,
a_bus_op_paddr_tag_sel => c.a_bus_op_paddr_tag_sel,
a_bus_op_paddr_index_sel => c.a_bus_op_paddr_index_sel,
a_bus_op_paddr_offset_sel => c.a_bus_op_paddr_offset_sel,
a_bus_op_cache_paddr_sel_old => c.a_bus_op_cache_paddr_sel_old,
b_request_complete => c.b_request_complete,
b_cache_owner => r.b_cache_owner,
b_cache_read_data_way => c.b_cache_read_data_way,
b_replace_way => c.b_replace_way,
b_result_inst_sel => c.b_result_inst_sel
);
cpu_l1mem_inst_cache_replace_ctrl_in <= (
re => c.a_replace_re,
we => c.b_replace_we,
wway => c.b_replace_wway
);
cpu_mmu_inst_ctrl_in <= (
request => c.a_mmu_request,
mmuen => c.a_request.mmuen
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
--pragma translate_off
a_dram_en_monitor : block is
signal a_dram_en_mon : std_ulogic_vector(0 downto 0);
begin
a_dram_en_mon(0) <= c.a_dram_en;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "a_dram_en",
data_bits => 1
)
port map (
clk => clk,
data => a_dram_en_mon
);
end block;
a_dram_we_monitor : block is
signal a_dram_we_mon : std_ulogic_vector(0 downto 0);
begin
with c.a_dram_en select
a_dram_we_mon(0) <= c.a_dram_we when '1',
'X' when others;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "a_dram_we",
data_bits => 1
)
port map (
clk => clk,
data => a_dram_we_mon
);
end block;
a_tram_en_monitor : block is
signal a_tram_en_mon : std_ulogic_vector(0 downto 0);
begin
a_tram_en_mon(0) <= c.a_tram_en;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "a_tram_en",
data_bits => 1
)
port map (
clk => clk,
data => a_tram_en_mon
);
end block;
a_tram_we_monitor : block is
signal a_tram_we_mon : std_ulogic_vector(0 downto 0);
begin
with c.a_tram_en select
a_tram_we_mon(0) <= c.a_tram_we when '1',
'X' when others;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "a_tram_we",
data_bits => 1
)
port map (
clk => clk,
data => a_tram_we_mon
);
end block;
a_vram_re_monitor : block is
signal a_vram_re_mon : std_ulogic_vector(0 downto 0);
begin
a_vram_re_mon(0) <= c.a_vram_re;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "a_vram_re",
data_bits => 1
)
port map (
clk => clk,
data => a_vram_re_mon
);
end block;
b_vram_we_monitor : block is
signal b_vram_we_mon : std_ulogic_vector(0 downto 0);
begin
b_vram_we_mon(0) <= c.b_vram_we;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "b_vram_we",
data_bits => 1
)
port map (
clk => clk,
data => b_vram_we_mon
);
end block;
a_replace_re_monitor : block is
signal a_replace_re_mon : std_ulogic_vector(0 downto 0);
begin
a_replace_re_mon(0) <= c.a_replace_re;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "a_replace_re",
data_bits => 1
)
port map (
clk => clk,
data => a_replace_re_mon
);
end block;
b_replace_we_monitor : block is
signal b_replace_we_mon : std_ulogic_vector(0 downto 0);
begin
b_replace_we_mon(0) <= c.b_replace_we;
mon : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
name => "b_replace_we",
data_bits => 1
)
port map (
clk => clk,
data => b_replace_we_mon
);
end block;
--monitor : block is
-- signal b_inst_fetch_valid : std_ulogic_vector(0 downto 0);
-- signal b_inst_fetch_cacheen : std_ulogic;
-- signal b_inst_fetch_mmuen : std_ulogic;
-- signal b_inst_fetch_vpc : cpu_ivaddr_type;
-- signal b_inst_fetch_ppc : cpu_ipaddr_type;
-- signal b_inst_fetch_cache_hit : std_ulogic_vector(0 downto 0);
-- signal b_inst_fetch_cache_miss : std_ulogic_vector(0 downto 0);
-- signal b_inst_fetch_fill_forward : std_ulogic_vector(0 downto 0);
--begin
--b_fetch(0) <= (
-- r.b_request.code(cpu_l1mem_inst_request_code_index_fetch) and
-- c.b_request_complete and
-- c.b_result_code(cpu_l1mem_inst_result_code_index_valid)
-- );
--b_cached(0) <= r.b_request.cacheen;
--b_cache_hit(0) <= c.b_request_cache_hit;
--b_cache_fill(0) <= c.b_fill_start;
--b_cache_invalidate(0) <= r.b_request.code(cpu_l1mem_inst_request_code_index_invalidate);
--b_fetch_monitor : entity sim.monitor_sync_watch(behav)
-- generic map (
-- instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
-- name => "b_fetch",
-- data_bits => 1
-- )
-- port map (
-- clk => clk,
-- data => b_fetch
-- );
--b_cached_monitor : entity sim.monitor_sync_watch(behav)
-- generic map (
-- instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
-- name => "b_cached",
-- data_bits => 1
-- )
-- port map (
-- clk => clk,
-- data => b_cached
-- );
--b_cache_hit_monitor : entity sim.monitor_sync_watch(behav)
-- generic map (
-- instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
-- name => "b_cache_hit",
-- data_bits => 1
-- )
-- port map (
-- clk => clk,
-- data => b_cache_hit
-- );
--b_invalidate_monitor : entity sim.monitor_sync_watch(behav)
-- generic map (
-- instance => entity_path_name(cpu_l1mem_inst_cache_ctrl'path_name),
-- name => "b_cache_invalidate",
-- data_bits => 1
-- )
-- port map (
-- clk => clk,
-- data => b_cache_invalidate
-- );
--end block;
--pragma translate_on
end;
| apache-2.0 | 607ec2a64bfa6692974876ca5a6d460c | 0.524822 | 3.336919 | false | false | false | false |
loa-org/loa-hdl | modules/utils/hdl/event_hold_stage.vhd | 2 | 1,968 | -------------------------------------------------------------------------------
-- Title : Event Hold Stage
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Xilinx Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- Extends and stores an event.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity event_hold_stage is
port(
dout_p : out std_logic; -- Data output
din_p : in std_logic; -- Data input
period_p : in std_logic; -- Next period
clk : in std_logic -- Clock input
);
end event_hold_stage;
-------------------------------------------------------------------------------
architecture behavioral of event_hold_stage is
type event_hold_stage_type is record
found : std_logic;
output : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : event_hold_stage_type := (found => '0',
output => '0');
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(r, din_p, period_p)
variable v : event_hold_stage_type;
begin
v := r;
if din_p = '1' then
v.found := '1';
end if;
if period_p = '1' then
v.output := v.found;
v.found := din_p;
end if;
rin <= v;
end process comb_proc;
dout_p <= r.output;
end behavioral;
| bsd-3-clause | a305b6e2e31e22a26a42b0dfaccac1aa | 0.388211 | 4.696897 | false | false | false | false |
loa-org/loa-hdl | modules/utils/hdl/dff.vhd | 2 | 1,566 | -------------------------------------------------------------------------------
-- Title : D Flip-Flop with synchronous Reset, Set and Clock Enable
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Xilinx Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- D Flip-Flop with Synchronous Reset, Set and Clock Enable.
-- Priority (high to low): reset_p, set_p, ce_p
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dff is
port(
dout_p : out std_logic; -- Data output
din_p : in std_logic; -- Data input
set_p : in std_logic; -- Synchronous set input
reset_p : in std_logic; -- Synchronous reset input
ce_p : in std_logic; -- Clock enable input
clk : in std_logic -- Clock input
);
end dff;
-------------------------------------------------------------------------------
architecture behavioral of dff is
begin
process (clk)
begin
if rising_edge(clk) then
if reset_p = '1' then
dout_p <= '0';
elsif set_p = '1' then
dout_p <= '1';
elsif ce_p = '1' then
dout_p <= din_p;
end if;
end if;
end process;
end behavioral;
| bsd-3-clause | 993e3eedf57f59ae3c415fd94aa4bf76 | 0.4106 | 4.592375 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_sim_netlist.vhdl | 1 | 18,057 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_debounce_0_0 -prefix
-- system_debounce_0_0_ system_debounce_0_0_sim_netlist.vhdl
-- Design : system_debounce_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0_debounce is
port (
signal_out : out STD_LOGIC;
clk : in STD_LOGIC;
signal_in : in STD_LOGIC
);
end system_debounce_0_0_debounce;
architecture STRUCTURE of system_debounce_0_0_debounce is
signal \c[0]_i_3_n_0\ : STD_LOGIC;
signal \c[0]_i_4_n_0\ : STD_LOGIC;
signal \c[0]_i_5_n_0\ : STD_LOGIC;
signal \c[0]_i_6_n_0\ : STD_LOGIC;
signal \c[12]_i_2_n_0\ : STD_LOGIC;
signal \c[12]_i_3_n_0\ : STD_LOGIC;
signal \c[12]_i_4_n_0\ : STD_LOGIC;
signal \c[12]_i_5_n_0\ : STD_LOGIC;
signal \c[16]_i_2_n_0\ : STD_LOGIC;
signal \c[16]_i_3_n_0\ : STD_LOGIC;
signal \c[16]_i_4_n_0\ : STD_LOGIC;
signal \c[16]_i_5_n_0\ : STD_LOGIC;
signal \c[20]_i_2_n_0\ : STD_LOGIC;
signal \c[20]_i_3_n_0\ : STD_LOGIC;
signal \c[20]_i_4_n_0\ : STD_LOGIC;
signal \c[20]_i_5_n_0\ : STD_LOGIC;
signal \c[4]_i_2_n_0\ : STD_LOGIC;
signal \c[4]_i_3_n_0\ : STD_LOGIC;
signal \c[4]_i_4_n_0\ : STD_LOGIC;
signal \c[4]_i_5_n_0\ : STD_LOGIC;
signal \c[8]_i_2_n_0\ : STD_LOGIC;
signal \c[8]_i_3_n_0\ : STD_LOGIC;
signal \c[8]_i_4_n_0\ : STD_LOGIC;
signal \c[8]_i_5_n_0\ : STD_LOGIC;
signal c_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \c_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_7\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal signal_out_i_1_n_0 : STD_LOGIC;
signal signal_out_i_2_n_0 : STD_LOGIC;
signal signal_out_i_3_n_0 : STD_LOGIC;
signal signal_out_i_4_n_0 : STD_LOGIC;
signal signal_out_i_5_n_0 : STD_LOGIC;
signal \NLW_c_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\c[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => signal_in,
O => clear
);
\c[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(3),
O => \c[0]_i_3_n_0\
);
\c[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(2),
O => \c[0]_i_4_n_0\
);
\c[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(1),
O => \c[0]_i_5_n_0\
);
\c[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => c_reg(0),
O => \c[0]_i_6_n_0\
);
\c[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(15),
O => \c[12]_i_2_n_0\
);
\c[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(14),
O => \c[12]_i_3_n_0\
);
\c[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(13),
O => \c[12]_i_4_n_0\
);
\c[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(12),
O => \c[12]_i_5_n_0\
);
\c[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(19),
O => \c[16]_i_2_n_0\
);
\c[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(18),
O => \c[16]_i_3_n_0\
);
\c[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(17),
O => \c[16]_i_4_n_0\
);
\c[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(16),
O => \c[16]_i_5_n_0\
);
\c[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(23),
O => \c[20]_i_2_n_0\
);
\c[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(22),
O => \c[20]_i_3_n_0\
);
\c[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(21),
O => \c[20]_i_4_n_0\
);
\c[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(20),
O => \c[20]_i_5_n_0\
);
\c[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(7),
O => \c[4]_i_2_n_0\
);
\c[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(6),
O => \c[4]_i_3_n_0\
);
\c[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(5),
O => \c[4]_i_4_n_0\
);
\c[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(4),
O => \c[4]_i_5_n_0\
);
\c[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(11),
O => \c[8]_i_2_n_0\
);
\c[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(10),
O => \c[8]_i_3_n_0\
);
\c[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(9),
O => \c[8]_i_4_n_0\
);
\c[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(8),
O => \c[8]_i_5_n_0\
);
\c_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_7\,
Q => c_reg(0),
R => clear
);
\c_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \c_reg[0]_i_2_n_0\,
CO(2) => \c_reg[0]_i_2_n_1\,
CO(1) => \c_reg[0]_i_2_n_2\,
CO(0) => \c_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \c_reg[0]_i_2_n_4\,
O(2) => \c_reg[0]_i_2_n_5\,
O(1) => \c_reg[0]_i_2_n_6\,
O(0) => \c_reg[0]_i_2_n_7\,
S(3) => \c[0]_i_3_n_0\,
S(2) => \c[0]_i_4_n_0\,
S(1) => \c[0]_i_5_n_0\,
S(0) => \c[0]_i_6_n_0\
);
\c_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_5\,
Q => c_reg(10),
R => clear
);
\c_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_4\,
Q => c_reg(11),
R => clear
);
\c_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_7\,
Q => c_reg(12),
R => clear
);
\c_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[8]_i_1_n_0\,
CO(3) => \c_reg[12]_i_1_n_0\,
CO(2) => \c_reg[12]_i_1_n_1\,
CO(1) => \c_reg[12]_i_1_n_2\,
CO(0) => \c_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[12]_i_1_n_4\,
O(2) => \c_reg[12]_i_1_n_5\,
O(1) => \c_reg[12]_i_1_n_6\,
O(0) => \c_reg[12]_i_1_n_7\,
S(3) => \c[12]_i_2_n_0\,
S(2) => \c[12]_i_3_n_0\,
S(1) => \c[12]_i_4_n_0\,
S(0) => \c[12]_i_5_n_0\
);
\c_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_6\,
Q => c_reg(13),
R => clear
);
\c_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_5\,
Q => c_reg(14),
R => clear
);
\c_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_4\,
Q => c_reg(15),
R => clear
);
\c_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_7\,
Q => c_reg(16),
R => clear
);
\c_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[12]_i_1_n_0\,
CO(3) => \c_reg[16]_i_1_n_0\,
CO(2) => \c_reg[16]_i_1_n_1\,
CO(1) => \c_reg[16]_i_1_n_2\,
CO(0) => \c_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[16]_i_1_n_4\,
O(2) => \c_reg[16]_i_1_n_5\,
O(1) => \c_reg[16]_i_1_n_6\,
O(0) => \c_reg[16]_i_1_n_7\,
S(3) => \c[16]_i_2_n_0\,
S(2) => \c[16]_i_3_n_0\,
S(1) => \c[16]_i_4_n_0\,
S(0) => \c[16]_i_5_n_0\
);
\c_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_6\,
Q => c_reg(17),
R => clear
);
\c_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_5\,
Q => c_reg(18),
R => clear
);
\c_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_4\,
Q => c_reg(19),
R => clear
);
\c_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_6\,
Q => c_reg(1),
R => clear
);
\c_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_7\,
Q => c_reg(20),
R => clear
);
\c_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[16]_i_1_n_0\,
CO(3) => \NLW_c_reg[20]_i_1_CO_UNCONNECTED\(3),
CO(2) => \c_reg[20]_i_1_n_1\,
CO(1) => \c_reg[20]_i_1_n_2\,
CO(0) => \c_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[20]_i_1_n_4\,
O(2) => \c_reg[20]_i_1_n_5\,
O(1) => \c_reg[20]_i_1_n_6\,
O(0) => \c_reg[20]_i_1_n_7\,
S(3) => \c[20]_i_2_n_0\,
S(2) => \c[20]_i_3_n_0\,
S(1) => \c[20]_i_4_n_0\,
S(0) => \c[20]_i_5_n_0\
);
\c_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_6\,
Q => c_reg(21),
R => clear
);
\c_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_5\,
Q => c_reg(22),
R => clear
);
\c_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_4\,
Q => c_reg(23),
R => clear
);
\c_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_5\,
Q => c_reg(2),
R => clear
);
\c_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_4\,
Q => c_reg(3),
R => clear
);
\c_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_7\,
Q => c_reg(4),
R => clear
);
\c_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[0]_i_2_n_0\,
CO(3) => \c_reg[4]_i_1_n_0\,
CO(2) => \c_reg[4]_i_1_n_1\,
CO(1) => \c_reg[4]_i_1_n_2\,
CO(0) => \c_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[4]_i_1_n_4\,
O(2) => \c_reg[4]_i_1_n_5\,
O(1) => \c_reg[4]_i_1_n_6\,
O(0) => \c_reg[4]_i_1_n_7\,
S(3) => \c[4]_i_2_n_0\,
S(2) => \c[4]_i_3_n_0\,
S(1) => \c[4]_i_4_n_0\,
S(0) => \c[4]_i_5_n_0\
);
\c_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_6\,
Q => c_reg(5),
R => clear
);
\c_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_5\,
Q => c_reg(6),
R => clear
);
\c_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_4\,
Q => c_reg(7),
R => clear
);
\c_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_7\,
Q => c_reg(8),
R => clear
);
\c_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[4]_i_1_n_0\,
CO(3) => \c_reg[8]_i_1_n_0\,
CO(2) => \c_reg[8]_i_1_n_1\,
CO(1) => \c_reg[8]_i_1_n_2\,
CO(0) => \c_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[8]_i_1_n_4\,
O(2) => \c_reg[8]_i_1_n_5\,
O(1) => \c_reg[8]_i_1_n_6\,
O(0) => \c_reg[8]_i_1_n_7\,
S(3) => \c[8]_i_2_n_0\,
S(2) => \c[8]_i_3_n_0\,
S(1) => \c[8]_i_4_n_0\,
S(0) => \c[8]_i_5_n_0\
);
\c_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_6\,
Q => c_reg(9),
R => clear
);
signal_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => signal_out_i_2_n_0,
I1 => signal_out_i_3_n_0,
I2 => signal_out_i_4_n_0,
I3 => c_reg(0),
I4 => signal_out_i_5_n_0,
O => signal_out_i_1_n_0
);
signal_out_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(3),
I1 => c_reg(4),
I2 => c_reg(1),
I3 => c_reg(2),
I4 => c_reg(6),
I5 => c_reg(5),
O => signal_out_i_2_n_0
);
signal_out_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(21),
I1 => c_reg(22),
I2 => c_reg(19),
I3 => c_reg(20),
I4 => signal_in,
I5 => c_reg(23),
O => signal_out_i_3_n_0
);
signal_out_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(15),
I1 => c_reg(16),
I2 => c_reg(13),
I3 => c_reg(14),
I4 => c_reg(18),
I5 => c_reg(17),
O => signal_out_i_4_n_0
);
signal_out_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(9),
I1 => c_reg(10),
I2 => c_reg(7),
I3 => c_reg(8),
I4 => c_reg(12),
I5 => c_reg(11),
O => signal_out_i_5_n_0
);
signal_out_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => signal_out_i_1_n_0,
Q => signal_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_debounce_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_debounce_0_0 : entity is "system_debounce_0_0,debounce,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_debounce_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_debounce_0_0 : entity is "debounce,Vivado 2016.4";
end system_debounce_0_0;
architecture STRUCTURE of system_debounce_0_0 is
begin
U0: entity work.system_debounce_0_0_debounce
port map (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
end STRUCTURE;
| mit | 35b30ece5edb6335e867213923fab62a | 0.461428 | 2.369685 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/replace/cache_replace_lru-rtl.vhdl | 1 | 6,132 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- LRU Cache Replacement Algorithm
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.numeric_pkg.all;
use util.logic_pkg.all;
library tech;
architecture rtl of cache_replace_lru is
constant assoc : natural := 2**log2_assoc;
constant state_bits : natural := (assoc-1)*log2_assoc;
type way_vector_type is array (natural range <>) of std_ulogic_vector(assoc-1 downto 0);
type statein_mru_way_tmp_type is array (assoc-1 downto 0) of std_ulogic_vector(assoc-2 downto 0);
type stateout_dec_sel_type is array (assoc-1 downto 0) of std_ulogic_vector(1 downto 0);
type comb_type is record
statein : std_ulogic_vector((assoc-1)*log2_assoc-1 downto 0);
wayin : std_ulogic_vector(assoc-1 downto 0);
statein_dec : way_vector_type(assoc-1 downto 0);
statein_mru_way_tmp : statein_mru_way_tmp_type;
statein_mru_way_unpri : std_ulogic_vector(assoc-1 downto 0);
statein_mru_way : std_ulogic_vector(assoc-1 downto 0);
stateout : std_ulogic_vector((assoc-1)*log2_assoc-1 downto 0);
stateout_dec_sel : std_ulogic_vector(assoc-2 downto 0);
stateout_dec : way_vector_type(assoc-2 downto 0);
sram_we : std_ulogic;
sram_waddr : std_ulogic_vector(index_bits-1 downto 0);
sram_wdata : std_ulogic_vector(state_bits-1 downto 0);
sram_re : std_ulogic;
sram_raddr : std_ulogic_vector(index_bits-1 downto 0);
sram_rdata : std_ulogic_vector(state_bits-1 downto 0);
end record;
signal c : comb_type;
begin
-- state is a list of queue orders
-- least significant bits -> least recently used
-- most significant bits -> most recently used
-- bits indicating MRU are not stored
-- bits are in (assoc-1) groups of size log2_assoc
-- so statein(log2_assoc-1 downto 0) is the encoded LRU way
-- stateout is statein after wayin has become the MRU way
-- stateout is generated by removing the new MRU way and shifting down less recently used ways in the decoded vector
c.statein <= wstate;
c.wayin <= wway;
statein_dec_loop : for n in assoc-2 downto 0 generate
statein_dec_decoder : entity tech.decoder(rtl)
generic map (
output_bits => assoc
)
port map (
datain => c.statein(log2_assoc*(n+1)-1 downto log2_assoc*n),
dataout => c.statein_dec(n)
);
end generate;
-- calculate the MRU way from the stored state.
-- this is just the way that isn't located at any position in the list of ways.
statein_mru_way_loop : for n in assoc-1 downto 0 generate
tmp_loop : for m in assoc-2 downto 0 generate
c.statein_mru_way_tmp(n)(m) <= c.statein_dec(m)(n);
end generate;
c.statein_mru_way(n) <= not reduce_or(c.statein_mru_way_tmp(n));
end generate;
-- if the state is uninitialized, there might be multiple ways not present in the list.
-- the prioritizer chooses the lowest of those ways as the MRU.
c.statein_dec(assoc-1) <= prioritize_least(c.statein_mru_way);
c.stateout_dec_sel(0) <= reduce_or(c.wayin and c.statein_dec(0));
stateout_dec_sel_loop : for n in assoc-2 downto 1 generate
c.stateout_dec_sel(n) <= reduce_or(c.wayin and c.statein_dec(n)) or c.stateout_dec_sel(n-1);
end generate;
with c.stateout_dec_sel(0) select
c.stateout_dec(0) <= c.statein_dec(0) when '0',
c.statein_dec(1) when '1',
(others => 'X') when others;
stateout_dec_loop : for n in assoc-2 downto 1 generate
with c.stateout_dec_sel(n) select
c.stateout_dec(n) <= c.statein_dec(n) when '0',
c.statein_dec(n+1) when '1',
(others => 'X') when others;
end generate;
stateout_loop : for n in assoc-2 downto 0 generate
stateout_encoder : entity tech.encoder(rtl)
generic map (
input_bits => assoc
)
port map (
datain => c.stateout_dec(n),
dataout => c.stateout(log2_assoc*(n+1)-1 downto log2_assoc*n)
);
end generate;
c.sram_we <= we;
c.sram_waddr <= windex;
c.sram_wdata <= c.stateout;
c.sram_re <= re;
c.sram_raddr <= rindex;
rstate <= c.sram_rdata;
-- if the stored state hasn't yet been initialized, the encoded LRU way might me larger than the total number of ways.
-- if that's the case, then return way 0 as the LRU way.
rway_decoder : entity tech.decoder(rtl)
generic map (
output_bits => 2**log2_assoc
)
port map (
datain => c.sram_rdata(log2_assoc-1 downto 0),
dataout => rway
);
sram : entity tech.syncram_1r1w(rtl)
generic map (
addr_bits => index_bits,
data_bits => state_bits,
write_first => true
)
port map (
clk => clk,
we => c.sram_we,
waddr => c.sram_waddr,
wdata => c.sram_wdata,
re => c.sram_re,
raddr => c.sram_raddr,
rdata => c.sram_rdata
);
end;
| apache-2.0 | 29c99a8f2bac0037d2c15f979bab1346 | 0.60225 | 3.573427 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_width_adapter.vhd | 1 | 10,477 | -- niosii_system_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 69;
IN_PKT_BYTE_CNT_L : integer := 67;
IN_PKT_TRANS_COMPRESSED_READ : integer := 61;
IN_PKT_BURSTWRAP_H : integer := 72;
IN_PKT_BURSTWRAP_L : integer := 70;
IN_PKT_BURST_SIZE_H : integer := 75;
IN_PKT_BURST_SIZE_L : integer := 73;
IN_PKT_RESPONSE_STATUS_H : integer := 99;
IN_PKT_RESPONSE_STATUS_L : integer := 98;
IN_PKT_TRANS_EXCLUSIVE : integer := 66;
IN_PKT_BURST_TYPE_H : integer := 77;
IN_PKT_BURST_TYPE_L : integer := 76;
IN_ST_DATA_W : integer := 100;
OUT_PKT_ADDR_H : integer := 42;
OUT_PKT_ADDR_L : integer := 18;
OUT_PKT_DATA_H : integer := 15;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 17;
OUT_PKT_BYTEEN_L : integer := 16;
OUT_PKT_BYTE_CNT_H : integer := 51;
OUT_PKT_BYTE_CNT_L : integer := 49;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 43;
OUT_PKT_BURST_SIZE_H : integer := 57;
OUT_PKT_BURST_SIZE_L : integer := 55;
OUT_PKT_RESPONSE_STATUS_H : integer := 81;
OUT_PKT_RESPONSE_STATUS_L : integer := 80;
OUT_PKT_TRANS_EXCLUSIVE : integer := 48;
OUT_PKT_BURST_TYPE_H : integer := 59;
OUT_PKT_BURST_TYPE_L : integer := 58;
OUT_ST_DATA_W : integer := 82;
ST_CHANNEL_W : integer := 13;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(99 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(81 downto 0); -- .data
out_channel : out std_logic_vector(12 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity niosii_system_width_adapter;
architecture rtl of niosii_system_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(81 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of niosii_system_width_adapter
| apache-2.0 | ff45df493cdd10fc1d0736b512875e30 | 0.460914 | 3.378588 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/bldc_motor_module.vhd | 2 | 3,955 | -------------------------------------------------------------------------------
-- Title : Motor control
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a symmetric (center-aligned) PWM with deadtime
--
-- Memory Map:
-- Base Address + 0 | W | PWM value
-- Base Address + 0 | R | unused
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
use work.commutation_pkg.all;
entity bldc_motor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
-- Number of bits for the PWM generation (e.g. 12 => 0..4095)
WIDTH : positive := 12;
PRESCALER : positive
);
port (
driver_stage_p : out bldc_driver_stage_type;
hall_p : in hall_sensor_type;
-- Disable switching
break_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end bldc_motor_module;
-------------------------------------------------------------------------------
architecture behavioral of bldc_motor_module is
type bldc_motor_module_type is record
data_out : std_logic_vector(15 downto 0); -- currently not used
pwm_value : std_logic_vector(WIDTH - 1 downto 0); -- PWM value
sd : std_logic; -- Shutdown
dir : std_logic;
end record;
signal clk_en : std_logic := '1';
signal center : std_logic; -- currently not used
signal pwm : half_bridge_type;
signal r, rin : bldc_motor_module_type := (
data_out => (others => '0'),
pwm_value => (others => '0'),
sd => '1',
dir => '0'
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i.addr, bus_i.data(15),
bus_i.data(WIDTH - 1 downto 0), bus_i.re, bus_i.we, r)
variable v : bldc_motor_module_type;
begin
v := r;
-- Set default values
v.data_out := (others => '0');
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
v.pwm_value := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
v.dir := bus_i.data(14);
elsif bus_i.re = '1' then
-- v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
pwm_generator : symmetric_pwm_deadtime
generic map (
WIDTH => WIDTH,
-- Deadtime settings:
-- 50 MHz clock => 20ns per cycle
-- T_DEAD = 20 * 20ns = 400ns
T_DEAD => 20)
port map (
pwm_p => pwm,
center_p => center,
clk_en_p => clk_en,
value_p => r.pwm_value,
break_p => break_p,
reset => '0',
clk => clk);
commutation_1 : commutation
port map (
driver_stage_p => driver_stage_p,
hall_p => hall_p,
pwm_p => pwm,
dir_p => r.dir,
sd_p => r.sd,
clk => clk);
end behavioral;
| bsd-3-clause | 490048621c434f10064ff0a8b6992520 | 0.468774 | 3.781071 | false | false | false | false |
pgavin/carpe | hdl/sim/uart/uart-behav.vhdl | 1 | 5,550 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- DEBUG
--use std.textio.all;
--library util;
--use util.io_pkg.all;
-- END DEBUG
library util;
use util.numeric_pkg.all;
use util.types_pkg.all;
use work.uart_pkg.all;
architecture behav of uart is
type uartfile is file of character;
file ifile : uartfile;
file ofile : uartfile;
type register_type is record
dataout : std_ulogic_vector2(data_bytes-1 downto 0, byte_bits-1 downto 0);
end record;
signal r : register_type;
begin
dataout <= r.dataout;
seq : process (clk) is
variable v_byte_address : std_ulogic_vector(uart_rsel_bits-1 downto 0);
variable v_status : file_open_status;
variable v_r_next : register_type;
variable v_char : character;
-- DEBUG
--variable tmpline : line;
-- END DEBUG
begin
if rising_edge(clk) then
if rstn = '0' then
file_close (ifile);
file_close (ofile);
file_open (v_status, ifile, ifilename, read_mode);
if (v_status /= open_ok) then
report "could not open UART input file " & ifilename severity error;
end if;
file_open (v_status, ofile, ofilename, write_mode);
if (v_status /= open_ok) then
report "could not open UART output file " & ofilename severity error;
end if;
r <= (
dataout => (others => (others => 'X'))
);
else
v_r_next := r;
if enable = '1' then
if wenable = '1' then
v_r_next.dataout := (others => (others => 'X'));
for n in 0 to data_bytes-1 loop
v_byte_address := address & std_ulogic_vector(to_unsigned(n, log2(data_bytes)));
if wmask(n) = '1' then
case v_byte_address is
when uart_rsel_tx => -- uart_rsel_dll
v_char := character'val(to_integer(unsigned(std_ulogic_vector2_row(datain, n))));
write(ofile, v_char);
when uart_rsel_dlm => -- uart_rsel_ier
when uart_rsel_fcr => -- uart_rsel_efr
when uart_rsel_lcr =>
when uart_rsel_mcr =>
when uart_rsel_scr =>
when others =>
end case;
end if;
end loop;
else
-- DEBUG
--write(tmpline, string'("reading address "));
--write(tmpline, address);
--write(tmpline, string'(" wmask "));
--write(tmpline, wmask);
--report tmpline.all;
--deallocate(tmpline);
-- END DEBUG
for n in 0 to data_bytes-1 loop
v_byte_address := address & std_ulogic_vector(to_unsigned(n, log2(data_bytes)));
-- DEBUG
--write(tmpline, string'("checking byte address "));
--write(tmpline, v_byte_address);
--report tmpline.all;
--deallocate(tmpline);
-- END DEBUG
if wmask(n) = '1' then
set_std_ulogic_vector2_row(v_r_next.dataout, n, (byte_bits-1 downto 0 => 'X'));
case v_byte_address is
when uart_rsel_rx =>
when uart_rsel_iir => -- uart_rsel_efr
when uart_rsel_lsr =>
set_std_ulogic_vector2_row(v_r_next.dataout, n, uart_lsr_temt or uart_lsr_thre);
-- DEBUG
--write(tmpline, string'("outputting "));
--write(tmpline, std_ulogic_vector2_row(v_r_next.dataout, n));
--report tmpline.all;
--deallocate(tmpline);
-- END DEBUG
when uart_rsel_msr =>
when uart_rsel_scr =>
when others =>
end case;
else
set_std_ulogic_vector2_row(v_r_next.dataout, n, (byte_bits-1 downto 0 => 'X'));
end if;
end loop;
end if;
end if;
r <= v_r_next;
end if;
end if;
end process;
end;
| apache-2.0 | bca43a7464a09ecd37209ea0ecf36607 | 0.478018 | 4.335938 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_sim_netlist.vhdl | 1 | 760,068 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 10:58:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_sim_netlist.vhdl
-- Design : system_vga_hessian_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_bindec : entity is "bindec";
end system_vga_hessian_0_0_bindec;
architecture STRUCTURE of system_vga_hessian_0_0_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => ena,
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => addra(1),
O => ena_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_bindec_0 is
port (
enb_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_bindec_0 : entity is "bindec";
end system_vga_hessian_0_0_bindec_0;
architecture STRUCTURE of system_vga_hessian_0_0_bindec_0 is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => enb,
I1 => addrb(0),
I2 => addrb(1),
O => enb_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(1),
I1 => addrb(0),
I2 => enb,
O => enb_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(0),
I1 => enb,
I2 => addrb(1),
O => enb_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end system_vga_hessian_0_0_blk_mem_gen_mux;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe_d1(0),
O => douta(3)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe_d1(0),
O => douta(4)
);
\douta[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe_d1(0),
O => douta(5)
);
\douta[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe_d1(0),
O => douta(6)
);
\douta[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe_d1(0),
O => douta(7)
);
\douta[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => sel_pipe_d1(0),
O => douta(8)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe_d1(0),
O => douta(0)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe_d1(0),
O => douta(1)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe_d1(0),
O => douta(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 8 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
clkb : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\ is
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC;
begin
\doutb[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(3)
);
\doutb[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(4)
);
\doutb[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(5)
);
\doutb[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(6)
);
\doutb[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(7)
);
\doutb[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPBDOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(8)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(0)
);
\doutb[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(1)
);
\doutb[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(0),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(1),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end system_vga_hessian_0_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => addrb(13 downto 0),
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 1) => B"000000000000000",
DIBDI(0) => dinb(0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => doutb(0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => enb,
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => DOPBDOP(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addra(13),
I1 => addra(12),
I2 => ena,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
I2 => enb,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end system_vga_hessian_0_0_blk_mem_gen_prim_width;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.system_vga_hessian_0_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(0) => DOPBDOP(0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end system_vga_hessian_0_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal enb_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_9\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.system_vga_hessian_0_0_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena => ena,
ena_array(2 downto 0) => ena_array(2 downto 0)
);
\bindec_b.bindec_inst_b\: entity work.system_vga_hessian_0_0_bindec_0
port map (
addrb(1 downto 0) => addrb(13 downto 12),
enb => enb,
enb_array(2 downto 0) => enb_array(2 downto 0)
);
\has_mux_a.A\: entity work.system_vga_hessian_0_0_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_16\,
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(15 downto 7),
ena => ena
);
\has_mux_b.B\: entity work.\system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_17\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addrb(1 downto 0) => addrb(13 downto 12),
clkb => clkb,
doutb(8 downto 0) => doutb(15 downto 7),
enb => enb
);
\ramloop[0].ram.r\: entity work.system_vga_hessian_0_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(2 downto 1),
dinb(1 downto 0) => dinb(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
doutb(1 downto 0) => doutb(2 downto 1),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(4 downto 3),
dinb(1 downto 0) => dinb(4 downto 3),
douta(1 downto 0) => douta(4 downto 3),
doutb(1 downto 0) => doutb(4 downto 3),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(6 downto 5),
dinb(1 downto 0) => dinb(6 downto 5),
douta(1 downto 0) => douta(6 downto 5),
doutb(1 downto 0) => doutb(6 downto 5),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[4].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[4].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[4].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[4].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[4].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[4].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[4].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[4].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[4].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7) => \ramloop[4].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[4].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[4].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[4].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[4].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[4].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[4].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[4].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[4].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[5].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[5].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[5].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[5].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[5].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[5].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[5].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[5].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[5].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[5].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(1),
enb => enb,
enb_array(0) => enb_array(1),
\top_right_1_reg[14]\(7) => \ramloop[5].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[5].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[5].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[5].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[5].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[5].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[5].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[5].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[5].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[6].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[6].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[6].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[6].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[6].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[6].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[6].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[6].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[6].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[6].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(2),
enb => enb,
enb_array(0) => enb_array(2),
\top_right_1_reg[14]\(7) => \ramloop[6].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[6].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[6].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[6].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[6].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[6].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[6].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[6].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[6].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[7].ram.r\: entity work.\system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6\
port map (
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end system_vga_hessian_0_0_blk_mem_gen_top;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.system_vga_hessian_0_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.system_vga_hessian_0_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 22.1485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 : entity is "yes";
end system_vga_hessian_0_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "blk_mem_gen_0";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_0_0_blk_mem_gen_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end system_vga_hessian_0_0_blk_mem_gen_0;
architecture STRUCTURE of system_vga_hessian_0_0_blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 22.1485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_vga_hessian_0_0_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(15 downto 0) => B"0000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0_vga_hessian is
port (
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
clk_x16 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_0_0_vga_hessian : entity is "vga_hessian";
end system_vga_hessian_0_0_vga_hessian;
architecture STRUCTURE of system_vga_hessian_0_0_vga_hessian is
signal A : STD_LOGIC_VECTOR ( 15 downto 0 );
signal B : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx : STD_LOGIC;
signal \Lxx0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_1\ : STD_LOGIC;
signal \Lxx0_carry__0_n_2\ : STD_LOGIC;
signal \Lxx0_carry__0_n_3\ : STD_LOGIC;
signal \Lxx0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_1\ : STD_LOGIC;
signal \Lxx0_carry__1_n_2\ : STD_LOGIC;
signal \Lxx0_carry__1_n_3\ : STD_LOGIC;
signal \Lxx0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_n_1\ : STD_LOGIC;
signal \Lxx0_carry__2_n_2\ : STD_LOGIC;
signal \Lxx0_carry__2_n_3\ : STD_LOGIC;
signal Lxx0_carry_i_1_n_0 : STD_LOGIC;
signal Lxx0_carry_i_2_n_0 : STD_LOGIC;
signal Lxx0_carry_i_3_n_0 : STD_LOGIC;
signal Lxx0_carry_i_4_n_0 : STD_LOGIC;
signal Lxx0_carry_i_5_n_0 : STD_LOGIC;
signal Lxx0_carry_i_6_n_0 : STD_LOGIC;
signal Lxx0_carry_n_0 : STD_LOGIC;
signal Lxx0_carry_n_1 : STD_LOGIC;
signal Lxx0_carry_n_2 : STD_LOGIC;
signal Lxx0_carry_n_3 : STD_LOGIC;
signal Lxx_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx_00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_00__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_3\ : STD_LOGIC;
signal Lxx_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lxx_11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_11__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_3\ : STD_LOGIC;
signal \Lxx_2[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[9]\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry_n_7\ : STD_LOGIC;
signal \Lxy_0[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_1 : STD_LOGIC;
signal \Lxy_1_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_2 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxy_3 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy0_carry__2_n_3\ : STD_LOGIC;
signal Lyy0_carry_i_1_n_0 : STD_LOGIC;
signal Lyy0_carry_i_2_n_0 : STD_LOGIC;
signal Lyy0_carry_i_3_n_0 : STD_LOGIC;
signal Lyy0_carry_i_4_n_0 : STD_LOGIC;
signal Lyy0_carry_i_5_n_0 : STD_LOGIC;
signal Lyy0_carry_i_6_n_0 : STD_LOGIC;
signal Lyy0_carry_n_0 : STD_LOGIC;
signal Lyy0_carry_n_1 : STD_LOGIC;
signal Lyy0_carry_n_2 : STD_LOGIC;
signal Lyy0_carry_n_3 : STD_LOGIC;
signal Lyy_0 : STD_LOGIC;
signal \Lyy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lyy_20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_20__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_3\ : STD_LOGIC;
signal \Lyy_2[15]_i_1_n_0\ : STD_LOGIC;
signal Lyy_2_bottom_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right01_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_3\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_2_top_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_top_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal addr_0 : STD_LOGIC;
signal \addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal bottom_left_0 : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \bottom_right_0[0]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[10]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[11]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[12]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[13]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[14]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_3_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_4_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_5_n_0\ : STD_LOGIC;
signal \bottom_right_0[1]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[2]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[3]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[4]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[5]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[6]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[7]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[8]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[9]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_right_1 : STD_LOGIC;
signal \bottom_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \cache[10]_5\ : STD_LOGIC;
signal \cache[9][15]_i_1_n_0\ : STD_LOGIC;
signal \cache_reg[0]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[10]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[3][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[4]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[7][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[8]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[9]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg_gate__0_n_0\ : STD_LOGIC;
signal \cache_reg_gate__10_n_0\ : STD_LOGIC;
signal \cache_reg_gate__11_n_0\ : STD_LOGIC;
signal \cache_reg_gate__12_n_0\ : STD_LOGIC;
signal \cache_reg_gate__13_n_0\ : STD_LOGIC;
signal \cache_reg_gate__14_n_0\ : STD_LOGIC;
signal \cache_reg_gate__15_n_0\ : STD_LOGIC;
signal \cache_reg_gate__16_n_0\ : STD_LOGIC;
signal \cache_reg_gate__17_n_0\ : STD_LOGIC;
signal \cache_reg_gate__18_n_0\ : STD_LOGIC;
signal \cache_reg_gate__19_n_0\ : STD_LOGIC;
signal \cache_reg_gate__1_n_0\ : STD_LOGIC;
signal \cache_reg_gate__20_n_0\ : STD_LOGIC;
signal \cache_reg_gate__21_n_0\ : STD_LOGIC;
signal \cache_reg_gate__22_n_0\ : STD_LOGIC;
signal \cache_reg_gate__23_n_0\ : STD_LOGIC;
signal \cache_reg_gate__24_n_0\ : STD_LOGIC;
signal \cache_reg_gate__25_n_0\ : STD_LOGIC;
signal \cache_reg_gate__26_n_0\ : STD_LOGIC;
signal \cache_reg_gate__27_n_0\ : STD_LOGIC;
signal \cache_reg_gate__28_n_0\ : STD_LOGIC;
signal \cache_reg_gate__29_n_0\ : STD_LOGIC;
signal \cache_reg_gate__2_n_0\ : STD_LOGIC;
signal \cache_reg_gate__30_n_0\ : STD_LOGIC;
signal \cache_reg_gate__3_n_0\ : STD_LOGIC;
signal \cache_reg_gate__4_n_0\ : STD_LOGIC;
signal \cache_reg_gate__5_n_0\ : STD_LOGIC;
signal \cache_reg_gate__6_n_0\ : STD_LOGIC;
signal \cache_reg_gate__7_n_0\ : STD_LOGIC;
signal \cache_reg_gate__8_n_0\ : STD_LOGIC;
signal \cache_reg_gate__9_n_0\ : STD_LOGIC;
signal cache_reg_gate_n_0 : STD_LOGIC;
signal cache_reg_r_0_n_0 : STD_LOGIC;
signal cache_reg_r_1_n_0 : STD_LOGIC;
signal cache_reg_r_n_0 : STD_LOGIC;
signal compute_addr_0 : STD_LOGIC;
signal \compute_addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal compute_addr_2 : STD_LOGIC;
signal \compute_addr_2[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_4_n_0\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_3 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_3[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[9]_i_1_n_0\ : STD_LOGIC;
signal corner : STD_LOGIC;
signal \corner_reg_n_0_[0]\ : STD_LOGIC;
signal \corner_reg_n_0_[10]\ : STD_LOGIC;
signal \corner_reg_n_0_[11]\ : STD_LOGIC;
signal \corner_reg_n_0_[12]\ : STD_LOGIC;
signal \corner_reg_n_0_[13]\ : STD_LOGIC;
signal \corner_reg_n_0_[14]\ : STD_LOGIC;
signal \corner_reg_n_0_[15]\ : STD_LOGIC;
signal \corner_reg_n_0_[1]\ : STD_LOGIC;
signal \corner_reg_n_0_[2]\ : STD_LOGIC;
signal \corner_reg_n_0_[3]\ : STD_LOGIC;
signal \corner_reg_n_0_[4]\ : STD_LOGIC;
signal \corner_reg_n_0_[5]\ : STD_LOGIC;
signal \corner_reg_n_0_[6]\ : STD_LOGIC;
signal \corner_reg_n_0_[7]\ : STD_LOGIC;
signal \corner_reg_n_0_[8]\ : STD_LOGIC;
signal \corner_reg_n_0_[9]\ : STD_LOGIC;
signal cycle : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cycle[0]_i_1_n_0\ : STD_LOGIC;
signal \cycle[0]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1__0_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_2_n_0\ : STD_LOGIC;
signal \cycle_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[2]_rep_n_0\ : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data2 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data5 : STD_LOGIC_VECTOR ( 13 downto 10 );
signal det_0 : STD_LOGIC;
signal det_0_reg_i_2_n_0 : STD_LOGIC;
signal det_0_reg_n_106 : STD_LOGIC;
signal det_0_reg_n_107 : STD_LOGIC;
signal det_0_reg_n_108 : STD_LOGIC;
signal det_0_reg_n_109 : STD_LOGIC;
signal det_0_reg_n_110 : STD_LOGIC;
signal det_0_reg_n_111 : STD_LOGIC;
signal det_0_reg_n_112 : STD_LOGIC;
signal det_0_reg_n_113 : STD_LOGIC;
signal det_0_reg_n_114 : STD_LOGIC;
signal det_0_reg_n_115 : STD_LOGIC;
signal det_0_reg_n_116 : STD_LOGIC;
signal det_0_reg_n_117 : STD_LOGIC;
signal det_0_reg_n_118 : STD_LOGIC;
signal det_0_reg_n_119 : STD_LOGIC;
signal det_0_reg_n_120 : STD_LOGIC;
signal det_0_reg_n_121 : STD_LOGIC;
signal det_0_reg_n_122 : STD_LOGIC;
signal det_0_reg_n_123 : STD_LOGIC;
signal det_0_reg_n_124 : STD_LOGIC;
signal det_0_reg_n_125 : STD_LOGIC;
signal det_0_reg_n_126 : STD_LOGIC;
signal det_0_reg_n_127 : STD_LOGIC;
signal det_0_reg_n_128 : STD_LOGIC;
signal det_0_reg_n_129 : STD_LOGIC;
signal det_0_reg_n_130 : STD_LOGIC;
signal det_0_reg_n_131 : STD_LOGIC;
signal det_0_reg_n_132 : STD_LOGIC;
signal det_0_reg_n_133 : STD_LOGIC;
signal det_0_reg_n_134 : STD_LOGIC;
signal det_0_reg_n_135 : STD_LOGIC;
signal det_0_reg_n_136 : STD_LOGIC;
signal det_0_reg_n_137 : STD_LOGIC;
signal det_0_reg_n_138 : STD_LOGIC;
signal det_0_reg_n_139 : STD_LOGIC;
signal det_0_reg_n_140 : STD_LOGIC;
signal det_0_reg_n_141 : STD_LOGIC;
signal det_0_reg_n_142 : STD_LOGIC;
signal det_0_reg_n_143 : STD_LOGIC;
signal det_0_reg_n_144 : STD_LOGIC;
signal det_0_reg_n_145 : STD_LOGIC;
signal det_0_reg_n_146 : STD_LOGIC;
signal det_0_reg_n_147 : STD_LOGIC;
signal det_0_reg_n_148 : STD_LOGIC;
signal det_0_reg_n_149 : STD_LOGIC;
signal det_0_reg_n_150 : STD_LOGIC;
signal det_0_reg_n_151 : STD_LOGIC;
signal det_0_reg_n_152 : STD_LOGIC;
signal det_0_reg_n_153 : STD_LOGIC;
signal det_abs : STD_LOGIC_VECTOR ( 31 downto 0 );
signal det_abs0 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \det_abs[10]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[11]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[13]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[14]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[15]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[17]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[18]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[19]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[1]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[21]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[22]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[23]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[25]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[26]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[27]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[29]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[2]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[30]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[3]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_7_n_0\ : STD_LOGIC;
signal \det_abs[5]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[6]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[7]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[9]_i_1_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_3\ : STD_LOGIC;
signal det_reg_n_100 : STD_LOGIC;
signal det_reg_n_101 : STD_LOGIC;
signal det_reg_n_102 : STD_LOGIC;
signal det_reg_n_103 : STD_LOGIC;
signal det_reg_n_104 : STD_LOGIC;
signal det_reg_n_105 : STD_LOGIC;
signal det_reg_n_74 : STD_LOGIC;
signal det_reg_n_75 : STD_LOGIC;
signal det_reg_n_76 : STD_LOGIC;
signal det_reg_n_77 : STD_LOGIC;
signal det_reg_n_78 : STD_LOGIC;
signal det_reg_n_79 : STD_LOGIC;
signal det_reg_n_80 : STD_LOGIC;
signal det_reg_n_81 : STD_LOGIC;
signal det_reg_n_82 : STD_LOGIC;
signal det_reg_n_83 : STD_LOGIC;
signal det_reg_n_84 : STD_LOGIC;
signal det_reg_n_85 : STD_LOGIC;
signal det_reg_n_86 : STD_LOGIC;
signal det_reg_n_87 : STD_LOGIC;
signal det_reg_n_88 : STD_LOGIC;
signal det_reg_n_89 : STD_LOGIC;
signal det_reg_n_90 : STD_LOGIC;
signal det_reg_n_91 : STD_LOGIC;
signal det_reg_n_92 : STD_LOGIC;
signal det_reg_n_93 : STD_LOGIC;
signal det_reg_n_94 : STD_LOGIC;
signal det_reg_n_95 : STD_LOGIC;
signal det_reg_n_96 : STD_LOGIC;
signal det_reg_n_97 : STD_LOGIC;
signal det_reg_n_98 : STD_LOGIC;
signal det_reg_n_99 : STD_LOGIC;
signal \din_reg_n_0_[0]\ : STD_LOGIC;
signal \din_reg_n_0_[10]\ : STD_LOGIC;
signal \din_reg_n_0_[11]\ : STD_LOGIC;
signal \din_reg_n_0_[12]\ : STD_LOGIC;
signal \din_reg_n_0_[13]\ : STD_LOGIC;
signal \din_reg_n_0_[14]\ : STD_LOGIC;
signal \din_reg_n_0_[15]\ : STD_LOGIC;
signal \din_reg_n_0_[1]\ : STD_LOGIC;
signal \din_reg_n_0_[2]\ : STD_LOGIC;
signal \din_reg_n_0_[3]\ : STD_LOGIC;
signal \din_reg_n_0_[4]\ : STD_LOGIC;
signal \din_reg_n_0_[5]\ : STD_LOGIC;
signal \din_reg_n_0_[6]\ : STD_LOGIC;
signal \din_reg_n_0_[7]\ : STD_LOGIC;
signal \din_reg_n_0_[8]\ : STD_LOGIC;
signal \din_reg_n_0_[9]\ : STD_LOGIC;
signal dout_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal dout_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal last_value : STD_LOGIC_VECTOR ( 7 downto 0 );
signal left : STD_LOGIC;
signal \left[15]_i_2_n_0\ : STD_LOGIC;
signal \left[15]_i_3_n_0\ : STD_LOGIC;
signal \left_reg_n_0_[0]\ : STD_LOGIC;
signal \left_reg_n_0_[10]\ : STD_LOGIC;
signal \left_reg_n_0_[11]\ : STD_LOGIC;
signal \left_reg_n_0_[12]\ : STD_LOGIC;
signal \left_reg_n_0_[13]\ : STD_LOGIC;
signal \left_reg_n_0_[14]\ : STD_LOGIC;
signal \left_reg_n_0_[15]\ : STD_LOGIC;
signal \left_reg_n_0_[1]\ : STD_LOGIC;
signal \left_reg_n_0_[2]\ : STD_LOGIC;
signal \left_reg_n_0_[3]\ : STD_LOGIC;
signal \left_reg_n_0_[4]\ : STD_LOGIC;
signal \left_reg_n_0_[5]\ : STD_LOGIC;
signal \left_reg_n_0_[6]\ : STD_LOGIC;
signal \left_reg_n_0_[7]\ : STD_LOGIC;
signal \left_reg_n_0_[8]\ : STD_LOGIC;
signal \left_reg_n_0_[9]\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \plusOp_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_7\ : STD_LOGIC;
signal top : STD_LOGIC;
signal \top[15]_i_2_n_0\ : STD_LOGIC;
signal top_left_0 : STD_LOGIC;
signal \top_left_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \top_left_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_reg_n_0_[0]\ : STD_LOGIC;
signal \top_reg_n_0_[10]\ : STD_LOGIC;
signal \top_reg_n_0_[11]\ : STD_LOGIC;
signal \top_reg_n_0_[12]\ : STD_LOGIC;
signal \top_reg_n_0_[13]\ : STD_LOGIC;
signal \top_reg_n_0_[14]\ : STD_LOGIC;
signal \top_reg_n_0_[15]\ : STD_LOGIC;
signal \top_reg_n_0_[1]\ : STD_LOGIC;
signal \top_reg_n_0_[2]\ : STD_LOGIC;
signal \top_reg_n_0_[3]\ : STD_LOGIC;
signal \top_reg_n_0_[4]\ : STD_LOGIC;
signal \top_reg_n_0_[5]\ : STD_LOGIC;
signal \top_reg_n_0_[6]\ : STD_LOGIC;
signal \top_reg_n_0_[7]\ : STD_LOGIC;
signal \top_reg_n_0_[8]\ : STD_LOGIC;
signal \top_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_0 : STD_LOGIC;
signal \top_right_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_1 : STD_LOGIC;
signal \top_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \value_reg_n_0_[0]\ : STD_LOGIC;
signal \value_reg_n_0_[1]\ : STD_LOGIC;
signal \value_reg_n_0_[2]\ : STD_LOGIC;
signal \value_reg_n_0_[3]\ : STD_LOGIC;
signal \value_reg_n_0_[4]\ : STD_LOGIC;
signal \value_reg_n_0_[5]\ : STD_LOGIC;
signal \value_reg_n_0_[6]\ : STD_LOGIC;
signal \value_reg_n_0_[7]\ : STD_LOGIC;
signal wen_i_1_n_0 : STD_LOGIC;
signal wen_i_2_n_0 : STD_LOGIC;
signal wen_reg_n_0 : STD_LOGIC;
signal x : STD_LOGIC;
signal \x0[0]_i_2_n_0\ : STD_LOGIC;
signal \x0[0]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_2_n_0\ : STD_LOGIC;
signal \x0[1]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_1_n_0\ : STD_LOGIC;
signal \x0[2]_i_2_n_0\ : STD_LOGIC;
signal \x0[2]_i_3_n_0\ : STD_LOGIC;
signal \x0[2]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_1_n_0\ : STD_LOGIC;
signal \x0[3]_i_2_n_0\ : STD_LOGIC;
signal \x0[3]_i_3_n_0\ : STD_LOGIC;
signal \x0[3]_i_4_n_0\ : STD_LOGIC;
signal \x0[3]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_6_n_0\ : STD_LOGIC;
signal \x0[4]_i_1_n_0\ : STD_LOGIC;
signal \x0[4]_i_2_n_0\ : STD_LOGIC;
signal \x0[4]_i_3_n_0\ : STD_LOGIC;
signal \x0[4]_i_4_n_0\ : STD_LOGIC;
signal \x0[4]_i_5_n_0\ : STD_LOGIC;
signal \x0[5]_i_1_n_0\ : STD_LOGIC;
signal \x0[5]_i_2_n_0\ : STD_LOGIC;
signal \x0[5]_i_3_n_0\ : STD_LOGIC;
signal \x0[5]_i_4_n_0\ : STD_LOGIC;
signal \x0[5]_i_5_n_0\ : STD_LOGIC;
signal \x0[6]_i_1_n_0\ : STD_LOGIC;
signal \x0[6]_i_2_n_0\ : STD_LOGIC;
signal \x0[6]_i_3_n_0\ : STD_LOGIC;
signal \x0[6]_i_4_n_0\ : STD_LOGIC;
signal \x0[6]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_1_n_0\ : STD_LOGIC;
signal \x0[7]_i_2_n_0\ : STD_LOGIC;
signal \x0[7]_i_3_n_0\ : STD_LOGIC;
signal \x0[7]_i_4_n_0\ : STD_LOGIC;
signal \x0[7]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_6_n_0\ : STD_LOGIC;
signal \x0[7]_i_7_n_0\ : STD_LOGIC;
signal \x0[8]_i_1_n_0\ : STD_LOGIC;
signal \x0[8]_i_2_n_0\ : STD_LOGIC;
signal \x0[8]_i_3_n_0\ : STD_LOGIC;
signal \x0[8]_i_4_n_0\ : STD_LOGIC;
signal \x0[8]_i_5_n_0\ : STD_LOGIC;
signal \x0[8]_i_6_n_0\ : STD_LOGIC;
signal \x0[8]_i_7_n_0\ : STD_LOGIC;
signal \x0[9]_i_1_n_0\ : STD_LOGIC;
signal \x0[9]_i_2_n_0\ : STD_LOGIC;
signal \x0[9]_i_3_n_0\ : STD_LOGIC;
signal \x0[9]_i_4_n_0\ : STD_LOGIC;
signal \x0[9]_i_5_n_0\ : STD_LOGIC;
signal \x0[9]_i_6_n_0\ : STD_LOGIC;
signal \x0[9]_i_7_n_0\ : STD_LOGIC;
signal \x0_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \x0_reg[1]_i_1_n_0\ : STD_LOGIC;
signal x1 : STD_LOGIC;
signal \x1[0]_i_1_n_0\ : STD_LOGIC;
signal \x1[1]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_2_n_0\ : STD_LOGIC;
signal \x1[2]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_1_n_0\ : STD_LOGIC;
signal \x1[3]_i_2_n_0\ : STD_LOGIC;
signal \x1[3]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_1_n_0\ : STD_LOGIC;
signal \x1[4]_i_2_n_0\ : STD_LOGIC;
signal \x1[4]_i_3_n_0\ : STD_LOGIC;
signal \x1[4]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_5_n_0\ : STD_LOGIC;
signal \x1[5]_i_1_n_0\ : STD_LOGIC;
signal \x1[5]_i_2_n_0\ : STD_LOGIC;
signal \x1[5]_i_3_n_0\ : STD_LOGIC;
signal \x1[5]_i_4_n_0\ : STD_LOGIC;
signal \x1[5]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_1_n_0\ : STD_LOGIC;
signal \x1[6]_i_2_n_0\ : STD_LOGIC;
signal \x1[6]_i_3_n_0\ : STD_LOGIC;
signal \x1[6]_i_4_n_0\ : STD_LOGIC;
signal \x1[6]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_6_n_0\ : STD_LOGIC;
signal \x1[6]_i_7_n_0\ : STD_LOGIC;
signal \x1[6]_i_8_n_0\ : STD_LOGIC;
signal \x1[7]_i_1_n_0\ : STD_LOGIC;
signal \x1[7]_i_2_n_0\ : STD_LOGIC;
signal \x1[7]_i_3_n_0\ : STD_LOGIC;
signal \x1[7]_i_4_n_0\ : STD_LOGIC;
signal \x1[7]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_1_n_0\ : STD_LOGIC;
signal \x1[8]_i_2_n_0\ : STD_LOGIC;
signal \x1[8]_i_3_n_0\ : STD_LOGIC;
signal \x1[8]_i_4_n_0\ : STD_LOGIC;
signal \x1[8]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_2_n_0\ : STD_LOGIC;
signal \x1[9]_i_3_n_0\ : STD_LOGIC;
signal \x1[9]_i_4_n_0\ : STD_LOGIC;
signal \x1[9]_i_5_n_0\ : STD_LOGIC;
signal \x1[9]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_7_n_0\ : STD_LOGIC;
signal \x1[9]_i_8_n_0\ : STD_LOGIC;
signal \x_reg_n_0_[0]\ : STD_LOGIC;
signal \x_reg_n_0_[1]\ : STD_LOGIC;
signal \x_reg_n_0_[2]\ : STD_LOGIC;
signal \x_reg_n_0_[3]\ : STD_LOGIC;
signal \x_reg_n_0_[4]\ : STD_LOGIC;
signal \x_reg_n_0_[5]\ : STD_LOGIC;
signal \x_reg_n_0_[6]\ : STD_LOGIC;
signal \x_reg_n_0_[7]\ : STD_LOGIC;
signal \x_reg_n_0_[8]\ : STD_LOGIC;
signal \x_reg_n_0_[9]\ : STD_LOGIC;
signal y1 : STD_LOGIC;
signal \y1[2]_i_1_n_0\ : STD_LOGIC;
signal \y1[3]_i_1_n_0\ : STD_LOGIC;
signal \y1_reg_n_0_[0]\ : STD_LOGIC;
signal \y1_reg_n_0_[1]\ : STD_LOGIC;
signal \y1_reg_n_0_[2]\ : STD_LOGIC;
signal \y1_reg_n_0_[3]\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2[1]_i_1_n_0\ : STD_LOGIC;
signal \y2[2]_i_1_n_0\ : STD_LOGIC;
signal \y2[3]_i_1_n_0\ : STD_LOGIC;
signal \y2_reg_n_0_[0]\ : STD_LOGIC;
signal \y2_reg_n_0_[1]\ : STD_LOGIC;
signal \y2_reg_n_0_[2]\ : STD_LOGIC;
signal \y2_reg_n_0_[3]\ : STD_LOGIC;
signal y3 : STD_LOGIC;
signal \y3[1]_i_1_n_0\ : STD_LOGIC;
signal \y3[2]_i_1_n_0\ : STD_LOGIC;
signal \y3[3]_i_1_n_0\ : STD_LOGIC;
signal \y3_reg_n_0_[0]\ : STD_LOGIC;
signal \y3_reg_n_0_[1]\ : STD_LOGIC;
signal \y3_reg_n_0_[2]\ : STD_LOGIC;
signal \y3_reg_n_0_[3]\ : STD_LOGIC;
signal \y4[2]_i_1_n_0\ : STD_LOGIC;
signal \y4[3]_i_1_n_0\ : STD_LOGIC;
signal y5 : STD_LOGIC;
signal \y5[0]_i_1_n_0\ : STD_LOGIC;
signal \y5[1]_i_1_n_0\ : STD_LOGIC;
signal \y5[2]_i_1_n_0\ : STD_LOGIC;
signal \y5[3]_i_1_n_0\ : STD_LOGIC;
signal y6 : STD_LOGIC;
signal \y6[2]_i_1_n_0\ : STD_LOGIC;
signal \y6[3]_i_1_n_0\ : STD_LOGIC;
signal \y6_reg_n_0_[0]\ : STD_LOGIC;
signal \y6_reg_n_0_[1]\ : STD_LOGIC;
signal \y6_reg_n_0_[2]\ : STD_LOGIC;
signal \y6_reg_n_0_[3]\ : STD_LOGIC;
signal y7 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y7[2]_i_1_n_0\ : STD_LOGIC;
signal \y7[3]_i_1_n_0\ : STD_LOGIC;
signal y8 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y8[3]_i_1_n_0\ : STD_LOGIC;
signal y9 : STD_LOGIC;
signal \y9[3]_i_1_n_0\ : STD_LOGIC;
signal \y_actual_reg_n_0_[0]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[1]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[2]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[3]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[4]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[5]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[6]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[7]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[8]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[9]\ : STD_LOGIC;
signal \NLW_Lxx0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_0_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_0_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_0_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_det_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute HLUTNM : string;
attribute HLUTNM of \Lxx0_carry__0_i_1\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_2\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_3\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__0_i_4\ : label is "lutpair1";
attribute HLUTNM of \Lxx0_carry__0_i_5\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__0_i_6\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_7\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_8\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__1_i_1\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_2\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_3\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__1_i_4\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__1_i_5\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__1_i_6\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_7\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_8\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__2_i_1\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_2\ : label is "lutpair10";
attribute HLUTNM of \Lxx0_carry__2_i_3\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__2_i_6\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_7\ : label is "lutpair10";
attribute HLUTNM of Lxx0_carry_i_1 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_2 : label is "lutpair24";
attribute HLUTNM of Lxx0_carry_i_3 : label is "lutpair1";
attribute HLUTNM of Lxx0_carry_i_4 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_5 : label is "lutpair24";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_10\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_8\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_10\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_8\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_10\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_8\ : label is "soft_lutpair32";
attribute HLUTNM of \Lyy0_carry__0_i_1\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_2\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_3\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__0_i_4\ : label is "lutpair13";
attribute HLUTNM of \Lyy0_carry__0_i_5\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__0_i_6\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_7\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_8\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__1_i_1\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_2\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_3\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__1_i_4\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__1_i_5\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__1_i_6\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_7\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_8\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__2_i_1\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_2\ : label is "lutpair22";
attribute HLUTNM of \Lyy0_carry__2_i_3\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__2_i_6\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_7\ : label is "lutpair22";
attribute HLUTNM of Lyy0_carry_i_1 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_2 : label is "lutpair25";
attribute HLUTNM of Lyy0_carry_i_3 : label is "lutpair13";
attribute HLUTNM of Lyy0_carry_i_4 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_5 : label is "lutpair25";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_10\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_11\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_9\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_10\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_9\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_10\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_8\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry_i_8\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_11\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \addr_0[0]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[10]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[11]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[12]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[13]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_0[2]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[5]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[6]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[7]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[8]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[9]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_1[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \addr_1[10]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[11]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[12]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[13]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[2]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[3]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[4]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[5]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[6]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[7]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[8]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[9]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \bottom_right_0[0]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bottom_right_0[14]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_5\ : label is "soft_lutpair12";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_0 : label is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_0 : label is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_0 : label is "blk_mem_gen_v8_3_5,Vivado 2016.4";
attribute srl_bus_name : string;
attribute srl_bus_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name : string;
attribute srl_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 ";
attribute SOFT_HLUTNM of cache_reg_gate : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__10\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \cache_reg_gate__11\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__12\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__13\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__14\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__15\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__16\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__17\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__18\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__19\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__20\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__21\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__22\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__23\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__24\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__25\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__26\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__27\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__28\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__29\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__3\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__30\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__4\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__5\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__6\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__7\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__8\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__9\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \compute_addr_0[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \compute_addr_2[10]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[11]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[12]_i_2\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_3[10]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[11]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[12]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \compute_addr_3[13]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \cycle[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \cycle[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[3]_i_2\ : label is "soft_lutpair15";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cycle_reg[0]\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[0]_rep\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[1]\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep__0\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[2]\ : label is "cycle_reg[2]";
attribute ORIG_CELL_NAME of \cycle_reg[2]_rep\ : label is "cycle_reg[2]";
attribute SOFT_HLUTNM of \det_abs[10]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[11]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[12]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[13]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[14]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[15]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[16]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[17]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[18]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[19]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \det_abs[1]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[21]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[22]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[24]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[25]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[26]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[27]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[28]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[30]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[5]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[6]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[8]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[9]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \left[15]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \left[15]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x0[1]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x0[2]_i_4\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[2]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x0[3]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \x0[3]_i_5\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[4]_i_4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[4]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[5]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x0[5]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[7]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x0[7]_i_6\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \x0[8]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[8]_i_5\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x0[8]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x0[8]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[9]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x1[3]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_5\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[5]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[5]_i_5\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x1[6]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x1[6]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[6]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[6]_i_8\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x1[7]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x1[7]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x1[8]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x1[9]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x1[9]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y1[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \y1[3]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y2[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y3[1]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y3[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y3[3]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y4[2]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y4[3]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y5[0]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y5[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y5[2]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y5[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y6[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y6[3]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y7[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y7[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y9[3]_i_1\ : label is "soft_lutpair20";
begin
Lxx0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lxx0_carry_n_0,
CO(2) => Lxx0_carry_n_1,
CO(1) => Lxx0_carry_n_2,
CO(0) => Lxx0_carry_n_3,
CYINIT => '0',
DI(3) => Lxx0_carry_i_1_n_0,
DI(2) => Lxx0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lxx_2_reg_n_0_[0]\,
O(3 downto 0) => A(3 downto 0),
S(3) => Lxx0_carry_i_3_n_0,
S(2) => Lxx0_carry_i_4_n_0,
S(1) => Lxx0_carry_i_5_n_0,
S(0) => Lxx0_carry_i_6_n_0
);
\Lxx0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lxx0_carry_n_0,
CO(3) => \Lxx0_carry__0_n_0\,
CO(2) => \Lxx0_carry__0_n_1\,
CO(1) => \Lxx0_carry__0_n_2\,
CO(0) => \Lxx0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__0_i_1_n_0\,
DI(2) => \Lxx0_carry__0_i_2_n_0\,
DI(1) => \Lxx0_carry__0_i_3_n_0\,
DI(0) => \Lxx0_carry__0_i_4_n_0\,
O(3 downto 0) => A(7 downto 4),
S(3) => \Lxx0_carry__0_i_5_n_0\,
S(2) => \Lxx0_carry__0_i_6_n_0\,
S(1) => \Lxx0_carry__0_i_7_n_0\,
S(0) => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
O => \Lxx0_carry__0_i_1_n_0\
);
\Lxx0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
O => \Lxx0_carry__0_i_2_n_0\
);
\Lxx0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
O => \Lxx0_carry__0_i_3_n_0\
);
\Lxx0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
O => \Lxx0_carry__0_i_4_n_0\
);
\Lxx0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
I3 => \Lxx0_carry__0_i_1_n_0\,
O => \Lxx0_carry__0_i_5_n_0\
);
\Lxx0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
I3 => \Lxx0_carry__0_i_2_n_0\,
O => \Lxx0_carry__0_i_6_n_0\
);
\Lxx0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
I3 => \Lxx0_carry__0_i_3_n_0\,
O => \Lxx0_carry__0_i_7_n_0\
);
\Lxx0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
I3 => \Lxx0_carry__0_i_4_n_0\,
O => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__0_n_0\,
CO(3) => \Lxx0_carry__1_n_0\,
CO(2) => \Lxx0_carry__1_n_1\,
CO(1) => \Lxx0_carry__1_n_2\,
CO(0) => \Lxx0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__1_i_1_n_0\,
DI(2) => \Lxx0_carry__1_i_2_n_0\,
DI(1) => \Lxx0_carry__1_i_3_n_0\,
DI(0) => \Lxx0_carry__1_i_4_n_0\,
O(3 downto 0) => A(11 downto 8),
S(3) => \Lxx0_carry__1_i_5_n_0\,
S(2) => \Lxx0_carry__1_i_6_n_0\,
S(1) => \Lxx0_carry__1_i_7_n_0\,
S(0) => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
O => \Lxx0_carry__1_i_1_n_0\
);
\Lxx0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
O => \Lxx0_carry__1_i_2_n_0\
);
\Lxx0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
O => \Lxx0_carry__1_i_3_n_0\
);
\Lxx0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
O => \Lxx0_carry__1_i_4_n_0\
);
\Lxx0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
I3 => \Lxx0_carry__1_i_1_n_0\,
O => \Lxx0_carry__1_i_5_n_0\
);
\Lxx0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
I3 => \Lxx0_carry__1_i_2_n_0\,
O => \Lxx0_carry__1_i_6_n_0\
);
\Lxx0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
I3 => \Lxx0_carry__1_i_3_n_0\,
O => \Lxx0_carry__1_i_7_n_0\
);
\Lxx0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
I3 => \Lxx0_carry__1_i_4_n_0\,
O => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__1_n_0\,
CO(3) => \NLW_Lxx0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx0_carry__2_n_1\,
CO(1) => \Lxx0_carry__2_n_2\,
CO(0) => \Lxx0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx0_carry__2_i_1_n_0\,
DI(1) => \Lxx0_carry__2_i_2_n_0\,
DI(0) => \Lxx0_carry__2_i_3_n_0\,
O(3 downto 0) => A(15 downto 12),
S(3) => \Lxx0_carry__2_i_4_n_0\,
S(2) => \Lxx0_carry__2_i_5_n_0\,
S(1) => \Lxx0_carry__2_i_6_n_0\,
S(0) => \Lxx0_carry__2_i_7_n_0\
);
\Lxx0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
O => \Lxx0_carry__2_i_1_n_0\
);
\Lxx0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
O => \Lxx0_carry__2_i_2_n_0\
);
\Lxx0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
O => \Lxx0_carry__2_i_3_n_0\
);
\Lxx0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => Lxx_0(14),
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => \Lxx_2_reg_n_0_[15]\,
I4 => Lxx_1(15),
I5 => Lxx_0(15),
O => \Lxx0_carry__2_i_4_n_0\
);
\Lxx0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxx0_carry__2_i_1_n_0\,
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => Lxx_0(14),
O => \Lxx0_carry__2_i_5_n_0\
);
\Lxx0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
I3 => \Lxx0_carry__2_i_2_n_0\,
O => \Lxx0_carry__2_i_6_n_0\
);
\Lxx0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
I3 => \Lxx0_carry__2_i_3_n_0\,
O => \Lxx0_carry__2_i_7_n_0\
);
Lxx0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
O => Lxx0_carry_i_1_n_0
);
Lxx0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_2_n_0
);
Lxx0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
I3 => Lxx0_carry_i_1_n_0,
O => Lxx0_carry_i_3_n_0
);
Lxx0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
I3 => Lxx0_carry_i_2_n_0,
O => Lxx0_carry_i_4_n_0
);
Lxx0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_5_n_0
);
Lxx0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lxx_2_reg_n_0_[0]\,
I1 => Lxx_0(0),
O => Lxx0_carry_i_6_n_0
);
\Lxx_00__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_00__1_carry_n_0\,
CO(2) => \Lxx_00__1_carry_n_1\,
CO(1) => \Lxx_00__1_carry_n_2\,
CO(0) => \Lxx_00__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry_i_1_n_0\,
DI(2) => \Lxx_00__1_carry_i_2_n_0\,
DI(1) => \Lxx_00__1_carry_i_3_n_0\,
DI(0) => \bottom_right_0_reg_n_0_[0]\,
O(3 downto 0) => Lxx_00(3 downto 0),
S(3) => \Lxx_00__1_carry_i_4_n_0\,
S(2) => \Lxx_00__1_carry_i_5_n_0\,
S(1) => \Lxx_00__1_carry_i_6_n_0\,
S(0) => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry_n_0\,
CO(3) => \Lxx_00__1_carry__0_n_0\,
CO(2) => \Lxx_00__1_carry__0_n_1\,
CO(1) => \Lxx_00__1_carry__0_n_2\,
CO(0) => \Lxx_00__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_00(7 downto 4),
S(3) => \Lxx_00__1_carry__0_i_5_n_0\,
S(2) => \Lxx_00__1_carry__0_i_6_n_0\,
S(1) => \Lxx_00__1_carry__0_i_7_n_0\,
S(0) => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[6]\,
I1 => \Lxx_00__1_carry__0_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[5]\,
I3 => \top_right_0_reg_n_0_[5]\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_1_n_0\
);
\Lxx_00__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[5]\,
I1 => \top_right_0_reg_n_0_[5]\,
I2 => \top_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_10_n_0\
);
\Lxx_00__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[4]\,
I1 => \top_right_0_reg_n_0_[4]\,
I2 => \top_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_11_n_0\
);
\Lxx_00__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[7]\,
I1 => \top_right_0_reg_n_0_[7]\,
I2 => \top_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__0_i_12_n_0\
);
\Lxx_00__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[5]\,
I1 => \Lxx_00__1_carry__0_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[4]\,
I3 => \top_right_0_reg_n_0_[4]\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_2_n_0\
);
\Lxx_00__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[4]\,
I1 => \Lxx_00__1_carry__0_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[3]\,
I3 => \top_right_0_reg_n_0_[3]\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry__0_i_3_n_0\
);
\Lxx_00__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[3]\,
I1 => \Lxx_00__1_carry_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[2]\,
I3 => \top_right_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry__0_i_4_n_0\
);
\Lxx_00__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[6]\,
I2 => \top_right_0_reg_n_0_[6]\,
I3 => \bottom_left_0_reg_n_0_[6]\,
I4 => \bottom_right_0_reg_n_0_[7]\,
I5 => \Lxx_00__1_carry__0_i_12_n_0\,
O => \Lxx_00__1_carry__0_i_5_n_0\
);
\Lxx_00__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[5]\,
I2 => \top_right_0_reg_n_0_[5]\,
I3 => \bottom_left_0_reg_n_0_[5]\,
I4 => \bottom_right_0_reg_n_0_[6]\,
I5 => \Lxx_00__1_carry__0_i_9_n_0\,
O => \Lxx_00__1_carry__0_i_6_n_0\
);
\Lxx_00__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[4]\,
I2 => \top_right_0_reg_n_0_[4]\,
I3 => \bottom_left_0_reg_n_0_[4]\,
I4 => \bottom_right_0_reg_n_0_[5]\,
I5 => \Lxx_00__1_carry__0_i_10_n_0\,
O => \Lxx_00__1_carry__0_i_7_n_0\
);
\Lxx_00__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[3]\,
I2 => \top_right_0_reg_n_0_[3]\,
I3 => \bottom_left_0_reg_n_0_[3]\,
I4 => \bottom_right_0_reg_n_0_[4]\,
I5 => \Lxx_00__1_carry__0_i_11_n_0\,
O => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[6]\,
I1 => \top_right_0_reg_n_0_[6]\,
I2 => \top_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__0_i_9_n_0\
);
\Lxx_00__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__0_n_0\,
CO(3) => \Lxx_00__1_carry__1_n_0\,
CO(2) => \Lxx_00__1_carry__1_n_1\,
CO(1) => \Lxx_00__1_carry__1_n_2\,
CO(0) => \Lxx_00__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_00(11 downto 8),
S(3) => \Lxx_00__1_carry__1_i_5_n_0\,
S(2) => \Lxx_00__1_carry__1_i_6_n_0\,
S(1) => \Lxx_00__1_carry__1_i_7_n_0\,
S(0) => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[10]\,
I1 => \Lxx_00__1_carry__1_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[9]\,
I3 => \top_right_0_reg_n_0_[9]\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_1_n_0\
);
\Lxx_00__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[9]\,
I1 => \top_right_0_reg_n_0_[9]\,
I2 => \top_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_10_n_0\
);
\Lxx_00__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[8]\,
I1 => \top_right_0_reg_n_0_[8]\,
I2 => \top_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_11_n_0\
);
\Lxx_00__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[11]\,
I1 => \top_right_0_reg_n_0_[11]\,
I2 => \top_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__1_i_12_n_0\
);
\Lxx_00__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[9]\,
I1 => \Lxx_00__1_carry__1_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[8]\,
I3 => \top_right_0_reg_n_0_[8]\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_2_n_0\
);
\Lxx_00__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[8]\,
I1 => \Lxx_00__1_carry__1_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[7]\,
I3 => \top_right_0_reg_n_0_[7]\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__1_i_3_n_0\
);
\Lxx_00__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[7]\,
I1 => \Lxx_00__1_carry__0_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[6]\,
I3 => \top_right_0_reg_n_0_[6]\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__1_i_4_n_0\
);
\Lxx_00__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[10]\,
I2 => \top_right_0_reg_n_0_[10]\,
I3 => \bottom_left_0_reg_n_0_[10]\,
I4 => \bottom_right_0_reg_n_0_[11]\,
I5 => \Lxx_00__1_carry__1_i_12_n_0\,
O => \Lxx_00__1_carry__1_i_5_n_0\
);
\Lxx_00__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[9]\,
I2 => \top_right_0_reg_n_0_[9]\,
I3 => \bottom_left_0_reg_n_0_[9]\,
I4 => \bottom_right_0_reg_n_0_[10]\,
I5 => \Lxx_00__1_carry__1_i_9_n_0\,
O => \Lxx_00__1_carry__1_i_6_n_0\
);
\Lxx_00__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[8]\,
I2 => \top_right_0_reg_n_0_[8]\,
I3 => \bottom_left_0_reg_n_0_[8]\,
I4 => \bottom_right_0_reg_n_0_[9]\,
I5 => \Lxx_00__1_carry__1_i_10_n_0\,
O => \Lxx_00__1_carry__1_i_7_n_0\
);
\Lxx_00__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[7]\,
I2 => \top_right_0_reg_n_0_[7]\,
I3 => \bottom_left_0_reg_n_0_[7]\,
I4 => \bottom_right_0_reg_n_0_[8]\,
I5 => \Lxx_00__1_carry__1_i_11_n_0\,
O => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[10]\,
I1 => \top_right_0_reg_n_0_[10]\,
I2 => \top_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__1_i_9_n_0\
);
\Lxx_00__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_00__1_carry__2_n_1\,
CO(1) => \Lxx_00__1_carry__2_n_2\,
CO(0) => \Lxx_00__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_00__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_00__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_00__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_00(15 downto 12),
S(3) => \Lxx_00__1_carry__2_i_4_n_0\,
S(2) => \Lxx_00__1_carry__2_i_5_n_0\,
S(1) => \Lxx_00__1_carry__2_i_6_n_0\,
S(0) => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[13]\,
I1 => \Lxx_00__1_carry__2_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[12]\,
I3 => \top_right_0_reg_n_0_[12]\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_1_n_0\
);
\Lxx_00__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => \top_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \bottom_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_10_n_0\
);
\Lxx_00__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_0_reg_n_0_[15]\,
I1 => \bottom_left_0_reg_n_0_[15]\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \top_left_0_reg_n_0_[15]\,
O => \Lxx_00__1_carry__2_i_11_n_0\
);
\Lxx_00__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[14]\,
I1 => \top_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
O => \Lxx_00__1_carry__2_i_12_n_0\
);
\Lxx_00__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[12]\,
I1 => \Lxx_00__1_carry__2_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[11]\,
I3 => \top_right_0_reg_n_0_[11]\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__2_i_2_n_0\
);
\Lxx_00__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[11]\,
I1 => \Lxx_00__1_carry__1_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[10]\,
I3 => \top_right_0_reg_n_0_[10]\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__2_i_3_n_0\
);
\Lxx_00__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_00__1_carry__2_i_10_n_0\,
I1 => \bottom_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
I3 => \top_right_0_reg_n_0_[14]\,
I4 => \bottom_left_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_11_n_0\,
O => \Lxx_00__1_carry__2_i_4_n_0\
);
\Lxx_00__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[13]\,
I2 => \top_right_0_reg_n_0_[13]\,
I3 => \bottom_left_0_reg_n_0_[13]\,
I4 => \bottom_right_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_12_n_0\,
O => \Lxx_00__1_carry__2_i_5_n_0\
);
\Lxx_00__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[12]\,
I2 => \top_right_0_reg_n_0_[12]\,
I3 => \bottom_left_0_reg_n_0_[12]\,
I4 => \bottom_right_0_reg_n_0_[13]\,
I5 => \Lxx_00__1_carry__2_i_8_n_0\,
O => \Lxx_00__1_carry__2_i_6_n_0\
);
\Lxx_00__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[11]\,
I2 => \top_right_0_reg_n_0_[11]\,
I3 => \bottom_left_0_reg_n_0_[11]\,
I4 => \bottom_right_0_reg_n_0_[12]\,
I5 => \Lxx_00__1_carry__2_i_9_n_0\,
O => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \top_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_8_n_0\
);
\Lxx_00__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[12]\,
I1 => \top_right_0_reg_n_0_[12]\,
I2 => \top_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_9_n_0\
);
\Lxx_00__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[2]\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[1]\,
I5 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_1_n_0\
);
\Lxx_00__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => \bottom_left_0_reg_n_0_[1]\,
I1 => \top_right_0_reg_n_0_[1]\,
I2 => \top_left_0_reg_n_0_[1]\,
I3 => \bottom_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_2_n_0\
);
\Lxx_00__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_0_reg_n_0_[1]\,
I1 => \bottom_left_0_reg_n_0_[1]\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \top_left_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_3_n_0\
);
\Lxx_00__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_right_0_reg_n_0_[3]\,
I5 => \Lxx_00__1_carry_i_8_n_0\,
O => \Lxx_00__1_carry_i_4_n_0\
);
\Lxx_00__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_00__1_carry_i_2_n_0\,
I1 => \bottom_right_0_reg_n_0_[2]\,
I2 => \Lxx_00__1_carry_i_9_n_0\,
I3 => \bottom_left_0_reg_n_0_[1]\,
I4 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_5_n_0\
);
\Lxx_00__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_00__1_carry_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[0]\,
I2 => \top_right_0_reg_n_0_[0]\,
I3 => \bottom_left_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_6_n_0\
);
\Lxx_00__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \bottom_left_0_reg_n_0_[0]\,
I1 => \top_right_0_reg_n_0_[0]\,
I2 => \top_left_0_reg_n_0_[0]\,
I3 => \bottom_right_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[3]\,
I1 => \top_right_0_reg_n_0_[3]\,
I2 => \top_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry_i_8_n_0\
);
\Lxx_00__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[2]\,
I1 => \top_right_0_reg_n_0_[2]\,
I2 => \top_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry_i_9_n_0\
);
\Lxx_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(0),
Q => Lxx_0(0),
R => '0'
);
\Lxx_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(10),
Q => Lxx_0(10),
R => '0'
);
\Lxx_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(11),
Q => Lxx_0(11),
R => '0'
);
\Lxx_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(12),
Q => Lxx_0(12),
R => '0'
);
\Lxx_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(13),
Q => Lxx_0(13),
R => '0'
);
\Lxx_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(14),
Q => Lxx_0(14),
R => '0'
);
\Lxx_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(15),
Q => Lxx_0(15),
R => '0'
);
\Lxx_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(1),
Q => Lxx_0(1),
R => '0'
);
\Lxx_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(2),
Q => Lxx_0(2),
R => '0'
);
\Lxx_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(3),
Q => Lxx_0(3),
R => '0'
);
\Lxx_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(4),
Q => Lxx_0(4),
R => '0'
);
\Lxx_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(5),
Q => Lxx_0(5),
R => '0'
);
\Lxx_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(6),
Q => Lxx_0(6),
R => '0'
);
\Lxx_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(7),
Q => Lxx_0(7),
R => '0'
);
\Lxx_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(8),
Q => Lxx_0(8),
R => '0'
);
\Lxx_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(9),
Q => Lxx_0(9),
R => '0'
);
\Lxx_11__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_11__1_carry_n_0\,
CO(2) => \Lxx_11__1_carry_n_1\,
CO(1) => \Lxx_11__1_carry_n_2\,
CO(0) => \Lxx_11__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry_i_1_n_0\,
DI(2) => \Lxx_11__1_carry_i_2_n_0\,
DI(1) => \Lxx_11__1_carry_i_3_n_0\,
DI(0) => \bottom_right_1_reg_n_0_[0]\,
O(3 downto 0) => Lxx_11(3 downto 0),
S(3) => \Lxx_11__1_carry_i_4_n_0\,
S(2) => \Lxx_11__1_carry_i_5_n_0\,
S(1) => \Lxx_11__1_carry_i_6_n_0\,
S(0) => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry_n_0\,
CO(3) => \Lxx_11__1_carry__0_n_0\,
CO(2) => \Lxx_11__1_carry__0_n_1\,
CO(1) => \Lxx_11__1_carry__0_n_2\,
CO(0) => \Lxx_11__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_11(7 downto 4),
S(3) => \Lxx_11__1_carry__0_i_5_n_0\,
S(2) => \Lxx_11__1_carry__0_i_6_n_0\,
S(1) => \Lxx_11__1_carry__0_i_7_n_0\,
S(0) => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[6]\,
I1 => \Lxx_11__1_carry__0_i_9_n_0\,
I2 => top_left_1(5),
I3 => \top_right_1_reg_n_0_[5]\,
I4 => bottom_left_1(5),
O => \Lxx_11__1_carry__0_i_1_n_0\
);
\Lxx_11__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(5),
I1 => \top_right_1_reg_n_0_[5]\,
I2 => top_left_1(5),
O => \Lxx_11__1_carry__0_i_10_n_0\
);
\Lxx_11__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(4),
I1 => \top_right_1_reg_n_0_[4]\,
I2 => top_left_1(4),
O => \Lxx_11__1_carry__0_i_11_n_0\
);
\Lxx_11__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(7),
I1 => \top_right_1_reg_n_0_[7]\,
I2 => top_left_1(7),
O => \Lxx_11__1_carry__0_i_12_n_0\
);
\Lxx_11__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[5]\,
I1 => \Lxx_11__1_carry__0_i_10_n_0\,
I2 => top_left_1(4),
I3 => \top_right_1_reg_n_0_[4]\,
I4 => bottom_left_1(4),
O => \Lxx_11__1_carry__0_i_2_n_0\
);
\Lxx_11__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[4]\,
I1 => \Lxx_11__1_carry__0_i_11_n_0\,
I2 => top_left_1(3),
I3 => \top_right_1_reg_n_0_[3]\,
I4 => bottom_left_1(3),
O => \Lxx_11__1_carry__0_i_3_n_0\
);
\Lxx_11__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[3]\,
I1 => \Lxx_11__1_carry_i_8_n_0\,
I2 => top_left_1(2),
I3 => \top_right_1_reg_n_0_[2]\,
I4 => bottom_left_1(2),
O => \Lxx_11__1_carry__0_i_4_n_0\
);
\Lxx_11__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_1_n_0\,
I1 => top_left_1(6),
I2 => \top_right_1_reg_n_0_[6]\,
I3 => bottom_left_1(6),
I4 => \bottom_right_1_reg_n_0_[7]\,
I5 => \Lxx_11__1_carry__0_i_12_n_0\,
O => \Lxx_11__1_carry__0_i_5_n_0\
);
\Lxx_11__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_2_n_0\,
I1 => top_left_1(5),
I2 => \top_right_1_reg_n_0_[5]\,
I3 => bottom_left_1(5),
I4 => \bottom_right_1_reg_n_0_[6]\,
I5 => \Lxx_11__1_carry__0_i_9_n_0\,
O => \Lxx_11__1_carry__0_i_6_n_0\
);
\Lxx_11__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_3_n_0\,
I1 => top_left_1(4),
I2 => \top_right_1_reg_n_0_[4]\,
I3 => bottom_left_1(4),
I4 => \bottom_right_1_reg_n_0_[5]\,
I5 => \Lxx_11__1_carry__0_i_10_n_0\,
O => \Lxx_11__1_carry__0_i_7_n_0\
);
\Lxx_11__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_4_n_0\,
I1 => top_left_1(3),
I2 => \top_right_1_reg_n_0_[3]\,
I3 => bottom_left_1(3),
I4 => \bottom_right_1_reg_n_0_[4]\,
I5 => \Lxx_11__1_carry__0_i_11_n_0\,
O => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(6),
I1 => \top_right_1_reg_n_0_[6]\,
I2 => top_left_1(6),
O => \Lxx_11__1_carry__0_i_9_n_0\
);
\Lxx_11__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__0_n_0\,
CO(3) => \Lxx_11__1_carry__1_n_0\,
CO(2) => \Lxx_11__1_carry__1_n_1\,
CO(1) => \Lxx_11__1_carry__1_n_2\,
CO(0) => \Lxx_11__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_11(11 downto 8),
S(3) => \Lxx_11__1_carry__1_i_5_n_0\,
S(2) => \Lxx_11__1_carry__1_i_6_n_0\,
S(1) => \Lxx_11__1_carry__1_i_7_n_0\,
S(0) => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[10]\,
I1 => \Lxx_11__1_carry__1_i_9_n_0\,
I2 => top_left_1(9),
I3 => \top_right_1_reg_n_0_[9]\,
I4 => bottom_left_1(9),
O => \Lxx_11__1_carry__1_i_1_n_0\
);
\Lxx_11__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(9),
I1 => \top_right_1_reg_n_0_[9]\,
I2 => top_left_1(9),
O => \Lxx_11__1_carry__1_i_10_n_0\
);
\Lxx_11__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(8),
I1 => \top_right_1_reg_n_0_[8]\,
I2 => top_left_1(8),
O => \Lxx_11__1_carry__1_i_11_n_0\
);
\Lxx_11__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(11),
I1 => \top_right_1_reg_n_0_[11]\,
I2 => top_left_1(11),
O => \Lxx_11__1_carry__1_i_12_n_0\
);
\Lxx_11__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[9]\,
I1 => \Lxx_11__1_carry__1_i_10_n_0\,
I2 => top_left_1(8),
I3 => \top_right_1_reg_n_0_[8]\,
I4 => bottom_left_1(8),
O => \Lxx_11__1_carry__1_i_2_n_0\
);
\Lxx_11__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[8]\,
I1 => \Lxx_11__1_carry__1_i_11_n_0\,
I2 => top_left_1(7),
I3 => \top_right_1_reg_n_0_[7]\,
I4 => bottom_left_1(7),
O => \Lxx_11__1_carry__1_i_3_n_0\
);
\Lxx_11__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[7]\,
I1 => \Lxx_11__1_carry__0_i_12_n_0\,
I2 => top_left_1(6),
I3 => \top_right_1_reg_n_0_[6]\,
I4 => bottom_left_1(6),
O => \Lxx_11__1_carry__1_i_4_n_0\
);
\Lxx_11__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_1_n_0\,
I1 => top_left_1(10),
I2 => \top_right_1_reg_n_0_[10]\,
I3 => bottom_left_1(10),
I4 => \bottom_right_1_reg_n_0_[11]\,
I5 => \Lxx_11__1_carry__1_i_12_n_0\,
O => \Lxx_11__1_carry__1_i_5_n_0\
);
\Lxx_11__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_2_n_0\,
I1 => top_left_1(9),
I2 => \top_right_1_reg_n_0_[9]\,
I3 => bottom_left_1(9),
I4 => \bottom_right_1_reg_n_0_[10]\,
I5 => \Lxx_11__1_carry__1_i_9_n_0\,
O => \Lxx_11__1_carry__1_i_6_n_0\
);
\Lxx_11__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_3_n_0\,
I1 => top_left_1(8),
I2 => \top_right_1_reg_n_0_[8]\,
I3 => bottom_left_1(8),
I4 => \bottom_right_1_reg_n_0_[9]\,
I5 => \Lxx_11__1_carry__1_i_10_n_0\,
O => \Lxx_11__1_carry__1_i_7_n_0\
);
\Lxx_11__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_4_n_0\,
I1 => top_left_1(7),
I2 => \top_right_1_reg_n_0_[7]\,
I3 => bottom_left_1(7),
I4 => \bottom_right_1_reg_n_0_[8]\,
I5 => \Lxx_11__1_carry__1_i_11_n_0\,
O => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(10),
I1 => \top_right_1_reg_n_0_[10]\,
I2 => top_left_1(10),
O => \Lxx_11__1_carry__1_i_9_n_0\
);
\Lxx_11__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_11__1_carry__2_n_1\,
CO(1) => \Lxx_11__1_carry__2_n_2\,
CO(0) => \Lxx_11__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_11__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_11__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_11__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_11(15 downto 12),
S(3) => \Lxx_11__1_carry__2_i_4_n_0\,
S(2) => \Lxx_11__1_carry__2_i_5_n_0\,
S(1) => \Lxx_11__1_carry__2_i_6_n_0\,
S(0) => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[13]\,
I1 => \Lxx_11__1_carry__2_i_8_n_0\,
I2 => top_left_1(12),
I3 => \top_right_1_reg_n_0_[12]\,
I4 => bottom_left_1(12),
O => \Lxx_11__1_carry__2_i_1_n_0\
);
\Lxx_11__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => top_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => bottom_left_1(13),
O => \Lxx_11__1_carry__2_i_10_n_0\
);
\Lxx_11__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_1_reg_n_0_[15]\,
I1 => bottom_left_1(15),
I2 => \bottom_right_1_reg_n_0_[15]\,
I3 => top_left_1(15),
O => \Lxx_11__1_carry__2_i_11_n_0\
);
\Lxx_11__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(14),
I1 => \top_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
O => \Lxx_11__1_carry__2_i_12_n_0\
);
\Lxx_11__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[12]\,
I1 => \Lxx_11__1_carry__2_i_9_n_0\,
I2 => top_left_1(11),
I3 => \top_right_1_reg_n_0_[11]\,
I4 => bottom_left_1(11),
O => \Lxx_11__1_carry__2_i_2_n_0\
);
\Lxx_11__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[11]\,
I1 => \Lxx_11__1_carry__1_i_12_n_0\,
I2 => top_left_1(10),
I3 => \top_right_1_reg_n_0_[10]\,
I4 => bottom_left_1(10),
O => \Lxx_11__1_carry__2_i_3_n_0\
);
\Lxx_11__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_11__1_carry__2_i_10_n_0\,
I1 => \bottom_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
I3 => \top_right_1_reg_n_0_[14]\,
I4 => bottom_left_1(14),
I5 => \Lxx_11__1_carry__2_i_11_n_0\,
O => \Lxx_11__1_carry__2_i_4_n_0\
);
\Lxx_11__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_1_n_0\,
I1 => top_left_1(13),
I2 => \top_right_1_reg_n_0_[13]\,
I3 => bottom_left_1(13),
I4 => \bottom_right_1_reg_n_0_[14]\,
I5 => \Lxx_11__1_carry__2_i_12_n_0\,
O => \Lxx_11__1_carry__2_i_5_n_0\
);
\Lxx_11__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_2_n_0\,
I1 => top_left_1(12),
I2 => \top_right_1_reg_n_0_[12]\,
I3 => bottom_left_1(12),
I4 => \bottom_right_1_reg_n_0_[13]\,
I5 => \Lxx_11__1_carry__2_i_8_n_0\,
O => \Lxx_11__1_carry__2_i_6_n_0\
);
\Lxx_11__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_3_n_0\,
I1 => top_left_1(11),
I2 => \top_right_1_reg_n_0_[11]\,
I3 => bottom_left_1(11),
I4 => \bottom_right_1_reg_n_0_[12]\,
I5 => \Lxx_11__1_carry__2_i_9_n_0\,
O => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => top_left_1(13),
O => \Lxx_11__1_carry__2_i_8_n_0\
);
\Lxx_11__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(12),
I1 => \top_right_1_reg_n_0_[12]\,
I2 => top_left_1(12),
O => \Lxx_11__1_carry__2_i_9_n_0\
);
\Lxx_11__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[2]\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => bottom_left_1(1),
I5 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_1_n_0\
);
\Lxx_11__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => bottom_left_1(1),
I1 => \top_right_1_reg_n_0_[1]\,
I2 => top_left_1(1),
I3 => \bottom_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_2_n_0\
);
\Lxx_11__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_1_reg_n_0_[1]\,
I1 => bottom_left_1(1),
I2 => \bottom_right_1_reg_n_0_[1]\,
I3 => top_left_1(1),
O => \Lxx_11__1_carry_i_3_n_0\
);
\Lxx_11__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry_i_1_n_0\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => \bottom_right_1_reg_n_0_[3]\,
I5 => \Lxx_11__1_carry_i_8_n_0\,
O => \Lxx_11__1_carry_i_4_n_0\
);
\Lxx_11__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_11__1_carry_i_2_n_0\,
I1 => \bottom_right_1_reg_n_0_[2]\,
I2 => \Lxx_11__1_carry_i_9_n_0\,
I3 => bottom_left_1(1),
I4 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_5_n_0\
);
\Lxx_11__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_11__1_carry_i_3_n_0\,
I1 => top_left_1(0),
I2 => \top_right_1_reg_n_0_[0]\,
I3 => bottom_left_1(0),
O => \Lxx_11__1_carry_i_6_n_0\
);
\Lxx_11__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => bottom_left_1(0),
I1 => \top_right_1_reg_n_0_[0]\,
I2 => top_left_1(0),
I3 => \bottom_right_1_reg_n_0_[0]\,
O => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(3),
I1 => \top_right_1_reg_n_0_[3]\,
I2 => top_left_1(3),
O => \Lxx_11__1_carry_i_8_n_0\
);
\Lxx_11__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(2),
I1 => \top_right_1_reg_n_0_[2]\,
I2 => top_left_1(2),
O => \Lxx_11__1_carry_i_9_n_0\
);
\Lxx_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(9),
Q => Lxx_1(10),
R => '0'
);
\Lxx_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(10),
Q => Lxx_1(11),
R => '0'
);
\Lxx_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(11),
Q => Lxx_1(12),
R => '0'
);
\Lxx_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(12),
Q => Lxx_1(13),
R => '0'
);
\Lxx_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(13),
Q => Lxx_1(14),
R => '0'
);
\Lxx_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(14),
Q => Lxx_1(15),
R => '0'
);
\Lxx_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(0),
Q => Lxx_1(1),
R => '0'
);
\Lxx_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(1),
Q => Lxx_1(2),
R => '0'
);
\Lxx_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(2),
Q => Lxx_1(3),
R => '0'
);
\Lxx_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(3),
Q => Lxx_1(4),
R => '0'
);
\Lxx_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(4),
Q => Lxx_1(5),
R => '0'
);
\Lxx_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(5),
Q => Lxx_1(6),
R => '0'
);
\Lxx_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(6),
Q => Lxx_1(7),
R => '0'
);
\Lxx_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(7),
Q => Lxx_1(8),
R => '0'
);
\Lxx_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(8),
Q => Lxx_1(9),
R => '0'
);
\Lxx_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => cycle(2),
I4 => rst,
I5 => active,
O => \Lxx_2[15]_i_1_n_0\
);
\Lxx_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxx_2_reg_n_0_[0]\,
R => '0'
);
\Lxx_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxx_2_reg_n_0_[10]\,
R => '0'
);
\Lxx_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxx_2_reg_n_0_[11]\,
R => '0'
);
\Lxx_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxx_2_reg_n_0_[12]\,
R => '0'
);
\Lxx_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxx_2_reg_n_0_[13]\,
R => '0'
);
\Lxx_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxx_2_reg_n_0_[14]\,
R => '0'
);
\Lxx_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxx_2_reg_n_0_[15]\,
R => '0'
);
\Lxx_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxx_2_reg_n_0_[1]\,
R => '0'
);
\Lxx_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxx_2_reg_n_0_[2]\,
R => '0'
);
\Lxx_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxx_2_reg_n_0_[3]\,
R => '0'
);
\Lxx_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxx_2_reg_n_0_[4]\,
R => '0'
);
\Lxx_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxx_2_reg_n_0_[5]\,
R => '0'
);
\Lxx_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxx_2_reg_n_0_[6]\,
R => '0'
);
\Lxx_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxx_2_reg_n_0_[7]\,
R => '0'
);
\Lxx_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxx_2_reg_n_0_[8]\,
R => '0'
);
\Lxx_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxx_2_reg_n_0_[9]\,
R => '0'
);
\Lxy0__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxy0__1_carry_n_0\,
CO(2) => \Lxy0__1_carry_n_1\,
CO(1) => \Lxy0__1_carry_n_2\,
CO(0) => \Lxy0__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry_i_1_n_0\,
DI(2) => \Lxy0__1_carry_i_2_n_0\,
DI(1) => \Lxy0__1_carry_i_3_n_0\,
DI(0) => \Lxy_0_reg_n_0_[0]\,
O(3) => \Lxy0__1_carry_n_4\,
O(2) => \Lxy0__1_carry_n_5\,
O(1) => \Lxy0__1_carry_n_6\,
O(0) => \Lxy0__1_carry_n_7\,
S(3) => \Lxy0__1_carry_i_4_n_0\,
S(2) => \Lxy0__1_carry_i_5_n_0\,
S(1) => \Lxy0__1_carry_i_6_n_0\,
S(0) => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry_n_0\,
CO(3) => \Lxy0__1_carry__0_n_0\,
CO(2) => \Lxy0__1_carry__0_n_1\,
CO(1) => \Lxy0__1_carry__0_n_2\,
CO(0) => \Lxy0__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__0_i_1_n_0\,
DI(2) => \Lxy0__1_carry__0_i_2_n_0\,
DI(1) => \Lxy0__1_carry__0_i_3_n_0\,
DI(0) => \Lxy0__1_carry__0_i_4_n_0\,
O(3) => \Lxy0__1_carry__0_n_4\,
O(2) => \Lxy0__1_carry__0_n_5\,
O(1) => \Lxy0__1_carry__0_n_6\,
O(0) => \Lxy0__1_carry__0_n_7\,
S(3) => \Lxy0__1_carry__0_i_5_n_0\,
S(2) => \Lxy0__1_carry__0_i_6_n_0\,
S(1) => \Lxy0__1_carry__0_i_7_n_0\,
S(0) => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[6]\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => Lxy_3(5),
I3 => Lxy_2(5),
I4 => \Lxy_1_reg_n_0_[5]\,
O => \Lxy0__1_carry__0_i_1_n_0\
);
\Lxy0__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(5),
I1 => \Lxy_1_reg_n_0_[5]\,
I2 => Lxy_2(5),
O => \Lxy0__1_carry__0_i_10_n_0\
);
\Lxy0__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(4),
I1 => \Lxy_1_reg_n_0_[4]\,
I2 => Lxy_2(4),
O => \Lxy0__1_carry__0_i_11_n_0\
);
\Lxy0__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(7),
I1 => \Lxy_1_reg_n_0_[7]\,
I2 => Lxy_2(7),
O => \Lxy0__1_carry__0_i_12_n_0\
);
\Lxy0__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[5]\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => Lxy_3(4),
I3 => Lxy_2(4),
I4 => \Lxy_1_reg_n_0_[4]\,
O => \Lxy0__1_carry__0_i_2_n_0\
);
\Lxy0__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[4]\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => Lxy_3(3),
I3 => Lxy_2(3),
I4 => \Lxy_1_reg_n_0_[3]\,
O => \Lxy0__1_carry__0_i_3_n_0\
);
\Lxy0__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[3]\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => Lxy_3(2),
I3 => Lxy_2(2),
I4 => \Lxy_1_reg_n_0_[2]\,
O => \Lxy0__1_carry__0_i_4_n_0\
);
\Lxy0__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_1_n_0\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[7]\,
I3 => \Lxy_1_reg_n_0_[6]\,
I4 => Lxy_2(6),
I5 => Lxy_3(6),
O => \Lxy0__1_carry__0_i_5_n_0\
);
\Lxy0__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_2_n_0\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[6]\,
I3 => \Lxy_1_reg_n_0_[5]\,
I4 => Lxy_2(5),
I5 => Lxy_3(5),
O => \Lxy0__1_carry__0_i_6_n_0\
);
\Lxy0__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_3_n_0\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[5]\,
I3 => \Lxy_1_reg_n_0_[4]\,
I4 => Lxy_2(4),
I5 => Lxy_3(4),
O => \Lxy0__1_carry__0_i_7_n_0\
);
\Lxy0__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_4_n_0\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[4]\,
I3 => \Lxy_1_reg_n_0_[3]\,
I4 => Lxy_2(3),
I5 => Lxy_3(3),
O => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(6),
I1 => \Lxy_1_reg_n_0_[6]\,
I2 => Lxy_2(6),
O => \Lxy0__1_carry__0_i_9_n_0\
);
\Lxy0__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__0_n_0\,
CO(3) => \Lxy0__1_carry__1_n_0\,
CO(2) => \Lxy0__1_carry__1_n_1\,
CO(1) => \Lxy0__1_carry__1_n_2\,
CO(0) => \Lxy0__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__1_i_1_n_0\,
DI(2) => \Lxy0__1_carry__1_i_2_n_0\,
DI(1) => \Lxy0__1_carry__1_i_3_n_0\,
DI(0) => \Lxy0__1_carry__1_i_4_n_0\,
O(3) => \Lxy0__1_carry__1_n_4\,
O(2) => \Lxy0__1_carry__1_n_5\,
O(1) => \Lxy0__1_carry__1_n_6\,
O(0) => \Lxy0__1_carry__1_n_7\,
S(3) => \Lxy0__1_carry__1_i_5_n_0\,
S(2) => \Lxy0__1_carry__1_i_6_n_0\,
S(1) => \Lxy0__1_carry__1_i_7_n_0\,
S(0) => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[10]\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => Lxy_3(9),
I3 => Lxy_2(9),
I4 => \Lxy_1_reg_n_0_[9]\,
O => \Lxy0__1_carry__1_i_1_n_0\
);
\Lxy0__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(9),
I1 => \Lxy_1_reg_n_0_[9]\,
I2 => Lxy_2(9),
O => \Lxy0__1_carry__1_i_10_n_0\
);
\Lxy0__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(8),
I1 => \Lxy_1_reg_n_0_[8]\,
I2 => Lxy_2(8),
O => \Lxy0__1_carry__1_i_11_n_0\
);
\Lxy0__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(11),
I1 => \Lxy_1_reg_n_0_[11]\,
I2 => Lxy_2(11),
O => \Lxy0__1_carry__1_i_12_n_0\
);
\Lxy0__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[9]\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => Lxy_3(8),
I3 => Lxy_2(8),
I4 => \Lxy_1_reg_n_0_[8]\,
O => \Lxy0__1_carry__1_i_2_n_0\
);
\Lxy0__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[8]\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => Lxy_3(7),
I3 => Lxy_2(7),
I4 => \Lxy_1_reg_n_0_[7]\,
O => \Lxy0__1_carry__1_i_3_n_0\
);
\Lxy0__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[7]\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => Lxy_3(6),
I3 => Lxy_2(6),
I4 => \Lxy_1_reg_n_0_[6]\,
O => \Lxy0__1_carry__1_i_4_n_0\
);
\Lxy0__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_1_n_0\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[11]\,
I3 => \Lxy_1_reg_n_0_[10]\,
I4 => Lxy_2(10),
I5 => Lxy_3(10),
O => \Lxy0__1_carry__1_i_5_n_0\
);
\Lxy0__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_2_n_0\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[10]\,
I3 => \Lxy_1_reg_n_0_[9]\,
I4 => Lxy_2(9),
I5 => Lxy_3(9),
O => \Lxy0__1_carry__1_i_6_n_0\
);
\Lxy0__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_3_n_0\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[9]\,
I3 => \Lxy_1_reg_n_0_[8]\,
I4 => Lxy_2(8),
I5 => Lxy_3(8),
O => \Lxy0__1_carry__1_i_7_n_0\
);
\Lxy0__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_4_n_0\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[8]\,
I3 => \Lxy_1_reg_n_0_[7]\,
I4 => Lxy_2(7),
I5 => Lxy_3(7),
O => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(10),
I1 => \Lxy_1_reg_n_0_[10]\,
I2 => Lxy_2(10),
O => \Lxy0__1_carry__1_i_9_n_0\
);
\Lxy0__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__1_n_0\,
CO(3) => \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxy0__1_carry__2_n_1\,
CO(1) => \Lxy0__1_carry__2_n_2\,
CO(0) => \Lxy0__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxy0__1_carry__2_i_1_n_0\,
DI(1) => \Lxy0__1_carry__2_i_2_n_0\,
DI(0) => \Lxy0__1_carry__2_i_3_n_0\,
O(3) => \Lxy0__1_carry__2_n_4\,
O(2) => \Lxy0__1_carry__2_n_5\,
O(1) => \Lxy0__1_carry__2_n_6\,
O(0) => \Lxy0__1_carry__2_n_7\,
S(3) => \Lxy0__1_carry__2_i_4_n_0\,
S(2) => \Lxy0__1_carry__2_i_5_n_0\,
S(1) => \Lxy0__1_carry__2_i_6_n_0\,
S(0) => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[13]\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => Lxy_3(12),
I3 => Lxy_2(12),
I4 => \Lxy_1_reg_n_0_[12]\,
O => \Lxy0__1_carry__2_i_1_n_0\
);
\Lxy0__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => \Lxy_1_reg_n_0_[13]\,
I1 => Lxy_2(13),
I2 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_10_n_0\
);
\Lxy0__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(15),
I1 => \Lxy_1_reg_n_0_[15]\,
I2 => Lxy_3(15),
I3 => \Lxy_0_reg_n_0_[15]\,
O => \Lxy0__1_carry__2_i_11_n_0\
);
\Lxy0__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(14),
I1 => \Lxy_1_reg_n_0_[14]\,
I2 => Lxy_2(14),
O => \Lxy0__1_carry__2_i_12_n_0\
);
\Lxy0__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[12]\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => Lxy_3(11),
I3 => Lxy_2(11),
I4 => \Lxy_1_reg_n_0_[11]\,
O => \Lxy0__1_carry__2_i_2_n_0\
);
\Lxy0__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[11]\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => Lxy_3(10),
I3 => Lxy_2(10),
I4 => \Lxy_1_reg_n_0_[10]\,
O => \Lxy0__1_carry__2_i_3_n_0\
);
\Lxy0__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E87781E87E11E87"
)
port map (
I0 => \Lxy0__1_carry__2_i_10_n_0\,
I1 => \Lxy_0_reg_n_0_[14]\,
I2 => \Lxy0__1_carry__2_i_11_n_0\,
I3 => \Lxy_1_reg_n_0_[14]\,
I4 => Lxy_2(14),
I5 => Lxy_3(14),
O => \Lxy0__1_carry__2_i_4_n_0\
);
\Lxy0__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_1_n_0\,
I1 => \Lxy0__1_carry__2_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[14]\,
I3 => \Lxy_1_reg_n_0_[13]\,
I4 => Lxy_2(13),
I5 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_5_n_0\
);
\Lxy0__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_2_n_0\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[13]\,
I3 => \Lxy_1_reg_n_0_[12]\,
I4 => Lxy_2(12),
I5 => Lxy_3(12),
O => \Lxy0__1_carry__2_i_6_n_0\
);
\Lxy0__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_3_n_0\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[12]\,
I3 => \Lxy_1_reg_n_0_[11]\,
I4 => Lxy_2(11),
I5 => Lxy_3(11),
O => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(13),
I1 => \Lxy_1_reg_n_0_[13]\,
I2 => Lxy_2(13),
O => \Lxy0__1_carry__2_i_8_n_0\
);
\Lxy0__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(12),
I1 => \Lxy_1_reg_n_0_[12]\,
I2 => Lxy_2(12),
O => \Lxy0__1_carry__2_i_9_n_0\
);
\Lxy0__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBEEBBE8228EBBE"
)
port map (
I0 => \Lxy_0_reg_n_0_[2]\,
I1 => Lxy_2(2),
I2 => \Lxy_1_reg_n_0_[2]\,
I3 => Lxy_3(2),
I4 => \Lxy_1_reg_n_0_[1]\,
I5 => Lxy_2(1),
O => \Lxy0__1_carry_i_1_n_0\
);
\Lxy0__1_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => Lxy_2(1),
I1 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_10_n_0\
);
\Lxy0__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4DD4"
)
port map (
I0 => Lxy_3(1),
I1 => \Lxy_0_reg_n_0_[1]\,
I2 => \Lxy_1_reg_n_0_[1]\,
I3 => Lxy_2(1),
O => \Lxy0__1_carry_i_2_n_0\
);
\Lxy0__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxy_1_reg_n_0_[1]\,
I1 => Lxy_2(1),
I2 => Lxy_3(1),
I3 => \Lxy_0_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_3_n_0\
);
\Lxy0__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry_i_1_n_0\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[3]\,
I3 => \Lxy_1_reg_n_0_[2]\,
I4 => Lxy_2(2),
I5 => Lxy_3(2),
O => \Lxy0__1_carry_i_4_n_0\
);
\Lxy0__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"69966969"
)
port map (
I0 => \Lxy0__1_carry_i_2_n_0\,
I1 => \Lxy0__1_carry_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[2]\,
I3 => Lxy_2(1),
I4 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_5_n_0\
);
\Lxy0__1_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy_0_reg_n_0_[1]\,
I1 => Lxy_3(1),
I2 => \Lxy0__1_carry_i_10_n_0\,
I3 => Lxy_3(0),
I4 => Lxy_2(0),
I5 => \Lxy_1_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_6_n_0\
);
\Lxy0__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(0),
I1 => \Lxy_1_reg_n_0_[0]\,
I2 => Lxy_3(0),
I3 => \Lxy_0_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(3),
I1 => \Lxy_1_reg_n_0_[3]\,
I2 => Lxy_2(3),
O => \Lxy0__1_carry_i_8_n_0\
);
\Lxy0__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(2),
I1 => \Lxy_1_reg_n_0_[2]\,
I2 => Lxy_2(2),
O => \Lxy0__1_carry_i_9_n_0\
);
\Lxy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => \Lxy_0[15]_i_1_n_0\
);
\Lxy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxy_0_reg_n_0_[0]\,
R => '0'
);
\Lxy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxy_0_reg_n_0_[10]\,
R => '0'
);
\Lxy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxy_0_reg_n_0_[11]\,
R => '0'
);
\Lxy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxy_0_reg_n_0_[12]\,
R => '0'
);
\Lxy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxy_0_reg_n_0_[13]\,
R => '0'
);
\Lxy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxy_0_reg_n_0_[14]\,
R => '0'
);
\Lxy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxy_0_reg_n_0_[15]\,
R => '0'
);
\Lxy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxy_0_reg_n_0_[1]\,
R => '0'
);
\Lxy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxy_0_reg_n_0_[2]\,
R => '0'
);
\Lxy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxy_0_reg_n_0_[3]\,
R => '0'
);
\Lxy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxy_0_reg_n_0_[4]\,
R => '0'
);
\Lxy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxy_0_reg_n_0_[5]\,
R => '0'
);
\Lxy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxy_0_reg_n_0_[6]\,
R => '0'
);
\Lxy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxy_0_reg_n_0_[7]\,
R => '0'
);
\Lxy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxy_0_reg_n_0_[8]\,
R => '0'
);
\Lxy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxy_0_reg_n_0_[9]\,
R => '0'
);
\Lxy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => Lxy_1
);
\Lxy_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(0),
Q => \Lxy_1_reg_n_0_[0]\,
R => '0'
);
\Lxy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(10),
Q => \Lxy_1_reg_n_0_[10]\,
R => '0'
);
\Lxy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(11),
Q => \Lxy_1_reg_n_0_[11]\,
R => '0'
);
\Lxy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(12),
Q => \Lxy_1_reg_n_0_[12]\,
R => '0'
);
\Lxy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(13),
Q => \Lxy_1_reg_n_0_[13]\,
R => '0'
);
\Lxy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(14),
Q => \Lxy_1_reg_n_0_[14]\,
R => '0'
);
\Lxy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(15),
Q => \Lxy_1_reg_n_0_[15]\,
R => '0'
);
\Lxy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(1),
Q => \Lxy_1_reg_n_0_[1]\,
R => '0'
);
\Lxy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(2),
Q => \Lxy_1_reg_n_0_[2]\,
R => '0'
);
\Lxy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(3),
Q => \Lxy_1_reg_n_0_[3]\,
R => '0'
);
\Lxy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(4),
Q => \Lxy_1_reg_n_0_[4]\,
R => '0'
);
\Lxy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(5),
Q => \Lxy_1_reg_n_0_[5]\,
R => '0'
);
\Lxy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(6),
Q => \Lxy_1_reg_n_0_[6]\,
R => '0'
);
\Lxy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(7),
Q => \Lxy_1_reg_n_0_[7]\,
R => '0'
);
\Lxy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(8),
Q => \Lxy_1_reg_n_0_[8]\,
R => '0'
);
\Lxy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(9),
Q => \Lxy_1_reg_n_0_[9]\,
R => '0'
);
\Lxy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(0),
Q => Lxy_2(0),
R => '0'
);
\Lxy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(10),
Q => Lxy_2(10),
R => '0'
);
\Lxy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(11),
Q => Lxy_2(11),
R => '0'
);
\Lxy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(12),
Q => Lxy_2(12),
R => '0'
);
\Lxy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(13),
Q => Lxy_2(13),
R => '0'
);
\Lxy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(14),
Q => Lxy_2(14),
R => '0'
);
\Lxy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(15),
Q => Lxy_2(15),
R => '0'
);
\Lxy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(1),
Q => Lxy_2(1),
R => '0'
);
\Lxy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(2),
Q => Lxy_2(2),
R => '0'
);
\Lxy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(3),
Q => Lxy_2(3),
R => '0'
);
\Lxy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(4),
Q => Lxy_2(4),
R => '0'
);
\Lxy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(5),
Q => Lxy_2(5),
R => '0'
);
\Lxy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(6),
Q => Lxy_2(6),
R => '0'
);
\Lxy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(7),
Q => Lxy_2(7),
R => '0'
);
\Lxy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(8),
Q => Lxy_2(8),
R => '0'
);
\Lxy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(9),
Q => Lxy_2(9),
R => '0'
);
\Lxy_3[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => cycle(3),
O => y6
);
\Lxy_3_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(0),
Q => Lxy_3(0),
R => '0'
);
\Lxy_3_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(10),
Q => Lxy_3(10),
R => '0'
);
\Lxy_3_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(11),
Q => Lxy_3(11),
R => '0'
);
\Lxy_3_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(12),
Q => Lxy_3(12),
R => '0'
);
\Lxy_3_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(13),
Q => Lxy_3(13),
R => '0'
);
\Lxy_3_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(14),
Q => Lxy_3(14),
R => '0'
);
\Lxy_3_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(15),
Q => Lxy_3(15),
R => '0'
);
\Lxy_3_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(1),
Q => Lxy_3(1),
R => '0'
);
\Lxy_3_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(2),
Q => Lxy_3(2),
R => '0'
);
\Lxy_3_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(3),
Q => Lxy_3(3),
R => '0'
);
\Lxy_3_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(4),
Q => Lxy_3(4),
R => '0'
);
\Lxy_3_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(5),
Q => Lxy_3(5),
R => '0'
);
\Lxy_3_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(6),
Q => Lxy_3(6),
R => '0'
);
\Lxy_3_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(7),
Q => Lxy_3(7),
R => '0'
);
\Lxy_3_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(8),
Q => Lxy_3(8),
R => '0'
);
\Lxy_3_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(9),
Q => Lxy_3(9),
R => '0'
);
Lyy0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lyy0_carry_n_0,
CO(2) => Lyy0_carry_n_1,
CO(1) => Lyy0_carry_n_2,
CO(0) => Lyy0_carry_n_3,
CYINIT => '0',
DI(3) => Lyy0_carry_i_1_n_0,
DI(2) => Lyy0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lyy_2_reg_n_0_[0]\,
O(3 downto 0) => B(3 downto 0),
S(3) => Lyy0_carry_i_3_n_0,
S(2) => Lyy0_carry_i_4_n_0,
S(1) => Lyy0_carry_i_5_n_0,
S(0) => Lyy0_carry_i_6_n_0
);
\Lyy0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lyy0_carry_n_0,
CO(3) => \Lyy0_carry__0_n_0\,
CO(2) => \Lyy0_carry__0_n_1\,
CO(1) => \Lyy0_carry__0_n_2\,
CO(0) => \Lyy0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__0_i_1_n_0\,
DI(2) => \Lyy0_carry__0_i_2_n_0\,
DI(1) => \Lyy0_carry__0_i_3_n_0\,
DI(0) => \Lyy0_carry__0_i_4_n_0\,
O(3 downto 0) => B(7 downto 4),
S(3) => \Lyy0_carry__0_i_5_n_0\,
S(2) => \Lyy0_carry__0_i_6_n_0\,
S(1) => \Lyy0_carry__0_i_7_n_0\,
S(0) => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
O => \Lyy0_carry__0_i_1_n_0\
);
\Lyy0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
O => \Lyy0_carry__0_i_2_n_0\
);
\Lyy0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
O => \Lyy0_carry__0_i_3_n_0\
);
\Lyy0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
O => \Lyy0_carry__0_i_4_n_0\
);
\Lyy0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
I3 => \Lyy0_carry__0_i_1_n_0\,
O => \Lyy0_carry__0_i_5_n_0\
);
\Lyy0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
I3 => \Lyy0_carry__0_i_2_n_0\,
O => \Lyy0_carry__0_i_6_n_0\
);
\Lyy0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
I3 => \Lyy0_carry__0_i_3_n_0\,
O => \Lyy0_carry__0_i_7_n_0\
);
\Lyy0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
I3 => \Lyy0_carry__0_i_4_n_0\,
O => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__0_n_0\,
CO(3) => \Lyy0_carry__1_n_0\,
CO(2) => \Lyy0_carry__1_n_1\,
CO(1) => \Lyy0_carry__1_n_2\,
CO(0) => \Lyy0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__1_i_1_n_0\,
DI(2) => \Lyy0_carry__1_i_2_n_0\,
DI(1) => \Lyy0_carry__1_i_3_n_0\,
DI(0) => \Lyy0_carry__1_i_4_n_0\,
O(3 downto 0) => B(11 downto 8),
S(3) => \Lyy0_carry__1_i_5_n_0\,
S(2) => \Lyy0_carry__1_i_6_n_0\,
S(1) => \Lyy0_carry__1_i_7_n_0\,
S(0) => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
O => \Lyy0_carry__1_i_1_n_0\
);
\Lyy0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
O => \Lyy0_carry__1_i_2_n_0\
);
\Lyy0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
O => \Lyy0_carry__1_i_3_n_0\
);
\Lyy0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
O => \Lyy0_carry__1_i_4_n_0\
);
\Lyy0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
I3 => \Lyy0_carry__1_i_1_n_0\,
O => \Lyy0_carry__1_i_5_n_0\
);
\Lyy0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
I3 => \Lyy0_carry__1_i_2_n_0\,
O => \Lyy0_carry__1_i_6_n_0\
);
\Lyy0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
I3 => \Lyy0_carry__1_i_3_n_0\,
O => \Lyy0_carry__1_i_7_n_0\
);
\Lyy0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
I3 => \Lyy0_carry__1_i_4_n_0\,
O => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__1_n_0\,
CO(3) => \NLW_Lyy0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy0_carry__2_n_1\,
CO(1) => \Lyy0_carry__2_n_2\,
CO(0) => \Lyy0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy0_carry__2_i_1_n_0\,
DI(1) => \Lyy0_carry__2_i_2_n_0\,
DI(0) => \Lyy0_carry__2_i_3_n_0\,
O(3 downto 0) => B(15 downto 12),
S(3) => \Lyy0_carry__2_i_4_n_0\,
S(2) => \Lyy0_carry__2_i_5_n_0\,
S(1) => \Lyy0_carry__2_i_6_n_0\,
S(0) => \Lyy0_carry__2_i_7_n_0\
);
\Lyy0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
O => \Lyy0_carry__2_i_1_n_0\
);
\Lyy0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
O => \Lyy0_carry__2_i_2_n_0\
);
\Lyy0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
O => \Lyy0_carry__2_i_3_n_0\
);
\Lyy0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \Lyy_0_reg_n_0_[14]\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_2_reg_n_0_[15]\,
I4 => Lyy_1(15),
I5 => \Lyy_0_reg_n_0_[15]\,
O => \Lyy0_carry__2_i_4_n_0\
);
\Lyy0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lyy0_carry__2_i_1_n_0\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_0_reg_n_0_[14]\,
O => \Lyy0_carry__2_i_5_n_0\
);
\Lyy0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
I3 => \Lyy0_carry__2_i_2_n_0\,
O => \Lyy0_carry__2_i_6_n_0\
);
\Lyy0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
I3 => \Lyy0_carry__2_i_3_n_0\,
O => \Lyy0_carry__2_i_7_n_0\
);
Lyy0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
O => Lyy0_carry_i_1_n_0
);
Lyy0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_2_n_0
);
Lyy0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
I3 => Lyy0_carry_i_1_n_0,
O => Lyy0_carry_i_3_n_0
);
Lyy0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
I3 => Lyy0_carry_i_2_n_0,
O => Lyy0_carry_i_4_n_0
);
Lyy0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_5_n_0
);
Lyy0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lyy_2_reg_n_0_[0]\,
I1 => \Lyy_0_reg_n_0_[0]\,
O => Lyy0_carry_i_6_n_0
);
\Lyy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[0]_rep_n_0\,
O => Lyy_0
);
\Lyy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(0),
Q => \Lyy_0_reg_n_0_[0]\,
R => '0'
);
\Lyy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(10),
Q => \Lyy_0_reg_n_0_[10]\,
R => '0'
);
\Lyy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(11),
Q => \Lyy_0_reg_n_0_[11]\,
R => '0'
);
\Lyy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(12),
Q => \Lyy_0_reg_n_0_[12]\,
R => '0'
);
\Lyy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(13),
Q => \Lyy_0_reg_n_0_[13]\,
R => '0'
);
\Lyy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(14),
Q => \Lyy_0_reg_n_0_[14]\,
R => '0'
);
\Lyy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(15),
Q => \Lyy_0_reg_n_0_[15]\,
R => '0'
);
\Lyy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(1),
Q => \Lyy_0_reg_n_0_[1]\,
R => '0'
);
\Lyy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(2),
Q => \Lyy_0_reg_n_0_[2]\,
R => '0'
);
\Lyy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(3),
Q => \Lyy_0_reg_n_0_[3]\,
R => '0'
);
\Lyy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(4),
Q => \Lyy_0_reg_n_0_[4]\,
R => '0'
);
\Lyy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(5),
Q => \Lyy_0_reg_n_0_[5]\,
R => '0'
);
\Lyy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(6),
Q => \Lyy_0_reg_n_0_[6]\,
R => '0'
);
\Lyy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(7),
Q => \Lyy_0_reg_n_0_[7]\,
R => '0'
);
\Lyy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(8),
Q => \Lyy_0_reg_n_0_[8]\,
R => '0'
);
\Lyy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(9),
Q => \Lyy_0_reg_n_0_[9]\,
R => '0'
);
\Lyy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => rst,
I3 => active,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y1
);
\Lyy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(9),
Q => Lyy_1(10),
R => '0'
);
\Lyy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(10),
Q => Lyy_1(11),
R => '0'
);
\Lyy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(11),
Q => Lyy_1(12),
R => '0'
);
\Lyy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(12),
Q => Lyy_1(13),
R => '0'
);
\Lyy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(13),
Q => Lyy_1(14),
R => '0'
);
\Lyy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(14),
Q => Lyy_1(15),
R => '0'
);
\Lyy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(0),
Q => Lyy_1(1),
R => '0'
);
\Lyy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(1),
Q => Lyy_1(2),
R => '0'
);
\Lyy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(2),
Q => Lyy_1(3),
R => '0'
);
\Lyy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(3),
Q => Lyy_1(4),
R => '0'
);
\Lyy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(4),
Q => Lyy_1(5),
R => '0'
);
\Lyy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(5),
Q => Lyy_1(6),
R => '0'
);
\Lyy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(6),
Q => Lyy_1(7),
R => '0'
);
\Lyy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(7),
Q => Lyy_1(8),
R => '0'
);
\Lyy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(8),
Q => Lyy_1(9),
R => '0'
);
\Lyy_20__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_20__1_carry_n_0\,
CO(2) => \Lyy_20__1_carry_n_1\,
CO(1) => \Lyy_20__1_carry_n_2\,
CO(0) => \Lyy_20__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry_i_1_n_0\,
DI(2) => \Lyy_20__1_carry_i_2_n_0\,
DI(1) => \Lyy_20__1_carry_i_3_n_0\,
DI(0) => Lyy_2_bottom_right(0),
O(3 downto 0) => Lyy_20(3 downto 0),
S(3) => \Lyy_20__1_carry_i_4_n_0\,
S(2) => \Lyy_20__1_carry_i_5_n_0\,
S(1) => \Lyy_20__1_carry_i_6_n_0\,
S(0) => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry_n_0\,
CO(3) => \Lyy_20__1_carry__0_n_0\,
CO(2) => \Lyy_20__1_carry__0_n_1\,
CO(1) => \Lyy_20__1_carry__0_n_2\,
CO(0) => \Lyy_20__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__0_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__0_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__0_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_20(7 downto 4),
S(3) => \Lyy_20__1_carry__0_i_5_n_0\,
S(2) => \Lyy_20__1_carry__0_i_6_n_0\,
S(1) => \Lyy_20__1_carry__0_i_7_n_0\,
S(0) => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(6),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_right(6),
I3 => \Lyy_20__1_carry__0_i_9_n_0\,
I4 => Lyy_2_bottom_right(6),
O => \Lyy_20__1_carry__0_i_1_n_0\
);
\Lyy_20__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(5),
I1 => Lyy_2_bottom_left(5),
I2 => Lyy_2_top_right(5),
O => \Lyy_20__1_carry__0_i_10_n_0\
);
\Lyy_20__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(3),
I1 => Lyy_2_top_left(3),
I2 => Lyy_2_bottom_left(3),
O => \Lyy_20__1_carry__0_i_11_n_0\
);
\Lyy_20__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(7),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_right(7),
O => \Lyy_20__1_carry__0_i_12_n_0\
);
\Lyy_20__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(5),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_left(4),
I3 => Lyy_2_top_right(4),
I4 => \Lyy_20__1_carry__0_i_10_n_0\,
O => \Lyy_20__1_carry__0_i_2_n_0\
);
\Lyy_20__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(4),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_right(4),
I3 => \Lyy_20__1_carry__0_i_11_n_0\,
I4 => Lyy_2_bottom_right(4),
O => \Lyy_20__1_carry__0_i_3_n_0\
);
\Lyy_20__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(3),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_left(2),
I3 => Lyy_2_top_right(2),
I4 => \Lyy_20__1_carry_i_8_n_0\,
O => \Lyy_20__1_carry__0_i_4_n_0\
);
\Lyy_20__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_1_n_0\,
I1 => \Lyy_20__1_carry__0_i_12_n_0\,
I2 => Lyy_2_bottom_right(7),
I3 => Lyy_2_top_right(6),
I4 => Lyy_2_top_left(6),
I5 => Lyy_2_bottom_left(6),
O => \Lyy_20__1_carry__0_i_5_n_0\
);
\Lyy_20__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_2_n_0\,
I1 => Lyy_2_top_right(6),
I2 => Lyy_2_bottom_left(6),
I3 => Lyy_2_top_left(6),
I4 => Lyy_2_bottom_right(6),
I5 => \Lyy_20__1_carry__0_i_9_n_0\,
O => \Lyy_20__1_carry__0_i_6_n_0\
);
\Lyy_20__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_3_n_0\,
I1 => \Lyy_20__1_carry__0_i_10_n_0\,
I2 => Lyy_2_bottom_right(5),
I3 => Lyy_2_top_right(4),
I4 => Lyy_2_top_left(4),
I5 => Lyy_2_bottom_left(4),
O => \Lyy_20__1_carry__0_i_7_n_0\
);
\Lyy_20__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_4_n_0\,
I1 => Lyy_2_top_right(4),
I2 => Lyy_2_bottom_left(4),
I3 => Lyy_2_top_left(4),
I4 => Lyy_2_bottom_right(4),
I5 => \Lyy_20__1_carry__0_i_11_n_0\,
O => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(5),
I1 => Lyy_2_top_left(5),
I2 => Lyy_2_bottom_left(5),
O => \Lyy_20__1_carry__0_i_9_n_0\
);
\Lyy_20__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__0_n_0\,
CO(3) => \Lyy_20__1_carry__1_n_0\,
CO(2) => \Lyy_20__1_carry__1_n_1\,
CO(1) => \Lyy_20__1_carry__1_n_2\,
CO(0) => \Lyy_20__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__1_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__1_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__1_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_20(11 downto 8),
S(3) => \Lyy_20__1_carry__1_i_5_n_0\,
S(2) => \Lyy_20__1_carry__1_i_6_n_0\,
S(1) => \Lyy_20__1_carry__1_i_7_n_0\,
S(0) => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(10),
I1 => Lyy_2_bottom_left(10),
I2 => Lyy_2_top_right(10),
I3 => \Lyy_20__1_carry__1_i_9_n_0\,
I4 => Lyy_2_bottom_right(10),
O => \Lyy_20__1_carry__1_i_1_n_0\
);
\Lyy_20__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(9),
I1 => Lyy_2_bottom_left(9),
I2 => Lyy_2_top_right(9),
O => \Lyy_20__1_carry__1_i_10_n_0\
);
\Lyy_20__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(8),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_right(8),
O => \Lyy_20__1_carry__1_i_11_n_0\
);
\Lyy_20__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(10),
I1 => Lyy_2_top_left(10),
I2 => Lyy_2_bottom_left(10),
O => \Lyy_20__1_carry__1_i_12_n_0\
);
\Lyy_20__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(9),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_left(8),
I3 => Lyy_2_top_right(8),
I4 => \Lyy_20__1_carry__1_i_10_n_0\,
O => \Lyy_20__1_carry__1_i_2_n_0\
);
\Lyy_20__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(8),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_left(7),
I3 => Lyy_2_top_right(7),
I4 => \Lyy_20__1_carry__1_i_11_n_0\,
O => \Lyy_20__1_carry__1_i_3_n_0\
);
\Lyy_20__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(7),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_left(6),
I3 => Lyy_2_top_right(6),
I4 => \Lyy_20__1_carry__0_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_4_n_0\
);
\Lyy_20__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_1_n_0\,
I1 => Lyy_2_top_right(11),
I2 => Lyy_2_bottom_left(11),
I3 => Lyy_2_top_left(11),
I4 => Lyy_2_bottom_right(11),
I5 => \Lyy_20__1_carry__1_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_5_n_0\
);
\Lyy_20__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_2_n_0\,
I1 => Lyy_2_top_right(10),
I2 => Lyy_2_bottom_left(10),
I3 => Lyy_2_top_left(10),
I4 => Lyy_2_bottom_right(10),
I5 => \Lyy_20__1_carry__1_i_9_n_0\,
O => \Lyy_20__1_carry__1_i_6_n_0\
);
\Lyy_20__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_3_n_0\,
I1 => \Lyy_20__1_carry__1_i_10_n_0\,
I2 => Lyy_2_bottom_right(9),
I3 => Lyy_2_top_right(8),
I4 => Lyy_2_top_left(8),
I5 => Lyy_2_bottom_left(8),
O => \Lyy_20__1_carry__1_i_7_n_0\
);
\Lyy_20__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_4_n_0\,
I1 => \Lyy_20__1_carry__1_i_11_n_0\,
I2 => Lyy_2_bottom_right(8),
I3 => Lyy_2_top_right(7),
I4 => Lyy_2_top_left(7),
I5 => Lyy_2_bottom_left(7),
O => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(9),
I1 => Lyy_2_top_left(9),
I2 => Lyy_2_bottom_left(9),
O => \Lyy_20__1_carry__1_i_9_n_0\
);
\Lyy_20__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__1_n_0\,
CO(3) => \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_20__1_carry__2_n_1\,
CO(1) => \Lyy_20__1_carry__2_n_2\,
CO(0) => \Lyy_20__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_20__1_carry__2_i_1_n_0\,
DI(1) => \Lyy_20__1_carry__2_i_2_n_0\,
DI(0) => \Lyy_20__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_20(15 downto 12),
S(3) => \Lyy_20__1_carry__2_i_4_n_0\,
S(2) => \Lyy_20__1_carry__2_i_5_n_0\,
S(1) => \Lyy_20__1_carry__2_i_6_n_0\,
S(0) => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(13),
I1 => Lyy_2_top_right(12),
I2 => Lyy_2_top_left(12),
I3 => Lyy_2_bottom_left(12),
I4 => \Lyy_20__1_carry__2_i_8_n_0\,
O => \Lyy_20__1_carry__2_i_1_n_0\
);
\Lyy_20__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_10_n_0\
);
\Lyy_20__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(15),
I1 => Lyy_2_bottom_left(15),
I2 => Lyy_2_top_left(15),
I3 => Lyy_2_bottom_right(15),
O => \Lyy_20__1_carry__2_i_11_n_0\
);
\Lyy_20__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(12),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_left(11),
I3 => Lyy_2_top_right(11),
I4 => \Lyy_20__1_carry__2_i_9_n_0\,
O => \Lyy_20__1_carry__2_i_2_n_0\
);
\Lyy_20__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(11),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_right(11),
I3 => \Lyy_20__1_carry__1_i_12_n_0\,
I4 => Lyy_2_bottom_right(11),
O => \Lyy_20__1_carry__2_i_3_n_0\
);
\Lyy_20__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E78871E871EE187"
)
port map (
I0 => Lyy_2_bottom_right(14),
I1 => \Lyy_20__1_carry__2_i_10_n_0\,
I2 => \Lyy_20__1_carry__2_i_11_n_0\,
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_left(14),
I5 => Lyy_2_top_right(14),
O => \Lyy_20__1_carry__2_i_4_n_0\
);
\Lyy_20__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__2_i_1_n_0\,
I1 => Lyy_2_top_right(14),
I2 => Lyy_2_bottom_left(14),
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_right(14),
I5 => \Lyy_20__1_carry__2_i_10_n_0\,
O => \Lyy_20__1_carry__2_i_5_n_0\
);
\Lyy_20__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_2_n_0\,
I1 => \Lyy_20__1_carry__2_i_8_n_0\,
I2 => Lyy_2_bottom_right(13),
I3 => Lyy_2_bottom_left(12),
I4 => Lyy_2_top_left(12),
I5 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_6_n_0\
);
\Lyy_20__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_3_n_0\,
I1 => \Lyy_20__1_carry__2_i_9_n_0\,
I2 => Lyy_2_bottom_right(12),
I3 => Lyy_2_top_right(11),
I4 => Lyy_2_top_left(11),
I5 => Lyy_2_bottom_left(11),
O => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_8_n_0\
);
\Lyy_20__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(12),
I1 => Lyy_2_bottom_left(12),
I2 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_9_n_0\
);
\Lyy_20__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FFFFFF00969696"
)
port map (
I0 => Lyy_2_top_left(2),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_right(2),
I3 => Lyy_2_top_right(1),
I4 => Lyy_2_bottom_left(1),
I5 => Lyy_2_bottom_right(2),
O => \Lyy_20__1_carry_i_1_n_0\
);
\Lyy_20__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => Lyy_2_top_right(1),
I1 => Lyy_2_bottom_left(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_2_n_0\
);
\Lyy_20__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_3_n_0\
);
\Lyy_20__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry_i_1_n_0\,
I1 => \Lyy_20__1_carry_i_8_n_0\,
I2 => Lyy_2_bottom_right(3),
I3 => Lyy_2_top_right(2),
I4 => Lyy_2_top_left(2),
I5 => Lyy_2_bottom_left(2),
O => \Lyy_20__1_carry_i_4_n_0\
);
\Lyy_20__1_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry_i_2_n_0\,
I1 => Lyy_2_top_right(2),
I2 => Lyy_2_bottom_left(2),
I3 => Lyy_2_top_left(2),
I4 => Lyy_2_bottom_right(2),
I5 => \Lyy_20__1_carry_i_9_n_0\,
O => \Lyy_20__1_carry_i_5_n_0\
);
\Lyy_20__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A59"
)
port map (
I0 => \Lyy_20__1_carry_i_3_n_0\,
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_top_right(0),
O => \Lyy_20__1_carry_i_6_n_0\
);
\Lyy_20__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(0),
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_bottom_right(0),
O => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(3),
I1 => Lyy_2_bottom_left(3),
I2 => Lyy_2_top_right(3),
O => \Lyy_20__1_carry_i_8_n_0\
);
\Lyy_20__1_carry_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
O => \Lyy_20__1_carry_i_9_n_0\
);
\Lyy_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \Lyy_2[15]_i_1_n_0\
);
\Lyy_2_bottom_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(0),
Q => Lyy_2_bottom_left(0),
R => '0'
);
\Lyy_2_bottom_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(10),
Q => Lyy_2_bottom_left(10),
R => '0'
);
\Lyy_2_bottom_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(11),
Q => Lyy_2_bottom_left(11),
R => '0'
);
\Lyy_2_bottom_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(12),
Q => Lyy_2_bottom_left(12),
R => '0'
);
\Lyy_2_bottom_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(13),
Q => Lyy_2_bottom_left(13),
R => '0'
);
\Lyy_2_bottom_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(14),
Q => Lyy_2_bottom_left(14),
R => '0'
);
\Lyy_2_bottom_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(15),
Q => Lyy_2_bottom_left(15),
R => '0'
);
\Lyy_2_bottom_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(1),
Q => Lyy_2_bottom_left(1),
R => '0'
);
\Lyy_2_bottom_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(2),
Q => Lyy_2_bottom_left(2),
R => '0'
);
\Lyy_2_bottom_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(3),
Q => Lyy_2_bottom_left(3),
R => '0'
);
\Lyy_2_bottom_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(4),
Q => Lyy_2_bottom_left(4),
R => '0'
);
\Lyy_2_bottom_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(5),
Q => Lyy_2_bottom_left(5),
R => '0'
);
\Lyy_2_bottom_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(6),
Q => Lyy_2_bottom_left(6),
R => '0'
);
\Lyy_2_bottom_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(7),
Q => Lyy_2_bottom_left(7),
R => '0'
);
\Lyy_2_bottom_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(8),
Q => Lyy_2_bottom_left(8),
R => '0'
);
\Lyy_2_bottom_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(9),
Q => Lyy_2_bottom_left(9),
R => '0'
);
\Lyy_2_bottom_right0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(3 downto 0),
S(3) => \Lyy_2_bottom_right0__0_carry_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__0_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__0_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(7 downto 4),
S(3) => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(6),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => \corner_reg_n_0_[5]\,
I3 => \top_reg_n_0_[5]\,
I4 => \left_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[5]\,
I1 => \left_reg_n_0_[5]\,
I2 => \top_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[4]\,
I1 => \left_reg_n_0_[4]\,
I2 => \top_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[7]\,
I1 => \left_reg_n_0_[7]\,
I2 => \top_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(5),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => \corner_reg_n_0_[4]\,
I3 => \top_reg_n_0_[4]\,
I4 => \left_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(4),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => \corner_reg_n_0_[3]\,
I3 => \top_reg_n_0_[3]\,
I4 => \left_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(3),
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => \corner_reg_n_0_[2]\,
I3 => \top_reg_n_0_[2]\,
I4 => \left_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => last_value(7),
I3 => \left_reg_n_0_[6]\,
I4 => \top_reg_n_0_[6]\,
I5 => \corner_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => last_value(6),
I3 => \left_reg_n_0_[5]\,
I4 => \top_reg_n_0_[5]\,
I5 => \corner_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => last_value(5),
I3 => \left_reg_n_0_[4]\,
I4 => \top_reg_n_0_[4]\,
I5 => \corner_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => last_value(4),
I3 => \left_reg_n_0_[3]\,
I4 => \top_reg_n_0_[3]\,
I5 => \corner_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[6]\,
I1 => \left_reg_n_0_[6]\,
I2 => \top_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__1_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__1_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(11 downto 8),
S(3) => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \corner_reg_n_0_[10]\,
I3 => \corner_reg_n_0_[9]\,
I4 => \top_reg_n_0_[9]\,
I5 => \left_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \top_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \top_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \top_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \corner_reg_n_0_[9]\,
I3 => \corner_reg_n_0_[8]\,
I4 => \top_reg_n_0_[8]\,
I5 => \left_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \corner_reg_n_0_[8]\,
I3 => \corner_reg_n_0_[7]\,
I4 => \top_reg_n_0_[7]\,
I5 => \left_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(7),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => \corner_reg_n_0_[6]\,
I3 => \top_reg_n_0_[6]\,
I4 => \left_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\,
I2 => \left_reg_n_0_[10]\,
I3 => \top_reg_n_0_[10]\,
I4 => \corner_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\,
I2 => \left_reg_n_0_[9]\,
I3 => \top_reg_n_0_[9]\,
I4 => \corner_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\,
I2 => \left_reg_n_0_[8]\,
I3 => \top_reg_n_0_[8]\,
I4 => \corner_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\,
I2 => \left_reg_n_0_[7]\,
I3 => \top_reg_n_0_[7]\,
I4 => \corner_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \top_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(3) => \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_2_bottom_right0__0_carry__2_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__2_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(15 downto 12),
S(3) => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
I3 => \corner_reg_n_0_[12]\,
I4 => \top_reg_n_0_[12]\,
I5 => \left_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \left_reg_n_0_[14]\,
I2 => \top_reg_n_0_[14]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \top_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \top_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \corner_reg_n_0_[12]\,
I3 => \corner_reg_n_0_[11]\,
I4 => \top_reg_n_0_[11]\,
I5 => \left_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \corner_reg_n_0_[11]\,
I3 => \corner_reg_n_0_[10]\,
I4 => \top_reg_n_0_[10]\,
I5 => \left_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D2882"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\,
I1 => \corner_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[14]\,
I4 => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\,
O => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\,
I2 => \left_reg_n_0_[13]\,
I3 => \top_reg_n_0_[13]\,
I4 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\,
I2 => \left_reg_n_0_[12]\,
I3 => \top_reg_n_0_[12]\,
I4 => \corner_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\,
I2 => \left_reg_n_0_[11]\,
I3 => \top_reg_n_0_[11]\,
I4 => \corner_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \left_reg_n_0_[13]\,
I1 => \top_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"D42B2BD42BD4D42B"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \top_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[15]\,
I4 => \left_reg_n_0_[15]\,
I5 => \corner_reg_n_0_[15]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(2),
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => \corner_reg_n_0_[1]\,
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[3]\,
I1 => \left_reg_n_0_[3]\,
I2 => \top_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \top_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"20BABA20BA2020BA"
)
port map (
I0 => last_value(1),
I1 => \corner_reg_n_0_[0]\,
I2 => last_value(0),
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669966969969669"
)
port map (
I0 => \top_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \corner_reg_n_0_[1]\,
I3 => last_value(1),
I4 => last_value(0),
I5 => \corner_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => last_value(3),
I3 => \left_reg_n_0_[2]\,
I4 => \top_reg_n_0_[2]\,
I5 => \corner_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => last_value(2),
I3 => \left_reg_n_0_[1]\,
I4 => \top_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB44B4BB4"
)
port map (
I0 => \corner_reg_n_0_[0]\,
I1 => last_value(0),
I2 => last_value(1),
I3 => \Lyy_2_bottom_right0__0_carry_i_11_n_0\,
I4 => \left_reg_n_0_[0]\,
I5 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
I2 => \corner_reg_n_0_[0]\,
I3 => last_value(0),
O => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[2]\,
I1 => \left_reg_n_0_[2]\,
I2 => \top_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_9_n_0\
);
\Lyy_2_bottom_right[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => y5
);
\Lyy_2_bottom_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(0),
Q => Lyy_2_bottom_right(0),
R => '0'
);
\Lyy_2_bottom_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(10),
Q => Lyy_2_bottom_right(10),
R => '0'
);
\Lyy_2_bottom_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(11),
Q => Lyy_2_bottom_right(11),
R => '0'
);
\Lyy_2_bottom_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(12),
Q => Lyy_2_bottom_right(12),
R => '0'
);
\Lyy_2_bottom_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(13),
Q => Lyy_2_bottom_right(13),
R => '0'
);
\Lyy_2_bottom_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(14),
Q => Lyy_2_bottom_right(14),
R => '0'
);
\Lyy_2_bottom_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(15),
Q => Lyy_2_bottom_right(15),
R => '0'
);
\Lyy_2_bottom_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(1),
Q => Lyy_2_bottom_right(1),
R => '0'
);
\Lyy_2_bottom_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(2),
Q => Lyy_2_bottom_right(2),
R => '0'
);
\Lyy_2_bottom_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(3),
Q => Lyy_2_bottom_right(3),
R => '0'
);
\Lyy_2_bottom_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(4),
Q => Lyy_2_bottom_right(4),
R => '0'
);
\Lyy_2_bottom_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(5),
Q => Lyy_2_bottom_right(5),
R => '0'
);
\Lyy_2_bottom_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(6),
Q => Lyy_2_bottom_right(6),
R => '0'
);
\Lyy_2_bottom_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(7),
Q => Lyy_2_bottom_right(7),
R => '0'
);
\Lyy_2_bottom_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(8),
Q => Lyy_2_bottom_right(8),
R => '0'
);
\Lyy_2_bottom_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(9),
Q => Lyy_2_bottom_right(9),
R => '0'
);
\Lyy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(0),
Q => \Lyy_2_reg_n_0_[0]\,
R => '0'
);
\Lyy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(10),
Q => \Lyy_2_reg_n_0_[10]\,
R => '0'
);
\Lyy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(11),
Q => \Lyy_2_reg_n_0_[11]\,
R => '0'
);
\Lyy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(12),
Q => \Lyy_2_reg_n_0_[12]\,
R => '0'
);
\Lyy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(13),
Q => \Lyy_2_reg_n_0_[13]\,
R => '0'
);
\Lyy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(14),
Q => \Lyy_2_reg_n_0_[14]\,
R => '0'
);
\Lyy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(15),
Q => \Lyy_2_reg_n_0_[15]\,
R => '0'
);
\Lyy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(1),
Q => \Lyy_2_reg_n_0_[1]\,
R => '0'
);
\Lyy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(2),
Q => \Lyy_2_reg_n_0_[2]\,
R => '0'
);
\Lyy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(3),
Q => \Lyy_2_reg_n_0_[3]\,
R => '0'
);
\Lyy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(4),
Q => \Lyy_2_reg_n_0_[4]\,
R => '0'
);
\Lyy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(5),
Q => \Lyy_2_reg_n_0_[5]\,
R => '0'
);
\Lyy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(6),
Q => \Lyy_2_reg_n_0_[6]\,
R => '0'
);
\Lyy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(7),
Q => \Lyy_2_reg_n_0_[7]\,
R => '0'
);
\Lyy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(8),
Q => \Lyy_2_reg_n_0_[8]\,
R => '0'
);
\Lyy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(9),
Q => \Lyy_2_reg_n_0_[9]\,
R => '0'
);
\Lyy_2_top_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(0),
Q => Lyy_2_top_left(0),
R => '0'
);
\Lyy_2_top_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(10),
Q => Lyy_2_top_left(10),
R => '0'
);
\Lyy_2_top_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(11),
Q => Lyy_2_top_left(11),
R => '0'
);
\Lyy_2_top_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(12),
Q => Lyy_2_top_left(12),
R => '0'
);
\Lyy_2_top_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(13),
Q => Lyy_2_top_left(13),
R => '0'
);
\Lyy_2_top_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(14),
Q => Lyy_2_top_left(14),
R => '0'
);
\Lyy_2_top_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(15),
Q => Lyy_2_top_left(15),
R => '0'
);
\Lyy_2_top_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(1),
Q => Lyy_2_top_left(1),
R => '0'
);
\Lyy_2_top_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(2),
Q => Lyy_2_top_left(2),
R => '0'
);
\Lyy_2_top_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(3),
Q => Lyy_2_top_left(3),
R => '0'
);
\Lyy_2_top_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(4),
Q => Lyy_2_top_left(4),
R => '0'
);
\Lyy_2_top_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(5),
Q => Lyy_2_top_left(5),
R => '0'
);
\Lyy_2_top_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(6),
Q => Lyy_2_top_left(6),
R => '0'
);
\Lyy_2_top_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(7),
Q => Lyy_2_top_left(7),
R => '0'
);
\Lyy_2_top_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(8),
Q => Lyy_2_top_left(8),
R => '0'
);
\Lyy_2_top_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(9),
Q => Lyy_2_top_left(9),
R => '0'
);
\Lyy_2_top_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[0]\,
Q => Lyy_2_top_right(0),
R => '0'
);
\Lyy_2_top_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[10]\,
Q => Lyy_2_top_right(10),
R => '0'
);
\Lyy_2_top_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[11]\,
Q => Lyy_2_top_right(11),
R => '0'
);
\Lyy_2_top_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[12]\,
Q => Lyy_2_top_right(12),
R => '0'
);
\Lyy_2_top_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[13]\,
Q => Lyy_2_top_right(13),
R => '0'
);
\Lyy_2_top_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[14]\,
Q => Lyy_2_top_right(14),
R => '0'
);
\Lyy_2_top_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[15]\,
Q => Lyy_2_top_right(15),
R => '0'
);
\Lyy_2_top_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[1]\,
Q => Lyy_2_top_right(1),
R => '0'
);
\Lyy_2_top_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[2]\,
Q => Lyy_2_top_right(2),
R => '0'
);
\Lyy_2_top_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[3]\,
Q => Lyy_2_top_right(3),
R => '0'
);
\Lyy_2_top_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[4]\,
Q => Lyy_2_top_right(4),
R => '0'
);
\Lyy_2_top_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[5]\,
Q => Lyy_2_top_right(5),
R => '0'
);
\Lyy_2_top_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[6]\,
Q => Lyy_2_top_right(6),
R => '0'
);
\Lyy_2_top_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[7]\,
Q => Lyy_2_top_right(7),
R => '0'
);
\Lyy_2_top_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[8]\,
Q => Lyy_2_top_right(8),
R => '0'
);
\Lyy_2_top_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[9]\,
Q => Lyy_2_top_right(9),
R => '0'
);
\addr_0[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[0]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[0]\,
O => \addr_0[0]_i_1_n_0\
);
\addr_0[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[10]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[10]\,
O => \addr_0[10]_i_1_n_0\
);
\addr_0[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[11]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[11]\,
O => \addr_0[11]_i_1_n_0\
);
\addr_0[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[12]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[12]\,
O => \addr_0[12]_i_1_n_0\
);
\addr_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888808888"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => addr_0
);
\addr_0[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[13]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[13]\,
O => \addr_0[13]_i_2_n_0\
);
\addr_0[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[1]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[1]\,
O => \addr_0[1]_i_1_n_0\
);
\addr_0[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[2]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[2]\,
O => \addr_0[2]_i_1_n_0\
);
\addr_0[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[3]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[3]\,
O => \addr_0[3]_i_1_n_0\
);
\addr_0[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[4]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[4]\,
O => \addr_0[4]_i_1_n_0\
);
\addr_0[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[5]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[5]\,
O => \addr_0[5]_i_1_n_0\
);
\addr_0[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[6]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[6]\,
O => \addr_0[6]_i_1_n_0\
);
\addr_0[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[7]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[7]\,
O => \addr_0[7]_i_1_n_0\
);
\addr_0[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[8]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[8]\,
O => \addr_0[8]_i_1_n_0\
);
\addr_0[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[9]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[9]\,
O => \addr_0[9]_i_1_n_0\
);
\addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[0]_i_1_n_0\,
Q => \addr_0_reg_n_0_[0]\,
R => '0'
);
\addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[10]_i_1_n_0\,
Q => \addr_0_reg_n_0_[10]\,
R => '0'
);
\addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[11]_i_1_n_0\,
Q => \addr_0_reg_n_0_[11]\,
R => '0'
);
\addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[12]_i_1_n_0\,
Q => \addr_0_reg_n_0_[12]\,
R => '0'
);
\addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[13]_i_2_n_0\,
Q => \addr_0_reg_n_0_[13]\,
R => '0'
);
\addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[1]_i_1_n_0\,
Q => \addr_0_reg_n_0_[1]\,
R => '0'
);
\addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[2]_i_1_n_0\,
Q => \addr_0_reg_n_0_[2]\,
R => '0'
);
\addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[3]_i_1_n_0\,
Q => \addr_0_reg_n_0_[3]\,
R => '0'
);
\addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[4]_i_1_n_0\,
Q => \addr_0_reg_n_0_[4]\,
R => '0'
);
\addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[5]_i_1_n_0\,
Q => \addr_0_reg_n_0_[5]\,
R => '0'
);
\addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[6]_i_1_n_0\,
Q => \addr_0_reg_n_0_[6]\,
R => '0'
);
\addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[7]_i_1_n_0\,
Q => \addr_0_reg_n_0_[7]\,
R => '0'
);
\addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[8]_i_1_n_0\,
Q => \addr_0_reg_n_0_[8]\,
R => '0'
);
\addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[9]_i_1_n_0\,
Q => \addr_0_reg_n_0_[9]\,
R => '0'
);
\addr_1[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(0),
O => \addr_1[0]_i_1_n_0\
);
\addr_1[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(10),
O => \addr_1[10]_i_1_n_0\
);
\addr_1[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(11),
O => \addr_1[11]_i_1_n_0\
);
\addr_1[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(12),
O => \addr_1[12]_i_1_n_0\
);
\addr_1[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(13),
O => \addr_1[13]_i_1_n_0\
);
\addr_1[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(1),
O => \addr_1[1]_i_1_n_0\
);
\addr_1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(2),
O => \addr_1[2]_i_1_n_0\
);
\addr_1[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(3),
O => \addr_1[3]_i_1_n_0\
);
\addr_1[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(4),
O => \addr_1[4]_i_1_n_0\
);
\addr_1[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(5),
O => \addr_1[5]_i_1_n_0\
);
\addr_1[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(6),
O => \addr_1[6]_i_1_n_0\
);
\addr_1[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(7),
O => \addr_1[7]_i_1_n_0\
);
\addr_1[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(8),
O => \addr_1[8]_i_1_n_0\
);
\addr_1[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(9),
O => \addr_1[9]_i_1_n_0\
);
\addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[0]_i_1_n_0\,
Q => addr_1(0),
R => '0'
);
\addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[10]_i_1_n_0\,
Q => addr_1(10),
R => '0'
);
\addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[11]_i_1_n_0\,
Q => addr_1(11),
R => '0'
);
\addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[12]_i_1_n_0\,
Q => addr_1(12),
R => '0'
);
\addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[13]_i_1_n_0\,
Q => addr_1(13),
R => '0'
);
\addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[1]_i_1_n_0\,
Q => addr_1(1),
R => '0'
);
\addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[2]_i_1_n_0\,
Q => addr_1(2),
R => '0'
);
\addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[3]_i_1_n_0\,
Q => addr_1(3),
R => '0'
);
\addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[4]_i_1_n_0\,
Q => addr_1(4),
R => '0'
);
\addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[5]_i_1_n_0\,
Q => addr_1(5),
R => '0'
);
\addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[6]_i_1_n_0\,
Q => addr_1(6),
R => '0'
);
\addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[7]_i_1_n_0\,
Q => addr_1(7),
R => '0'
);
\addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[8]_i_1_n_0\,
Q => addr_1(8),
R => '0'
);
\addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[9]_i_1_n_0\,
Q => addr_1(9),
R => '0'
);
\bottom_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8800880000000800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[1]_rep_n_0\,
O => bottom_left_0
);
\bottom_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(0),
Q => \bottom_left_0_reg_n_0_[0]\,
R => '0'
);
\bottom_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(10),
Q => \bottom_left_0_reg_n_0_[10]\,
R => '0'
);
\bottom_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(11),
Q => \bottom_left_0_reg_n_0_[11]\,
R => '0'
);
\bottom_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(12),
Q => \bottom_left_0_reg_n_0_[12]\,
R => '0'
);
\bottom_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(13),
Q => \bottom_left_0_reg_n_0_[13]\,
R => '0'
);
\bottom_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(14),
Q => \bottom_left_0_reg_n_0_[14]\,
R => '0'
);
\bottom_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(15),
Q => \bottom_left_0_reg_n_0_[15]\,
R => '0'
);
\bottom_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(1),
Q => \bottom_left_0_reg_n_0_[1]\,
R => '0'
);
\bottom_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(2),
Q => \bottom_left_0_reg_n_0_[2]\,
R => '0'
);
\bottom_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(3),
Q => \bottom_left_0_reg_n_0_[3]\,
R => '0'
);
\bottom_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(4),
Q => \bottom_left_0_reg_n_0_[4]\,
R => '0'
);
\bottom_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(5),
Q => \bottom_left_0_reg_n_0_[5]\,
R => '0'
);
\bottom_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(6),
Q => \bottom_left_0_reg_n_0_[6]\,
R => '0'
);
\bottom_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(7),
Q => \bottom_left_0_reg_n_0_[7]\,
R => '0'
);
\bottom_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(8),
Q => \bottom_left_0_reg_n_0_[8]\,
R => '0'
);
\bottom_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(9),
Q => \bottom_left_0_reg_n_0_[9]\,
R => '0'
);
\bottom_left_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000040"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
O => top_right_1
);
\bottom_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(0),
Q => bottom_left_1(0),
R => '0'
);
\bottom_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(10),
Q => bottom_left_1(10),
R => '0'
);
\bottom_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(11),
Q => bottom_left_1(11),
R => '0'
);
\bottom_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(12),
Q => bottom_left_1(12),
R => '0'
);
\bottom_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(13),
Q => bottom_left_1(13),
R => '0'
);
\bottom_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(14),
Q => bottom_left_1(14),
R => '0'
);
\bottom_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(15),
Q => bottom_left_1(15),
R => '0'
);
\bottom_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(1),
Q => bottom_left_1(1),
R => '0'
);
\bottom_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(2),
Q => bottom_left_1(2),
R => '0'
);
\bottom_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(3),
Q => bottom_left_1(3),
R => '0'
);
\bottom_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(4),
Q => bottom_left_1(4),
R => '0'
);
\bottom_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(5),
Q => bottom_left_1(5),
R => '0'
);
\bottom_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(6),
Q => bottom_left_1(6),
R => '0'
);
\bottom_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(7),
Q => bottom_left_1(7),
R => '0'
);
\bottom_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(8),
Q => bottom_left_1(8),
R => '0'
);
\bottom_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(9),
Q => bottom_left_1(9),
R => '0'
);
\bottom_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[0]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(0),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(0),
O => p_0_out(0)
);
\bottom_right_0[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(0),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[0]_i_2_n_0\
);
\bottom_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[10]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(10),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(10),
O => p_0_out(10)
);
\bottom_right_0[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(10),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(10),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[10]_i_2_n_0\
);
\bottom_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[11]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(11),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(11),
O => p_0_out(11)
);
\bottom_right_0[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(11),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(11),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[11]_i_2_n_0\
);
\bottom_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[12]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(12),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(12),
O => p_0_out(12)
);
\bottom_right_0[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(12),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(12),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[12]_i_2_n_0\
);
\bottom_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[13]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(13),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(13),
O => p_0_out(13)
);
\bottom_right_0[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(13),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(13),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[13]_i_2_n_0\
);
\bottom_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[14]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(14),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(14),
O => p_0_out(14)
);
\bottom_right_0[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(14),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(14),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[14]_i_2_n_0\
);
\bottom_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"444A000000000000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \bottom_right_0[15]_i_1_n_0\
);
\bottom_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[15]_i_4_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(15),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(15),
O => p_0_out(15)
);
\bottom_right_0[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(2),
O => \bottom_right_0[15]_i_3_n_0\
);
\bottom_right_0[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(15),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(15),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[15]_i_4_n_0\
);
\bottom_right_0[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(0),
O => \bottom_right_0[15]_i_5_n_0\
);
\bottom_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[1]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(1),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(1),
O => p_0_out(1)
);
\bottom_right_0[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(1),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[1]_i_2_n_0\
);
\bottom_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[2]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(2),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(2),
O => p_0_out(2)
);
\bottom_right_0[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(2),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[2]_i_2_n_0\
);
\bottom_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[3]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(3),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(3),
O => p_0_out(3)
);
\bottom_right_0[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(3),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[3]_i_2_n_0\
);
\bottom_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[4]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(4),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(4),
O => p_0_out(4)
);
\bottom_right_0[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(4),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[4]_i_2_n_0\
);
\bottom_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[5]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(5),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(5),
O => p_0_out(5)
);
\bottom_right_0[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(5),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[5]_i_2_n_0\
);
\bottom_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[6]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(6),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(6),
O => p_0_out(6)
);
\bottom_right_0[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(6),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[6]_i_2_n_0\
);
\bottom_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[7]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(7),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(7),
O => p_0_out(7)
);
\bottom_right_0[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(7),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[7]_i_2_n_0\
);
\bottom_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[8]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(8),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(8),
O => p_0_out(8)
);
\bottom_right_0[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(8),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[8]_i_2_n_0\
);
\bottom_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[9]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(9),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(9),
O => p_0_out(9)
);
\bottom_right_0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(9),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[9]_i_2_n_0\
);
\bottom_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(0),
Q => \bottom_right_0_reg_n_0_[0]\,
R => '0'
);
\bottom_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(10),
Q => \bottom_right_0_reg_n_0_[10]\,
R => '0'
);
\bottom_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(11),
Q => \bottom_right_0_reg_n_0_[11]\,
R => '0'
);
\bottom_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(12),
Q => \bottom_right_0_reg_n_0_[12]\,
R => '0'
);
\bottom_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(13),
Q => \bottom_right_0_reg_n_0_[13]\,
R => '0'
);
\bottom_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(14),
Q => \bottom_right_0_reg_n_0_[14]\,
R => '0'
);
\bottom_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(15),
Q => \bottom_right_0_reg_n_0_[15]\,
R => '0'
);
\bottom_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(1),
Q => \bottom_right_0_reg_n_0_[1]\,
R => '0'
);
\bottom_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(2),
Q => \bottom_right_0_reg_n_0_[2]\,
R => '0'
);
\bottom_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(3),
Q => \bottom_right_0_reg_n_0_[3]\,
R => '0'
);
\bottom_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(4),
Q => \bottom_right_0_reg_n_0_[4]\,
R => '0'
);
\bottom_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(5),
Q => \bottom_right_0_reg_n_0_[5]\,
R => '0'
);
\bottom_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(6),
Q => \bottom_right_0_reg_n_0_[6]\,
R => '0'
);
\bottom_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(7),
Q => \bottom_right_0_reg_n_0_[7]\,
R => '0'
);
\bottom_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(8),
Q => \bottom_right_0_reg_n_0_[8]\,
R => '0'
);
\bottom_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(9),
Q => \bottom_right_0_reg_n_0_[9]\,
R => '0'
);
\bottom_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[0]\,
O => \bottom_right_1[0]_i_1_n_0\
);
\bottom_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(10),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \bottom_right_1[10]_i_1_n_0\
);
\bottom_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(11),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \bottom_right_1[11]_i_1_n_0\
);
\bottom_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(12),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \bottom_right_1[12]_i_1_n_0\
);
\bottom_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(13),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[13]\,
O => \bottom_right_1[13]_i_1_n_0\
);
\bottom_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(14),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[14]\,
O => \bottom_right_1[14]_i_1_n_0\
);
\bottom_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(15),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[15]\,
O => \bottom_right_1[15]_i_1_n_0\
);
\bottom_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(1),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[1]\,
O => \bottom_right_1[1]_i_1_n_0\
);
\bottom_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(2),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \bottom_right_1[2]_i_1_n_0\
);
\bottom_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(3),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \bottom_right_1[3]_i_1_n_0\
);
\bottom_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(4),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \bottom_right_1[4]_i_1_n_0\
);
\bottom_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(5),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \bottom_right_1[5]_i_1_n_0\
);
\bottom_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(6),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \bottom_right_1[6]_i_1_n_0\
);
\bottom_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(7),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \bottom_right_1[7]_i_1_n_0\
);
\bottom_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \bottom_right_1[8]_i_1_n_0\
);
\bottom_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(9),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \bottom_right_1[9]_i_1_n_0\
);
\bottom_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[0]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[0]\,
R => '0'
);
\bottom_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[10]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[10]\,
R => '0'
);
\bottom_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[11]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[11]\,
R => '0'
);
\bottom_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[12]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[12]\,
R => '0'
);
\bottom_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[13]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[13]\,
R => '0'
);
\bottom_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[14]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[14]\,
R => '0'
);
\bottom_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[15]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[15]\,
R => '0'
);
\bottom_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[1]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[1]\,
R => '0'
);
\bottom_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[2]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[2]\,
R => '0'
);
\bottom_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[3]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[3]\,
R => '0'
);
\bottom_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[4]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[4]\,
R => '0'
);
\bottom_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[5]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[5]\,
R => '0'
);
\bottom_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[6]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[6]\,
R => '0'
);
\bottom_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[7]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[7]\,
R => '0'
);
\bottom_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[8]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[8]\,
R => '0'
);
\bottom_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[9]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[9]\,
R => '0'
);
bram_0: entity work.system_vga_hessian_0_0_blk_mem_gen_0
port map (
addra(13) => \addr_0_reg_n_0_[13]\,
addra(12) => \addr_0_reg_n_0_[12]\,
addra(11) => \addr_0_reg_n_0_[11]\,
addra(10) => \addr_0_reg_n_0_[10]\,
addra(9) => \addr_0_reg_n_0_[9]\,
addra(8) => \addr_0_reg_n_0_[8]\,
addra(7) => \addr_0_reg_n_0_[7]\,
addra(6) => \addr_0_reg_n_0_[6]\,
addra(5) => \addr_0_reg_n_0_[5]\,
addra(4) => \addr_0_reg_n_0_[4]\,
addra(3) => \addr_0_reg_n_0_[3]\,
addra(2) => \addr_0_reg_n_0_[2]\,
addra(1) => \addr_0_reg_n_0_[1]\,
addra(0) => \addr_0_reg_n_0_[0]\,
addrb(13 downto 0) => addr_1(13 downto 0),
clka => clk_x16,
clkb => clk_x16,
dina(15) => \din_reg_n_0_[15]\,
dina(14) => \din_reg_n_0_[14]\,
dina(13) => \din_reg_n_0_[13]\,
dina(12) => \din_reg_n_0_[12]\,
dina(11) => \din_reg_n_0_[11]\,
dina(10) => \din_reg_n_0_[10]\,
dina(9) => \din_reg_n_0_[9]\,
dina(8) => \din_reg_n_0_[8]\,
dina(7) => \din_reg_n_0_[7]\,
dina(6) => \din_reg_n_0_[6]\,
dina(5) => \din_reg_n_0_[5]\,
dina(4) => \din_reg_n_0_[4]\,
dina(3) => \din_reg_n_0_[3]\,
dina(2) => \din_reg_n_0_[2]\,
dina(1) => \din_reg_n_0_[1]\,
dina(0) => \din_reg_n_0_[0]\,
dinb(15 downto 0) => B"0000000000000000",
douta(15 downto 0) => dout_0(15 downto 0),
doutb(15 downto 0) => dout_1(15 downto 0),
ena => '1',
enb => '1',
wea(0) => wen_reg_n_0,
web(0) => '0'
);
\cache[9][15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => \cache[9][15]_i_1_n_0\
);
\cache[9][15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => active,
I1 => cycle(2),
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => \cycle_reg[0]_rep_n_0\,
O => \cache[10]_5\
);
\cache_reg[0][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(0),
Q => \cache_reg[0]_4\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(10),
Q => \cache_reg[0]_4\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(11),
Q => \cache_reg[0]_4\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(12),
Q => \cache_reg[0]_4\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(13),
Q => \cache_reg[0]_4\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(14),
Q => \cache_reg[0]_4\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(15),
Q => \cache_reg[0]_4\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(1),
Q => \cache_reg[0]_4\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(2),
Q => \cache_reg[0]_4\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(3),
Q => \cache_reg[0]_4\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(4),
Q => \cache_reg[0]_4\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(5),
Q => \cache_reg[0]_4\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(6),
Q => \cache_reg[0]_4\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(7),
Q => \cache_reg[0]_4\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(8),
Q => \cache_reg[0]_4\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(9),
Q => \cache_reg[0]_4\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(0),
Q => \cache_reg[10]_3\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(10),
Q => \cache_reg[10]_3\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(11),
Q => \cache_reg[10]_3\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(12),
Q => \cache_reg[10]_3\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(13),
Q => \cache_reg[10]_3\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(14),
Q => \cache_reg[10]_3\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(15),
Q => \cache_reg[10]_3\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(1),
Q => \cache_reg[10]_3\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(2),
Q => \cache_reg[10]_3\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(3),
Q => \cache_reg[10]_3\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(4),
Q => \cache_reg[10]_3\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(5),
Q => \cache_reg[10]_3\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(6),
Q => \cache_reg[10]_3\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(7),
Q => \cache_reg[10]_3\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(8),
Q => \cache_reg[10]_3\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(9),
Q => \cache_reg[10]_3\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[2][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(0),
Q => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(10),
Q => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(11),
Q => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(12),
Q => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(13),
Q => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(14),
Q => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(15),
Q => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(1),
Q => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(2),
Q => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(3),
Q => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(4),
Q => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(5),
Q => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(6),
Q => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(7),
Q => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(8),
Q => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(9),
Q => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[3][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[4][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__14_n_0\,
Q => \cache_reg[4]_0\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__4_n_0\,
Q => \cache_reg[4]_0\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__3_n_0\,
Q => \cache_reg[4]_0\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__2_n_0\,
Q => \cache_reg[4]_0\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__1_n_0\,
Q => \cache_reg[4]_0\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__0_n_0\,
Q => \cache_reg[4]_0\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_gate_n_0,
Q => \cache_reg[4]_0\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__13_n_0\,
Q => \cache_reg[4]_0\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__12_n_0\,
Q => \cache_reg[4]_0\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__11_n_0\,
Q => \cache_reg[4]_0\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__10_n_0\,
Q => \cache_reg[4]_0\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__9_n_0\,
Q => \cache_reg[4]_0\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__8_n_0\,
Q => \cache_reg[4]_0\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__7_n_0\,
Q => \cache_reg[4]_0\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__6_n_0\,
Q => \cache_reg[4]_0\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__5_n_0\,
Q => \cache_reg[4]_0\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[6][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(0),
Q => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(10),
Q => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(11),
Q => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(12),
Q => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(13),
Q => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(14),
Q => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(15),
Q => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(1),
Q => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(2),
Q => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(3),
Q => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(4),
Q => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(5),
Q => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(6),
Q => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(7),
Q => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(8),
Q => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(9),
Q => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[7][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__30_n_0\,
Q => \cache_reg[8]_1\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__20_n_0\,
Q => \cache_reg[8]_1\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__19_n_0\,
Q => \cache_reg[8]_1\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__18_n_0\,
Q => \cache_reg[8]_1\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__17_n_0\,
Q => \cache_reg[8]_1\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__16_n_0\,
Q => \cache_reg[8]_1\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__15_n_0\,
Q => \cache_reg[8]_1\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__29_n_0\,
Q => \cache_reg[8]_1\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__28_n_0\,
Q => \cache_reg[8]_1\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__27_n_0\,
Q => \cache_reg[8]_1\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__26_n_0\,
Q => \cache_reg[8]_1\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__25_n_0\,
Q => \cache_reg[8]_1\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__24_n_0\,
Q => \cache_reg[8]_1\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__23_n_0\,
Q => \cache_reg[8]_1\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__22_n_0\,
Q => \cache_reg[8]_1\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__21_n_0\,
Q => \cache_reg[8]_1\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(0),
Q => \cache_reg[9]_2\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(10),
Q => \cache_reg[9]_2\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(11),
Q => \cache_reg[9]_2\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(12),
Q => \cache_reg[9]_2\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(13),
Q => \cache_reg[9]_2\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(14),
Q => \cache_reg[9]_2\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(15),
Q => \cache_reg[9]_2\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(1),
Q => \cache_reg[9]_2\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(2),
Q => \cache_reg[9]_2\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(3),
Q => \cache_reg[9]_2\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(4),
Q => \cache_reg[9]_2\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(5),
Q => \cache_reg[9]_2\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(6),
Q => \cache_reg[9]_2\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(7),
Q => \cache_reg[9]_2\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(8),
Q => \cache_reg[9]_2\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(9),
Q => \cache_reg[9]_2\(9),
R => \cache[9][15]_i_1_n_0\
);
cache_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => cache_reg_gate_n_0
);
\cache_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__0_n_0\
);
\cache_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__1_n_0\
);
\cache_reg_gate__10\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__10_n_0\
);
\cache_reg_gate__11\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__11_n_0\
);
\cache_reg_gate__12\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__12_n_0\
);
\cache_reg_gate__13\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__13_n_0\
);
\cache_reg_gate__14\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__14_n_0\
);
\cache_reg_gate__15\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__15_n_0\
);
\cache_reg_gate__16\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__16_n_0\
);
\cache_reg_gate__17\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__17_n_0\
);
\cache_reg_gate__18\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__18_n_0\
);
\cache_reg_gate__19\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__19_n_0\
);
\cache_reg_gate__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__2_n_0\
);
\cache_reg_gate__20\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__20_n_0\
);
\cache_reg_gate__21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__21_n_0\
);
\cache_reg_gate__22\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__22_n_0\
);
\cache_reg_gate__23\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__23_n_0\
);
\cache_reg_gate__24\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__24_n_0\
);
\cache_reg_gate__25\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__25_n_0\
);
\cache_reg_gate__26\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__26_n_0\
);
\cache_reg_gate__27\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__27_n_0\
);
\cache_reg_gate__28\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__28_n_0\
);
\cache_reg_gate__29\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__29_n_0\
);
\cache_reg_gate__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__3_n_0\
);
\cache_reg_gate__30\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__30_n_0\
);
\cache_reg_gate__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__4_n_0\
);
\cache_reg_gate__5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__5_n_0\
);
\cache_reg_gate__6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__6_n_0\
);
\cache_reg_gate__7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__7_n_0\
);
\cache_reg_gate__8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__8_n_0\
);
\cache_reg_gate__9\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__9_n_0\
);
cache_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => '1',
Q => cache_reg_r_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_n_0,
Q => cache_reg_r_0_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_0_n_0,
Q => cache_reg_r_1_n_0,
R => \cache[9][15]_i_1_n_0\
);
\compute_addr_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(0),
O => \compute_addr_0[0]_i_1_n_0\
);
\compute_addr_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[10]_i_2_n_0\,
O => \compute_addr_0[10]_i_1_n_0\
);
\compute_addr_0[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[0]\,
I1 => data5(10),
I2 => cycle(3),
I3 => \y1_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[10]_i_2_n_0\
);
\compute_addr_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDCDC88888"
)
port map (
I0 => cycle(0),
I1 => data5(11),
I2 => cycle(3),
I3 => \y1_reg_n_0_[1]\,
I4 => \compute_addr_0[11]_i_2_n_0\,
I5 => \compute_addr_0[11]_i_3_n_0\,
O => \compute_addr_0[11]_i_1_n_0\
);
\compute_addr_0[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_2_n_0\
);
\compute_addr_0[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAAAAAACFC0"
)
port map (
I0 => \compute_addr_2[11]_i_2_n_0\,
I1 => \y1_reg_n_0_[1]\,
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_3_n_0\
);
\compute_addr_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[12]_i_2_n_0\,
O => \compute_addr_0[12]_i_1_n_0\
);
\compute_addr_0[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[2]\,
I1 => data5(12),
I2 => cycle(3),
I3 => \y1_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[12]_i_2_n_0\
);
\compute_addr_0[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(0),
O => compute_addr_0
);
\compute_addr_0[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[13]_i_3_n_0\,
O => \compute_addr_0[13]_i_2_n_0\
);
\compute_addr_0[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => \y1_reg_n_0_[3]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[13]_i_3_n_0\
);
\compute_addr_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(1),
O => \compute_addr_0[1]_i_1_n_0\
);
\compute_addr_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \compute_addr_0[2]_i_1_n_0\
);
\compute_addr_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(3),
O => \compute_addr_0[3]_i_1_n_0\
);
\compute_addr_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(4),
O => \compute_addr_0[4]_i_1_n_0\
);
\compute_addr_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(5),
O => \compute_addr_0[5]_i_1_n_0\
);
\compute_addr_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(6),
O => \compute_addr_0[6]_i_1_n_0\
);
\compute_addr_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \compute_addr_0[7]_i_1_n_0\
);
\compute_addr_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(8),
O => \compute_addr_0[8]_i_1_n_0\
);
\compute_addr_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data1(9),
O => \compute_addr_0[9]_i_1_n_0\
);
\compute_addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[0]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[0]\,
R => '0'
);
\compute_addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[10]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[10]\,
R => '0'
);
\compute_addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[11]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[11]\,
R => '0'
);
\compute_addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[12]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[12]\,
R => '0'
);
\compute_addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[13]_i_2_n_0\,
Q => \compute_addr_0_reg_n_0_[13]\,
R => '0'
);
\compute_addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[1]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[1]\,
R => '0'
);
\compute_addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[2]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[2]\,
R => '0'
);
\compute_addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[3]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[3]\,
R => '0'
);
\compute_addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[4]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[4]\,
R => '0'
);
\compute_addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[5]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[5]\,
R => '0'
);
\compute_addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[6]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[6]\,
R => '0'
);
\compute_addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[7]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[7]\,
R => '0'
);
\compute_addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[8]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[8]\,
R => '0'
);
\compute_addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[9]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[9]\,
R => '0'
);
\compute_addr_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(0),
O => \compute_addr_1[0]_i_1_n_0\
);
\compute_addr_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[10]_i_2_n_0\,
O => \compute_addr_1[10]_i_1_n_0\
);
\compute_addr_1[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(10),
I1 => data2(10),
I2 => cycle(3),
I3 => \y3_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[10]_i_2_n_0\
);
\compute_addr_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(11),
I1 => cycle(0),
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[11]_i_2_n_0\,
O => \compute_addr_1[11]_i_1_n_0\
);
\compute_addr_1[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(11),
I1 => data2(11),
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[11]_i_2_n_0\
);
\compute_addr_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[12]_i_2_n_0\,
O => \compute_addr_1[12]_i_1_n_0\
);
\compute_addr_1[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(12),
I1 => data2(12),
I2 => cycle(3),
I3 => \y3_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[12]_i_2_n_0\
);
\compute_addr_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[13]_i_2_n_0\,
O => \compute_addr_1[13]_i_1_n_0\
);
\compute_addr_1[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => data2(13),
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[13]_i_2_n_0\
);
\compute_addr_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(1),
O => \compute_addr_1[1]_i_1_n_0\
);
\compute_addr_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(2),
O => \compute_addr_1[2]_i_1_n_0\
);
\compute_addr_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(3),
O => \compute_addr_1[3]_i_1_n_0\
);
\compute_addr_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(4),
O => \compute_addr_1[4]_i_1_n_0\
);
\compute_addr_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(5),
O => \compute_addr_1[5]_i_1_n_0\
);
\compute_addr_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(6),
O => \compute_addr_1[6]_i_1_n_0\
);
\compute_addr_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(7),
O => \compute_addr_1[7]_i_1_n_0\
);
\compute_addr_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(8),
O => \compute_addr_1[8]_i_1_n_0\
);
\compute_addr_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(9),
O => \compute_addr_1[9]_i_1_n_0\
);
\compute_addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[0]_i_1_n_0\,
Q => compute_addr_1(0),
R => '0'
);
\compute_addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[10]_i_1_n_0\,
Q => compute_addr_1(10),
R => '0'
);
\compute_addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[11]_i_1_n_0\,
Q => compute_addr_1(11),
R => '0'
);
\compute_addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[12]_i_1_n_0\,
Q => compute_addr_1(12),
R => '0'
);
\compute_addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[13]_i_1_n_0\,
Q => compute_addr_1(13),
R => '0'
);
\compute_addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[1]_i_1_n_0\,
Q => compute_addr_1(1),
R => '0'
);
\compute_addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[2]_i_1_n_0\,
Q => compute_addr_1(2),
R => '0'
);
\compute_addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[3]_i_1_n_0\,
Q => compute_addr_1(3),
R => '0'
);
\compute_addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[4]_i_1_n_0\,
Q => compute_addr_1(4),
R => '0'
);
\compute_addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[5]_i_1_n_0\,
Q => compute_addr_1(5),
R => '0'
);
\compute_addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[6]_i_1_n_0\,
Q => compute_addr_1(6),
R => '0'
);
\compute_addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[7]_i_1_n_0\,
Q => compute_addr_1(7),
R => '0'
);
\compute_addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[8]_i_1_n_0\,
Q => compute_addr_1(8),
R => '0'
);
\compute_addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[9]_i_1_n_0\,
Q => compute_addr_1(9),
R => '0'
);
\compute_addr_2[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[0]\,
O => \compute_addr_2[10]_i_1_n_0\
);
\compute_addr_2[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[0]\,
I1 => cycle(3),
I2 => data1(10),
O => \compute_addr_2[10]_i_2_n_0\
);
\compute_addr_2[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[1]\,
O => \compute_addr_2[11]_i_1_n_0\
);
\compute_addr_2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[1]\,
I1 => cycle(3),
I2 => data1(11),
O => \compute_addr_2[11]_i_2_n_0\
);
\compute_addr_2[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[2]\,
O => \compute_addr_2[12]_i_1_n_0\
);
\compute_addr_2[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[2]\,
I1 => cycle(3),
I2 => data1(12),
O => \compute_addr_2[12]_i_2_n_0\
);
\compute_addr_2[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808080808000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => compute_addr_2
);
\compute_addr_2[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[3]\,
O => \compute_addr_2[13]_i_2_n_0\
);
\compute_addr_2[13]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"81FF"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
O => \compute_addr_2[13]_i_3_n_0\
);
\compute_addr_2[13]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[3]\,
I1 => cycle(3),
I2 => data1(13),
O => \compute_addr_2[13]_i_4_n_0\
);
\compute_addr_2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(0),
Q => \compute_addr_2_reg_n_0_[0]\,
R => '0'
);
\compute_addr_2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[10]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[10]\,
R => '0'
);
\compute_addr_2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[11]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[11]\,
R => '0'
);
\compute_addr_2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[12]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[12]\,
R => '0'
);
\compute_addr_2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[13]_i_2_n_0\,
Q => \compute_addr_2_reg_n_0_[13]\,
R => '0'
);
\compute_addr_2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(1),
Q => \compute_addr_2_reg_n_0_[1]\,
R => '0'
);
\compute_addr_2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(2),
Q => \compute_addr_2_reg_n_0_[2]\,
R => '0'
);
\compute_addr_2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(3),
Q => \compute_addr_2_reg_n_0_[3]\,
R => '0'
);
\compute_addr_2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(4),
Q => \compute_addr_2_reg_n_0_[4]\,
R => '0'
);
\compute_addr_2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(5),
Q => \compute_addr_2_reg_n_0_[5]\,
R => '0'
);
\compute_addr_2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(6),
Q => \compute_addr_2_reg_n_0_[6]\,
R => '0'
);
\compute_addr_2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(7),
Q => \compute_addr_2_reg_n_0_[7]\,
R => '0'
);
\compute_addr_2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(8),
Q => \compute_addr_2_reg_n_0_[8]\,
R => '0'
);
\compute_addr_2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(9),
Q => \compute_addr_2_reg_n_0_[9]\,
R => '0'
);
\compute_addr_3[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(0),
O => \compute_addr_3[0]_i_1_n_0\
);
\compute_addr_3[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(10),
O => \compute_addr_3[10]_i_1_n_0\
);
\compute_addr_3[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(0),
I1 => cycle(3),
I2 => y8(0),
O => \compute_addr_3[10]_i_2_n_0\
);
\compute_addr_3[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(11),
O => \compute_addr_3[11]_i_1_n_0\
);
\compute_addr_3[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(1),
I1 => cycle(3),
I2 => y8(1),
O => \compute_addr_3[11]_i_2_n_0\
);
\compute_addr_3[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(12),
O => \compute_addr_3[12]_i_1_n_0\
);
\compute_addr_3[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(2),
I1 => cycle(3),
I2 => y8(2),
O => \compute_addr_3[12]_i_2_n_0\
);
\compute_addr_3[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(13),
O => \compute_addr_3[13]_i_1_n_0\
);
\compute_addr_3[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(3),
I1 => cycle(3),
I2 => y8(3),
O => \compute_addr_3[13]_i_2_n_0\
);
\compute_addr_3[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(1),
O => \compute_addr_3[1]_i_1_n_0\
);
\compute_addr_3[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(2),
O => \compute_addr_3[2]_i_1_n_0\
);
\compute_addr_3[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(3),
O => \compute_addr_3[3]_i_1_n_0\
);
\compute_addr_3[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(4),
O => \compute_addr_3[4]_i_1_n_0\
);
\compute_addr_3[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(5),
O => \compute_addr_3[5]_i_1_n_0\
);
\compute_addr_3[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(6),
O => \compute_addr_3[6]_i_1_n_0\
);
\compute_addr_3[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(7),
O => \compute_addr_3[7]_i_1_n_0\
);
\compute_addr_3[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(8),
O => \compute_addr_3[8]_i_1_n_0\
);
\compute_addr_3[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(9),
O => \compute_addr_3[9]_i_1_n_0\
);
\compute_addr_3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[0]_i_1_n_0\,
Q => compute_addr_3(0),
R => '0'
);
\compute_addr_3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[10]_i_1_n_0\,
Q => compute_addr_3(10),
R => '0'
);
\compute_addr_3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[11]_i_1_n_0\,
Q => compute_addr_3(11),
R => '0'
);
\compute_addr_3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[12]_i_1_n_0\,
Q => compute_addr_3(12),
R => '0'
);
\compute_addr_3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[13]_i_1_n_0\,
Q => compute_addr_3(13),
R => '0'
);
\compute_addr_3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[1]_i_1_n_0\,
Q => compute_addr_3(1),
R => '0'
);
\compute_addr_3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[2]_i_1_n_0\,
Q => compute_addr_3(2),
R => '0'
);
\compute_addr_3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[3]_i_1_n_0\,
Q => compute_addr_3(3),
R => '0'
);
\compute_addr_3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[4]_i_1_n_0\,
Q => compute_addr_3(4),
R => '0'
);
\compute_addr_3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[5]_i_1_n_0\,
Q => compute_addr_3(5),
R => '0'
);
\compute_addr_3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[6]_i_1_n_0\,
Q => compute_addr_3(6),
R => '0'
);
\compute_addr_3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[7]_i_1_n_0\,
Q => compute_addr_3(7),
R => '0'
);
\compute_addr_3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[8]_i_1_n_0\,
Q => compute_addr_3(8),
R => '0'
);
\compute_addr_3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[9]_i_1_n_0\,
Q => compute_addr_3(9),
R => '0'
);
\corner[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
I5 => top,
O => corner
);
\corner_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(0),
Q => \corner_reg_n_0_[0]\,
R => corner
);
\corner_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(10),
Q => \corner_reg_n_0_[10]\,
R => corner
);
\corner_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(11),
Q => \corner_reg_n_0_[11]\,
R => corner
);
\corner_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(12),
Q => \corner_reg_n_0_[12]\,
R => corner
);
\corner_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(13),
Q => \corner_reg_n_0_[13]\,
R => corner
);
\corner_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(14),
Q => \corner_reg_n_0_[14]\,
R => corner
);
\corner_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(15),
Q => \corner_reg_n_0_[15]\,
R => corner
);
\corner_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(1),
Q => \corner_reg_n_0_[1]\,
R => corner
);
\corner_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(2),
Q => \corner_reg_n_0_[2]\,
R => corner
);
\corner_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(3),
Q => \corner_reg_n_0_[3]\,
R => corner
);
\corner_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(4),
Q => \corner_reg_n_0_[4]\,
R => corner
);
\corner_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(5),
Q => \corner_reg_n_0_[5]\,
R => corner
);
\corner_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(6),
Q => \corner_reg_n_0_[6]\,
R => corner
);
\corner_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(7),
Q => \corner_reg_n_0_[7]\,
R => corner
);
\corner_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(8),
Q => \corner_reg_n_0_[8]\,
R => corner
);
\corner_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(9),
Q => \corner_reg_n_0_[9]\,
R => corner
);
\cycle[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_i_1_n_0\
);
\cycle[0]_rep_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_rep_i_1_n_0\
);
\cycle[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_i_1_n_0\
);
\cycle[1]_rep_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1_n_0\
);
\cycle[1]_rep_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1__0_n_0\
);
\cycle[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => cycle(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
O => \cycle[2]_i_1_n_0\
);
\cycle[2]_rep_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => cycle(0),
I2 => cycle(2),
O => \cycle[2]_rep_i_1_n_0\
);
\cycle[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rst,
I1 => active,
O => \cycle[3]_i_1_n_0\
);
\cycle[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => cycle(1),
I3 => \cycle_reg[0]_rep_n_0\,
O => \cycle[3]_i_2_n_0\
);
\cycle_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_i_1_n_0\,
Q => cycle(0),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_rep_i_1_n_0\,
Q => \cycle_reg[0]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_i_1_n_0\,
Q => cycle(1),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1_n_0\,
Q => \cycle_reg[1]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1__0_n_0\,
Q => \cycle_reg[1]_rep__0_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_i_1_n_0\,
Q => cycle(2),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_rep_i_1_n_0\,
Q => \cycle_reg[2]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[3]_i_2_n_0\,
Q => cycle(3),
R => \cycle[3]_i_1_n_0\
);
det_0_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => A(15),
A(28) => A(15),
A(27) => A(15),
A(26) => A(15),
A(25) => A(15),
A(24) => A(15),
A(23) => A(15),
A(22) => A(15),
A(21) => A(15),
A(20) => A(15),
A(19) => A(15),
A(18) => A(15),
A(17) => A(15),
A(16) => A(15),
A(15 downto 0) => A(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_0_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => B(15),
B(16) => B(15),
B(15 downto 0) => B(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_0_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_0_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => Lxx,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => det_0_reg_i_2_n_0,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => det_0,
CEP => '0',
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_det_0_reg_OVERFLOW_UNCONNECTED,
P(47 downto 0) => NLW_det_0_reg_P_UNCONNECTED(47 downto 0),
PATTERNBDETECT => NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_0_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => det_0_reg_n_106,
PCOUT(46) => det_0_reg_n_107,
PCOUT(45) => det_0_reg_n_108,
PCOUT(44) => det_0_reg_n_109,
PCOUT(43) => det_0_reg_n_110,
PCOUT(42) => det_0_reg_n_111,
PCOUT(41) => det_0_reg_n_112,
PCOUT(40) => det_0_reg_n_113,
PCOUT(39) => det_0_reg_n_114,
PCOUT(38) => det_0_reg_n_115,
PCOUT(37) => det_0_reg_n_116,
PCOUT(36) => det_0_reg_n_117,
PCOUT(35) => det_0_reg_n_118,
PCOUT(34) => det_0_reg_n_119,
PCOUT(33) => det_0_reg_n_120,
PCOUT(32) => det_0_reg_n_121,
PCOUT(31) => det_0_reg_n_122,
PCOUT(30) => det_0_reg_n_123,
PCOUT(29) => det_0_reg_n_124,
PCOUT(28) => det_0_reg_n_125,
PCOUT(27) => det_0_reg_n_126,
PCOUT(26) => det_0_reg_n_127,
PCOUT(25) => det_0_reg_n_128,
PCOUT(24) => det_0_reg_n_129,
PCOUT(23) => det_0_reg_n_130,
PCOUT(22) => det_0_reg_n_131,
PCOUT(21) => det_0_reg_n_132,
PCOUT(20) => det_0_reg_n_133,
PCOUT(19) => det_0_reg_n_134,
PCOUT(18) => det_0_reg_n_135,
PCOUT(17) => det_0_reg_n_136,
PCOUT(16) => det_0_reg_n_137,
PCOUT(15) => det_0_reg_n_138,
PCOUT(14) => det_0_reg_n_139,
PCOUT(13) => det_0_reg_n_140,
PCOUT(12) => det_0_reg_n_141,
PCOUT(11) => det_0_reg_n_142,
PCOUT(10) => det_0_reg_n_143,
PCOUT(9) => det_0_reg_n_144,
PCOUT(8) => det_0_reg_n_145,
PCOUT(7) => det_0_reg_n_146,
PCOUT(6) => det_0_reg_n_147,
PCOUT(5) => det_0_reg_n_148,
PCOUT(4) => det_0_reg_n_149,
PCOUT(3) => det_0_reg_n_150,
PCOUT(2) => det_0_reg_n_151,
PCOUT(1) => det_0_reg_n_152,
PCOUT(0) => det_0_reg_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_0_reg_UNDERFLOW_UNCONNECTED
);
det_0_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => Lxx
);
det_0_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => rst,
I5 => active,
O => det_0_reg_i_2_n_0
);
det_0_reg_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => cycle(1),
I3 => rst,
I4 => active,
I5 => \cycle_reg[0]_rep_n_0\,
O => det_0
);
\det_abs[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(10),
I1 => det_reg_n_95,
I2 => det_reg_n_74,
O => \det_abs[10]_i_1_n_0\
);
\det_abs[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(11),
I1 => det_reg_n_94,
I2 => det_reg_n_74,
O => \det_abs[11]_i_1_n_0\
);
\det_abs[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(12),
I1 => det_reg_n_93,
I2 => det_reg_n_74,
O => \det_abs[12]_i_1_n_0\
);
\det_abs[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_93,
O => \det_abs[12]_i_3_n_0\
);
\det_abs[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_94,
O => \det_abs[12]_i_4_n_0\
);
\det_abs[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_95,
O => \det_abs[12]_i_5_n_0\
);
\det_abs[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_96,
O => \det_abs[12]_i_6_n_0\
);
\det_abs[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(13),
I1 => det_reg_n_92,
I2 => det_reg_n_74,
O => \det_abs[13]_i_1_n_0\
);
\det_abs[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(14),
I1 => det_reg_n_91,
I2 => det_reg_n_74,
O => \det_abs[14]_i_1_n_0\
);
\det_abs[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(15),
I1 => det_reg_n_90,
I2 => det_reg_n_74,
O => \det_abs[15]_i_1_n_0\
);
\det_abs[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(16),
I1 => det_reg_n_89,
I2 => det_reg_n_74,
O => \det_abs[16]_i_1_n_0\
);
\det_abs[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_89,
O => \det_abs[16]_i_3_n_0\
);
\det_abs[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_90,
O => \det_abs[16]_i_4_n_0\
);
\det_abs[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_91,
O => \det_abs[16]_i_5_n_0\
);
\det_abs[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_92,
O => \det_abs[16]_i_6_n_0\
);
\det_abs[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(17),
I1 => det_reg_n_88,
I2 => det_reg_n_74,
O => \det_abs[17]_i_1_n_0\
);
\det_abs[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(18),
I1 => det_reg_n_87,
I2 => det_reg_n_74,
O => \det_abs[18]_i_1_n_0\
);
\det_abs[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(19),
I1 => det_reg_n_86,
I2 => det_reg_n_74,
O => \det_abs[19]_i_1_n_0\
);
\det_abs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(1),
I1 => det_reg_n_104,
I2 => det_reg_n_74,
O => \det_abs[1]_i_1_n_0\
);
\det_abs[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(20),
I1 => det_reg_n_85,
I2 => det_reg_n_74,
O => \det_abs[20]_i_1_n_0\
);
\det_abs[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_85,
O => \det_abs[20]_i_3_n_0\
);
\det_abs[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_86,
O => \det_abs[20]_i_4_n_0\
);
\det_abs[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_87,
O => \det_abs[20]_i_5_n_0\
);
\det_abs[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_88,
O => \det_abs[20]_i_6_n_0\
);
\det_abs[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(21),
I1 => det_reg_n_84,
I2 => det_reg_n_74,
O => \det_abs[21]_i_1_n_0\
);
\det_abs[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(22),
I1 => det_reg_n_83,
I2 => det_reg_n_74,
O => \det_abs[22]_i_1_n_0\
);
\det_abs[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(23),
I1 => det_reg_n_82,
I2 => det_reg_n_74,
O => \det_abs[23]_i_1_n_0\
);
\det_abs[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(24),
I1 => det_reg_n_81,
I2 => det_reg_n_74,
O => \det_abs[24]_i_1_n_0\
);
\det_abs[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_81,
O => \det_abs[24]_i_3_n_0\
);
\det_abs[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_82,
O => \det_abs[24]_i_4_n_0\
);
\det_abs[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_83,
O => \det_abs[24]_i_5_n_0\
);
\det_abs[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_84,
O => \det_abs[24]_i_6_n_0\
);
\det_abs[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(25),
I1 => det_reg_n_80,
I2 => det_reg_n_74,
O => \det_abs[25]_i_1_n_0\
);
\det_abs[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(26),
I1 => det_reg_n_79,
I2 => det_reg_n_74,
O => \det_abs[26]_i_1_n_0\
);
\det_abs[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(27),
I1 => det_reg_n_78,
I2 => det_reg_n_74,
O => \det_abs[27]_i_1_n_0\
);
\det_abs[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(28),
I1 => det_reg_n_77,
I2 => det_reg_n_74,
O => \det_abs[28]_i_1_n_0\
);
\det_abs[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_77,
O => \det_abs[28]_i_3_n_0\
);
\det_abs[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_78,
O => \det_abs[28]_i_4_n_0\
);
\det_abs[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_79,
O => \det_abs[28]_i_5_n_0\
);
\det_abs[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_80,
O => \det_abs[28]_i_6_n_0\
);
\det_abs[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(29),
I1 => det_reg_n_76,
I2 => det_reg_n_74,
O => \det_abs[29]_i_1_n_0\
);
\det_abs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(2),
I1 => det_reg_n_103,
I2 => det_reg_n_74,
O => \det_abs[2]_i_1_n_0\
);
\det_abs[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(30),
I1 => det_reg_n_75,
I2 => det_reg_n_74,
O => \det_abs[30]_i_1_n_0\
);
\det_abs[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => det_abs0(31),
I1 => det_reg_n_74,
O => \det_abs[31]_i_1_n_0\
);
\det_abs[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_74,
O => \det_abs[31]_i_3_n_0\
);
\det_abs[31]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_75,
O => \det_abs[31]_i_4_n_0\
);
\det_abs[31]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_76,
O => \det_abs[31]_i_5_n_0\
);
\det_abs[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(3),
I1 => det_reg_n_102,
I2 => det_reg_n_74,
O => \det_abs[3]_i_1_n_0\
);
\det_abs[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(4),
I1 => det_reg_n_101,
I2 => det_reg_n_74,
O => \det_abs[4]_i_1_n_0\
);
\det_abs[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_105,
O => \det_abs[4]_i_3_n_0\
);
\det_abs[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_101,
O => \det_abs[4]_i_4_n_0\
);
\det_abs[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_102,
O => \det_abs[4]_i_5_n_0\
);
\det_abs[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_103,
O => \det_abs[4]_i_6_n_0\
);
\det_abs[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_104,
O => \det_abs[4]_i_7_n_0\
);
\det_abs[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(5),
I1 => det_reg_n_100,
I2 => det_reg_n_74,
O => \det_abs[5]_i_1_n_0\
);
\det_abs[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(6),
I1 => det_reg_n_99,
I2 => det_reg_n_74,
O => \det_abs[6]_i_1_n_0\
);
\det_abs[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(7),
I1 => det_reg_n_98,
I2 => det_reg_n_74,
O => \det_abs[7]_i_1_n_0\
);
\det_abs[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(8),
I1 => det_reg_n_97,
I2 => det_reg_n_74,
O => \det_abs[8]_i_1_n_0\
);
\det_abs[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_97,
O => \det_abs[8]_i_3_n_0\
);
\det_abs[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_98,
O => \det_abs[8]_i_4_n_0\
);
\det_abs[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_99,
O => \det_abs[8]_i_5_n_0\
);
\det_abs[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_100,
O => \det_abs[8]_i_6_n_0\
);
\det_abs[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(9),
I1 => det_reg_n_96,
I2 => det_reg_n_74,
O => \det_abs[9]_i_1_n_0\
);
\det_abs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => det_reg_n_105,
Q => det_abs(0),
R => '0'
);
\det_abs_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[10]_i_1_n_0\,
Q => det_abs(10),
R => '0'
);
\det_abs_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[11]_i_1_n_0\,
Q => det_abs(11),
R => '0'
);
\det_abs_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[12]_i_1_n_0\,
Q => det_abs(12),
R => '0'
);
\det_abs_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[8]_i_2_n_0\,
CO(3) => \det_abs_reg[12]_i_2_n_0\,
CO(2) => \det_abs_reg[12]_i_2_n_1\,
CO(1) => \det_abs_reg[12]_i_2_n_2\,
CO(0) => \det_abs_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(12 downto 9),
S(3) => \det_abs[12]_i_3_n_0\,
S(2) => \det_abs[12]_i_4_n_0\,
S(1) => \det_abs[12]_i_5_n_0\,
S(0) => \det_abs[12]_i_6_n_0\
);
\det_abs_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[13]_i_1_n_0\,
Q => det_abs(13),
R => '0'
);
\det_abs_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[14]_i_1_n_0\,
Q => det_abs(14),
R => '0'
);
\det_abs_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[15]_i_1_n_0\,
Q => det_abs(15),
R => '0'
);
\det_abs_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[16]_i_1_n_0\,
Q => det_abs(16),
R => '0'
);
\det_abs_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[12]_i_2_n_0\,
CO(3) => \det_abs_reg[16]_i_2_n_0\,
CO(2) => \det_abs_reg[16]_i_2_n_1\,
CO(1) => \det_abs_reg[16]_i_2_n_2\,
CO(0) => \det_abs_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(16 downto 13),
S(3) => \det_abs[16]_i_3_n_0\,
S(2) => \det_abs[16]_i_4_n_0\,
S(1) => \det_abs[16]_i_5_n_0\,
S(0) => \det_abs[16]_i_6_n_0\
);
\det_abs_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[17]_i_1_n_0\,
Q => det_abs(17),
R => '0'
);
\det_abs_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[18]_i_1_n_0\,
Q => det_abs(18),
R => '0'
);
\det_abs_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[19]_i_1_n_0\,
Q => det_abs(19),
R => '0'
);
\det_abs_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[1]_i_1_n_0\,
Q => det_abs(1),
R => '0'
);
\det_abs_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[20]_i_1_n_0\,
Q => det_abs(20),
R => '0'
);
\det_abs_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[16]_i_2_n_0\,
CO(3) => \det_abs_reg[20]_i_2_n_0\,
CO(2) => \det_abs_reg[20]_i_2_n_1\,
CO(1) => \det_abs_reg[20]_i_2_n_2\,
CO(0) => \det_abs_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(20 downto 17),
S(3) => \det_abs[20]_i_3_n_0\,
S(2) => \det_abs[20]_i_4_n_0\,
S(1) => \det_abs[20]_i_5_n_0\,
S(0) => \det_abs[20]_i_6_n_0\
);
\det_abs_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[21]_i_1_n_0\,
Q => det_abs(21),
R => '0'
);
\det_abs_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[22]_i_1_n_0\,
Q => det_abs(22),
R => '0'
);
\det_abs_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[23]_i_1_n_0\,
Q => det_abs(23),
R => '0'
);
\det_abs_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[24]_i_1_n_0\,
Q => det_abs(24),
R => '0'
);
\det_abs_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[20]_i_2_n_0\,
CO(3) => \det_abs_reg[24]_i_2_n_0\,
CO(2) => \det_abs_reg[24]_i_2_n_1\,
CO(1) => \det_abs_reg[24]_i_2_n_2\,
CO(0) => \det_abs_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(24 downto 21),
S(3) => \det_abs[24]_i_3_n_0\,
S(2) => \det_abs[24]_i_4_n_0\,
S(1) => \det_abs[24]_i_5_n_0\,
S(0) => \det_abs[24]_i_6_n_0\
);
\det_abs_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[25]_i_1_n_0\,
Q => det_abs(25),
R => '0'
);
\det_abs_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[26]_i_1_n_0\,
Q => det_abs(26),
R => '0'
);
\det_abs_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[27]_i_1_n_0\,
Q => det_abs(27),
R => '0'
);
\det_abs_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[28]_i_1_n_0\,
Q => det_abs(28),
R => '0'
);
\det_abs_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[24]_i_2_n_0\,
CO(3) => \det_abs_reg[28]_i_2_n_0\,
CO(2) => \det_abs_reg[28]_i_2_n_1\,
CO(1) => \det_abs_reg[28]_i_2_n_2\,
CO(0) => \det_abs_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(28 downto 25),
S(3) => \det_abs[28]_i_3_n_0\,
S(2) => \det_abs[28]_i_4_n_0\,
S(1) => \det_abs[28]_i_5_n_0\,
S(0) => \det_abs[28]_i_6_n_0\
);
\det_abs_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[29]_i_1_n_0\,
Q => det_abs(29),
R => '0'
);
\det_abs_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[2]_i_1_n_0\,
Q => det_abs(2),
R => '0'
);
\det_abs_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[30]_i_1_n_0\,
Q => det_abs(30),
R => '0'
);
\det_abs_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[31]_i_1_n_0\,
Q => det_abs(31),
R => '0'
);
\det_abs_reg[31]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \det_abs_reg[31]_i_2_n_2\,
CO(0) => \det_abs_reg[31]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\(3),
O(2 downto 0) => det_abs0(31 downto 29),
S(3) => '0',
S(2) => \det_abs[31]_i_3_n_0\,
S(1) => \det_abs[31]_i_4_n_0\,
S(0) => \det_abs[31]_i_5_n_0\
);
\det_abs_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[3]_i_1_n_0\,
Q => det_abs(3),
R => '0'
);
\det_abs_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[4]_i_1_n_0\,
Q => det_abs(4),
R => '0'
);
\det_abs_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \det_abs_reg[4]_i_2_n_0\,
CO(2) => \det_abs_reg[4]_i_2_n_1\,
CO(1) => \det_abs_reg[4]_i_2_n_2\,
CO(0) => \det_abs_reg[4]_i_2_n_3\,
CYINIT => \det_abs[4]_i_3_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(4 downto 1),
S(3) => \det_abs[4]_i_4_n_0\,
S(2) => \det_abs[4]_i_5_n_0\,
S(1) => \det_abs[4]_i_6_n_0\,
S(0) => \det_abs[4]_i_7_n_0\
);
\det_abs_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[5]_i_1_n_0\,
Q => det_abs(5),
R => '0'
);
\det_abs_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[6]_i_1_n_0\,
Q => det_abs(6),
R => '0'
);
\det_abs_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[7]_i_1_n_0\,
Q => det_abs(7),
R => '0'
);
\det_abs_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[8]_i_1_n_0\,
Q => det_abs(8),
R => '0'
);
\det_abs_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[4]_i_2_n_0\,
CO(3) => \det_abs_reg[8]_i_2_n_0\,
CO(2) => \det_abs_reg[8]_i_2_n_1\,
CO(1) => \det_abs_reg[8]_i_2_n_2\,
CO(0) => \det_abs_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(8 downto 5),
S(3) => \det_abs[8]_i_3_n_0\,
S(2) => \det_abs[8]_i_4_n_0\,
S(1) => \det_abs[8]_i_5_n_0\,
S(0) => \det_abs[8]_i_6_n_0\
);
\det_abs_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[9]_i_1_n_0\,
Q => det_abs(9),
R => '0'
);
det_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \Lxy0__1_carry__2_n_4\,
A(28) => \Lxy0__1_carry__2_n_4\,
A(27) => \Lxy0__1_carry__2_n_4\,
A(26) => \Lxy0__1_carry__2_n_4\,
A(25) => \Lxy0__1_carry__2_n_4\,
A(24) => \Lxy0__1_carry__2_n_4\,
A(23) => \Lxy0__1_carry__2_n_4\,
A(22) => \Lxy0__1_carry__2_n_4\,
A(21) => \Lxy0__1_carry__2_n_4\,
A(20) => \Lxy0__1_carry__2_n_4\,
A(19) => \Lxy0__1_carry__2_n_4\,
A(18) => \Lxy0__1_carry__2_n_4\,
A(17) => \Lxy0__1_carry__2_n_4\,
A(16) => \Lxy0__1_carry__2_n_4\,
A(15) => \Lxy0__1_carry__2_n_4\,
A(14) => \Lxy0__1_carry__2_n_5\,
A(13) => \Lxy0__1_carry__2_n_6\,
A(12) => \Lxy0__1_carry__2_n_7\,
A(11) => \Lxy0__1_carry__1_n_4\,
A(10) => \Lxy0__1_carry__1_n_5\,
A(9) => \Lxy0__1_carry__1_n_6\,
A(8) => \Lxy0__1_carry__1_n_7\,
A(7) => \Lxy0__1_carry__0_n_4\,
A(6) => \Lxy0__1_carry__0_n_5\,
A(5) => \Lxy0__1_carry__0_n_6\,
A(4) => \Lxy0__1_carry__0_n_7\,
A(3) => \Lxy0__1_carry_n_4\,
A(2) => \Lxy0__1_carry_n_5\,
A(1) => \Lxy0__1_carry_n_6\,
A(0) => \Lxy0__1_carry_n_7\,
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0011",
B(17) => \Lxy0__1_carry__2_n_4\,
B(16) => \Lxy0__1_carry__2_n_4\,
B(15) => \Lxy0__1_carry__2_n_4\,
B(14) => \Lxy0__1_carry__2_n_5\,
B(13) => \Lxy0__1_carry__2_n_6\,
B(12) => \Lxy0__1_carry__2_n_7\,
B(11) => \Lxy0__1_carry__1_n_4\,
B(10) => \Lxy0__1_carry__1_n_5\,
B(9) => \Lxy0__1_carry__1_n_6\,
B(8) => \Lxy0__1_carry__1_n_7\,
B(7) => \Lxy0__1_carry__0_n_4\,
B(6) => \Lxy0__1_carry__0_n_5\,
B(5) => \Lxy0__1_carry__0_n_6\,
B(4) => \Lxy0__1_carry__0_n_7\,
B(3) => \Lxy0__1_carry_n_4\,
B(2) => \Lxy0__1_carry_n_5\,
B(1) => \Lxy0__1_carry_n_6\,
B(0) => \Lxy0__1_carry_n_7\,
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => y3,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => y3,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => y2,
CEP => y9,
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0010101",
OVERFLOW => NLW_det_reg_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_det_reg_P_UNCONNECTED(47 downto 32),
P(31) => det_reg_n_74,
P(30) => det_reg_n_75,
P(29) => det_reg_n_76,
P(28) => det_reg_n_77,
P(27) => det_reg_n_78,
P(26) => det_reg_n_79,
P(25) => det_reg_n_80,
P(24) => det_reg_n_81,
P(23) => det_reg_n_82,
P(22) => det_reg_n_83,
P(21) => det_reg_n_84,
P(20) => det_reg_n_85,
P(19) => det_reg_n_86,
P(18) => det_reg_n_87,
P(17) => det_reg_n_88,
P(16) => det_reg_n_89,
P(15) => det_reg_n_90,
P(14) => det_reg_n_91,
P(13) => det_reg_n_92,
P(12) => det_reg_n_93,
P(11) => det_reg_n_94,
P(10) => det_reg_n_95,
P(9) => det_reg_n_96,
P(8) => det_reg_n_97,
P(7) => det_reg_n_98,
P(6) => det_reg_n_99,
P(5) => det_reg_n_100,
P(4) => det_reg_n_101,
P(3) => det_reg_n_102,
P(2) => det_reg_n_103,
P(1) => det_reg_n_104,
P(0) => det_reg_n_105,
PATTERNBDETECT => NLW_det_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47) => det_0_reg_n_106,
PCIN(46) => det_0_reg_n_107,
PCIN(45) => det_0_reg_n_108,
PCIN(44) => det_0_reg_n_109,
PCIN(43) => det_0_reg_n_110,
PCIN(42) => det_0_reg_n_111,
PCIN(41) => det_0_reg_n_112,
PCIN(40) => det_0_reg_n_113,
PCIN(39) => det_0_reg_n_114,
PCIN(38) => det_0_reg_n_115,
PCIN(37) => det_0_reg_n_116,
PCIN(36) => det_0_reg_n_117,
PCIN(35) => det_0_reg_n_118,
PCIN(34) => det_0_reg_n_119,
PCIN(33) => det_0_reg_n_120,
PCIN(32) => det_0_reg_n_121,
PCIN(31) => det_0_reg_n_122,
PCIN(30) => det_0_reg_n_123,
PCIN(29) => det_0_reg_n_124,
PCIN(28) => det_0_reg_n_125,
PCIN(27) => det_0_reg_n_126,
PCIN(26) => det_0_reg_n_127,
PCIN(25) => det_0_reg_n_128,
PCIN(24) => det_0_reg_n_129,
PCIN(23) => det_0_reg_n_130,
PCIN(22) => det_0_reg_n_131,
PCIN(21) => det_0_reg_n_132,
PCIN(20) => det_0_reg_n_133,
PCIN(19) => det_0_reg_n_134,
PCIN(18) => det_0_reg_n_135,
PCIN(17) => det_0_reg_n_136,
PCIN(16) => det_0_reg_n_137,
PCIN(15) => det_0_reg_n_138,
PCIN(14) => det_0_reg_n_139,
PCIN(13) => det_0_reg_n_140,
PCIN(12) => det_0_reg_n_141,
PCIN(11) => det_0_reg_n_142,
PCIN(10) => det_0_reg_n_143,
PCIN(9) => det_0_reg_n_144,
PCIN(8) => det_0_reg_n_145,
PCIN(7) => det_0_reg_n_146,
PCIN(6) => det_0_reg_n_147,
PCIN(5) => det_0_reg_n_148,
PCIN(4) => det_0_reg_n_149,
PCIN(3) => det_0_reg_n_150,
PCIN(2) => det_0_reg_n_151,
PCIN(1) => det_0_reg_n_152,
PCIN(0) => det_0_reg_n_153,
PCOUT(47 downto 0) => NLW_det_reg_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_reg_UNDERFLOW_UNCONNECTED
);
det_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y2
);
det_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y9
);
\din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(0),
Q => \din_reg_n_0_[0]\,
R => '0'
);
\din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(10),
Q => \din_reg_n_0_[10]\,
R => '0'
);
\din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(11),
Q => \din_reg_n_0_[11]\,
R => '0'
);
\din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(12),
Q => \din_reg_n_0_[12]\,
R => '0'
);
\din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(13),
Q => \din_reg_n_0_[13]\,
R => '0'
);
\din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(14),
Q => \din_reg_n_0_[14]\,
R => '0'
);
\din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(15),
Q => \din_reg_n_0_[15]\,
R => '0'
);
\din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(1),
Q => \din_reg_n_0_[1]\,
R => '0'
);
\din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(2),
Q => \din_reg_n_0_[2]\,
R => '0'
);
\din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(3),
Q => \din_reg_n_0_[3]\,
R => '0'
);
\din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(4),
Q => \din_reg_n_0_[4]\,
R => '0'
);
\din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(5),
Q => \din_reg_n_0_[5]\,
R => '0'
);
\din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(6),
Q => \din_reg_n_0_[6]\,
R => '0'
);
\din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(7),
Q => \din_reg_n_0_[7]\,
R => '0'
);
\din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(8),
Q => \din_reg_n_0_[8]\,
R => '0'
);
\din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(9),
Q => \din_reg_n_0_[9]\,
R => '0'
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y3
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(0),
Q => hessian_out(0),
R => '0'
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(10),
Q => hessian_out(10),
R => '0'
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(11),
Q => hessian_out(11),
R => '0'
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(12),
Q => hessian_out(12),
R => '0'
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(13),
Q => hessian_out(13),
R => '0'
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(14),
Q => hessian_out(14),
R => '0'
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(15),
Q => hessian_out(15),
R => '0'
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(16),
Q => hessian_out(16),
R => '0'
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(17),
Q => hessian_out(17),
R => '0'
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(18),
Q => hessian_out(18),
R => '0'
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(19),
Q => hessian_out(19),
R => '0'
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(1),
Q => hessian_out(1),
R => '0'
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(20),
Q => hessian_out(20),
R => '0'
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(21),
Q => hessian_out(21),
R => '0'
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(22),
Q => hessian_out(22),
R => '0'
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(23),
Q => hessian_out(23),
R => '0'
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(24),
Q => hessian_out(24),
R => '0'
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(25),
Q => hessian_out(25),
R => '0'
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(26),
Q => hessian_out(26),
R => '0'
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(27),
Q => hessian_out(27),
R => '0'
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(28),
Q => hessian_out(28),
R => '0'
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(29),
Q => hessian_out(29),
R => '0'
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(2),
Q => hessian_out(2),
R => '0'
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(30),
Q => hessian_out(30),
R => '0'
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(31),
Q => hessian_out(31),
R => '0'
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(3),
Q => hessian_out(3),
R => '0'
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(4),
Q => hessian_out(4),
R => '0'
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(5),
Q => hessian_out(5),
R => '0'
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(6),
Q => hessian_out(6),
R => '0'
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(7),
Q => hessian_out(7),
R => '0'
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(8),
Q => hessian_out(8),
R => '0'
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(9),
Q => hessian_out(9),
R => '0'
);
\i__carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(3),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[7]\,
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[6]\,
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[5]\,
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[4]\,
O => \i__carry__0_i_5_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[9]\,
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[8]\,
O => \i__carry__1_i_2_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[3]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55599555"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"5595"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_4_n_0\
);
\last_value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[0]\,
Q => last_value(0),
R => '0'
);
\last_value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[1]\,
Q => last_value(1),
R => '0'
);
\last_value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[2]\,
Q => last_value(2),
R => '0'
);
\last_value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[3]\,
Q => last_value(3),
R => '0'
);
\last_value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[4]\,
Q => last_value(4),
R => '0'
);
\last_value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[5]\,
Q => last_value(5),
R => '0'
);
\last_value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[6]\,
Q => last_value(6),
R => '0'
);
\last_value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[7]\,
Q => last_value(7),
R => '0'
);
\left[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
O => left
);
\left[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[6]\,
I3 => \left[15]_i_3_n_0\,
O => \left[15]_i_2_n_0\
);
\left[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \left[15]_i_3_n_0\
);
\left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(0),
Q => \left_reg_n_0_[0]\,
R => left
);
\left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(10),
Q => \left_reg_n_0_[10]\,
R => left
);
\left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(11),
Q => \left_reg_n_0_[11]\,
R => left
);
\left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(12),
Q => \left_reg_n_0_[12]\,
R => left
);
\left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(13),
Q => \left_reg_n_0_[13]\,
R => left
);
\left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(14),
Q => \left_reg_n_0_[14]\,
R => left
);
\left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(15),
Q => \left_reg_n_0_[15]\,
R => left
);
\left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(1),
Q => \left_reg_n_0_[1]\,
R => left
);
\left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(2),
Q => \left_reg_n_0_[2]\,
R => left
);
\left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(3),
Q => \left_reg_n_0_[3]\,
R => left
);
\left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(4),
Q => \left_reg_n_0_[4]\,
R => left
);
\left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(5),
Q => \left_reg_n_0_[5]\,
R => left
);
\left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(6),
Q => \left_reg_n_0_[6]\,
R => left
);
\left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(7),
Q => \left_reg_n_0_[7]\,
R => left
);
\left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(8),
Q => \left_reg_n_0_[8]\,
R => left
);
\left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(9),
Q => \left_reg_n_0_[9]\,
R => left
);
\plusOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \plusOp_inferred__0/i__carry_n_0\,
CO(2) => \plusOp_inferred__0/i__carry_n_1\,
CO(1) => \plusOp_inferred__0/i__carry_n_2\,
CO(0) => \plusOp_inferred__0/i__carry_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[3]\,
DI(2) => \x_reg_n_0_[2]\,
DI(1) => \x_reg_n_0_[1]\,
DI(0) => \x_reg_n_0_[0]\,
O(3) => \plusOp_inferred__0/i__carry_n_4\,
O(2) => \plusOp_inferred__0/i__carry_n_5\,
O(1) => \plusOp_inferred__0/i__carry_n_6\,
O(0) => \plusOp_inferred__0/i__carry_n_7\,
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\plusOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry_n_0\,
CO(3) => \plusOp_inferred__0/i__carry__0_n_0\,
CO(2) => \plusOp_inferred__0/i__carry__0_n_1\,
CO(1) => \plusOp_inferred__0/i__carry__0_n_2\,
CO(0) => \plusOp_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[6]\,
DI(2) => \x_reg_n_0_[5]\,
DI(1) => \x_reg_n_0_[4]\,
DI(0) => \i__carry__0_i_1_n_0\,
O(3) => \plusOp_inferred__0/i__carry__0_n_4\,
O(2) => \plusOp_inferred__0/i__carry__0_n_5\,
O(1) => \plusOp_inferred__0/i__carry__0_n_6\,
O(0) => \plusOp_inferred__0/i__carry__0_n_7\,
S(3) => \i__carry__0_i_2_n_0\,
S(2) => \i__carry__0_i_3_n_0\,
S(1) => \i__carry__0_i_4_n_0\,
S(0) => \i__carry__0_i_5_n_0\
);
\plusOp_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_reg_n_0_[7]\,
O(3 downto 2) => \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_inferred__0/i__carry__1_n_6\,
O(0) => \plusOp_inferred__0/i__carry__1_n_7\,
S(3 downto 2) => B"00",
S(1) => \i__carry__1_i_1_n_0\,
S(0) => \i__carry__1_i_2_n_0\
);
\top[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => x,
I1 => \top[15]_i_2_n_0\,
I2 => \y_actual_reg_n_0_[3]\,
I3 => \y_actual_reg_n_0_[0]\,
I4 => \y_actual_reg_n_0_[1]\,
I5 => \y_actual_reg_n_0_[2]\,
O => top
);
\top[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \y_actual_reg_n_0_[8]\,
I1 => \y_actual_reg_n_0_[9]\,
I2 => \y_actual_reg_n_0_[6]\,
I3 => \y_actual_reg_n_0_[7]\,
I4 => \y_actual_reg_n_0_[4]\,
I5 => \y_actual_reg_n_0_[5]\,
O => \top[15]_i_2_n_0\
);
\top_left_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(0),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_left_0[0]_i_1_n_0\
);
\top_left_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(10),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_left_0[10]_i_1_n_0\
);
\top_left_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(11),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_left_0[11]_i_1_n_0\
);
\top_left_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(12),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_left_0[12]_i_1_n_0\
);
\top_left_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(13),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_left_0[13]_i_1_n_0\
);
\top_left_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(14),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_left_0[14]_i_1_n_0\
);
\top_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000700010000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep_n_0\,
O => top_left_0
);
\top_left_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(15),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_left_0[15]_i_2_n_0\
);
\top_left_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(1),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_left_0[1]_i_1_n_0\
);
\top_left_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(2),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_left_0[2]_i_1_n_0\
);
\top_left_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_left_0[3]_i_1_n_0\
);
\top_left_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(4),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_left_0[4]_i_1_n_0\
);
\top_left_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(5),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_left_0[5]_i_1_n_0\
);
\top_left_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(6),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_left_0[6]_i_1_n_0\
);
\top_left_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(7),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_left_0[7]_i_1_n_0\
);
\top_left_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(8),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_left_0[8]_i_1_n_0\
);
\top_left_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(9),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_left_0[9]_i_1_n_0\
);
\top_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[0]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[0]\,
R => '0'
);
\top_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[10]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[10]\,
R => '0'
);
\top_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[11]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[11]\,
R => '0'
);
\top_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[12]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[12]\,
R => '0'
);
\top_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[13]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[13]\,
R => '0'
);
\top_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[14]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[14]\,
R => '0'
);
\top_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[15]_i_2_n_0\,
Q => \top_left_0_reg_n_0_[15]\,
R => '0'
);
\top_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[1]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[1]\,
R => '0'
);
\top_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[2]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[2]\,
R => '0'
);
\top_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[3]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[3]\,
R => '0'
);
\top_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[4]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[4]\,
R => '0'
);
\top_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[5]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[5]\,
R => '0'
);
\top_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[6]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[6]\,
R => '0'
);
\top_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[7]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[7]\,
R => '0'
);
\top_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[8]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[8]\,
R => '0'
);
\top_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[9]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[9]\,
R => '0'
);
\top_left_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[0]\,
O => \top_left_1[0]_i_1_n_0\
);
\top_left_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[10]\,
O => \top_left_1[10]_i_1_n_0\
);
\top_left_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[11]\,
O => \top_left_1[11]_i_1_n_0\
);
\top_left_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[12]\,
O => \top_left_1[12]_i_1_n_0\
);
\top_left_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[13]\,
O => \top_left_1[13]_i_1_n_0\
);
\top_left_1[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(14),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[14]\,
O => \top_left_1[14]_i_1_n_0\
);
\top_left_1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
O => bottom_right_1
);
\top_left_1[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(15),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[15]\,
O => \top_left_1[15]_i_2_n_0\
);
\top_left_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[1]\,
O => \top_left_1[1]_i_1_n_0\
);
\top_left_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[2]\,
O => \top_left_1[2]_i_1_n_0\
);
\top_left_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[3]\,
O => \top_left_1[3]_i_1_n_0\
);
\top_left_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[4]\,
O => \top_left_1[4]_i_1_n_0\
);
\top_left_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[5]\,
O => \top_left_1[5]_i_1_n_0\
);
\top_left_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[6]\,
O => \top_left_1[6]_i_1_n_0\
);
\top_left_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[7]\,
O => \top_left_1[7]_i_1_n_0\
);
\top_left_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[8]\,
O => \top_left_1[8]_i_1_n_0\
);
\top_left_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[9]\,
O => \top_left_1[9]_i_1_n_0\
);
\top_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[0]_i_1_n_0\,
Q => top_left_1(0),
R => '0'
);
\top_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[10]_i_1_n_0\,
Q => top_left_1(10),
R => '0'
);
\top_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[11]_i_1_n_0\,
Q => top_left_1(11),
R => '0'
);
\top_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[12]_i_1_n_0\,
Q => top_left_1(12),
R => '0'
);
\top_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[13]_i_1_n_0\,
Q => top_left_1(13),
R => '0'
);
\top_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[14]_i_1_n_0\,
Q => top_left_1(14),
R => '0'
);
\top_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[15]_i_2_n_0\,
Q => top_left_1(15),
R => '0'
);
\top_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[1]_i_1_n_0\,
Q => top_left_1(1),
R => '0'
);
\top_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[2]_i_1_n_0\,
Q => top_left_1(2),
R => '0'
);
\top_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[3]_i_1_n_0\,
Q => top_left_1(3),
R => '0'
);
\top_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[4]_i_1_n_0\,
Q => top_left_1(4),
R => '0'
);
\top_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[5]_i_1_n_0\,
Q => top_left_1(5),
R => '0'
);
\top_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[6]_i_1_n_0\,
Q => top_left_1(6),
R => '0'
);
\top_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[7]_i_1_n_0\,
Q => top_left_1(7),
R => '0'
);
\top_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[8]_i_1_n_0\,
Q => top_left_1(8),
R => '0'
);
\top_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[9]_i_1_n_0\,
Q => top_left_1(9),
R => '0'
);
\top_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(0),
Q => \top_reg_n_0_[0]\,
R => top
);
\top_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(10),
Q => \top_reg_n_0_[10]\,
R => top
);
\top_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(11),
Q => \top_reg_n_0_[11]\,
R => top
);
\top_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(12),
Q => \top_reg_n_0_[12]\,
R => top
);
\top_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(13),
Q => \top_reg_n_0_[13]\,
R => top
);
\top_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(14),
Q => \top_reg_n_0_[14]\,
R => top
);
\top_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(15),
Q => \top_reg_n_0_[15]\,
R => top
);
\top_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(1),
Q => \top_reg_n_0_[1]\,
R => top
);
\top_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(2),
Q => \top_reg_n_0_[2]\,
R => top
);
\top_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(3),
Q => \top_reg_n_0_[3]\,
R => top
);
\top_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(4),
Q => \top_reg_n_0_[4]\,
R => top
);
\top_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(5),
Q => \top_reg_n_0_[5]\,
R => top
);
\top_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(6),
Q => \top_reg_n_0_[6]\,
R => top
);
\top_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(7),
Q => \top_reg_n_0_[7]\,
R => top
);
\top_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(8),
Q => \top_reg_n_0_[8]\,
R => top
);
\top_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(9),
Q => \top_reg_n_0_[9]\,
R => top
);
\top_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_right_0[0]_i_1_n_0\
);
\top_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(10),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_right_0[10]_i_1_n_0\
);
\top_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(11),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_right_0[11]_i_1_n_0\
);
\top_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(12),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_right_0[12]_i_1_n_0\
);
\top_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(13),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_right_0[13]_i_1_n_0\
);
\top_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(14),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_right_0[14]_i_1_n_0\
);
\top_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0880000080080800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => top_right_0
);
\top_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(15),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_right_0[15]_i_2_n_0\
);
\top_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(1),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_right_0[1]_i_1_n_0\
);
\top_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(2),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_right_0[2]_i_1_n_0\
);
\top_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(3),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_right_0[3]_i_1_n_0\
);
\top_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(4),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_right_0[4]_i_1_n_0\
);
\top_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(5),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_right_0[5]_i_1_n_0\
);
\top_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(6),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_right_0[6]_i_1_n_0\
);
\top_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(7),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_right_0[7]_i_1_n_0\
);
\top_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(8),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_right_0[8]_i_1_n_0\
);
\top_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(9),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_right_0[9]_i_1_n_0\
);
\top_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[0]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[0]\,
R => '0'
);
\top_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[10]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[10]\,
R => '0'
);
\top_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[11]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[11]\,
R => '0'
);
\top_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[12]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[12]\,
R => '0'
);
\top_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[13]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[13]\,
R => '0'
);
\top_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[14]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[14]\,
R => '0'
);
\top_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[15]_i_2_n_0\,
Q => \top_right_0_reg_n_0_[15]\,
R => '0'
);
\top_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[1]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[1]\,
R => '0'
);
\top_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[2]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[2]\,
R => '0'
);
\top_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[3]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[3]\,
R => '0'
);
\top_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[4]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[4]\,
R => '0'
);
\top_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[5]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[5]\,
R => '0'
);
\top_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[6]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[6]\,
R => '0'
);
\top_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[7]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[7]\,
R => '0'
);
\top_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[8]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[8]\,
R => '0'
);
\top_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[9]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[9]\,
R => '0'
);
\top_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[0]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[0]\,
O => \top_right_1[0]_i_1_n_0\
);
\top_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[10]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[10]\,
O => \top_right_1[10]_i_1_n_0\
);
\top_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[11]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[11]\,
O => \top_right_1[11]_i_1_n_0\
);
\top_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[12]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[12]\,
O => \top_right_1[12]_i_1_n_0\
);
\top_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[13]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[13]\,
O => \top_right_1[13]_i_1_n_0\
);
\top_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[14]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[14]\,
O => \top_right_1[14]_i_1_n_0\
);
\top_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[15]\,
O => \top_right_1[15]_i_1_n_0\
);
\top_right_1[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => cycle(3),
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \top_right_1[15]_i_2_n_0\
);
\top_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[1]\,
O => \top_right_1[1]_i_1_n_0\
);
\top_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[2]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[2]\,
O => \top_right_1[2]_i_1_n_0\
);
\top_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[3]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[3]\,
O => \top_right_1[3]_i_1_n_0\
);
\top_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[4]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[4]\,
O => \top_right_1[4]_i_1_n_0\
);
\top_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[5]\,
O => \top_right_1[5]_i_1_n_0\
);
\top_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[6]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[6]\,
O => \top_right_1[6]_i_1_n_0\
);
\top_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[7]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[7]\,
O => \top_right_1[7]_i_1_n_0\
);
\top_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[8]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[8]\,
O => \top_right_1[8]_i_1_n_0\
);
\top_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[9]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[9]\,
O => \top_right_1[9]_i_1_n_0\
);
\top_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[0]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[0]\,
R => '0'
);
\top_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[10]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[10]\,
R => '0'
);
\top_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[11]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[11]\,
R => '0'
);
\top_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[12]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[12]\,
R => '0'
);
\top_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[13]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[13]\,
R => '0'
);
\top_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[14]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[14]\,
R => '0'
);
\top_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[15]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[15]\,
R => '0'
);
\top_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[1]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[1]\,
R => '0'
);
\top_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[2]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[2]\,
R => '0'
);
\top_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[3]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[3]\,
R => '0'
);
\top_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[4]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[4]\,
R => '0'
);
\top_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[5]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[5]\,
R => '0'
);
\top_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[6]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[6]\,
R => '0'
);
\top_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[7]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[7]\,
R => '0'
);
\top_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[8]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[8]\,
R => '0'
);
\top_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[9]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[9]\,
R => '0'
);
\value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(0),
Q => \value_reg_n_0_[0]\,
R => '0'
);
\value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(1),
Q => \value_reg_n_0_[1]\,
R => '0'
);
\value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(2),
Q => \value_reg_n_0_[2]\,
R => '0'
);
\value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(3),
Q => \value_reg_n_0_[3]\,
R => '0'
);
\value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(4),
Q => \value_reg_n_0_[4]\,
R => '0'
);
\value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(5),
Q => \value_reg_n_0_[5]\,
R => '0'
);
\value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(6),
Q => \value_reg_n_0_[6]\,
R => '0'
);
\value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(7),
Q => \value_reg_n_0_[7]\,
R => '0'
);
wen_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAAA2AAAA"
)
port map (
I0 => wen_reg_n_0,
I1 => wen_i_2_n_0,
I2 => \cycle_reg[0]_rep_n_0\,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => wen_i_1_n_0
);
wen_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => active,
I1 => rst,
O => wen_i_2_n_0
);
wen_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => wen_i_1_n_0,
Q => wen_reg_n_0,
R => '0'
);
\x0[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3B01FFC53A00FEC4"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => data2(0),
I4 => \x_reg_n_0_[0]\,
I5 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_2_n_0\
);
\x0[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(0),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_3_n_0\
);
\x0[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCEECCEEEEEECCFC"
)
port map (
I0 => data2(1),
I1 => \x0[1]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_6\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_2_n_0\
);
\x0[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(1),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_6\,
O => \x0[1]_i_3_n_0\
);
\x0[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"60600060"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[0]\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_4_n_0\
);
\x0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBBBFBBBFFBBBBBB"
)
port map (
I0 => \x0[2]_i_2_n_0\,
I1 => \x0[2]_i_3_n_0\,
I2 => data2(2),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry_n_5\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[2]_i_1_n_0\
);
\x0[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88AA22A0880022A0"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x0[2]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(2),
O => \x0[2]_i_2_n_0\
);
\x0[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FF3F3F377777777"
)
port map (
I0 => data2(2),
I1 => \x0[2]_i_5_n_0\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
I5 => \x1[6]_i_8_n_0\,
O => \x0[2]_i_3_n_0\
);
\x0[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[2]_i_4_n_0\
);
\x0[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
O => \x0[2]_i_5_n_0\
);
\x0[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x0[3]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[3]_i_3_n_0\,
I3 => cycle(3),
I4 => \x0[3]_i_4_n_0\,
O => \x0[3]_i_1_n_0\
);
\x0[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"660FFF00660FFFFF"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_5_n_0\,
I2 => data2(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_2_n_0\
);
\x0[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F9F090000900"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(3),
O => \x0[3]_i_3_n_0\
);
\x0[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(3),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_4_n_0\
);
\x0[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_5_n_0\
);
\x0[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_6_n_0\
);
\x0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[4]_i_2_n_0\,
I1 => \x0[4]_i_3_n_0\,
I2 => data2(4),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[4]_i_1_n_0\
);
\x0[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x0[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[4]_i_2_n_0\
);
\x0[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"008A0080A08AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data2(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x0[4]_i_5_n_0\,
O => \x0[4]_i_3_n_0\
);
\x0[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
O => \x0[4]_i_4_n_0\
);
\x0[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"95555555"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
O => \x0[4]_i_5_n_0\
);
\x0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[5]_i_2_n_0\,
I1 => \x0[5]_i_3_n_0\,
I2 => data2(5),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_6\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[5]_i_1_n_0\
);
\x0[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(5),
I1 => \x_reg_n_0_[5]\,
I2 => \x0[8]_i_7_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[5]_i_2_n_0\
);
\x0[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A80008AAAAAAAA"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \plusOp_inferred__0/i__carry__0_n_6\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => data2(5),
I5 => \x0[5]_i_4_n_0\,
O => \x0[5]_i_3_n_0\
);
\x0[5]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x0[5]_i_5_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(0),
O => \x0[5]_i_4_n_0\
);
\x0[5]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x0[5]_i_5_n_0\
);
\x0[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0507"
)
port map (
I0 => \x0[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(3),
I3 => \x0[6]_i_3_n_0\,
I4 => \x0[6]_i_4_n_0\,
O => \x0[6]_i_1_n_0\
);
\x0[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0707077077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data2(6),
I2 => \x_reg_n_0_[6]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x0[8]_i_5_n_0\,
O => \x0[6]_i_2_n_0\
);
\x0[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6600FF0F66FFFF0F"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x0[6]_i_5_n_0\,
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(6),
O => \x0[6]_i_3_n_0\
);
\x0[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C0C0C0C0C0C088"
)
port map (
I0 => data2(6),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[6]_i_4_n_0\
);
\x0[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x0[6]_i_5_n_0\
);
\x0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF020000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x0[7]_i_2_n_0\,
I3 => \x0[7]_i_3_n_0\,
I4 => \x0[7]_i_4_n_0\,
I5 => \x0[7]_i_5_n_0\,
O => \x0[7]_i_1_n_0\
);
\x0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[8]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \x_reg_n_0_[6]\,
O => \x0[7]_i_2_n_0\
);
\x0[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99F000FF99F00000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[7]_i_6_n_0\,
I2 => data2(7),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_3_n_0\
);
\x0[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
O => \x0[7]_i_4_n_0\
);
\x0[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x0[7]_i_7_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data2(7),
I4 => cycle(3),
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_5_n_0\
);
\x0[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x0[6]_i_5_n_0\,
I1 => \x_reg_n_0_[6]\,
O => \x0[7]_i_6_n_0\
);
\x0[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x_reg_n_0_[6]\,
I3 => \x_reg_n_0_[5]\,
I4 => \x0[8]_i_7_n_0\,
I5 => \x_reg_n_0_[7]\,
O => \x0[7]_i_7_n_0\
);
\x0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0FFF1F1F1"
)
port map (
I0 => \x0[8]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[8]_i_3_n_0\,
I3 => \x0[8]_i_4_n_0\,
I4 => \x0[8]_i_5_n_0\,
I5 => cycle(3),
O => \x0[8]_i_1_n_0\
);
\x0[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"990FFF00990FFFFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x0[8]_i_6_n_0\,
I2 => data2(8),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__1_n_7\,
O => \x0[8]_i_2_n_0\
);
\x0[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888B888B888B8C0"
)
port map (
I0 => \plusOp_inferred__0/i__carry__1_n_7\,
I1 => cycle(3),
I2 => data2(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[8]_i_3_n_0\
);
\x0[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x0[8]_i_4_n_0\
);
\x0[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x0[8]_i_5_n_0\
);
\x0[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x0[6]_i_5_n_0\,
O => \x0[8]_i_6_n_0\
);
\x0[8]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEEE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[0]\,
I4 => \x_reg_n_0_[3]\,
O => \x0[8]_i_7_n_0\
);
\x0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"77FE000000000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => active,
I5 => rst,
O => \x0[9]_i_1_n_0\
);
\x0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0101"
)
port map (
I0 => \x0[9]_i_3_n_0\,
I1 => cycle(3),
I2 => cycle(2),
I3 => \x0[9]_i_4_n_0\,
I4 => \x0[9]_i_5_n_0\,
O => \x0[9]_i_2_n_0\
);
\x0[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF03AFF3A003A0F3"
)
port map (
I0 => \x0[9]_i_6_n_0\,
I1 => \plusOp_inferred__0/i__carry__1_n_6\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => data2(9),
I5 => \x0[9]_i_7_n_0\,
O => \x0[9]_i_3_n_0\
);
\x0[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C0C0C0C0C44"
)
port map (
I0 => data2(9),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__1_n_6\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \x0[9]_i_4_n_0\
);
\x0[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5CCC0000"
)
port map (
I0 => \x0[9]_i_7_n_0\,
I1 => data2(9),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => \x0[9]_i_5_n_0\
);
\x0[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"55559555"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x_reg_n_0_[6]\,
I4 => \x0[6]_i_5_n_0\,
O => \x0[9]_i_6_n_0\
);
\x0[9]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x_reg_n_0_[6]\,
O => \x0[9]_i_7_n_0\
);
\x0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[0]_i_1_n_0\,
Q => data1(0),
R => '0'
);
\x0_reg[0]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[0]_i_2_n_0\,
I1 => \x0[0]_i_3_n_0\,
O => \x0_reg[0]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[1]_i_1_n_0\,
Q => data1(1),
R => '0'
);
\x0_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[1]_i_2_n_0\,
I1 => \x0[1]_i_3_n_0\,
O => \x0_reg[1]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[2]_i_1_n_0\,
Q => data1(2),
R => '0'
);
\x0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[3]_i_1_n_0\,
Q => data1(3),
R => '0'
);
\x0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[4]_i_1_n_0\,
Q => data1(4),
R => '0'
);
\x0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[5]_i_1_n_0\,
Q => data1(5),
R => '0'
);
\x0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[6]_i_1_n_0\,
Q => data1(6),
R => '0'
);
\x0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[7]_i_1_n_0\,
Q => data1(7),
R => '0'
);
\x0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[8]_i_1_n_0\,
Q => data1(8),
R => '0'
);
\x0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[9]_i_2_n_0\,
Q => data1(9),
R => '0'
);
\x1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF01FF4EFE00B100"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \x_reg_n_0_[0]\,
I4 => cycle(3),
I5 => data1(0),
O => \x1[0]_i_1_n_0\
);
\x1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFEFAAA955565010"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => data1(1),
I5 => \x_reg_n_0_[1]\,
O => \x1[1]_i_1_n_0\
);
\x1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEAEAEAEFEAE"
)
port map (
I0 => \x1[2]_i_2_n_0\,
I1 => \x1[2]_i_3_n_0\,
I2 => cycle(3),
I3 => \x_reg_n_0_[2]\,
I4 => \x1[5]_i_3_n_0\,
I5 => data1(2),
O => \x1[2]_i_1_n_0\
);
\x1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A2A288880202888"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x_reg_n_0_[2]\,
I2 => cycle(0),
I3 => \x_reg_n_0_[1]\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \x1[2]_i_2_n_0\
);
\x1[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3CAAAAAA00000000"
)
port map (
I0 => data1(2),
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[2]_i_3_n_0\
);
\x1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[3]_i_2_n_0\,
I1 => \x1[3]_i_3_n_0\,
I2 => data1(3),
I3 => cycle(3),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[3]_i_1_n_0\
);
\x1[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0770707077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data1(3),
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x0[8]_i_5_n_0\,
O => \x1[3]_i_2_n_0\
);
\x1[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[3]_i_4_n_0\,
O => \x1[3]_i_3_n_0\
);
\x1[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[2]\,
O => \x1[3]_i_4_n_0\
);
\x1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[4]_i_2_n_0\,
I1 => \x1[4]_i_3_n_0\,
I2 => data1(4),
I3 => cycle(3),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[4]_i_1_n_0\
);
\x1[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data1(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x1[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[4]_i_2_n_0\
);
\x1[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[4]_i_5_n_0\,
O => \x1[4]_i_3_n_0\
);
\x1[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_4_n_0\
);
\x1[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_5_n_0\
);
\x1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => \x1[5]_i_2_n_0\,
I1 => data1(5),
I2 => \x1[5]_i_3_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => cycle(3),
O => \x1[5]_i_1_n_0\
);
\x1[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDFDCDCDFDFDFDCD"
)
port map (
I0 => \x1[5]_i_4_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[6]_i_8_n_0\,
I4 => data1(5),
I5 => \x1[5]_i_5_n_0\,
O => \x1[5]_i_2_n_0\
);
\x1[5]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
O => \x1[5]_i_3_n_0\
);
\x1[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0530FA3FF5300A3F"
)
port map (
I0 => \x1[6]_i_7_n_0\,
I1 => data1(5),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[5]\,
I5 => \left[15]_i_3_n_0\,
O => \x1[5]_i_4_n_0\
);
\x1[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555666"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[4]\,
O => \x1[5]_i_5_n_0\
);
\x1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[6]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[6]_i_4_n_0\,
O => \x1[6]_i_1_n_0\
);
\x1[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05050CFC05F5F"
)
port map (
I0 => data1(6),
I1 => \x1[6]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[6]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[6]\,
O => \x1[6]_i_2_n_0\
);
\x1[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A900FF00A9000000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x1[6]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \x1[6]_i_8_n_0\,
I5 => data1(6),
O => \x1[6]_i_3_n_0\
);
\x1[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(6),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[6]\,
O => \x1[6]_i_4_n_0\
);
\x1[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_5_n_0\
);
\x1[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555666"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_6_n_0\
);
\x1[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x1[6]_i_7_n_0\
);
\x1[6]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
O => \x1[6]_i_8_n_0\
);
\x1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[7]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[7]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[7]_i_4_n_0\,
O => \x1[7]_i_1_n_0\
);
\x1[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"303F5050CFC05F5F"
)
port map (
I0 => data1(7),
I1 => \x1[7]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[9]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[7]\,
O => \x1[7]_i_2_n_0\
);
\x1[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F0F090000000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x1[9]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \x1[7]_i_3_n_0\
);
\x1[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(7),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[7]_i_4_n_0\
);
\x1[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[4]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[7]_i_5_n_0\
);
\x1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => \x1[8]_i_2_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[8]_i_3_n_0\,
O => \x1[8]_i_1_n_0\
);
\x1[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA300A3F0A30FA3F"
)
port map (
I0 => \x1[8]_i_4_n_0\,
I1 => data1(8),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[8]\,
I5 => \left[15]_i_2_n_0\,
O => \x1[8]_i_2_n_0\
);
\x1[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[8]_i_5_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(8),
I4 => cycle(3),
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_3_n_0\
);
\x1[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555556"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x1[6]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[8]_i_4_n_0\
);
\x1[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000002"
)
port map (
I0 => \x1[8]_i_6_n_0\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[6]_i_7_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_5_n_0\
);
\x1[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x1[8]_i_6_n_0\
);
\x1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088008880880880"
)
port map (
I0 => active,
I1 => rst,
I2 => cycle(0),
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => x1
);
\x1[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000047"
)
port map (
I0 => \x1[9]_i_3_n_0\,
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x1[9]_i_4_n_0\,
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \x1[9]_i_5_n_0\,
O => \x1[9]_i_2_n_0\
);
\x1[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C335555"
)
port map (
I0 => data1(9),
I1 => \x_reg_n_0_[9]\,
I2 => \x_reg_n_0_[8]\,
I3 => \left[15]_i_2_n_0\,
I4 => cycle(0),
O => \x1[9]_i_3_n_0\
);
\x1[9]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0100FEFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[9]_i_6_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[9]\,
O => \x1[9]_i_4_n_0\
);
\x1[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[9]_i_8_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(9),
I4 => cycle(3),
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_5_n_0\
);
\x1[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFE"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x_reg_n_0_[4]\,
O => \x1[9]_i_6_n_0\
);
\x1[9]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \x1[9]_i_7_n_0\
);
\x1[9]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x1[9]_i_6_n_0\,
I3 => \x_reg_n_0_[7]\,
I4 => \x_reg_n_0_[8]\,
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_8_n_0\
);
\x1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[0]_i_1_n_0\,
Q => data2(0),
R => '0'
);
\x1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[1]_i_1_n_0\,
Q => data2(1),
R => '0'
);
\x1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[2]_i_1_n_0\,
Q => data2(2),
R => '0'
);
\x1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[3]_i_1_n_0\,
Q => data2(3),
R => '0'
);
\x1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[4]_i_1_n_0\,
Q => data2(4),
R => '0'
);
\x1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[5]_i_1_n_0\,
Q => data2(5),
R => '0'
);
\x1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[6]_i_1_n_0\,
Q => data2(6),
R => '0'
);
\x1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[7]_i_1_n_0\,
Q => data2(7),
R => '0'
);
\x1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[8]_i_1_n_0\,
Q => data2(8),
R => '0'
);
\x1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[9]_i_2_n_0\,
Q => data2(9),
R => '0'
);
\x[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => x
);
\x_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(0),
Q => \x_reg_n_0_[0]\,
R => '0'
);
\x_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(1),
Q => \x_reg_n_0_[1]\,
R => '0'
);
\x_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(2),
Q => \x_reg_n_0_[2]\,
R => '0'
);
\x_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(3),
Q => \x_reg_n_0_[3]\,
R => '0'
);
\x_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(4),
Q => \x_reg_n_0_[4]\,
R => '0'
);
\x_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(5),
Q => \x_reg_n_0_[5]\,
R => '0'
);
\x_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(6),
Q => \x_reg_n_0_[6]\,
R => '0'
);
\x_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(7),
Q => \x_reg_n_0_[7]\,
R => '0'
);
\x_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(8),
Q => \x_reg_n_0_[8]\,
R => '0'
);
\x_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(9),
Q => \x_reg_n_0_[9]\,
R => '0'
);
\y1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y1[2]_i_1_n_0\
);
\y1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
I3 => \y_actual_reg_n_0_[3]\,
O => \y1[3]_i_1_n_0\
);
\y1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[0]_i_1_n_0\,
Q => \y1_reg_n_0_[0]\,
R => '0'
);
\y1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[1]_i_1_n_0\,
Q => \y1_reg_n_0_[1]\,
R => '0'
);
\y1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[2]_i_1_n_0\,
Q => \y1_reg_n_0_[2]\,
R => '0'
);
\y1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[3]_i_1_n_0\,
Q => \y1_reg_n_0_[3]\,
R => '0'
);
\y2[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
O => \y2[1]_i_1_n_0\
);
\y2[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y2[2]_i_1_n_0\
);
\y2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y2[3]_i_1_n_0\
);
\y2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y_actual_reg_n_0_[0]\,
Q => \y2_reg_n_0_[0]\,
R => '0'
);
\y2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[1]_i_1_n_0\,
Q => \y2_reg_n_0_[1]\,
R => '0'
);
\y2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[2]_i_1_n_0\,
Q => \y2_reg_n_0_[2]\,
R => '0'
);
\y2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[3]_i_1_n_0\,
Q => \y2_reg_n_0_[3]\,
R => '0'
);
\y3[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y3[1]_i_1_n_0\
);
\y3[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"87"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y3[2]_i_1_n_0\
);
\y3[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y3[3]_i_1_n_0\
);
\y3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y5[0]_i_1_n_0\,
Q => \y3_reg_n_0_[0]\,
R => '0'
);
\y3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[1]_i_1_n_0\,
Q => \y3_reg_n_0_[1]\,
R => '0'
);
\y3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[2]_i_1_n_0\,
Q => \y3_reg_n_0_[2]\,
R => '0'
);
\y3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[3]_i_1_n_0\,
Q => \y3_reg_n_0_[3]\,
R => '0'
);
\y4[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
O => \y4[2]_i_1_n_0\
);
\y4[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y4[3]_i_1_n_0\
);
\y4_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[0]\,
Q => data2(10),
R => '0'
);
\y4_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[1]\,
Q => data2(11),
R => '0'
);
\y4_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[2]_i_1_n_0\,
Q => data2(12),
R => '0'
);
\y4_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[3]_i_1_n_0\,
Q => data2(13),
R => '0'
);
\y5[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
O => \y5[0]_i_1_n_0\
);
\y5[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[0]\,
O => \y5[1]_i_1_n_0\
);
\y5[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y5[2]_i_1_n_0\
);
\y5[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A955"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y5[3]_i_1_n_0\
);
\y5_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[0]_i_1_n_0\,
Q => data1(10),
R => '0'
);
\y5_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[1]_i_1_n_0\,
Q => data1(11),
R => '0'
);
\y5_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[2]_i_1_n_0\,
Q => data1(12),
R => '0'
);
\y5_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[3]_i_1_n_0\,
Q => data1(13),
R => '0'
);
\y6[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y6[2]_i_1_n_0\
);
\y6[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y6[3]_i_1_n_0\
);
\y6_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y_actual_reg_n_0_[0]\,
Q => \y6_reg_n_0_[0]\,
R => '0'
);
\y6_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y2[1]_i_1_n_0\,
Q => \y6_reg_n_0_[1]\,
R => '0'
);
\y6_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[2]_i_1_n_0\,
Q => \y6_reg_n_0_[2]\,
R => '0'
);
\y6_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[3]_i_1_n_0\,
Q => \y6_reg_n_0_[3]\,
R => '0'
);
\y7[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y7[2]_i_1_n_0\
);
\y7[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y7[3]_i_1_n_0\
);
\y7_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y5[0]_i_1_n_0\,
Q => y7(0),
R => '0'
);
\y7_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y3[1]_i_1_n_0\,
Q => y7(1),
R => '0'
);
\y7_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[2]_i_1_n_0\,
Q => y7(2),
R => '0'
);
\y7_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[3]_i_1_n_0\,
Q => y7(3),
R => '0'
);
\y8[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
O => \y8[3]_i_1_n_0\
);
\y8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[0]\,
Q => y8(0),
R => '0'
);
\y8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[1]\,
Q => y8(1),
R => '0'
);
\y8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[2]\,
Q => y8(2),
R => '0'
);
\y8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y8[3]_i_1_n_0\,
Q => y8(3),
R => '0'
);
\y9[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y9[3]_i_1_n_0\
);
\y9_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[0]_i_1_n_0\,
Q => data5(10),
R => '0'
);
\y9_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[1]_i_1_n_0\,
Q => data5(11),
R => '0'
);
\y9_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y1[2]_i_1_n_0\,
Q => data5(12),
R => '0'
);
\y9_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y9[3]_i_1_n_0\,
Q => data5(13),
R => '0'
);
\y_actual_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(0),
Q => \y_actual_reg_n_0_[0]\,
R => '0'
);
\y_actual_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(1),
Q => \y_actual_reg_n_0_[1]\,
R => '0'
);
\y_actual_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(2),
Q => \y_actual_reg_n_0_[2]\,
R => '0'
);
\y_actual_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(3),
Q => \y_actual_reg_n_0_[3]\,
R => '0'
);
\y_actual_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(4),
Q => \y_actual_reg_n_0_[4]\,
R => '0'
);
\y_actual_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(5),
Q => \y_actual_reg_n_0_[5]\,
R => '0'
);
\y_actual_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(6),
Q => \y_actual_reg_n_0_[6]\,
R => '0'
);
\y_actual_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(7),
Q => \y_actual_reg_n_0_[7]\,
R => '0'
);
\y_actual_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(8),
Q => \y_actual_reg_n_0_[8]\,
R => '0'
);
\y_actual_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(9),
Q => \y_actual_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_hessian_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_0_0 : entity is "system_vga_hessian_0_0,vga_hessian,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_0_0 : entity is "vga_hessian,Vivado 2016.4";
end system_vga_hessian_0_0;
architecture STRUCTURE of system_vga_hessian_0_0 is
begin
U0: entity work.system_vga_hessian_0_0_vga_hessian
port map (
active => active,
clk_x16 => clk_x16,
g_in(7 downto 0) => g_in(7 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
rst => rst,
x_addr(9 downto 0) => x_addr(9 downto 0),
y_addr(9 downto 0) => y_addr(9 downto 0)
);
end STRUCTURE;
| mit | 2c384ad3b4ed2e0b921c35a4a30a29f9 | 0.546372 | 2.727797 | false | false | false | false |
loa-org/loa-hdl | modules/us_rx/tb/us_rx_module_tb.vhd | 2 | 1,797 | -------------------------------------------------------------------------------
-- Title : Testbench for design "us_rx_module"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity us_rx_module_tb is
end entity us_rx_module_tb;
-------------------------------------------------------------------------------
architecture behavourial of us_rx_module_tb is
-- component generics
constant BASE_ADDRESS : natural := 16#0100#;
-- component ports
signal bus_o_p : busdevice_out_type;
signal bus_i_p : busdevice_in_type;
signal timestamp : timestamp_type;
-- clock
signal clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT : entity work.us_rx_module
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
bus_o_p => bus_o_p,
bus_i_p => bus_i_p,
clk_sample_en_i_p => '0',
timestamp_i_p => timestamp,
clk => clk);
-- clock generation 50 MHz
clk <= not clk after 20 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | b2019e98f5ea47da61167f1a24388e16 | 0.423484 | 5.047753 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ad7266/tb/adc_ad7266_module_tb.vhd | 2 | 8,595 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc_ad7266_single_ended_module"
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Standard: VHDL '87
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.adc_ad7266_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity adc_ad7266_module_tb is
end adc_ad7266_module_tb;
architecture tb of adc_ad7266_module_tb is
component adc_ad7266_single_ended_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive);
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
adc_values_o : out adc_ad7266_values_type(CHANNELS - 1 downto 0);
clk : in std_logic);
end component;
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
constant CHANNELS : positive := 12;
-- component ports
signal adc_out : adc_ad7266_spi_out_type;
signal adc_in : adc_ad7266_spi_in_type;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal adc_values_o : adc_ad7266_values_type(CHANNELS - 1 downto 0);
signal clk : std_logic := '1';
-- adc_stimulus parametres (vectors are mirrored)
signal bitstream_a : std_logic_vector(11 downto 0) := "111000111001"; -- result 0x9C7
signal bitstream_b : std_logic_vector(11 downto 0) := "010111100110"; -- result 0x67A
signal bitcounter : integer range 0 to 16;
begin -- tb
-- component instantiation
DUT: adc_ad7266_single_ended_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
CHANNELS => CHANNELS)
port map (
adc_out_p => adc_out,
adc_in_p => adc_in,
bus_o => bus_o,
bus_i => bus_i,
adc_values_o => open,
clk => clk);
-- clock generation
clk <= not clk after 20 ns;
-- waveform generation
bus_stimulus_proc: process
begin
-- insert signal assignments here
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
bus_i.addr(0) <= '0';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- do the same reads, but the DUT shouldn't react
bus_i.addr(0) <= '0';
bus_i.addr(8) <= '0'; -- another address
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait for 10000 NS;
end process bus_stimulus_proc;
-----------------------------------------------------------------------------
-- ADC side stimulus
-----------------------------------------------------------------------------
-- process
-- begin
-- -- adc_in.d_a <= 'Z';
-- -- adc_in.d_b <= 'Z';
-- wait until adc_out.cs_n = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '0';
-- -- wait until sck_p = '1';
-- -- wait until sck_p = '0';
-- -- wait until sck_p = '0';
-- -- wait until sck_p = '0';
-- -- wait until sck_p = '0';
-- -- wait until sck_p = '0';
-- -- wait until sck_p = '0';
-- -- leading zero of AD7266
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '0';
-- -- actual MSB of conversion
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '0';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '0';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '0';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '1';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '1';
-- adc_in.d_b <= '0';
----trailing TWO zeros
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '0';
-- wait until adc_out.sck = '0';
-- adc_in.d_a <= '0';
-- adc_in.d_b <= '0';
-- ------------------------------------------------------------------------------
-- wait until adc_out.sck = '0';
-- -- adc_in.d_a <= 'Z';
-- -- adc_in.d_b <= 'Z';
-- end process;
-------------------------------------------------------------------------------
-- ADC stimulus
------------------------------------------------------------------------------
ADC_input: process
begin
wait for 14900 ns;
bitstream_a <= "111000111010"; -- result
bitstream_b <= "010111100111"; -- result
end process ADC_input;
ADC_stimulus: process(adc_out.sck, adc_out.cs_n)
-- bitstream with second leading and two trailing zeros
-- DUT should set cs_n HIGH bevor trailing zeros are read in
variable v_bitstream_a : std_logic_vector(14 downto 0) := '0' & bitstream_a(11 downto 0) & "00";
variable v_bitstream_b : std_logic_vector(14 downto 0) := '0' & bitstream_b(11 downto 0) & "00";
variable vbitcounter : integer range 0 to 16 := bitcounter;
begin
v_bitstream_a := '0' & bitstream_a(11 downto 0) & "00";
v_bitstream_b := '0' & bitstream_b(11 downto 0) & "00";
if falling_edge(adc_out.cs_n) then
-- first leading zero
adc_in.d_a <= '0';
adc_in.d_b <= '0';
-- reset bitcounter
vbitcounter := 0;
elsif adc_out.cs_n = '0' then
if vbitcounter < 15 then
if falling_edge(adc_out.sck) then
vbitcounter := vbitcounter + 1;
adc_in.d_a <= v_bitstream_a(vbitcounter);
adc_in.d_b <= v_bitstream_b(vbitcounter);
end if;
end if;
else
adc_in.d_a <= 'Z';
adc_in.d_b <= 'Z';
end if;
bitcounter <= vbitcounter;
end process ADC_stimulus;
end tb;
-------------------------------------------------------------------------------
configuration adc_ad7266_module_tb_cfg of adc_ad7266_module_tb is
for tb
end for;
end adc_ad7266_module_tb_cfg;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
| bsd-3-clause | e926cf70b98307c5cd4837fc87f0af63 | 0.426643 | 3.310863 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_switches_s1_translator.vhd | 1 | 14,258 | -- niosii_system_switches_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_switches_s1_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_write : out std_logic;
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writedata : out std_logic_vector(31 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_switches_s1_translator;
architecture rtl of niosii_system_switches_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
switches_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_readdata => av_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_switches_s1_translator
| apache-2.0 | c2a5e31ed96296ee1eff698f11cd3c88 | 0.435405 | 4.293285 | false | false | false | false |
loa-org/loa-hdl | modules/ir_canon/tb/ir_canon_tb.vhd | 1 | 2,249 | -------------------------------------------------------------------------------
-- Title : Testbench for design "ir_canon"
-- Project :
-------------------------------------------------------------------------------
-- File : ir_canon_tb.vhd
-- Author : user <calle@alukiste>
-- Company :
-- Created : 2014-12-16
-- Last update: 2014-12-16
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-12-16 1.0 calle Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ir_canon_pkg.all;
-------------------------------------------------------------------------------
entity ir_canon_tb is
end ir_canon_tb;
-------------------------------------------------------------------------------
architecture tb of ir_canon_tb is
component ir_canon
port (
ir_canon_in : in ir_canon_in_type;
ir_canon_out : out ir_canon_out_type;
clk : in std_logic);
end component;
-- component ports
signal ir_canon_in : ir_canon_in_type;
signal ir_canon_out : ir_canon_out_type;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : ir_canon
port map (
ir_canon_in => ir_canon_in,
ir_canon_out => ir_canon_out,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
ir_canon_in.trigger <= '0';
wait until Clk = '1';
wait until Clk = '1';
ir_canon_in.trigger <= '1';
wait until Clk = '1';
ir_canon_in.trigger <= '0';
wait for 15 ms;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration ir_canon_tb_tb_cfg of ir_canon_tb is
for tb
end for;
end ir_canon_tb_tb_cfg;
| bsd-3-clause | b4808c9c39704d8e9c01d4bac8697785 | 0.408626 | 4.141805 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/sqrt_sim_netlist.vhdl | 1 | 678,677 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 11:55:10 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/general_ip/svd_2x2/svd_2x2.runs/sqrt_synth_1/sqrt_sim_netlist.vhdl
-- Design : sqrt
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sqrt_cordic_v6_0_11 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_cartesian_tvalid : in STD_LOGIC;
s_axis_cartesian_tready : out STD_LOGIC;
s_axis_cartesian_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_cartesian_tlast : in STD_LOGIC;
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tready : in STD_LOGIC;
m_axis_dout_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_dout_tlast : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute C_ARCHITECTURE : integer;
attribute C_ARCHITECTURE of sqrt_cordic_v6_0_11 : entity is 2;
attribute C_COARSE_ROTATE : integer;
attribute C_COARSE_ROTATE of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_CORDIC_FUNCTION : integer;
attribute C_CORDIC_FUNCTION of sqrt_cordic_v6_0_11 : entity is 6;
attribute C_DATA_FORMAT : integer;
attribute C_DATA_FORMAT of sqrt_cordic_v6_0_11 : entity is 1;
attribute C_HAS_ACLK : integer;
attribute C_HAS_ACLK of sqrt_cordic_v6_0_11 : entity is 1;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_HAS_S_AXIS_CARTESIAN : integer;
attribute C_HAS_S_AXIS_CARTESIAN of sqrt_cordic_v6_0_11 : entity is 1;
attribute C_HAS_S_AXIS_CARTESIAN_TLAST : integer;
attribute C_HAS_S_AXIS_CARTESIAN_TLAST of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_HAS_S_AXIS_CARTESIAN_TUSER : integer;
attribute C_HAS_S_AXIS_CARTESIAN_TUSER of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_HAS_S_AXIS_PHASE : integer;
attribute C_HAS_S_AXIS_PHASE of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_HAS_S_AXIS_PHASE_TLAST : integer;
attribute C_HAS_S_AXIS_PHASE_TLAST of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_HAS_S_AXIS_PHASE_TUSER : integer;
attribute C_HAS_S_AXIS_PHASE_TUSER of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_INPUT_WIDTH : integer;
attribute C_INPUT_WIDTH of sqrt_cordic_v6_0_11 : entity is 16;
attribute C_ITERATIONS : integer;
attribute C_ITERATIONS of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_M_AXIS_DOUT_TDATA_WIDTH : integer;
attribute C_M_AXIS_DOUT_TDATA_WIDTH of sqrt_cordic_v6_0_11 : entity is 16;
attribute C_M_AXIS_DOUT_TUSER_WIDTH : integer;
attribute C_M_AXIS_DOUT_TUSER_WIDTH of sqrt_cordic_v6_0_11 : entity is 1;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of sqrt_cordic_v6_0_11 : entity is 16;
attribute C_PHASE_FORMAT : integer;
attribute C_PHASE_FORMAT of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_PIPELINE_MODE : integer;
attribute C_PIPELINE_MODE of sqrt_cordic_v6_0_11 : entity is -2;
attribute C_PRECISION : integer;
attribute C_PRECISION of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_ROUND_MODE : integer;
attribute C_ROUND_MODE of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_SCALE_COMP : integer;
attribute C_SCALE_COMP of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_S_AXIS_CARTESIAN_TDATA_WIDTH : integer;
attribute C_S_AXIS_CARTESIAN_TDATA_WIDTH of sqrt_cordic_v6_0_11 : entity is 16;
attribute C_S_AXIS_CARTESIAN_TUSER_WIDTH : integer;
attribute C_S_AXIS_CARTESIAN_TUSER_WIDTH of sqrt_cordic_v6_0_11 : entity is 1;
attribute C_S_AXIS_PHASE_TDATA_WIDTH : integer;
attribute C_S_AXIS_PHASE_TDATA_WIDTH of sqrt_cordic_v6_0_11 : entity is 16;
attribute C_S_AXIS_PHASE_TUSER_WIDTH : integer;
attribute C_S_AXIS_PHASE_TUSER_WIDTH of sqrt_cordic_v6_0_11 : entity is 1;
attribute C_THROTTLE_SCHEME : integer;
attribute C_THROTTLE_SCHEME of sqrt_cordic_v6_0_11 : entity is 3;
attribute C_TLAST_RESOLUTION : integer;
attribute C_TLAST_RESOLUTION of sqrt_cordic_v6_0_11 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of sqrt_cordic_v6_0_11 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of sqrt_cordic_v6_0_11 : entity is "cordic_v6_0_11";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of sqrt_cordic_v6_0_11 : entity is "yes";
end sqrt_cordic_v6_0_11;
architecture STRUCTURE of sqrt_cordic_v6_0_11 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_m_axis_dout_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_cartesian_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_i_synth_m_axis_dout_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_HAS_ACLK of i_synth : label is 1;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_S_AXIS_CARTESIAN of i_synth : label is 1;
attribute C_HAS_S_AXIS_CARTESIAN_TLAST of i_synth : label is 0;
attribute C_HAS_S_AXIS_CARTESIAN_TUSER of i_synth : label is 0;
attribute C_HAS_S_AXIS_PHASE of i_synth : label is 0;
attribute C_HAS_S_AXIS_PHASE_TLAST of i_synth : label is 0;
attribute C_HAS_S_AXIS_PHASE_TUSER of i_synth : label is 0;
attribute C_M_AXIS_DOUT_TDATA_WIDTH of i_synth : label is 16;
attribute C_M_AXIS_DOUT_TUSER_WIDTH of i_synth : label is 1;
attribute C_S_AXIS_CARTESIAN_TDATA_WIDTH of i_synth : label is 16;
attribute C_S_AXIS_CARTESIAN_TUSER_WIDTH of i_synth : label is 1;
attribute C_S_AXIS_PHASE_TDATA_WIDTH of i_synth : label is 16;
attribute C_S_AXIS_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_THROTTLE_SCHEME of i_synth : label is 3;
attribute C_TLAST_RESOLUTION of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute c_architecture of i_synth : label is 2;
attribute c_coarse_rotate of i_synth : label is 0;
attribute c_cordic_function of i_synth : label is 6;
attribute c_data_format of i_synth : label is 1;
attribute c_input_width of i_synth : label is 16;
attribute c_iterations of i_synth : label is 0;
attribute c_output_width of i_synth : label is 16;
attribute c_phase_format of i_synth : label is 0;
attribute c_pipeline_mode of i_synth : label is -2;
attribute c_precision of i_synth : label is 0;
attribute c_round_mode of i_synth : label is 0;
attribute c_scale_comp of i_synth : label is 0;
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
m_axis_dout_tlast <= \<const0>\;
m_axis_dout_tuser(0) <= \<const0>\;
s_axis_cartesian_tready <= \<const1>\;
s_axis_phase_tready <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.sqrt_cordic_v6_0_11_viv
port map (
aclk => aclk,
aclken => '0',
aresetn => '0',
m_axis_dout_tdata(15 downto 0) => m_axis_dout_tdata(15 downto 0),
m_axis_dout_tlast => NLW_i_synth_m_axis_dout_tlast_UNCONNECTED,
m_axis_dout_tready => '0',
m_axis_dout_tuser(0) => NLW_i_synth_m_axis_dout_tuser_UNCONNECTED(0),
m_axis_dout_tvalid => m_axis_dout_tvalid,
s_axis_cartesian_tdata(15 downto 0) => s_axis_cartesian_tdata(15 downto 0),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tready => NLW_i_synth_s_axis_cartesian_tready_UNCONNECTED,
s_axis_cartesian_tuser(0) => '0',
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_phase_tdata(15 downto 0) => B"0000000000000000",
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sqrt is
port (
aclk : in STD_LOGIC;
s_axis_cartesian_tvalid : in STD_LOGIC;
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of sqrt : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of sqrt : entity is "sqrt,cordic_v6_0_11,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of sqrt : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of sqrt : entity is "cordic_v6_0_11,Vivado 2016.4";
end sqrt;
architecture STRUCTURE of sqrt is
signal NLW_U0_m_axis_dout_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_cartesian_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_dout_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_HAS_ACLK : integer;
attribute C_HAS_ACLK of U0 : label is 1;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_S_AXIS_CARTESIAN : integer;
attribute C_HAS_S_AXIS_CARTESIAN of U0 : label is 1;
attribute C_HAS_S_AXIS_CARTESIAN_TLAST : integer;
attribute C_HAS_S_AXIS_CARTESIAN_TLAST of U0 : label is 0;
attribute C_HAS_S_AXIS_CARTESIAN_TUSER : integer;
attribute C_HAS_S_AXIS_CARTESIAN_TUSER of U0 : label is 0;
attribute C_HAS_S_AXIS_PHASE : integer;
attribute C_HAS_S_AXIS_PHASE of U0 : label is 0;
attribute C_HAS_S_AXIS_PHASE_TLAST : integer;
attribute C_HAS_S_AXIS_PHASE_TLAST of U0 : label is 0;
attribute C_HAS_S_AXIS_PHASE_TUSER : integer;
attribute C_HAS_S_AXIS_PHASE_TUSER of U0 : label is 0;
attribute C_M_AXIS_DOUT_TDATA_WIDTH : integer;
attribute C_M_AXIS_DOUT_TDATA_WIDTH of U0 : label is 16;
attribute C_M_AXIS_DOUT_TUSER_WIDTH : integer;
attribute C_M_AXIS_DOUT_TUSER_WIDTH of U0 : label is 1;
attribute C_S_AXIS_CARTESIAN_TDATA_WIDTH : integer;
attribute C_S_AXIS_CARTESIAN_TDATA_WIDTH of U0 : label is 16;
attribute C_S_AXIS_CARTESIAN_TUSER_WIDTH : integer;
attribute C_S_AXIS_CARTESIAN_TUSER_WIDTH of U0 : label is 1;
attribute C_S_AXIS_PHASE_TDATA_WIDTH : integer;
attribute C_S_AXIS_PHASE_TDATA_WIDTH of U0 : label is 16;
attribute C_S_AXIS_PHASE_TUSER_WIDTH : integer;
attribute C_S_AXIS_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_THROTTLE_SCHEME : integer;
attribute C_THROTTLE_SCHEME of U0 : label is 3;
attribute C_TLAST_RESOLUTION : integer;
attribute C_TLAST_RESOLUTION of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute c_architecture : integer;
attribute c_architecture of U0 : label is 2;
attribute c_coarse_rotate : integer;
attribute c_coarse_rotate of U0 : label is 0;
attribute c_cordic_function : integer;
attribute c_cordic_function of U0 : label is 6;
attribute c_data_format : integer;
attribute c_data_format of U0 : label is 1;
attribute c_input_width : integer;
attribute c_input_width of U0 : label is 16;
attribute c_iterations : integer;
attribute c_iterations of U0 : label is 0;
attribute c_output_width : integer;
attribute c_output_width of U0 : label is 16;
attribute c_phase_format : integer;
attribute c_phase_format of U0 : label is 0;
attribute c_pipeline_mode : integer;
attribute c_pipeline_mode of U0 : label is -2;
attribute c_precision : integer;
attribute c_precision of U0 : label is 0;
attribute c_round_mode : integer;
attribute c_round_mode of U0 : label is 0;
attribute c_scale_comp : integer;
attribute c_scale_comp of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.sqrt_cordic_v6_0_11
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
m_axis_dout_tdata(15 downto 0) => m_axis_dout_tdata(15 downto 0),
m_axis_dout_tlast => NLW_U0_m_axis_dout_tlast_UNCONNECTED,
m_axis_dout_tready => '0',
m_axis_dout_tuser(0) => NLW_U0_m_axis_dout_tuser_UNCONNECTED(0),
m_axis_dout_tvalid => m_axis_dout_tvalid,
s_axis_cartesian_tdata(15 downto 0) => s_axis_cartesian_tdata(15 downto 0),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tready => NLW_U0_s_axis_cartesian_tready_UNCONNECTED,
s_axis_cartesian_tuser(0) => '0',
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_phase_tdata(15 downto 0) => B"0000000000000000",
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => '0'
);
end STRUCTURE;
| mit | 882455928a57450a511e002163ce484a | 0.950219 | 1.821463 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/synth/system_vga_feature_transform_0_0.vhd | 1 | 5,944 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_feature_transform:1.0
-- IP Revision: 74
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_feature_transform_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_vga_feature_transform_0_0;
ARCHITECTURE system_vga_feature_transform_0_0_arch OF system_vga_feature_transform_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_feature_transform IS
GENERIC (
NUM_FEATURES : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT vga_feature_transform;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "vga_feature_transform,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_feature_transform_0_0_arch : ARCHITECTURE IS "system_vga_feature_transform_0_0,vga_feature_transform,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "system_vga_feature_transform_0_0,vga_feature_transform,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_feature_transform,x_ipVersion=1.0,x_ipCoreRevision=74,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,NUM_FEATURES=64}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_feature_transform
GENERIC MAP (
NUM_FEATURES => 64
)
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
rst => rst,
active => active,
vsync => vsync,
x_addr_0 => x_addr_0,
y_addr_0 => y_addr_0,
hessian_0 => hessian_0,
x_addr_1 => x_addr_1,
y_addr_1 => y_addr_1,
hessian_1 => hessian_1,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
state => state
);
END system_vga_feature_transform_0_0_arch;
| mit | c44bfaab17b5a950c0b4f06b3ad2c65b | 0.695491 | 3.453806 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 2 | 15,258 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_" &
"loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C" &
"_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=" &
"0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 22.148499999999999 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 22.148499999999999 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit | c7257e2a2813c7edcaa24a1b4d092bd1 | 0.630751 | 3.02019 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/i2s_controller.vhd | 3 | 13,243 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 1; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
BCLK_O : out std_logic; -- Bit Clock
LRCLK_O : out std_logic; -- Frame Clock
SDATA_O : out std_logic; -- Serial Data Output
SDATA_I : in std_logic; -- Serial Data Input
EN_TX_I : in std_logic; -- Enable TX
EN_RX_I : in std_logic; -- Enable RX
OE_S_O : out std_logic; -- Request new Slot Data
WE_S_O : out std_logic; -- Valid Slot Data
D_S_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
D_S_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameters
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0)
--NR_CHANNELS_I : in std_logic_vector(3 downto 0) -- Number of channels (2 - Stereo, 4- TDM4, 8 - TDM8)
);
end i2s_controller;
architecture Behavioral of i2s_controller is
-- Divide value for the serial clock divider
signal DIV_RATE : natural range 0 to 255 := 0;
signal PREV_DIV_RATE : natural range 0 to 255 := 0;
-- Divide value for the frame clock divider
signal LRCLK_RATE : natural range 0 to 255 := 0;
signal PREV_LRCLK_RATE : natural range 0 to 255 := 0;
-- Counter for the serial clock divider
signal Cnt_Bclk : integer range 0 to 255;
-- Counter for the frame clock divider
signal Cnt_Lrclk : integer range 0 to 512;
signal Cnt_Lrclk_TDM : std_logic;
-- Counter for TDM4 and TDM8 Output Enable signal
signal Cnt_Lrclk_OE_S : std_logic;
-- Counter for TDM4 and TDM8 Write Enable signal
signal Cnt_Lrclk_WE_S : std_logic;
-- Internal synchronous BCLK signal
signal BCLK_int : std_logic;
-- Rising and Falling edge impulses of the serial clock
signal BCLK_Fall : std_logic;
signal BCLK_Rise : std_logic;
-- Internal synchronous LRCLK signal
signal LRCLK_int : std_logic;
-- Data Out internal signal
signal Data_Out_int : std_logic_vector(31 downto 0);
-- Data In internal signal
signal Data_In_int : std_logic_vector(31 downto 0);
-- Data Left, Right and Slot internal signal
signal D_L_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_R_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal D_S_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
--Internal synchronous OE signals
signal OE_R_int : std_logic;
signal OE_L_int : std_logic;
signal OE_S_int : std_logic;
--Internal synchronous WE signals
signal WE_R_int : std_logic;
signal WE_L_int : std_logic;
signal WE_S_int : std_logic;
signal enable : std_logic;
signal BCLK_trailing_edge : std_logic;
signal BCLK_leading_edge : std_logic;
signal EN_RX_INT : std_logic;
signal EN_TX_INT : std_logic;
begin
-- Division rate to ensure 48K sample rate
-- BCLK division rate
--DIV_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 16 when (NR_CHANNELS_I = "0100") else
-- 8 when (NR_CHANNELS_I = "1000") else 0;
--
DIV_RATE <= conv_integer(DIV_RATE_I);
-- LRCLK division rate
--LRCLK_RATE <= 32 when (NR_CHANNELS_I = "0010") else
-- 64 when (NR_CHANNELS_I = "0100") else
-- 128 when (NR_CHANNELS_I = "1000") else 0;
--
LRCLK_RATE <= conv_integer(LRCLK_RATE_I);
enable <= '1' when (EN_TX_I = '1') or (EN_RX_I = '1') else '0';
-----------------------------------------------------------------------------------
-- Serial clock generation (BCLK_O, BCLK_FALL, BCLK_RISE)
-----------------------------------------------------------------------------------
SER_CLK: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (DIV_RATE /= PREV_DIV_RATE) or (enable = '0')) then
Cnt_Bclk <= 0;
BCLK_Int <= '0';
PREV_DIV_RATE <= DIV_RATE;
elsif(Cnt_Bclk = ((DIV_RATE/2)-1)) then
Cnt_Bclk <= 0;
BCLK_int <= not BCLK_int;
else
Cnt_Bclk <= Cnt_Bclk + 1;
end if;
end if;
end process SER_CLK;
-- Serial clock Falling edge, Rising Edge
BCLK_Fall <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '1') and (enable = '1')) else '0';
BCLK_Rise <= '1' when ((Cnt_Bclk = ((DIV_RATE/2)-1)) and (BCLK_int = '0') and (enable = '1')) else '0';
BCLK_trailing_edge <= BCLK_Rise when (C_BCLK_POL = 1) else BCLK_Fall;
BCLK_leading_edge <= BCLK_Fall when (C_BCLK_POL = 1) else BCLK_Rise;
-- Serial clock output
BCLK_O <= BCLK_int when enable = '1' else '1';
-----------------------------------------------------------------------------------
-- Frame clock generator (LRCLK_O)
-----------------------------------------------------------------------------------
LRCLK_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (LRCLK_RATE /= PREV_LRCLK_RATE) or (enable = '0')) then
Cnt_Lrclk <= 0;
LRCLK_int <= '0';
PREV_LRCLK_RATE <= LRCLK_RATE;
if(C_FRM_SYNC = 1) then
Cnt_Lrclk <= LRCLK_RATE*2;
end if;
-- 50% Duty Cycle LRCLK signal, used for Stereo Mode
elsif(C_FRM_SYNC = 0) then
if (BCLK_trailing_edge = '1') then
if(Cnt_Lrclk = LRCLK_RATE-1) then
Cnt_Lrclk <= 0;
LRCLK_int <= not LRCLK_int;
else
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
-- Pulse mode LRCLK signal, used for TDM4 and TDM8
elsif(C_FRM_SYNC = 1) then
if (BCLK_trailing_edge = '1') then
-- If the number of bits has been sent, pulse new frame
if(Cnt_Lrclk = LRCLK_RATE*2) then
Cnt_Lrclk <= 0;
LRCLK_int <= '1';
else
LRCLK_int <= '0';
Cnt_Lrclk <= Cnt_Lrclk + 1;
end if;
end if;
end if;
end if;
end process LRCLK_GEN;
-- Frame clock output
LRCLK_O <= LRCLK_int when (enable = '1') else '0';
-- Used to change data in the Slots in TDM Mode
Cnt_Lrclk_TDM <= '0' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224)or(Cnt_Lrclk=256))
else '1';
-- Used to signal data request (TX)
Cnt_Lrclk_OE_S <= '1' when ((Cnt_Lrclk = 0)or(Cnt_Lrclk = 32)or(Cnt_Lrclk = 64)or(Cnt_Lrclk = 96)or
(Cnt_Lrclk = 128)or(Cnt_Lrclk = 160)or(Cnt_Lrclk=192)or(Cnt_Lrclk=224))
else '0';
-- Used to signal valid data (RX)
Cnt_Lrclk_WE_S <= '1' when (Cnt_Lrclk = 1)or(Cnt_Lrclk = 33)or(Cnt_Lrclk = 65)or(Cnt_Lrclk = 97)or
(Cnt_Lrclk = 129)or(Cnt_Lrclk = 161)or(Cnt_Lrclk=193)or(Cnt_Lrclk=225)
else '0';
-----------------------------------------------------------------------------------
-- Load in parallel data, shift out serial data (SDATA_O)
-----------------------------------------------------------------------------------
SER_DATA_O: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
-- If 50% Duty Cycle
if(C_FRM_SYNC = 0) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
elsif((Cnt_Lrclk_TDM = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
-- 50% Duty Cycle mode
if(C_FRM_SYNC = 0) then
Data_Out_int(31) <= '0';
Data_Out_int(30 downto 31-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(30-C_SLOT_WIDTH downto 0) <= (others => '0');
-- If Pulse mode
elsif(C_FRM_SYNC = 1) then
Data_Out_int(31 downto 32-C_SLOT_WIDTH) <= D_S_I;
Data_Out_int(31-C_SLOT_WIDTH downto 0) <= (others => '0');
end if;
end if;
-- Shift out serial data
elsif(BCLK_trailing_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_Out_int <= Data_Out_int(30 downto 0) & '0';
end if;
end if;
end if;
end process SER_DATA_O;
-- Serial data output
SDATA_O <= Data_Out_int(31) when ((EN_TX_I = '1') and (C_MSB_POS = 0)) else
Data_Out_int(0) when ((EN_TX_I = '1') and (C_MSB_POS = 1)) else '0';
-----------------------------------------------------------------------------------
-- Shift in serial data, load out parallel data (SDATA_I)
-----------------------------------------------------------------------------------
SER_DATA_I: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
-- Reset
if((RST_I = '1') or (enable = '0')) then
Data_In_int <= (others => '0');
D_S_O_int <= (others => '0');
-- 50% Duty Cycle mode
elsif(C_FRM_SYNC = 0) then
-- Stereo mode
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0') and (BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif(BCLK_leading_edge = '1') then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
-- Pulse mode
elsif(C_FRM_SYNC = 1) then
-- Load parallel data
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_TDM = '0')and(BCLK_trailing_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
D_S_O_int <= Data_In_int(31 downto 32-C_SLOT_WIDTH);
Data_In_int <= (others => '0');
end if;
-- Shift in serial data
-- Depending on BCLK polarity settings
elsif((Lrclk_int = '0')and(BCLK_leading_edge = '1')) then
if((C_MSB_POS = 0)or(C_MSB_POS = 1)) then
Data_In_int <= Data_In_int(30 downto 0) & SDATA_I;
end if;
end if;
end if;
end if;
end process SER_DATA_I;
D_S_O <= D_S_O_int;
------------------------------------------------------------------------
-- Output Enable signals (for FIFO)
------------------------------------------------------------------------
OE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
OE_S_int <= '0';
else
if((Cnt_Lrclk_OE_S = '1')and(BCLK_trailing_edge = '1')) then
OE_S_int <= '1';
else
OE_S_int <= '0';
end if;
end if;
end if;
end process OE_GEN;
EN_TX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_TX_INT <= '0';
else
-- After enabling TX the first request needs to be syncronized to Cnt_Lrclk = 0
-- otherwise we will mess up the channel order.
if((EN_TX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 0) and (BCLK_trailing_edge = '1')) then
EN_TX_INT <= '1';
elsif (EN_TX_I = '0') then
EN_TX_INT <= '0';
end if;
end if;
end if;
end process EN_TX_INT_GEN;
OE_S_O <= OE_S_int when (EN_TX_INT = '1') else '0';
------------------------------------------------------------------------
-- Write Enable signals (for FIFO)
------------------------------------------------------------------------
WE_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if((RST_I = '1') or (enable = '0')) then
WE_S_int <= '0';
else
-- Depending on BCLK polarity settings
if((Cnt_Lrclk_WE_S = '1')and(BCLK_leading_edge = '1')) then
WE_S_int <= '1';
else
WE_S_int <= '0';
end if;
end if;
end if;
end process WE_GEN;
EN_RX_INT_GEN: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
EN_RX_INT <= '0';
else
-- After enabling RX the first request needs to be syncronized to Cnt_Lrclk = 31
-- otherwise we will mess up the channel order.
if((EN_RX_I = '1') and (Lrclk_int = '0') and (Cnt_Lrclk = 31) and (BCLK_trailing_edge = '1')) then
EN_RX_INT <= '1';
elsif (EN_RX_I = '0') then
EN_RX_INT <= '0';
end if;
end if;
end if;
end process EN_RX_INT_GEN;
WE_S_O <= WE_S_int when (EN_RX_INT = '1') else '0';
end Behavioral;
| mit | 59c8f7968d2e3d4ecdd8aceffddf2529 | 0.527902 | 2.90991 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/synth/system_ov7670_controller_1_0.vhd | 2 | 4,423 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_1_0_arch : ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
| mit | d2e601523a6fc7a2b14fa7540fb724fc | 0.732534 | 3.914159 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/timestamp_taker.vhd | 2 | 4,870 | -------------------------------------------------------------------------------
-- Title : Timestamp Taker module
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A double buffered register that takes timestamps from the
-- global timestamp and is readable by the internal bus.
--
-- bank_x_i_p: Bus Bank
-- bank_y_i_p: Application Bank (timestamp)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity timestamp_taker is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF# -- Base address of the timestamp registers
);
port (
-- Timestamp in
timestamp_i_p : in timestamp_type;
-- Trigger and control signals
trigger_i_p : in std_logic; -- When this trigger is strobed the
-- current timestamp is stored in the
-- register.
bank_x_i_p : in std_logic; -- The bank that is mapped to the bus.
bank_y_i_p : in std_logic; -- The bank that is mapped to the
-- application.
-- Bus interface
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- Clock
clk : in std_logic
);
end timestamp_taker;
-------------------------------------------------------------------------------
architecture behavioural of timestamp_taker is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
-- signal timestamp : timestamp_type := (others => '0');
signal reg_timestamp_s : reg_file_type(7 downto 0) := (others => (others => '0'));
signal bus_i_s : busdevice_in_type;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
-- Bit 2 of the register address is control by the bank switch 'bank_x_i_p'
bus_i_s.addr <= bus_i.addr(14 downto 3) & bank_x_i_p & bus_i.addr(1 downto 0);
bus_i_s.data <= bus_i.data;
bus_i_s.re <= bus_i.re;
bus_i_s.we <= bus_i.we;
----------------------------------------------------------------------------
-- Sequential process
----------------------------------------------------------------------------
-- When the goertzel is finished, the goertzel_done_s signal is strobed.
-- Copy timestamp to the register at this moment.
timestamp_taker : process (clk) is
begin -- process timestamp_taker
if rising_edge(clk) then -- rising clock edge
if trigger_i_p = '1' then
if bank_y_i_p = '0' then
reg_timestamp_s(0) <= std_logic_vector(timestamp_i_p(15 downto 0));
reg_timestamp_s(1) <= std_logic_vector(timestamp_i_p(31 downto 16));
reg_timestamp_s(2) <= std_logic_vector(timestamp_i_p(47 downto 32));
else
reg_timestamp_s(4) <= std_logic_vector(timestamp_i_p(15 downto 0));
reg_timestamp_s(5) <= std_logic_vector(timestamp_i_p(31 downto 16));
reg_timestamp_s(6) <= std_logic_vector(timestamp_i_p(47 downto 32));
end if;
end if;
end if;
end process timestamp_taker;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Register with 8 16 bit values for two timestamps
reg_file_timestamp_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => 3)
port map (
bus_o => bus_o,
bus_i => bus_i_s, -- the modified address
reg_o => open, -- read only register
reg_i => reg_timestamp_s,
clk => clk);
end behavioural;
| bsd-3-clause | c1637796c95cf09591fe60f630aacf0d | 0.414374 | 4.914228 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/synth/system_affine_rotation_generator_0_0.vhd | 1 | 4,441 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:affine_rotation_generator:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_affine_rotation_generator_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
reset : IN STD_LOGIC;
a00 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_affine_rotation_generator_0_0;
ARCHITECTURE system_affine_rotation_generator_0_0_arch OF system_affine_rotation_generator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_affine_rotation_generator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT affine_rotation_generator IS
PORT (
clk_25 : IN STD_LOGIC;
reset : IN STD_LOGIC;
a00 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT affine_rotation_generator;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_affine_rotation_generator_0_0_arch: ARCHITECTURE IS "affine_rotation_generator,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_affine_rotation_generator_0_0_arch : ARCHITECTURE IS "system_affine_rotation_generator_0_0,affine_rotation_generator,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_affine_rotation_generator_0_0_arch: ARCHITECTURE IS "system_affine_rotation_generator_0_0,affine_rotation_generator,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=affine_rotation_generator,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : affine_rotation_generator
PORT MAP (
clk_25 => clk_25,
reset => reset,
a00 => a00,
a01 => a01,
a10 => a10,
a11 => a11
);
END system_affine_rotation_generator_0_0_arch;
| mit | a4238338538a3c1a7a82e83b0181c762 | 0.7415 | 3.776361 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_1_0/synth/system_vga_sync_ref_1_0.vhd | 2 | 4,637 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_ref:1.0
-- IP Revision: 65
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_ref_1_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_ref_1_0;
ARCHITECTURE system_vga_sync_ref_1_0_arch OF system_vga_sync_ref_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_ref_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_ref IS
GENERIC (
H_SIZE : INTEGER;
H_SYNC_SIZE : INTEGER;
V_SIZE : INTEGER;
DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
start : OUT STD_LOGIC;
active : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_ref;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_ref_1_0_arch: ARCHITECTURE IS "vga_sync_ref,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_ref_1_0_arch : ARCHITECTURE IS "system_vga_sync_ref_1_0,vga_sync_ref,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_ref_1_0_arch: ARCHITECTURE IS "system_vga_sync_ref_1_0,vga_sync_ref,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync_ref,x_ipVersion=1.0,x_ipCoreRevision=65,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_SYNC_SIZE=144,V_SIZE=480,DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_ref
GENERIC MAP (
H_SIZE => 640,
H_SYNC_SIZE => 144,
V_SIZE => 480,
DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
hsync => hsync,
vsync => vsync,
start => start,
active => active,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_ref_1_0_arch;
| mit | 5e85f5a26e210f1d72d2d660050aa79f | 0.70757 | 3.703674 | false | false | false | false |
pgavin/carpe | hdl/cpu/btb/cache/replace/lru/cpu_btb_cache_replace_lru-rtl.vhdl | 1 | 1,983 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library mem;
use work.cpu_btb_cache_config_pkg.all;
architecture rtl of cpu_btb_cache_replace_lru is
begin
lru : entity mem.cache_replace_lru(rtl)
generic map (
log2_assoc => cpu_btb_cache_log2_assoc,
index_bits => cpu_btb_cache_index_bits
)
port map (
clk => clk,
rstn => rstn,
re => cpu_btb_cache_replace_lru_ctrl_in.re,
rindex => cpu_btb_cache_replace_lru_dp_in.rindex,
rway => cpu_btb_cache_replace_lru_dp_out.rway,
rstate => cpu_btb_cache_replace_lru_dp_out.rstate,
we => cpu_btb_cache_replace_lru_ctrl_in.we,
windex => cpu_btb_cache_replace_lru_dp_in.windex,
wway => cpu_btb_cache_replace_lru_dp_in.wway,
wstate => cpu_btb_cache_replace_lru_dp_in.wstate
);
end;
| apache-2.0 | 9af10f63223d2ef76d2940716fd6da17 | 0.530005 | 4.201271 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/system_affine_rotation_generator_0_0_sim_netlist.vhdl | 1 | 165,007 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 14:24:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_rotation_generator_0_0/system_affine_rotation_generator_0_0_sim_netlist.vhdl
-- Design : system_affine_rotation_generator_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_affine_rotation_generator_0_0_affine_rotation_generator is
port (
a00 : out STD_LOGIC_VECTOR ( 26 downto 0 );
a01 : out STD_LOGIC_VECTOR ( 29 downto 0 );
reset : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_affine_rotation_generator_0_0_affine_rotation_generator : entity is "affine_rotation_generator";
end system_affine_rotation_generator_0_0_affine_rotation_generator;
architecture STRUCTURE of system_affine_rotation_generator_0_0_affine_rotation_generator is
signal \^a01\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \a01[0]_i_1_n_0\ : STD_LOGIC;
signal \a01[10]_i_1_n_0\ : STD_LOGIC;
signal \a01[11]_i_1_n_0\ : STD_LOGIC;
signal \a01[12]_i_1_n_0\ : STD_LOGIC;
signal \a01[13]_i_1_n_0\ : STD_LOGIC;
signal \a01[14]_i_1_n_0\ : STD_LOGIC;
signal \a01[15]_i_1_n_0\ : STD_LOGIC;
signal \a01[16]_i_1_n_0\ : STD_LOGIC;
signal \a01[17]_i_1_n_0\ : STD_LOGIC;
signal \a01[18]_i_1_n_0\ : STD_LOGIC;
signal \a01[19]_i_1_n_0\ : STD_LOGIC;
signal \a01[1]_i_1_n_0\ : STD_LOGIC;
signal \a01[20]_i_1_n_0\ : STD_LOGIC;
signal \a01[21]_i_1_n_0\ : STD_LOGIC;
signal \a01[22]_i_1_n_0\ : STD_LOGIC;
signal \a01[23]_i_1_n_0\ : STD_LOGIC;
signal \a01[24]_i_1_n_0\ : STD_LOGIC;
signal \a01[25]_i_1_n_0\ : STD_LOGIC;
signal \a01[25]_i_2_n_0\ : STD_LOGIC;
signal \a01[25]_i_3_n_0\ : STD_LOGIC;
signal \a01[25]_i_4_n_0\ : STD_LOGIC;
signal \a01[25]_i_5_n_0\ : STD_LOGIC;
signal \a01[26]_i_1_n_0\ : STD_LOGIC;
signal \a01[27]_i_1_n_0\ : STD_LOGIC;
signal \a01[28]_i_1_n_0\ : STD_LOGIC;
signal \a01[29]_i_10_n_0\ : STD_LOGIC;
signal \a01[29]_i_11_n_0\ : STD_LOGIC;
signal \a01[29]_i_12_n_0\ : STD_LOGIC;
signal \a01[29]_i_1_n_0\ : STD_LOGIC;
signal \a01[29]_i_2_n_0\ : STD_LOGIC;
signal \a01[29]_i_3_n_0\ : STD_LOGIC;
signal \a01[29]_i_4_n_0\ : STD_LOGIC;
signal \a01[29]_i_5_n_0\ : STD_LOGIC;
signal \a01[29]_i_6_n_0\ : STD_LOGIC;
signal \a01[29]_i_7_n_0\ : STD_LOGIC;
signal \a01[29]_i_8_n_0\ : STD_LOGIC;
signal \a01[29]_i_9_n_0\ : STD_LOGIC;
signal \a01[2]_i_1_n_0\ : STD_LOGIC;
signal \a01[3]_i_1_n_0\ : STD_LOGIC;
signal \a01[4]_i_1_n_0\ : STD_LOGIC;
signal \a01[5]_i_1_n_0\ : STD_LOGIC;
signal \a01[6]_i_1_n_0\ : STD_LOGIC;
signal \a01[7]_i_1_n_0\ : STD_LOGIC;
signal \a01[8]_i_1_n_0\ : STD_LOGIC;
signal \a01[9]_i_1_n_0\ : STD_LOGIC;
signal angle : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \angle1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \angle1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \angle1_carry__0_n_0\ : STD_LOGIC;
signal \angle1_carry__0_n_1\ : STD_LOGIC;
signal \angle1_carry__0_n_2\ : STD_LOGIC;
signal \angle1_carry__0_n_3\ : STD_LOGIC;
signal \angle1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \angle1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \angle1_carry__1_n_0\ : STD_LOGIC;
signal \angle1_carry__1_n_1\ : STD_LOGIC;
signal \angle1_carry__1_n_2\ : STD_LOGIC;
signal \angle1_carry__1_n_3\ : STD_LOGIC;
signal \angle1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \angle1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \angle1_carry__2_n_0\ : STD_LOGIC;
signal \angle1_carry__2_n_1\ : STD_LOGIC;
signal \angle1_carry__2_n_2\ : STD_LOGIC;
signal \angle1_carry__2_n_3\ : STD_LOGIC;
signal angle1_carry_i_1_n_0 : STD_LOGIC;
signal angle1_carry_i_2_n_0 : STD_LOGIC;
signal angle1_carry_i_3_n_0 : STD_LOGIC;
signal angle1_carry_i_4_n_0 : STD_LOGIC;
signal angle1_carry_i_5_n_0 : STD_LOGIC;
signal angle1_carry_n_0 : STD_LOGIC;
signal angle1_carry_n_1 : STD_LOGIC;
signal angle1_carry_n_2 : STD_LOGIC;
signal angle1_carry_n_3 : STD_LOGIC;
signal \angle2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__0_n_0\ : STD_LOGIC;
signal \angle2_carry__0_n_1\ : STD_LOGIC;
signal \angle2_carry__0_n_2\ : STD_LOGIC;
signal \angle2_carry__0_n_3\ : STD_LOGIC;
signal \angle2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__1_n_0\ : STD_LOGIC;
signal \angle2_carry__1_n_1\ : STD_LOGIC;
signal \angle2_carry__1_n_2\ : STD_LOGIC;
signal \angle2_carry__1_n_3\ : STD_LOGIC;
signal \angle2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__2_n_0\ : STD_LOGIC;
signal \angle2_carry__2_n_1\ : STD_LOGIC;
signal \angle2_carry__2_n_2\ : STD_LOGIC;
signal \angle2_carry__2_n_3\ : STD_LOGIC;
signal \angle2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__3_n_0\ : STD_LOGIC;
signal \angle2_carry__3_n_1\ : STD_LOGIC;
signal \angle2_carry__3_n_2\ : STD_LOGIC;
signal \angle2_carry__3_n_3\ : STD_LOGIC;
signal \angle2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__4_n_0\ : STD_LOGIC;
signal \angle2_carry__4_n_1\ : STD_LOGIC;
signal \angle2_carry__4_n_2\ : STD_LOGIC;
signal \angle2_carry__4_n_3\ : STD_LOGIC;
signal \angle2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \angle2_carry__5_n_0\ : STD_LOGIC;
signal \angle2_carry__5_n_1\ : STD_LOGIC;
signal \angle2_carry__5_n_2\ : STD_LOGIC;
signal \angle2_carry__5_n_3\ : STD_LOGIC;
signal \angle2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \angle2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \angle2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \angle2_carry__6_n_2\ : STD_LOGIC;
signal \angle2_carry__6_n_3\ : STD_LOGIC;
signal angle2_carry_i_1_n_0 : STD_LOGIC;
signal angle2_carry_i_2_n_0 : STD_LOGIC;
signal angle2_carry_i_3_n_0 : STD_LOGIC;
signal angle2_carry_i_4_n_0 : STD_LOGIC;
signal angle2_carry_n_0 : STD_LOGIC;
signal angle2_carry_n_1 : STD_LOGIC;
signal angle2_carry_n_2 : STD_LOGIC;
signal angle2_carry_n_3 : STD_LOGIC;
signal \angle[10]_i_1_n_0\ : STD_LOGIC;
signal \angle[11]_i_1_n_0\ : STD_LOGIC;
signal \angle[12]_i_1_n_0\ : STD_LOGIC;
signal \angle[13]_i_1_n_0\ : STD_LOGIC;
signal \angle[14]_i_1_n_0\ : STD_LOGIC;
signal \angle[15]_i_1_n_0\ : STD_LOGIC;
signal \angle[16]_i_1_n_0\ : STD_LOGIC;
signal \angle[17]_i_1_n_0\ : STD_LOGIC;
signal \angle[18]_i_1_n_0\ : STD_LOGIC;
signal \angle[19]_i_1_n_0\ : STD_LOGIC;
signal \angle[1]_i_1_n_0\ : STD_LOGIC;
signal \angle[20]_i_1_n_0\ : STD_LOGIC;
signal \angle[21]_i_1_n_0\ : STD_LOGIC;
signal \angle[22]_i_1_n_0\ : STD_LOGIC;
signal \angle[23]_i_1_n_0\ : STD_LOGIC;
signal \angle[24]_i_1_n_0\ : STD_LOGIC;
signal \angle[25]_i_1_n_0\ : STD_LOGIC;
signal \angle[26]_i_1_n_0\ : STD_LOGIC;
signal \angle[27]_i_1_n_0\ : STD_LOGIC;
signal \angle[28]_i_1_n_0\ : STD_LOGIC;
signal \angle[29]_i_1_n_0\ : STD_LOGIC;
signal \angle[2]_i_1_n_0\ : STD_LOGIC;
signal \angle[30]_i_1_n_0\ : STD_LOGIC;
signal \angle[31]_i_1_n_0\ : STD_LOGIC;
signal \angle[3]_i_1_n_0\ : STD_LOGIC;
signal \angle[4]_i_1_n_0\ : STD_LOGIC;
signal \angle[5]_i_1_n_0\ : STD_LOGIC;
signal \angle[6]_i_1_n_0\ : STD_LOGIC;
signal \angle[7]_i_1_n_0\ : STD_LOGIC;
signal \angle[8]_i_1_n_0\ : STD_LOGIC;
signal \angle[9]_i_1_n_0\ : STD_LOGIC;
signal \cosine[0]_i_1_n_0\ : STD_LOGIC;
signal \cosine[10]_i_1_n_0\ : STD_LOGIC;
signal \cosine[10]_i_2_n_0\ : STD_LOGIC;
signal \cosine[10]_i_3_n_0\ : STD_LOGIC;
signal \cosine[10]_i_4_n_0\ : STD_LOGIC;
signal \cosine[11]_i_1_n_0\ : STD_LOGIC;
signal \cosine[12]_i_1_n_0\ : STD_LOGIC;
signal \cosine[12]_i_2_n_0\ : STD_LOGIC;
signal \cosine[12]_i_3_n_0\ : STD_LOGIC;
signal \cosine[13]_i_1_n_0\ : STD_LOGIC;
signal \cosine[14]_i_1_n_0\ : STD_LOGIC;
signal \cosine[14]_i_2_n_0\ : STD_LOGIC;
signal \cosine[14]_i_3_n_0\ : STD_LOGIC;
signal \cosine[14]_i_4_n_0\ : STD_LOGIC;
signal \cosine[15]_i_1_n_0\ : STD_LOGIC;
signal \cosine[16]_i_1_n_0\ : STD_LOGIC;
signal \cosine[17]_i_1_n_0\ : STD_LOGIC;
signal \cosine[18]_i_1_n_0\ : STD_LOGIC;
signal \cosine[19]_i_10_n_0\ : STD_LOGIC;
signal \cosine[19]_i_11_n_0\ : STD_LOGIC;
signal \cosine[19]_i_12_n_0\ : STD_LOGIC;
signal \cosine[19]_i_1_n_0\ : STD_LOGIC;
signal \cosine[19]_i_2_n_0\ : STD_LOGIC;
signal \cosine[19]_i_3_n_0\ : STD_LOGIC;
signal \cosine[19]_i_4_n_0\ : STD_LOGIC;
signal \cosine[19]_i_5_n_0\ : STD_LOGIC;
signal \cosine[19]_i_6_n_0\ : STD_LOGIC;
signal \cosine[19]_i_7_n_0\ : STD_LOGIC;
signal \cosine[19]_i_8_n_0\ : STD_LOGIC;
signal \cosine[19]_i_9_n_0\ : STD_LOGIC;
signal \cosine[1]_i_1_n_0\ : STD_LOGIC;
signal \cosine[20]_i_1_n_0\ : STD_LOGIC;
signal \cosine[20]_i_2_n_0\ : STD_LOGIC;
signal \cosine[21]_i_1_n_0\ : STD_LOGIC;
signal \cosine[22]_i_10_n_0\ : STD_LOGIC;
signal \cosine[22]_i_11_n_0\ : STD_LOGIC;
signal \cosine[22]_i_12_n_0\ : STD_LOGIC;
signal \cosine[22]_i_13_n_0\ : STD_LOGIC;
signal \cosine[22]_i_14_n_0\ : STD_LOGIC;
signal \cosine[22]_i_15_n_0\ : STD_LOGIC;
signal \cosine[22]_i_1_n_0\ : STD_LOGIC;
signal \cosine[22]_i_2_n_0\ : STD_LOGIC;
signal \cosine[22]_i_3_n_0\ : STD_LOGIC;
signal \cosine[22]_i_4_n_0\ : STD_LOGIC;
signal \cosine[22]_i_5_n_0\ : STD_LOGIC;
signal \cosine[22]_i_6_n_0\ : STD_LOGIC;
signal \cosine[22]_i_7_n_0\ : STD_LOGIC;
signal \cosine[22]_i_8_n_0\ : STD_LOGIC;
signal \cosine[22]_i_9_n_0\ : STD_LOGIC;
signal \cosine[23]_i_1_n_0\ : STD_LOGIC;
signal \cosine[23]_i_2_n_0\ : STD_LOGIC;
signal \cosine[23]_i_3_n_0\ : STD_LOGIC;
signal \cosine[24]_i_1_n_0\ : STD_LOGIC;
signal \cosine[24]_i_2_n_0\ : STD_LOGIC;
signal \cosine[24]_i_3_n_0\ : STD_LOGIC;
signal \cosine[24]_i_4_n_0\ : STD_LOGIC;
signal \cosine[24]_i_5_n_0\ : STD_LOGIC;
signal \cosine[24]_i_6_n_0\ : STD_LOGIC;
signal \cosine[24]_i_7_n_0\ : STD_LOGIC;
signal \cosine[24]_i_8_n_0\ : STD_LOGIC;
signal \cosine[24]_i_9_n_0\ : STD_LOGIC;
signal \cosine[25]_i_1_n_0\ : STD_LOGIC;
signal \cosine[25]_i_2_n_0\ : STD_LOGIC;
signal \cosine[25]_i_3_n_0\ : STD_LOGIC;
signal \cosine[25]_i_4_n_0\ : STD_LOGIC;
signal \cosine[25]_i_5_n_0\ : STD_LOGIC;
signal \cosine[25]_i_6_n_0\ : STD_LOGIC;
signal \cosine[29]_i_10_n_0\ : STD_LOGIC;
signal \cosine[29]_i_11_n_0\ : STD_LOGIC;
signal \cosine[29]_i_12_n_0\ : STD_LOGIC;
signal \cosine[29]_i_13_n_0\ : STD_LOGIC;
signal \cosine[29]_i_14_n_0\ : STD_LOGIC;
signal \cosine[29]_i_15_n_0\ : STD_LOGIC;
signal \cosine[29]_i_16_n_0\ : STD_LOGIC;
signal \cosine[29]_i_17_n_0\ : STD_LOGIC;
signal \cosine[29]_i_18_n_0\ : STD_LOGIC;
signal \cosine[29]_i_19_n_0\ : STD_LOGIC;
signal \cosine[29]_i_20_n_0\ : STD_LOGIC;
signal \cosine[29]_i_21_n_0\ : STD_LOGIC;
signal \cosine[29]_i_22_n_0\ : STD_LOGIC;
signal \cosine[29]_i_23_n_0\ : STD_LOGIC;
signal \cosine[29]_i_24_n_0\ : STD_LOGIC;
signal \cosine[29]_i_25_n_0\ : STD_LOGIC;
signal \cosine[29]_i_26_n_0\ : STD_LOGIC;
signal \cosine[29]_i_27_n_0\ : STD_LOGIC;
signal \cosine[29]_i_28_n_0\ : STD_LOGIC;
signal \cosine[29]_i_29_n_0\ : STD_LOGIC;
signal \cosine[29]_i_2_n_0\ : STD_LOGIC;
signal \cosine[29]_i_30_n_0\ : STD_LOGIC;
signal \cosine[29]_i_31_n_0\ : STD_LOGIC;
signal \cosine[29]_i_32_n_0\ : STD_LOGIC;
signal \cosine[29]_i_33_n_0\ : STD_LOGIC;
signal \cosine[29]_i_34_n_0\ : STD_LOGIC;
signal \cosine[29]_i_35_n_0\ : STD_LOGIC;
signal \cosine[29]_i_3_n_0\ : STD_LOGIC;
signal \cosine[29]_i_4_n_0\ : STD_LOGIC;
signal \cosine[29]_i_5_n_0\ : STD_LOGIC;
signal \cosine[29]_i_6_n_0\ : STD_LOGIC;
signal \cosine[29]_i_7_n_0\ : STD_LOGIC;
signal \cosine[29]_i_8_n_0\ : STD_LOGIC;
signal \cosine[29]_i_9_n_0\ : STD_LOGIC;
signal \cosine[2]_i_1_n_0\ : STD_LOGIC;
signal \cosine[3]_i_1_n_0\ : STD_LOGIC;
signal \cosine[4]_i_1_n_0\ : STD_LOGIC;
signal \cosine[4]_i_2_n_0\ : STD_LOGIC;
signal \cosine[4]_i_3_n_0\ : STD_LOGIC;
signal \cosine[5]_i_1_n_0\ : STD_LOGIC;
signal \cosine[6]_i_1_n_0\ : STD_LOGIC;
signal \cosine[6]_i_2_n_0\ : STD_LOGIC;
signal \cosine[7]_i_1_n_0\ : STD_LOGIC;
signal \cosine[7]_i_2_n_0\ : STD_LOGIC;
signal \cosine[7]_i_3_n_0\ : STD_LOGIC;
signal \cosine[7]_i_4_n_0\ : STD_LOGIC;
signal \cosine[7]_i_5_n_0\ : STD_LOGIC;
signal \cosine[8]_i_1_n_0\ : STD_LOGIC;
signal \cosine[8]_i_2_n_0\ : STD_LOGIC;
signal \cosine[8]_i_3_n_0\ : STD_LOGIC;
signal \cosine[9]_i_1_n_0\ : STD_LOGIC;
signal \cosine[9]_i_2_n_0\ : STD_LOGIC;
signal \cosine[9]_i_3_n_0\ : STD_LOGIC;
signal \cosine[9]_i_4_n_0\ : STD_LOGIC;
signal \cosine[9]_i_5_n_0\ : STD_LOGIC;
signal \cosine[9]_i_6_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry__2_n_3\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \counter0_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \counter[0]_i_1_n_0\ : STD_LOGIC;
signal \counter[0]_i_3_n_0\ : STD_LOGIC;
signal \counter[0]_i_4_n_0\ : STD_LOGIC;
signal \counter[0]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_2_n_0\ : STD_LOGIC;
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_2_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_2_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_2_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_2_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_2_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_2_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal counter_reg : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \i__carry__0_i_10_n_0\ : STD_LOGIC;
signal \i__carry__0_i_11_n_0\ : STD_LOGIC;
signal \i__carry__0_i_12_n_0\ : STD_LOGIC;
signal \i__carry__0_i_13_n_0\ : STD_LOGIC;
signal \i__carry__0_i_14_n_0\ : STD_LOGIC;
signal \i__carry__0_i_15_n_0\ : STD_LOGIC;
signal \i__carry__0_i_16_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1_n_1\ : STD_LOGIC;
signal \i__carry__0_i_1_n_2\ : STD_LOGIC;
signal \i__carry__0_i_1_n_3\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__0_i_6_n_0\ : STD_LOGIC;
signal \i__carry__0_i_7_n_0\ : STD_LOGIC;
signal \i__carry__0_i_8_n_0\ : STD_LOGIC;
signal \i__carry__0_i_8_n_1\ : STD_LOGIC;
signal \i__carry__0_i_8_n_2\ : STD_LOGIC;
signal \i__carry__0_i_8_n_3\ : STD_LOGIC;
signal \i__carry__0_i_9_n_0\ : STD_LOGIC;
signal \i__carry__1_i_10_n_0\ : STD_LOGIC;
signal \i__carry__1_i_11_n_0\ : STD_LOGIC;
signal \i__carry__1_i_12_n_0\ : STD_LOGIC;
signal \i__carry__1_i_13_n_0\ : STD_LOGIC;
signal \i__carry__1_i_14_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_1\ : STD_LOGIC;
signal \i__carry__1_i_1_n_2\ : STD_LOGIC;
signal \i__carry__1_i_1_n_3\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_1\ : STD_LOGIC;
signal \i__carry__1_i_2_n_2\ : STD_LOGIC;
signal \i__carry__1_i_2_n_3\ : STD_LOGIC;
signal \i__carry__1_i_3_n_0\ : STD_LOGIC;
signal \i__carry__1_i_4_n_0\ : STD_LOGIC;
signal \i__carry__1_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_6_n_0\ : STD_LOGIC;
signal \i__carry__1_i_7_n_0\ : STD_LOGIC;
signal \i__carry__1_i_8_n_0\ : STD_LOGIC;
signal \i__carry__1_i_9_n_0\ : STD_LOGIC;
signal \i__carry__2_i_10_n_0\ : STD_LOGIC;
signal \i__carry__2_i_11_n_0\ : STD_LOGIC;
signal \i__carry__2_i_12_n_0\ : STD_LOGIC;
signal \i__carry__2_i_13_n_0\ : STD_LOGIC;
signal \i__carry__2_i_14_n_0\ : STD_LOGIC;
signal \i__carry__2_i_15_n_0\ : STD_LOGIC;
signal \i__carry__2_i_16_n_0\ : STD_LOGIC;
signal \i__carry__2_i_1_n_0\ : STD_LOGIC;
signal \i__carry__2_i_2_n_0\ : STD_LOGIC;
signal \i__carry__2_i_3_n_0\ : STD_LOGIC;
signal \i__carry__2_i_4_n_0\ : STD_LOGIC;
signal \i__carry__2_i_4_n_1\ : STD_LOGIC;
signal \i__carry__2_i_4_n_2\ : STD_LOGIC;
signal \i__carry__2_i_4_n_3\ : STD_LOGIC;
signal \i__carry__2_i_5_n_0\ : STD_LOGIC;
signal \i__carry__2_i_6_n_0\ : STD_LOGIC;
signal \i__carry__2_i_7_n_0\ : STD_LOGIC;
signal \i__carry__2_i_8_n_0\ : STD_LOGIC;
signal \i__carry__2_i_9_n_2\ : STD_LOGIC;
signal \i__carry__2_i_9_n_3\ : STD_LOGIC;
signal \i__carry_i_10_n_0\ : STD_LOGIC;
signal \i__carry_i_11_n_0\ : STD_LOGIC;
signal \i__carry_i_12_n_0\ : STD_LOGIC;
signal \i__carry_i_13_n_0\ : STD_LOGIC;
signal \i__carry_i_14_n_0\ : STD_LOGIC;
signal \i__carry_i_15_n_0\ : STD_LOGIC;
signal \i__carry_i_16_n_0\ : STD_LOGIC;
signal \i__carry_i_17_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_1\ : STD_LOGIC;
signal \i__carry_i_1_n_2\ : STD_LOGIC;
signal \i__carry_i_1_n_3\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_1\ : STD_LOGIC;
signal \i__carry_i_9_n_2\ : STD_LOGIC;
signal \i__carry_i_9_n_3\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 1 );
signal NLW_angle1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_angle2_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_angle2_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_counter0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter0_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter0_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter0_inferred__0/i__carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_i__carry__2_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_i__carry__2_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \a01[29]_i_11\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \a01[29]_i_6\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \a01[29]_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \angle[10]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \angle[11]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \angle[12]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \angle[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \angle[14]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \angle[15]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \angle[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \angle[17]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \angle[18]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \angle[19]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \angle[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \angle[20]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \angle[21]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \angle[22]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \angle[23]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \angle[24]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \angle[25]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \angle[26]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \angle[27]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \angle[28]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \angle[29]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \angle[2]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \angle[30]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \angle[31]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \angle[3]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \angle[4]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \angle[5]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \angle[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \angle[8]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \angle[9]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cosine[10]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cosine[12]_i_3\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \cosine[14]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cosine[19]_i_10\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \cosine[19]_i_11\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \cosine[19]_i_12\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cosine[19]_i_2\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cosine[19]_i_5\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \cosine[19]_i_7\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \cosine[19]_i_9\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cosine[24]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \cosine[24]_i_5\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \cosine[24]_i_7\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cosine[24]_i_8\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cosine[24]_i_9\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \cosine[29]_i_10\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \cosine[29]_i_11\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cosine[29]_i_13\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \cosine[29]_i_14\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \cosine[29]_i_15\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cosine[29]_i_16\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \cosine[29]_i_17\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cosine[29]_i_18\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \cosine[29]_i_19\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \cosine[29]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \cosine[29]_i_20\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cosine[29]_i_21\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cosine[29]_i_22\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cosine[29]_i_23\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cosine[29]_i_24\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \cosine[29]_i_25\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cosine[29]_i_26\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cosine[29]_i_27\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \cosine[29]_i_28\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \cosine[29]_i_29\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cosine[29]_i_3\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \cosine[29]_i_30\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cosine[29]_i_31\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cosine[29]_i_32\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cosine[29]_i_33\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \cosine[29]_i_34\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \cosine[29]_i_35\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cosine[29]_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cosine[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \cosine[6]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \cosine[7]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cosine[7]_i_3\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \cosine[7]_i_5\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \cosine[8]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cosine[9]_i_4\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cosine[9]_i_5\ : label is "soft_lutpair34";
begin
a01(29 downto 0) <= \^a01\(29 downto 0);
\a01[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E291D5F7E6B39180"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(0),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[0]_i_1_n_0\
);
\a01[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1F791A29191E6C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(10),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[10]_i_1_n_0\
);
\a01[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D180F7F7F7E6E6A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(11),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[11]_i_1_n_0\
);
\a01[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3A2F7C4F7F7E6C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(12),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[12]_i_1_n_0\
);
\a01[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2B3D5C4A2B3A2A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(13),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[13]_i_1_n_0\
);
\a01[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1F780F7C4C48080"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(14),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[14]_i_1_n_0\
);
\a01[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBCBE98A23436102"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[25]_i_4_n_0\,
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \^a01\(15),
O => \a01[15]_i_1_n_0\
);
\a01[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2A2B3C4C4C491A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(16),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[16]_i_1_n_0\
);
\a01[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0D580B3C4A2D5E6"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(17),
I3 => \a01[29]_i_3_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[17]_i_1_n_0\
);
\a01[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE269B13DF57FE76"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_4_n_0\,
I3 => \^a01\(18),
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[18]_i_1_n_0\
);
\a01[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2F7C4D5C4F79180"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(19),
I3 => \a01[29]_i_3_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[19]_i_1_n_0\
);
\a01[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2A2A2A2A29191E6"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(1),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[1]_i_1_n_0\
);
\a01[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF37FC74CE46A820"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_4_n_0\,
I3 => \^a01\(20),
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[20]_i_1_n_0\
);
\a01[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD15CE46EC64EC64"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(21),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[21]_i_1_n_0\
);
\a01[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE36FC74DC54CC44"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(22),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[22]_i_1_n_0\
);
\a01[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D898101099991111"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[25]_i_4_n_0\,
I3 => \a01[29]_i_4_n_0\,
I4 => \^a01\(23),
I5 => \a01[29]_i_3_n_0\,
O => \a01[23]_i_1_n_0\
);
\a01[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE26EE66EF67EF67"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(24),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[24]_i_1_n_0\
);
\a01[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF37FF77FE76FF77"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \^a01\(25),
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[25]_i_4_n_0\,
O => \a01[25]_i_1_n_0\
);
\a01[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \cosine[29]_i_3_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[19]_i_5_n_0\,
I4 => \a01[29]_i_6_n_0\,
I5 => \cosine[19]_i_6_n_0\,
O => \a01[25]_i_2_n_0\
);
\a01[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFDFFFF"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[29]_i_3_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \a01[25]_i_5_n_0\,
I4 => \cosine[19]_i_5_n_0\,
I5 => \cosine[19]_i_6_n_0\,
O => \a01[25]_i_3_n_0\
);
\a01[25]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \a01[29]_i_7_n_0\,
I1 => \cosine[7]_i_5_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[7]_i_3_n_0\,
O => \a01[25]_i_4_n_0\
);
\a01[25]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(7),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(7),
I5 => \cosine[25]_i_5_n_0\,
O => \a01[25]_i_5_n_0\
);
\a01[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(26),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[26]_i_1_n_0\
);
\a01[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(27),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[27]_i_1_n_0\
);
\a01[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(28),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[28]_i_1_n_0\
);
\a01[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFF5F5"
)
port map (
I0 => \a01[29]_i_2_n_0\,
I1 => \a01[29]_i_3_n_0\,
I2 => \^a01\(29),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[29]_i_5_n_0\,
O => \a01[29]_i_1_n_0\
);
\a01[29]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \cosine[24]_i_7_n_0\,
I1 => \cosine[24]_i_9_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[25]_i_6_n_0\,
I5 => \cosine[7]_i_5_n_0\,
O => \a01[29]_i_10_n_0\
);
\a01[29]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_9_n_0\,
I3 => \cosine[29]_i_11_n_0\,
O => \a01[29]_i_11_n_0\
);
\a01[29]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7FFFFFFFF"
)
port map (
I0 => \cosine[29]_i_30_n_0\,
I1 => \cosine[29]_i_10_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \cosine[29]_i_17_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[19]_i_5_n_0\,
O => \a01[29]_i_12_n_0\
);
\a01[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040000"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[19]_i_5_n_0\,
I2 => \a01[29]_i_6_n_0\,
I3 => \cosine[29]_i_3_n_0\,
I4 => \cosine[29]_i_7_n_0\,
O => \a01[29]_i_2_n_0\
);
\a01[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \a01[29]_i_7_n_0\,
I1 => \cosine[7]_i_5_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[29]_i_4_n_0\,
I5 => \cosine[7]_i_3_n_0\,
O => \a01[29]_i_3_n_0\
);
\a01[29]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \a01[29]_i_7_n_0\,
I1 => \cosine[7]_i_5_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[29]_i_5_n_0\,
I5 => \cosine[7]_i_3_n_0\,
O => \a01[29]_i_4_n_0\
);
\a01[29]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF1FFF1FFF11111"
)
port map (
I0 => \a01[29]_i_8_n_0\,
I1 => \a01[29]_i_9_n_0\,
I2 => \a01[29]_i_7_n_0\,
I3 => \a01[29]_i_10_n_0\,
I4 => \a01[29]_i_11_n_0\,
I5 => \a01[29]_i_12_n_0\,
O => \a01[29]_i_5_n_0\
);
\a01[29]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[24]_i_3_n_0\,
O => \a01[29]_i_6_n_0\
);
\a01[29]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[9]_i_6_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[29]_i_16_n_0\,
I3 => \cosine[24]_i_8_n_0\,
I4 => \cosine[9]_i_5_n_0\,
O => \a01[29]_i_7_n_0\
);
\a01[29]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF7F"
)
port map (
I0 => \cosine[29]_i_30_n_0\,
I1 => \cosine[29]_i_10_n_0\,
I2 => \cosine[19]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[29]_i_17_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \a01[29]_i_8_n_0\
);
\a01[29]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cosine[29]_i_9_n_0\,
I1 => \cosine[29]_i_11_n_0\,
I2 => \cosine[29]_i_7_n_0\,
O => \a01[29]_i_9_n_0\
);
\a01[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3D5E691D5C4F7C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(2),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[2]_i_1_n_0\
);
\a01[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0D5B3A2C4F7E6E6"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(3),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[3]_i_1_n_0\
);
\a01[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3E680B3C4F7E6C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(4),
I3 => \a01[29]_i_3_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[4]_i_1_n_0\
);
\a01[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0A2C4D580F7A280"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(5),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_3_n_0\,
I5 => \a01[29]_i_4_n_0\,
O => \a01[5]_i_1_n_0\
);
\a01[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EDBD2535DDDE5556"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \a01[29]_i_3_n_0\,
I3 => \a01[29]_i_4_n_0\,
I4 => \^a01\(6),
I5 => \a01[25]_i_4_n_0\,
O => \a01[6]_i_1_n_0\
);
\a01[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F391B3A2C4C4A2A2"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(7),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[7]_i_1_n_0\
);
\a01[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2E6B3B3B3E680C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(8),
I3 => \a01[25]_i_4_n_0\,
I4 => \a01[29]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[8]_i_1_n_0\
);
\a01[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3B39191A2A2C4C4"
)
port map (
I0 => \a01[25]_i_2_n_0\,
I1 => \a01[25]_i_3_n_0\,
I2 => \^a01\(9),
I3 => \a01[29]_i_4_n_0\,
I4 => \a01[25]_i_4_n_0\,
I5 => \a01[29]_i_3_n_0\,
O => \a01[9]_i_1_n_0\
);
\a01_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[0]_i_1_n_0\,
Q => \^a01\(0),
R => '0'
);
\a01_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[10]_i_1_n_0\,
Q => \^a01\(10),
R => '0'
);
\a01_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[11]_i_1_n_0\,
Q => \^a01\(11),
R => '0'
);
\a01_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[12]_i_1_n_0\,
Q => \^a01\(12),
R => '0'
);
\a01_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[13]_i_1_n_0\,
Q => \^a01\(13),
R => '0'
);
\a01_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[14]_i_1_n_0\,
Q => \^a01\(14),
R => '0'
);
\a01_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[15]_i_1_n_0\,
Q => \^a01\(15),
R => '0'
);
\a01_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[16]_i_1_n_0\,
Q => \^a01\(16),
R => '0'
);
\a01_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[17]_i_1_n_0\,
Q => \^a01\(17),
R => '0'
);
\a01_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[18]_i_1_n_0\,
Q => \^a01\(18),
R => '0'
);
\a01_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[19]_i_1_n_0\,
Q => \^a01\(19),
R => '0'
);
\a01_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[1]_i_1_n_0\,
Q => \^a01\(1),
R => '0'
);
\a01_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[20]_i_1_n_0\,
Q => \^a01\(20),
R => '0'
);
\a01_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[21]_i_1_n_0\,
Q => \^a01\(21),
R => '0'
);
\a01_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[22]_i_1_n_0\,
Q => \^a01\(22),
R => '0'
);
\a01_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[23]_i_1_n_0\,
Q => \^a01\(23),
R => '0'
);
\a01_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[24]_i_1_n_0\,
Q => \^a01\(24),
R => '0'
);
\a01_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[25]_i_1_n_0\,
Q => \^a01\(25),
R => '0'
);
\a01_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[26]_i_1_n_0\,
Q => \^a01\(26),
R => '0'
);
\a01_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[27]_i_1_n_0\,
Q => \^a01\(27),
R => '0'
);
\a01_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[28]_i_1_n_0\,
Q => \^a01\(28),
R => '0'
);
\a01_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[29]_i_1_n_0\,
Q => \^a01\(29),
R => '0'
);
\a01_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[2]_i_1_n_0\,
Q => \^a01\(2),
R => '0'
);
\a01_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[3]_i_1_n_0\,
Q => \^a01\(3),
R => '0'
);
\a01_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[4]_i_1_n_0\,
Q => \^a01\(4),
R => '0'
);
\a01_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[5]_i_1_n_0\,
Q => \^a01\(5),
R => '0'
);
\a01_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[6]_i_1_n_0\,
Q => \^a01\(6),
R => '0'
);
\a01_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[7]_i_1_n_0\,
Q => \^a01\(7),
R => '0'
);
\a01_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[8]_i_1_n_0\,
Q => \^a01\(8),
R => '0'
);
\a01_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \a01[9]_i_1_n_0\,
Q => \^a01\(9),
R => '0'
);
angle1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => angle1_carry_n_0,
CO(2) => angle1_carry_n_1,
CO(1) => angle1_carry_n_2,
CO(0) => angle1_carry_n_3,
CYINIT => '1',
DI(3) => p_1_in(7),
DI(2) => p_1_in(5),
DI(1) => angle1_carry_i_1_n_0,
DI(0) => '0',
O(3 downto 0) => NLW_angle1_carry_O_UNCONNECTED(3 downto 0),
S(3) => angle1_carry_i_2_n_0,
S(2) => angle1_carry_i_3_n_0,
S(1) => angle1_carry_i_4_n_0,
S(0) => angle1_carry_i_5_n_0
);
\angle1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => angle1_carry_n_0,
CO(3) => \angle1_carry__0_n_0\,
CO(2) => \angle1_carry__0_n_1\,
CO(1) => \angle1_carry__0_n_2\,
CO(0) => \angle1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \angle1_carry__0_i_1_n_0\,
DI(2) => \angle1_carry__0_i_2_n_0\,
DI(1) => \angle1_carry__0_i_3_n_0\,
DI(0) => \angle1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_angle1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \angle1_carry__0_i_5_n_0\,
S(2) => \angle1_carry__0_i_6_n_0\,
S(1) => \angle1_carry__0_i_7_n_0\,
S(0) => \angle1_carry__0_i_8_n_0\
);
\angle1_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(14),
I1 => p_1_in(15),
O => \angle1_carry__0_i_1_n_0\
);
\angle1_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(12),
I1 => p_1_in(13),
O => \angle1_carry__0_i_2_n_0\
);
\angle1_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(10),
I1 => p_1_in(11),
O => \angle1_carry__0_i_3_n_0\
);
\angle1_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(8),
I1 => p_1_in(9),
O => \angle1_carry__0_i_4_n_0\
);
\angle1_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(14),
I1 => p_1_in(15),
O => \angle1_carry__0_i_5_n_0\
);
\angle1_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(12),
I1 => p_1_in(13),
O => \angle1_carry__0_i_6_n_0\
);
\angle1_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(10),
I1 => p_1_in(11),
O => \angle1_carry__0_i_7_n_0\
);
\angle1_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(8),
I1 => p_1_in(9),
O => \angle1_carry__0_i_8_n_0\
);
\angle1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \angle1_carry__0_n_0\,
CO(3) => \angle1_carry__1_n_0\,
CO(2) => \angle1_carry__1_n_1\,
CO(1) => \angle1_carry__1_n_2\,
CO(0) => \angle1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \angle1_carry__1_i_1_n_0\,
DI(2) => \angle1_carry__1_i_2_n_0\,
DI(1) => \angle1_carry__1_i_3_n_0\,
DI(0) => \angle1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_angle1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \angle1_carry__1_i_5_n_0\,
S(2) => \angle1_carry__1_i_6_n_0\,
S(1) => \angle1_carry__1_i_7_n_0\,
S(0) => \angle1_carry__1_i_8_n_0\
);
\angle1_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(22),
I1 => p_1_in(23),
O => \angle1_carry__1_i_1_n_0\
);
\angle1_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(20),
I1 => p_1_in(21),
O => \angle1_carry__1_i_2_n_0\
);
\angle1_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(18),
I1 => p_1_in(19),
O => \angle1_carry__1_i_3_n_0\
);
\angle1_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(16),
I1 => p_1_in(17),
O => \angle1_carry__1_i_4_n_0\
);
\angle1_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(22),
I1 => p_1_in(23),
O => \angle1_carry__1_i_5_n_0\
);
\angle1_carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(20),
I1 => p_1_in(21),
O => \angle1_carry__1_i_6_n_0\
);
\angle1_carry__1_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(18),
I1 => p_1_in(19),
O => \angle1_carry__1_i_7_n_0\
);
\angle1_carry__1_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(16),
I1 => p_1_in(17),
O => \angle1_carry__1_i_8_n_0\
);
\angle1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \angle1_carry__1_n_0\,
CO(3) => \angle1_carry__2_n_0\,
CO(2) => \angle1_carry__2_n_1\,
CO(1) => \angle1_carry__2_n_2\,
CO(0) => \angle1_carry__2_n_3\,
CYINIT => '0',
DI(3) => \angle1_carry__2_i_1_n_0\,
DI(2) => \angle1_carry__2_i_2_n_0\,
DI(1) => \angle1_carry__2_i_3_n_0\,
DI(0) => \angle1_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_angle1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \angle1_carry__2_i_5_n_0\,
S(2) => \angle1_carry__2_i_6_n_0\,
S(1) => \angle1_carry__2_i_7_n_0\,
S(0) => \angle1_carry__2_i_8_n_0\
);
\angle1_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(30),
I1 => p_1_in(31),
O => \angle1_carry__2_i_1_n_0\
);
\angle1_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(28),
I1 => p_1_in(29),
O => \angle1_carry__2_i_2_n_0\
);
\angle1_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(26),
I1 => p_1_in(27),
O => \angle1_carry__2_i_3_n_0\
);
\angle1_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in(24),
I1 => p_1_in(25),
O => \angle1_carry__2_i_4_n_0\
);
\angle1_carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(30),
I1 => p_1_in(31),
O => \angle1_carry__2_i_5_n_0\
);
\angle1_carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(28),
I1 => p_1_in(29),
O => \angle1_carry__2_i_6_n_0\
);
\angle1_carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(26),
I1 => p_1_in(27),
O => \angle1_carry__2_i_7_n_0\
);
\angle1_carry__2_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_1_in(24),
I1 => p_1_in(25),
O => \angle1_carry__2_i_8_n_0\
);
angle1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in(2),
I1 => p_1_in(3),
O => angle1_carry_i_1_n_0
);
angle1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(6),
I1 => p_1_in(7),
O => angle1_carry_i_2_n_0
);
angle1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(4),
I1 => p_1_in(5),
O => angle1_carry_i_3_n_0
);
angle1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(3),
I1 => p_1_in(2),
O => angle1_carry_i_4_n_0
);
angle1_carry_i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(1),
O => angle1_carry_i_5_n_0
);
angle2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => angle2_carry_n_0,
CO(2) => angle2_carry_n_1,
CO(1) => angle2_carry_n_2,
CO(0) => angle2_carry_n_3,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => angle(2),
DI(0) => '0',
O(3 downto 0) => p_1_in(4 downto 1),
S(3) => angle2_carry_i_1_n_0,
S(2) => angle2_carry_i_2_n_0,
S(1) => angle2_carry_i_3_n_0,
S(0) => angle2_carry_i_4_n_0
);
\angle2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => angle2_carry_n_0,
CO(3) => \angle2_carry__0_n_0\,
CO(2) => \angle2_carry__0_n_1\,
CO(1) => \angle2_carry__0_n_2\,
CO(0) => \angle2_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(8 downto 5),
S(3) => \angle2_carry__0_i_1_n_0\,
S(2) => \angle2_carry__0_i_2_n_0\,
S(1) => \angle2_carry__0_i_3_n_0\,
S(0) => \angle2_carry__0_i_4_n_0\
);
\angle2_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(8),
O => \angle2_carry__0_i_1_n_0\
);
\angle2_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(7),
O => \angle2_carry__0_i_2_n_0\
);
\angle2_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(6),
O => \angle2_carry__0_i_3_n_0\
);
\angle2_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(5),
O => \angle2_carry__0_i_4_n_0\
);
\angle2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__0_n_0\,
CO(3) => \angle2_carry__1_n_0\,
CO(2) => \angle2_carry__1_n_1\,
CO(1) => \angle2_carry__1_n_2\,
CO(0) => \angle2_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(12 downto 9),
S(3) => \angle2_carry__1_i_1_n_0\,
S(2) => \angle2_carry__1_i_2_n_0\,
S(1) => \angle2_carry__1_i_3_n_0\,
S(0) => \angle2_carry__1_i_4_n_0\
);
\angle2_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(12),
O => \angle2_carry__1_i_1_n_0\
);
\angle2_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(11),
O => \angle2_carry__1_i_2_n_0\
);
\angle2_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(10),
O => \angle2_carry__1_i_3_n_0\
);
\angle2_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(9),
O => \angle2_carry__1_i_4_n_0\
);
\angle2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__1_n_0\,
CO(3) => \angle2_carry__2_n_0\,
CO(2) => \angle2_carry__2_n_1\,
CO(1) => \angle2_carry__2_n_2\,
CO(0) => \angle2_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(16 downto 13),
S(3) => \angle2_carry__2_i_1_n_0\,
S(2) => \angle2_carry__2_i_2_n_0\,
S(1) => \angle2_carry__2_i_3_n_0\,
S(0) => \angle2_carry__2_i_4_n_0\
);
\angle2_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(16),
O => \angle2_carry__2_i_1_n_0\
);
\angle2_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(15),
O => \angle2_carry__2_i_2_n_0\
);
\angle2_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(14),
O => \angle2_carry__2_i_3_n_0\
);
\angle2_carry__2_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(13),
O => \angle2_carry__2_i_4_n_0\
);
\angle2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__2_n_0\,
CO(3) => \angle2_carry__3_n_0\,
CO(2) => \angle2_carry__3_n_1\,
CO(1) => \angle2_carry__3_n_2\,
CO(0) => \angle2_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(20 downto 17),
S(3) => \angle2_carry__3_i_1_n_0\,
S(2) => \angle2_carry__3_i_2_n_0\,
S(1) => \angle2_carry__3_i_3_n_0\,
S(0) => \angle2_carry__3_i_4_n_0\
);
\angle2_carry__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(20),
O => \angle2_carry__3_i_1_n_0\
);
\angle2_carry__3_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(19),
O => \angle2_carry__3_i_2_n_0\
);
\angle2_carry__3_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(18),
O => \angle2_carry__3_i_3_n_0\
);
\angle2_carry__3_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(17),
O => \angle2_carry__3_i_4_n_0\
);
\angle2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__3_n_0\,
CO(3) => \angle2_carry__4_n_0\,
CO(2) => \angle2_carry__4_n_1\,
CO(1) => \angle2_carry__4_n_2\,
CO(0) => \angle2_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(24 downto 21),
S(3) => \angle2_carry__4_i_1_n_0\,
S(2) => \angle2_carry__4_i_2_n_0\,
S(1) => \angle2_carry__4_i_3_n_0\,
S(0) => \angle2_carry__4_i_4_n_0\
);
\angle2_carry__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(24),
O => \angle2_carry__4_i_1_n_0\
);
\angle2_carry__4_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(23),
O => \angle2_carry__4_i_2_n_0\
);
\angle2_carry__4_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(22),
O => \angle2_carry__4_i_3_n_0\
);
\angle2_carry__4_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(21),
O => \angle2_carry__4_i_4_n_0\
);
\angle2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__4_n_0\,
CO(3) => \angle2_carry__5_n_0\,
CO(2) => \angle2_carry__5_n_1\,
CO(1) => \angle2_carry__5_n_2\,
CO(0) => \angle2_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_1_in(28 downto 25),
S(3) => \angle2_carry__5_i_1_n_0\,
S(2) => \angle2_carry__5_i_2_n_0\,
S(1) => \angle2_carry__5_i_3_n_0\,
S(0) => \angle2_carry__5_i_4_n_0\
);
\angle2_carry__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(28),
O => \angle2_carry__5_i_1_n_0\
);
\angle2_carry__5_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(27),
O => \angle2_carry__5_i_2_n_0\
);
\angle2_carry__5_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(26),
O => \angle2_carry__5_i_3_n_0\
);
\angle2_carry__5_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(25),
O => \angle2_carry__5_i_4_n_0\
);
\angle2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \angle2_carry__5_n_0\,
CO(3 downto 2) => \NLW_angle2_carry__6_CO_UNCONNECTED\(3 downto 2),
CO(1) => \angle2_carry__6_n_2\,
CO(0) => \angle2_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_angle2_carry__6_O_UNCONNECTED\(3),
O(2 downto 0) => p_1_in(31 downto 29),
S(3) => '0',
S(2) => \angle2_carry__6_i_1_n_0\,
S(1) => \angle2_carry__6_i_2_n_0\,
S(0) => \angle2_carry__6_i_3_n_0\
);
\angle2_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(31),
O => \angle2_carry__6_i_1_n_0\
);
\angle2_carry__6_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(30),
O => \angle2_carry__6_i_2_n_0\
);
\angle2_carry__6_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(29),
O => \angle2_carry__6_i_3_n_0\
);
angle2_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(4),
O => angle2_carry_i_1_n_0
);
angle2_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(3),
O => angle2_carry_i_2_n_0
);
angle2_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => angle(2),
O => angle2_carry_i_3_n_0
);
angle2_carry_i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => angle(1),
O => angle2_carry_i_4_n_0
);
\angle[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(10),
I1 => \angle1_carry__2_n_0\,
O => \angle[10]_i_1_n_0\
);
\angle[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(11),
I1 => \angle1_carry__2_n_0\,
O => \angle[11]_i_1_n_0\
);
\angle[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(12),
I1 => \angle1_carry__2_n_0\,
O => \angle[12]_i_1_n_0\
);
\angle[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(13),
I1 => \angle1_carry__2_n_0\,
O => \angle[13]_i_1_n_0\
);
\angle[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(14),
I1 => \angle1_carry__2_n_0\,
O => \angle[14]_i_1_n_0\
);
\angle[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(15),
I1 => \angle1_carry__2_n_0\,
O => \angle[15]_i_1_n_0\
);
\angle[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(16),
I1 => \angle1_carry__2_n_0\,
O => \angle[16]_i_1_n_0\
);
\angle[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(17),
I1 => \angle1_carry__2_n_0\,
O => \angle[17]_i_1_n_0\
);
\angle[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(18),
I1 => \angle1_carry__2_n_0\,
O => \angle[18]_i_1_n_0\
);
\angle[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(19),
I1 => \angle1_carry__2_n_0\,
O => \angle[19]_i_1_n_0\
);
\angle[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(1),
I1 => \angle1_carry__2_n_0\,
O => \angle[1]_i_1_n_0\
);
\angle[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(20),
I1 => \angle1_carry__2_n_0\,
O => \angle[20]_i_1_n_0\
);
\angle[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(21),
I1 => \angle1_carry__2_n_0\,
O => \angle[21]_i_1_n_0\
);
\angle[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(22),
I1 => \angle1_carry__2_n_0\,
O => \angle[22]_i_1_n_0\
);
\angle[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(23),
I1 => \angle1_carry__2_n_0\,
O => \angle[23]_i_1_n_0\
);
\angle[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(24),
I1 => \angle1_carry__2_n_0\,
O => \angle[24]_i_1_n_0\
);
\angle[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(25),
I1 => \angle1_carry__2_n_0\,
O => \angle[25]_i_1_n_0\
);
\angle[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(26),
I1 => \angle1_carry__2_n_0\,
O => \angle[26]_i_1_n_0\
);
\angle[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(27),
I1 => \angle1_carry__2_n_0\,
O => \angle[27]_i_1_n_0\
);
\angle[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(28),
I1 => \angle1_carry__2_n_0\,
O => \angle[28]_i_1_n_0\
);
\angle[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(29),
I1 => \angle1_carry__2_n_0\,
O => \angle[29]_i_1_n_0\
);
\angle[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(2),
I1 => \angle1_carry__2_n_0\,
O => \angle[2]_i_1_n_0\
);
\angle[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(30),
I1 => \angle1_carry__2_n_0\,
O => \angle[30]_i_1_n_0\
);
\angle[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(31),
I1 => \angle1_carry__2_n_0\,
O => \angle[31]_i_1_n_0\
);
\angle[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(3),
I1 => \angle1_carry__2_n_0\,
O => \angle[3]_i_1_n_0\
);
\angle[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(4),
I1 => \angle1_carry__2_n_0\,
O => \angle[4]_i_1_n_0\
);
\angle[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(5),
I1 => \angle1_carry__2_n_0\,
O => \angle[5]_i_1_n_0\
);
\angle[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(6),
I1 => \angle1_carry__2_n_0\,
O => \angle[6]_i_1_n_0\
);
\angle[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(7),
I1 => \angle1_carry__2_n_0\,
O => \angle[7]_i_1_n_0\
);
\angle[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(8),
I1 => \angle1_carry__2_n_0\,
O => \angle[8]_i_1_n_0\
);
\angle[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_1_in(9),
I1 => \angle1_carry__2_n_0\,
O => \angle[9]_i_1_n_0\
);
\angle_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[10]_i_1_n_0\,
Q => angle(10),
R => reset
);
\angle_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[11]_i_1_n_0\,
Q => angle(11),
R => reset
);
\angle_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[12]_i_1_n_0\,
Q => angle(12),
R => reset
);
\angle_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[13]_i_1_n_0\,
Q => angle(13),
R => reset
);
\angle_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[14]_i_1_n_0\,
Q => angle(14),
R => reset
);
\angle_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[15]_i_1_n_0\,
Q => angle(15),
R => reset
);
\angle_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[16]_i_1_n_0\,
Q => angle(16),
R => reset
);
\angle_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[17]_i_1_n_0\,
Q => angle(17),
R => reset
);
\angle_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[18]_i_1_n_0\,
Q => angle(18),
R => reset
);
\angle_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[19]_i_1_n_0\,
Q => angle(19),
R => reset
);
\angle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[1]_i_1_n_0\,
Q => angle(1),
R => reset
);
\angle_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[20]_i_1_n_0\,
Q => angle(20),
R => reset
);
\angle_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[21]_i_1_n_0\,
Q => angle(21),
R => reset
);
\angle_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[22]_i_1_n_0\,
Q => angle(22),
R => reset
);
\angle_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[23]_i_1_n_0\,
Q => angle(23),
R => reset
);
\angle_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[24]_i_1_n_0\,
Q => angle(24),
R => reset
);
\angle_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[25]_i_1_n_0\,
Q => angle(25),
R => reset
);
\angle_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[26]_i_1_n_0\,
Q => angle(26),
R => reset
);
\angle_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[27]_i_1_n_0\,
Q => angle(27),
R => reset
);
\angle_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[28]_i_1_n_0\,
Q => angle(28),
R => reset
);
\angle_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[29]_i_1_n_0\,
Q => angle(29),
R => reset
);
\angle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[2]_i_1_n_0\,
Q => angle(2),
R => reset
);
\angle_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[30]_i_1_n_0\,
Q => angle(30),
R => reset
);
\angle_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[31]_i_1_n_0\,
Q => angle(31),
R => reset
);
\angle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[3]_i_1_n_0\,
Q => angle(3),
R => reset
);
\angle_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[4]_i_1_n_0\,
Q => angle(4),
R => reset
);
\angle_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[5]_i_1_n_0\,
Q => angle(5),
R => reset
);
\angle_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[6]_i_1_n_0\,
Q => angle(6),
R => reset
);
\angle_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[7]_i_1_n_0\,
Q => angle(7),
R => reset
);
\angle_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[8]_i_1_n_0\,
Q => angle(8),
R => reset
);
\angle_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => \counter0_inferred__0/i__carry__2_n_0\,
D => \angle[9]_i_1_n_0\,
Q => angle(9),
R => reset
);
\cosine[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55520C3600000000"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_2_n_0\,
O => \cosine[0]_i_1_n_0\
);
\cosine[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020202000"
)
port map (
I0 => \cosine[10]_i_2_n_0\,
I1 => \cosine[10]_i_3_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[10]_i_4_n_0\,
I5 => \cosine[29]_i_3_n_0\,
O => \cosine[10]_i_1_n_0\
);
\cosine[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"11441FE4"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[25]_i_4_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
O => \cosine[10]_i_2_n_0\
);
\cosine[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[24]_i_3_n_0\,
I2 => \cosine[29]_i_17_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[19]_i_5_n_0\,
O => \cosine[10]_i_3_n_0\
);
\cosine[10]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(6),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(6),
I5 => \cosine[29]_i_4_n_0\,
O => \cosine[10]_i_4_n_0\
);
\cosine[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A37E0"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[22]_i_2_n_0\,
O => \cosine[11]_i_1_n_0\
);
\cosine[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF06A6"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[25]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[12]_i_2_n_0\,
I5 => \cosine[19]_i_3_n_0\,
O => \cosine[12]_i_1_n_0\
);
\cosine[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFB"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[19]_i_5_n_0\,
I2 => \cosine[29]_i_13_n_0\,
I3 => \cosine[29]_i_17_n_0\,
I4 => \cosine[12]_i_3_n_0\,
O => \cosine[12]_i_2_n_0\
);
\cosine[12]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBAAAA"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
O => \cosine[12]_i_3_n_0\
);
\cosine[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF6FFF0FFF4FF14"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[24]_i_5_n_0\,
I4 => \cosine[29]_i_4_n_0\,
I5 => \cosine[25]_i_3_n_0\,
O => \cosine[13]_i_1_n_0\
);
\cosine[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \cosine[14]_i_2_n_0\,
I1 => \cosine[19]_i_6_n_0\,
I2 => \cosine[19]_i_5_n_0\,
I3 => \cosine[14]_i_3_n_0\,
I4 => \cosine[19]_i_3_n_0\,
O => \cosine[14]_i_1_n_0\
);
\cosine[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBAF0044"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
O => \cosine[14]_i_2_n_0\
);
\cosine[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFABBAAAAA"
)
port map (
I0 => \cosine[14]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \cosine[14]_i_3_n_0\
);
\cosine[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(7),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(7),
I5 => \cosine[29]_i_13_n_0\,
O => \cosine[14]_i_4_n_0\
);
\cosine[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBAFFAAEFBEFAAE"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[25]_i_3_n_0\,
O => \cosine[15]_i_1_n_0\
);
\cosine[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000040623F4"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[22]_i_2_n_0\,
O => \cosine[16]_i_1_n_0\
);
\cosine[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFABFBFFFAEEAE"
)
port map (
I0 => \cosine[24]_i_5_n_0\,
I1 => \cosine[25]_i_4_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[17]_i_1_n_0\
);
\cosine[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBABBFEFEEBEE"
)
port map (
I0 => \cosine[24]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[18]_i_1_n_0\
);
\cosine[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \cosine[19]_i_2_n_0\,
I1 => \cosine[19]_i_3_n_0\,
I2 => \cosine[19]_i_4_n_0\,
I3 => \cosine[19]_i_5_n_0\,
I4 => \cosine[19]_i_6_n_0\,
I5 => \cosine[19]_i_7_n_0\,
O => \cosine[19]_i_1_n_0\
);
\cosine[19]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(11),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(11),
I4 => reset,
O => \cosine[19]_i_10_n_0\
);
\cosine[19]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(8),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(8),
I4 => reset,
O => \cosine[19]_i_11_n_0\
);
\cosine[19]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(9),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(9),
I4 => reset,
O => \cosine[19]_i_12_n_0\
);
\cosine[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4C3C"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
O => \cosine[19]_i_2_n_0\
);
\cosine[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \cosine[19]_i_8_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[29]_i_3_n_0\,
O => \cosine[19]_i_3_n_0\
);
\cosine[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEEEEFE"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \cosine[19]_i_4_n_0\
);
\cosine[19]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[19]_i_9_n_0\,
I1 => \cosine[19]_i_10_n_0\,
I2 => \cosine[19]_i_11_n_0\,
I3 => \cosine[19]_i_12_n_0\,
O => \cosine[19]_i_5_n_0\
);
\cosine[19]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \cosine[29]_i_10_n_0\,
I1 => \cosine[29]_i_30_n_0\,
O => \cosine[19]_i_6_n_0\
);
\cosine[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8C38"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
O => \cosine[19]_i_7_n_0\
);
\cosine[19]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABBBBAABAAAAA"
)
port map (
I0 => \cosine[29]_i_16_n_0\,
I1 => reset,
I2 => p_1_in(28),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(28),
O => \cosine[19]_i_8_n_0\
);
\cosine[19]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(10),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(10),
I4 => reset,
O => \cosine[19]_i_9_n_0\
);
\cosine[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFBBFEEFEFFABBA"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_5_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[1]_i_1_n_0\
);
\cosine[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000BBB6"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[29]_i_8_n_0\,
I5 => \cosine[20]_i_2_n_0\,
O => \cosine[20]_i_1_n_0\
);
\cosine[20]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFD5"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_3_n_0\,
O => \cosine[20]_i_2_n_0\
);
\cosine[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004105D7E"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[22]_i_2_n_0\,
O => \cosine[21]_i_1_n_0\
);
\cosine[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0105010105111114"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[29]_i_5_n_0\,
I5 => \cosine[25]_i_4_n_0\,
O => \cosine[22]_i_1_n_0\
);
\cosine[22]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(24),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(24),
I5 => \cosine[29]_i_19_n_0\,
O => \cosine[22]_i_10_n_0\
);
\cosine[22]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(22),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(22),
I5 => \cosine[29]_i_21_n_0\,
O => \cosine[22]_i_11_n_0\
);
\cosine[22]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(26),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(26),
I5 => \cosine[29]_i_29_n_0\,
O => \cosine[22]_i_12_n_0\
);
\cosine[22]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(10),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(10),
I5 => \cosine[19]_i_12_n_0\,
O => \cosine[22]_i_13_n_0\
);
\cosine[22]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(12),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(12),
I5 => \cosine[19]_i_10_n_0\,
O => \cosine[22]_i_14_n_0\
);
\cosine[22]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(8),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(8),
I5 => \cosine[29]_i_17_n_0\,
O => \cosine[22]_i_15_n_0\
);
\cosine[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \cosine[22]_i_3_n_0\,
I1 => \cosine[22]_i_4_n_0\,
I2 => \cosine[22]_i_5_n_0\,
I3 => \cosine[22]_i_6_n_0\,
I4 => \cosine[22]_i_7_n_0\,
I5 => \cosine[22]_i_8_n_0\,
O => \cosine[22]_i_2_n_0\
);
\cosine[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \cosine[22]_i_9_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[22]_i_10_n_0\,
I3 => \cosine[22]_i_11_n_0\,
I4 => \cosine[9]_i_6_n_0\,
I5 => \cosine[22]_i_12_n_0\,
O => \cosine[22]_i_3_n_0\
);
\cosine[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[22]_i_13_n_0\,
I1 => \cosine[22]_i_14_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \cosine[22]_i_15_n_0\,
O => \cosine[22]_i_4_n_0\
);
\cosine[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(18),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(18),
I5 => \cosine[29]_i_25_n_0\,
O => \cosine[22]_i_5_n_0\
);
\cosine[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(20),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(20),
I5 => \cosine[29]_i_23_n_0\,
O => \cosine[22]_i_6_n_0\
);
\cosine[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(14),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(14),
I5 => \cosine[29]_i_35_n_0\,
O => \cosine[22]_i_7_n_0\
);
\cosine[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(16),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(16),
I5 => \cosine[29]_i_33_n_0\,
O => \cosine[22]_i_8_n_0\
);
\cosine[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABBBBAABAAAAA"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => reset,
I2 => p_1_in(29),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(29),
O => \cosine[22]_i_9_n_0\
);
\cosine[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000001D"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[23]_i_2_n_0\,
I4 => \cosine[23]_i_3_n_0\,
I5 => \cosine[29]_i_3_n_0\,
O => \cosine[23]_i_1_n_0\
);
\cosine[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[24]_i_3_n_0\,
I3 => \cosine[25]_i_3_n_0\,
I4 => \cosine[19]_i_5_n_0\,
O => \cosine[23]_i_2_n_0\
);
\cosine[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBAAFBFFFFFFFFFF"
)
port map (
I0 => reset,
I1 => p_1_in(6),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(6),
I5 => \cosine[29]_i_7_n_0\,
O => \cosine[23]_i_3_n_0\
);
\cosine[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020202000"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[29]_i_8_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[29]_i_6_n_0\,
I4 => \cosine[24]_i_4_n_0\,
I5 => \cosine[29]_i_3_n_0\,
O => \cosine[24]_i_1_n_0\
);
\cosine[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEF0FFFFFFFE"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[24]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_5_n_0\,
O => \cosine[24]_i_2_n_0\
);
\cosine[24]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(1),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(1),
I4 => reset,
O => \cosine[24]_i_3_n_0\
);
\cosine[24]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFDDDDFFDFFFFF"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => reset,
I2 => p_1_in(2),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(2),
O => \cosine[24]_i_4_n_0\
);
\cosine[24]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[24]_i_6_n_0\,
I1 => \cosine[24]_i_7_n_0\,
I2 => \cosine[7]_i_5_n_0\,
I3 => \cosine[24]_i_8_n_0\,
I4 => \cosine[24]_i_9_n_0\,
O => \cosine[24]_i_5_n_0\
);
\cosine[24]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[29]_i_14_n_0\,
I1 => \cosine[9]_i_5_n_0\,
I2 => \cosine[29]_i_16_n_0\,
I3 => \cosine[29]_i_13_n_0\,
I4 => \cosine[9]_i_6_n_0\,
O => \cosine[24]_i_6_n_0\
);
\cosine[24]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_35_n_0\,
I1 => \cosine[29]_i_32_n_0\,
I2 => \cosine[19]_i_10_n_0\,
I3 => \cosine[29]_i_34_n_0\,
O => \cosine[24]_i_7_n_0\
);
\cosine[24]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_21_n_0\,
I1 => \cosine[29]_i_18_n_0\,
I2 => \cosine[29]_i_23_n_0\,
I3 => \cosine[29]_i_20_n_0\,
O => \cosine[24]_i_8_n_0\
);
\cosine[24]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_25_n_0\,
I1 => \cosine[29]_i_22_n_0\,
I2 => \cosine[29]_i_33_n_0\,
I3 => \cosine[29]_i_24_n_0\,
O => \cosine[24]_i_9_n_0\
);
\cosine[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"080AAAAAAAAAAAA8"
)
port map (
I0 => \cosine[25]_i_2_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
I5 => \cosine[25]_i_5_n_0\,
O => \cosine[25]_i_1_n_0\
);
\cosine[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => \cosine[29]_i_7_n_0\,
I1 => \cosine[29]_i_3_n_0\,
I2 => \cosine[25]_i_6_n_0\,
I3 => \cosine[29]_i_17_n_0\,
I4 => \cosine[19]_i_5_n_0\,
I5 => \cosine[19]_i_6_n_0\,
O => \cosine[25]_i_2_n_0\
);
\cosine[25]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(5),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(5),
I4 => reset,
O => \cosine[25]_i_3_n_0\
);
\cosine[25]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(4),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(4),
I4 => reset,
O => \cosine[25]_i_4_n_0\
);
\cosine[25]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(6),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(6),
I4 => reset,
O => \cosine[25]_i_5_n_0\
);
\cosine[25]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[25]_i_3_n_0\,
O => \cosine[25]_i_6_n_0\
);
\cosine[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055150000"
)
port map (
I0 => \cosine[29]_i_3_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[29]_i_6_n_0\,
I4 => \cosine[29]_i_7_n_0\,
I5 => \cosine[29]_i_8_n_0\,
O => p_0_out
);
\cosine[29]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_22_n_0\,
I1 => \cosine[29]_i_23_n_0\,
I2 => \cosine[29]_i_24_n_0\,
I3 => \cosine[29]_i_25_n_0\,
O => \cosine[29]_i_10_n_0\
);
\cosine[29]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_26_n_0\,
I1 => \cosine[29]_i_27_n_0\,
I2 => \cosine[29]_i_28_n_0\,
I3 => \cosine[29]_i_29_n_0\,
O => \cosine[29]_i_11_n_0\
);
\cosine[29]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => \cosine[19]_i_5_n_0\,
I1 => \cosine[29]_i_30_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[24]_i_3_n_0\,
I5 => \cosine[29]_i_31_n_0\,
O => \cosine[29]_i_12_n_0\
);
\cosine[29]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(31),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(31),
I4 => reset,
O => \cosine[29]_i_13_n_0\
);
\cosine[29]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(30),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(30),
I4 => reset,
O => \cosine[29]_i_14_n_0\
);
\cosine[29]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(28),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(28),
I4 => reset,
O => \cosine[29]_i_15_n_0\
);
\cosine[29]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(29),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(29),
I4 => reset,
O => \cosine[29]_i_16_n_0\
);
\cosine[29]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(7),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(7),
I4 => reset,
O => \cosine[29]_i_17_n_0\
);
\cosine[29]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(22),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(22),
I4 => reset,
O => \cosine[29]_i_18_n_0\
);
\cosine[29]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(23),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(23),
I4 => reset,
O => \cosine[29]_i_19_n_0\
);
\cosine[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \cosine[29]_i_9_n_0\,
I1 => \cosine[29]_i_10_n_0\,
I2 => \cosine[29]_i_7_n_0\,
I3 => \cosine[29]_i_11_n_0\,
I4 => \cosine[29]_i_12_n_0\,
O => \cosine[29]_i_2_n_0\
);
\cosine[29]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(20),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(20),
I4 => reset,
O => \cosine[29]_i_20_n_0\
);
\cosine[29]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(21),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(21),
I4 => reset,
O => \cosine[29]_i_21_n_0\
);
\cosine[29]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(18),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(18),
I4 => reset,
O => \cosine[29]_i_22_n_0\
);
\cosine[29]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(19),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(19),
I4 => reset,
O => \cosine[29]_i_23_n_0\
);
\cosine[29]_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(16),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(16),
I4 => reset,
O => \cosine[29]_i_24_n_0\
);
\cosine[29]_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(17),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(17),
I4 => reset,
O => \cosine[29]_i_25_n_0\
);
\cosine[29]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(26),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(26),
I4 => reset,
O => \cosine[29]_i_26_n_0\
);
\cosine[29]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(27),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(27),
I4 => reset,
O => \cosine[29]_i_27_n_0\
);
\cosine[29]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(24),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(24),
I4 => reset,
O => \cosine[29]_i_28_n_0\
);
\cosine[29]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(25),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(25),
I4 => reset,
O => \cosine[29]_i_29_n_0\
);
\cosine[29]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \cosine[29]_i_11_n_0\,
I1 => \cosine[29]_i_9_n_0\,
O => \cosine[29]_i_3_n_0\
);
\cosine[29]_i_30\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_32_n_0\,
I1 => \cosine[29]_i_33_n_0\,
I2 => \cosine[29]_i_34_n_0\,
I3 => \cosine[29]_i_35_n_0\,
O => \cosine[29]_i_30_n_0\
);
\cosine[29]_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[25]_i_5_n_0\,
I1 => \cosine[29]_i_17_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_3_n_0\,
O => \cosine[29]_i_31_n_0\
);
\cosine[29]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(14),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(14),
I4 => reset,
O => \cosine[29]_i_32_n_0\
);
\cosine[29]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(15),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(15),
I4 => reset,
O => \cosine[29]_i_33_n_0\
);
\cosine[29]_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(12),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(12),
I4 => reset,
O => \cosine[29]_i_34_n_0\
);
\cosine[29]_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(13),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(13),
I4 => reset,
O => \cosine[29]_i_35_n_0\
);
\cosine[29]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(3),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(3),
I4 => reset,
O => \cosine[29]_i_4_n_0\
);
\cosine[29]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002E22"
)
port map (
I0 => angle(2),
I1 => \counter0_inferred__0/i__carry__2_n_0\,
I2 => \angle1_carry__2_n_0\,
I3 => p_1_in(2),
I4 => reset,
O => \cosine[29]_i_5_n_0\
);
\cosine[29]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFDDDDFFDFFFFF"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => reset,
I2 => p_1_in(6),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(6),
O => \cosine[29]_i_6_n_0\
);
\cosine[29]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => \cosine[29]_i_14_n_0\,
I2 => \cosine[29]_i_15_n_0\,
I3 => \cosine[29]_i_16_n_0\,
O => \cosine[29]_i_7_n_0\
);
\cosine[29]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => \cosine[19]_i_6_n_0\,
I1 => \cosine[24]_i_3_n_0\,
I2 => \cosine[29]_i_17_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[19]_i_5_n_0\,
O => \cosine[29]_i_8_n_0\
);
\cosine[29]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \cosine[29]_i_18_n_0\,
I1 => \cosine[29]_i_19_n_0\,
I2 => \cosine[29]_i_20_n_0\,
I3 => \cosine[29]_i_21_n_0\,
O => \cosine[29]_i_9_n_0\
);
\cosine[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FECEFFEFFEFFFFFE"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[22]_i_2_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[29]_i_4_n_0\,
I5 => \cosine[29]_i_5_n_0\,
O => \cosine[2]_i_1_n_0\
);
\cosine[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100040501051150"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_4_n_0\,
O => \cosine[3]_i_1_n_0\
);
\cosine[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \cosine[4]_i_2_n_0\,
I1 => \cosine[19]_i_6_n_0\,
I2 => \cosine[19]_i_5_n_0\,
I3 => \cosine[4]_i_3_n_0\,
I4 => \cosine[29]_i_3_n_0\,
I5 => \cosine[29]_i_7_n_0\,
O => \cosine[4]_i_1_n_0\
);
\cosine[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF331D0C"
)
port map (
I0 => \cosine[25]_i_3_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[29]_i_4_n_0\,
O => \cosine[4]_i_2_n_0\
);
\cosine[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEAEAAA"
)
port map (
I0 => \cosine[29]_i_17_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[24]_i_3_n_0\,
O => \cosine[4]_i_3_n_0\
);
\cosine[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00150514"
)
port map (
I0 => \cosine[22]_i_2_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[25]_i_4_n_0\,
I4 => \cosine[29]_i_4_n_0\,
O => \cosine[5]_i_1_n_0\
);
\cosine[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFAFFFFFFFF"
)
port map (
I0 => \cosine[24]_i_3_n_0\,
I1 => \cosine[25]_i_5_n_0\,
I2 => \cosine[24]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[6]_i_2_n_0\,
O => \cosine[6]_i_1_n_0\
);
\cosine[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"82979D9D"
)
port map (
I0 => \cosine[29]_i_5_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_4_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
O => \cosine[6]_i_2_n_0\
);
\cosine[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[7]_i_2_n_0\,
I1 => \cosine[7]_i_3_n_0\,
I2 => \cosine[7]_i_4_n_0\,
I3 => \cosine[7]_i_5_n_0\,
I4 => \cosine[9]_i_3_n_0\,
O => \cosine[7]_i_1_n_0\
);
\cosine[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F7000A0"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[29]_i_5_n_0\,
I3 => \cosine[25]_i_5_n_0\,
I4 => \cosine[25]_i_4_n_0\,
O => \cosine[7]_i_2_n_0\
);
\cosine[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cosine[24]_i_9_n_0\,
I1 => \cosine[24]_i_7_n_0\,
O => \cosine[7]_i_3_n_0\
);
\cosine[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEEEFEFFEEEE"
)
port map (
I0 => \cosine[29]_i_13_n_0\,
I1 => \cosine[29]_i_16_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[29]_i_4_n_0\,
I4 => \cosine[25]_i_3_n_0\,
I5 => \cosine[25]_i_4_n_0\,
O => \cosine[7]_i_4_n_0\
);
\cosine[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[19]_i_12_n_0\,
I1 => \cosine[19]_i_9_n_0\,
I2 => \cosine[29]_i_17_n_0\,
I3 => \cosine[19]_i_11_n_0\,
O => \cosine[7]_i_5_n_0\
);
\cosine[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000444000000000"
)
port map (
I0 => \cosine[29]_i_8_n_0\,
I1 => \cosine[29]_i_7_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[8]_i_2_n_0\,
I4 => \cosine[29]_i_3_n_0\,
I5 => \cosine[8]_i_3_n_0\,
O => \cosine[8]_i_1_n_0\
);
\cosine[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA9A9999AA9AAAAA"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => reset,
I2 => p_1_in(4),
I3 => \angle1_carry__2_n_0\,
I4 => \counter0_inferred__0/i__carry__2_n_0\,
I5 => angle(4),
O => \cosine[8]_i_2_n_0\
);
\cosine[8]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"33DD3FD3"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[29]_i_4_n_0\,
I2 => \cosine[25]_i_3_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[25]_i_5_n_0\,
O => \cosine[8]_i_3_n_0\
);
\cosine[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF6A"
)
port map (
I0 => \cosine[29]_i_4_n_0\,
I1 => \cosine[29]_i_5_n_0\,
I2 => \cosine[25]_i_4_n_0\,
I3 => \cosine[9]_i_2_n_0\,
I4 => \cosine[9]_i_3_n_0\,
O => \cosine[9]_i_1_n_0\
);
\cosine[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[7]_i_3_n_0\,
I1 => \cosine[29]_i_13_n_0\,
I2 => \cosine[29]_i_16_n_0\,
I3 => \cosine[9]_i_4_n_0\,
I4 => \cosine[7]_i_5_n_0\,
O => \cosine[9]_i_2_n_0\
);
\cosine[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \cosine[9]_i_5_n_0\,
I1 => \cosine[24]_i_8_n_0\,
I2 => \cosine[29]_i_14_n_0\,
I3 => \cosine[9]_i_6_n_0\,
I4 => \cosine[24]_i_3_n_0\,
O => \cosine[9]_i_3_n_0\
);
\cosine[9]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0CCD0"
)
port map (
I0 => \cosine[25]_i_4_n_0\,
I1 => \cosine[25]_i_3_n_0\,
I2 => \cosine[25]_i_5_n_0\,
I3 => \cosine[29]_i_5_n_0\,
I4 => \cosine[29]_i_4_n_0\,
O => \cosine[9]_i_4_n_0\
);
\cosine[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \cosine[29]_i_29_n_0\,
I1 => \cosine[29]_i_26_n_0\,
I2 => \cosine[29]_i_19_n_0\,
I3 => \cosine[29]_i_28_n_0\,
O => \cosine[9]_i_5_n_0\
);
\cosine[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF04550400"
)
port map (
I0 => reset,
I1 => p_1_in(28),
I2 => \angle1_carry__2_n_0\,
I3 => \counter0_inferred__0/i__carry__2_n_0\,
I4 => angle(28),
I5 => \cosine[29]_i_27_n_0\,
O => \cosine[9]_i_6_n_0\
);
\cosine_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[0]_i_1_n_0\,
Q => a00(0),
R => '0'
);
\cosine_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[10]_i_1_n_0\,
Q => a00(10),
R => '0'
);
\cosine_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[11]_i_1_n_0\,
Q => a00(11),
R => '0'
);
\cosine_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[12]_i_1_n_0\,
Q => a00(12),
R => '0'
);
\cosine_reg[13]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[13]_i_1_n_0\,
Q => a00(13),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[14]_i_1_n_0\,
Q => a00(14),
R => '0'
);
\cosine_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[15]_i_1_n_0\,
Q => a00(15),
R => '0'
);
\cosine_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[16]_i_1_n_0\,
Q => a00(16),
R => '0'
);
\cosine_reg[17]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[17]_i_1_n_0\,
Q => a00(17),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[18]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[18]_i_1_n_0\,
Q => a00(18),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[19]_i_1_n_0\,
Q => a00(19),
R => '0'
);
\cosine_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[1]_i_1_n_0\,
Q => a00(1),
R => '0'
);
\cosine_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[20]_i_1_n_0\,
Q => a00(20),
R => '0'
);
\cosine_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[21]_i_1_n_0\,
Q => a00(21),
R => '0'
);
\cosine_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[22]_i_1_n_0\,
Q => a00(22),
R => '0'
);
\cosine_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[23]_i_1_n_0\,
Q => a00(23),
R => '0'
);
\cosine_reg[24]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[24]_i_2_n_0\,
Q => a00(24),
S => \cosine[24]_i_1_n_0\
);
\cosine_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[25]_i_1_n_0\,
Q => a00(25),
R => '0'
);
\cosine_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[29]_i_2_n_0\,
Q => a00(26),
R => '0'
);
\cosine_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[2]_i_1_n_0\,
Q => a00(2),
R => '0'
);
\cosine_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[3]_i_1_n_0\,
Q => a00(3),
R => '0'
);
\cosine_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[4]_i_1_n_0\,
Q => a00(4),
R => '0'
);
\cosine_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[5]_i_1_n_0\,
Q => a00(5),
R => '0'
);
\cosine_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[6]_i_1_n_0\,
Q => a00(6),
R => '0'
);
\cosine_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[7]_i_1_n_0\,
Q => a00(7),
R => '0'
);
\cosine_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[8]_i_1_n_0\,
Q => a00(8),
R => '0'
);
\cosine_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => p_0_out,
D => \cosine[9]_i_1_n_0\,
Q => a00(9),
R => '0'
);
\counter0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter0_inferred__0/i__carry_n_0\,
CO(2) => \counter0_inferred__0/i__carry_n_1\,
CO(1) => \counter0_inferred__0/i__carry_n_2\,
CO(0) => \counter0_inferred__0/i__carry_n_3\,
CYINIT => '1',
DI(3) => p_0_in(7),
DI(2) => \i__carry_i_2_n_0\,
DI(1) => \i__carry_i_3_n_0\,
DI(0) => \i__carry_i_4_n_0\,
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_5_n_0\,
S(2) => \i__carry_i_6_n_0\,
S(1) => \i__carry_i_7_n_0\,
S(0) => \i__carry_i_8_n_0\
);
\counter0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \counter0_inferred__0/i__carry_n_0\,
CO(3) => \counter0_inferred__0/i__carry__0_n_0\,
CO(2) => \counter0_inferred__0/i__carry__0_n_1\,
CO(1) => \counter0_inferred__0/i__carry__0_n_2\,
CO(0) => \counter0_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => p_0_in(15),
DI(2) => '0',
DI(1) => \i__carry__0_i_2_n_0\,
DI(0) => \i__carry__0_i_3_n_0\,
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__0_i_4_n_0\,
S(2) => \i__carry__0_i_5_n_0\,
S(1) => \i__carry__0_i_6_n_0\,
S(0) => \i__carry__0_i_7_n_0\
);
\counter0_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \counter0_inferred__0/i__carry__0_n_0\,
CO(3) => \counter0_inferred__0/i__carry__1_n_0\,
CO(2) => \counter0_inferred__0/i__carry__1_n_1\,
CO(1) => \counter0_inferred__0/i__carry__1_n_2\,
CO(0) => \counter0_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3) => p_0_in(23),
DI(2 downto 1) => B"00",
DI(0) => p_0_in(17),
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__1_i_3_n_0\,
S(2) => \i__carry__1_i_4_n_0\,
S(1) => \i__carry__1_i_5_n_0\,
S(0) => \i__carry__1_i_6_n_0\
);
\counter0_inferred__0/i__carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \counter0_inferred__0/i__carry__1_n_0\,
CO(3) => \counter0_inferred__0/i__carry__2_n_0\,
CO(2) => \counter0_inferred__0/i__carry__2_n_1\,
CO(1) => \counter0_inferred__0/i__carry__2_n_2\,
CO(0) => \counter0_inferred__0/i__carry__2_n_3\,
CYINIT => '0',
DI(3) => \i__carry__2_i_1_n_0\,
DI(2) => \i__carry__2_i_2_n_0\,
DI(1) => \i__carry__2_i_3_n_0\,
DI(0) => p_0_in(25),
O(3 downto 0) => \NLW_counter0_inferred__0/i__carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__2_i_5_n_0\,
S(2) => \i__carry__2_i_6_n_0\,
S(1) => \i__carry__2_i_7_n_0\,
S(0) => \i__carry__2_i_8_n_0\
);
\counter[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => reset,
I1 => \counter0_inferred__0/i__carry__2_n_0\,
O => \counter[0]_i_1_n_0\
);
\counter[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(3),
O => \counter[0]_i_3_n_0\
);
\counter[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(2),
O => \counter[0]_i_4_n_0\
);
\counter[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(1),
O => \counter[0]_i_5_n_0\
);
\counter[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(0),
O => p_0_in(0)
);
\counter[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(15),
O => \counter[12]_i_2_n_0\
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(14),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(13),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(12),
O => \counter[12]_i_5_n_0\
);
\counter[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(19),
O => \counter[16]_i_2_n_0\
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(18),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(17),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(16),
O => \counter[16]_i_5_n_0\
);
\counter[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(23),
O => \counter[20]_i_2_n_0\
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(22),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(21),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(20),
O => \counter[20]_i_5_n_0\
);
\counter[24]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(27),
O => \counter[24]_i_2_n_0\
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(26),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(25),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(24),
O => \counter[24]_i_5_n_0\
);
\counter[28]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(31),
O => \counter[28]_i_2_n_0\
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(30),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(29),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(28),
O => \counter[28]_i_5_n_0\
);
\counter[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(7),
O => \counter[4]_i_2_n_0\
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(6),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(5),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(4),
O => \counter[4]_i_5_n_0\
);
\counter[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(11),
O => \counter[8]_i_2_n_0\
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(10),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(9),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(8),
O => \counter[8]_i_5_n_0\
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_7\,
Q => counter_reg(0),
R => \counter[0]_i_1_n_0\
);
\counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[0]_i_2_n_0\,
CO(2) => \counter_reg[0]_i_2_n_1\,
CO(1) => \counter_reg[0]_i_2_n_2\,
CO(0) => \counter_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \counter_reg[0]_i_2_n_4\,
O(2) => \counter_reg[0]_i_2_n_5\,
O(1) => \counter_reg[0]_i_2_n_6\,
O(0) => \counter_reg[0]_i_2_n_7\,
S(3) => \counter[0]_i_3_n_0\,
S(2) => \counter[0]_i_4_n_0\,
S(1) => \counter[0]_i_5_n_0\,
S(0) => p_0_in(0)
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_5\,
Q => counter_reg(10),
R => \counter[0]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_4\,
Q => counter_reg(11),
R => \counter[0]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_7\,
Q => counter_reg(12),
R => \counter[0]_i_1_n_0\
);
\counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_1_n_0\,
CO(3) => \counter_reg[12]_i_1_n_0\,
CO(2) => \counter_reg[12]_i_1_n_1\,
CO(1) => \counter_reg[12]_i_1_n_2\,
CO(0) => \counter_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_1_n_4\,
O(2) => \counter_reg[12]_i_1_n_5\,
O(1) => \counter_reg[12]_i_1_n_6\,
O(0) => \counter_reg[12]_i_1_n_7\,
S(3) => \counter[12]_i_2_n_0\,
S(2) => \counter[12]_i_3_n_0\,
S(1) => \counter[12]_i_4_n_0\,
S(0) => \counter[12]_i_5_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_6\,
Q => counter_reg(13),
R => \counter[0]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_5\,
Q => counter_reg(14),
R => \counter[0]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[12]_i_1_n_4\,
Q => counter_reg(15),
R => \counter[0]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_7\,
Q => counter_reg(16),
R => \counter[0]_i_1_n_0\
);
\counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_1_n_0\,
CO(3) => \counter_reg[16]_i_1_n_0\,
CO(2) => \counter_reg[16]_i_1_n_1\,
CO(1) => \counter_reg[16]_i_1_n_2\,
CO(0) => \counter_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_1_n_4\,
O(2) => \counter_reg[16]_i_1_n_5\,
O(1) => \counter_reg[16]_i_1_n_6\,
O(0) => \counter_reg[16]_i_1_n_7\,
S(3) => \counter[16]_i_2_n_0\,
S(2) => \counter[16]_i_3_n_0\,
S(1) => \counter[16]_i_4_n_0\,
S(0) => \counter[16]_i_5_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_6\,
Q => counter_reg(17),
R => \counter[0]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_5\,
Q => counter_reg(18),
R => \counter[0]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[16]_i_1_n_4\,
Q => counter_reg(19),
R => \counter[0]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_6\,
Q => counter_reg(1),
R => \counter[0]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_7\,
Q => counter_reg(20),
R => \counter[0]_i_1_n_0\
);
\counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_1_n_0\,
CO(3) => \counter_reg[20]_i_1_n_0\,
CO(2) => \counter_reg[20]_i_1_n_1\,
CO(1) => \counter_reg[20]_i_1_n_2\,
CO(0) => \counter_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_1_n_4\,
O(2) => \counter_reg[20]_i_1_n_5\,
O(1) => \counter_reg[20]_i_1_n_6\,
O(0) => \counter_reg[20]_i_1_n_7\,
S(3) => \counter[20]_i_2_n_0\,
S(2) => \counter[20]_i_3_n_0\,
S(1) => \counter[20]_i_4_n_0\,
S(0) => \counter[20]_i_5_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_6\,
Q => counter_reg(21),
R => \counter[0]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_5\,
Q => counter_reg(22),
R => \counter[0]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[20]_i_1_n_4\,
Q => counter_reg(23),
R => \counter[0]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_7\,
Q => counter_reg(24),
R => \counter[0]_i_1_n_0\
);
\counter_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_1_n_0\,
CO(3) => \counter_reg[24]_i_1_n_0\,
CO(2) => \counter_reg[24]_i_1_n_1\,
CO(1) => \counter_reg[24]_i_1_n_2\,
CO(0) => \counter_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_1_n_4\,
O(2) => \counter_reg[24]_i_1_n_5\,
O(1) => \counter_reg[24]_i_1_n_6\,
O(0) => \counter_reg[24]_i_1_n_7\,
S(3) => \counter[24]_i_2_n_0\,
S(2) => \counter[24]_i_3_n_0\,
S(1) => \counter[24]_i_4_n_0\,
S(0) => \counter[24]_i_5_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_6\,
Q => counter_reg(25),
R => \counter[0]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_5\,
Q => counter_reg(26),
R => \counter[0]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[24]_i_1_n_4\,
Q => counter_reg(27),
R => \counter[0]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_7\,
Q => counter_reg(28),
R => \counter[0]_i_1_n_0\
);
\counter_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_1_n_0\,
CO(3) => \NLW_counter_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \counter_reg[28]_i_1_n_1\,
CO(1) => \counter_reg[28]_i_1_n_2\,
CO(0) => \counter_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_1_n_4\,
O(2) => \counter_reg[28]_i_1_n_5\,
O(1) => \counter_reg[28]_i_1_n_6\,
O(0) => \counter_reg[28]_i_1_n_7\,
S(3) => \counter[28]_i_2_n_0\,
S(2) => \counter[28]_i_3_n_0\,
S(1) => \counter[28]_i_4_n_0\,
S(0) => \counter[28]_i_5_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_6\,
Q => counter_reg(29),
R => \counter[0]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_5\,
Q => counter_reg(2),
R => \counter[0]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_5\,
Q => counter_reg(30),
R => \counter[0]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[28]_i_1_n_4\,
Q => counter_reg(31),
R => \counter[0]_i_1_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[0]_i_2_n_4\,
Q => counter_reg(3),
R => \counter[0]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_7\,
Q => counter_reg(4),
R => \counter[0]_i_1_n_0\
);
\counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[0]_i_2_n_0\,
CO(3) => \counter_reg[4]_i_1_n_0\,
CO(2) => \counter_reg[4]_i_1_n_1\,
CO(1) => \counter_reg[4]_i_1_n_2\,
CO(0) => \counter_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_1_n_4\,
O(2) => \counter_reg[4]_i_1_n_5\,
O(1) => \counter_reg[4]_i_1_n_6\,
O(0) => \counter_reg[4]_i_1_n_7\,
S(3) => \counter[4]_i_2_n_0\,
S(2) => \counter[4]_i_3_n_0\,
S(1) => \counter[4]_i_4_n_0\,
S(0) => \counter[4]_i_5_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_6\,
Q => counter_reg(5),
R => \counter[0]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_5\,
Q => counter_reg(6),
R => \counter[0]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[4]_i_1_n_4\,
Q => counter_reg(7),
R => \counter[0]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_7\,
Q => counter_reg(8),
R => \counter[0]_i_1_n_0\
);
\counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_1_n_0\,
CO(3) => \counter_reg[8]_i_1_n_0\,
CO(2) => \counter_reg[8]_i_1_n_1\,
CO(1) => \counter_reg[8]_i_1_n_2\,
CO(0) => \counter_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_1_n_4\,
O(2) => \counter_reg[8]_i_1_n_5\,
O(1) => \counter_reg[8]_i_1_n_6\,
O(0) => \counter_reg[8]_i_1_n_7\,
S(3) => \counter[8]_i_2_n_0\,
S(2) => \counter[8]_i_3_n_0\,
S(1) => \counter[8]_i_4_n_0\,
S(0) => \counter[8]_i_5_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \counter_reg[8]_i_1_n_6\,
Q => counter_reg(9),
R => \counter[0]_i_1_n_0\
);
\i__carry__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__0_i_8_n_0\,
CO(3) => \i__carry__0_i_1_n_0\,
CO(2) => \i__carry__0_i_1_n_1\,
CO(1) => \i__carry__0_i_1_n_2\,
CO(0) => \i__carry__0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(16 downto 13),
S(3) => \i__carry__0_i_9_n_0\,
S(2) => \i__carry__0_i_10_n_0\,
S(1) => \i__carry__0_i_11_n_0\,
S(0) => \i__carry__0_i_12_n_0\
);
\i__carry__0_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(15),
O => \i__carry__0_i_10_n_0\
);
\i__carry__0_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(14),
O => \i__carry__0_i_11_n_0\
);
\i__carry__0_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(13),
O => \i__carry__0_i_12_n_0\
);
\i__carry__0_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(12),
O => \i__carry__0_i_13_n_0\
);
\i__carry__0_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(11),
O => \i__carry__0_i_14_n_0\
);
\i__carry__0_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(10),
O => \i__carry__0_i_15_n_0\
);
\i__carry__0_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(9),
O => \i__carry__0_i_16_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(10),
I1 => p_0_in(11),
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(8),
I1 => p_0_in(9),
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(14),
I1 => p_0_in(15),
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(12),
I1 => p_0_in(13),
O => \i__carry__0_i_5_n_0\
);
\i__carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(11),
I1 => p_0_in(10),
O => \i__carry__0_i_6_n_0\
);
\i__carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(8),
I1 => p_0_in(9),
O => \i__carry__0_i_7_n_0\
);
\i__carry__0_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry_i_1_n_0\,
CO(3) => \i__carry__0_i_8_n_0\,
CO(2) => \i__carry__0_i_8_n_1\,
CO(1) => \i__carry__0_i_8_n_2\,
CO(0) => \i__carry__0_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(12 downto 9),
S(3) => \i__carry__0_i_13_n_0\,
S(2) => \i__carry__0_i_14_n_0\,
S(1) => \i__carry__0_i_15_n_0\,
S(0) => \i__carry__0_i_16_n_0\
);
\i__carry__0_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(16),
O => \i__carry__0_i_9_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__1_i_2_n_0\,
CO(3) => \i__carry__1_i_1_n_0\,
CO(2) => \i__carry__1_i_1_n_1\,
CO(1) => \i__carry__1_i_1_n_2\,
CO(0) => \i__carry__1_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(24 downto 21),
S(3) => \i__carry__1_i_7_n_0\,
S(2) => \i__carry__1_i_8_n_0\,
S(1) => \i__carry__1_i_9_n_0\,
S(0) => \i__carry__1_i_10_n_0\
);
\i__carry__1_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(21),
O => \i__carry__1_i_10_n_0\
);
\i__carry__1_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(20),
O => \i__carry__1_i_11_n_0\
);
\i__carry__1_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(19),
O => \i__carry__1_i_12_n_0\
);
\i__carry__1_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(18),
O => \i__carry__1_i_13_n_0\
);
\i__carry__1_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(17),
O => \i__carry__1_i_14_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__0_i_1_n_0\,
CO(3) => \i__carry__1_i_2_n_0\,
CO(2) => \i__carry__1_i_2_n_1\,
CO(1) => \i__carry__1_i_2_n_2\,
CO(0) => \i__carry__1_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(20 downto 17),
S(3) => \i__carry__1_i_11_n_0\,
S(2) => \i__carry__1_i_12_n_0\,
S(1) => \i__carry__1_i_13_n_0\,
S(0) => \i__carry__1_i_14_n_0\
);
\i__carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(22),
I1 => p_0_in(23),
O => \i__carry__1_i_3_n_0\
);
\i__carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(20),
I1 => p_0_in(21),
O => \i__carry__1_i_4_n_0\
);
\i__carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(18),
I1 => p_0_in(19),
O => \i__carry__1_i_5_n_0\
);
\i__carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(16),
I1 => p_0_in(17),
O => \i__carry__1_i_6_n_0\
);
\i__carry__1_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(24),
O => \i__carry__1_i_7_n_0\
);
\i__carry__1_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(23),
O => \i__carry__1_i_8_n_0\
);
\i__carry__1_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(22),
O => \i__carry__1_i_9_n_0\
);
\i__carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(30),
I1 => p_0_in(31),
O => \i__carry__2_i_1_n_0\
);
\i__carry__2_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(28),
O => \i__carry__2_i_10_n_0\
);
\i__carry__2_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(27),
O => \i__carry__2_i_11_n_0\
);
\i__carry__2_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(26),
O => \i__carry__2_i_12_n_0\
);
\i__carry__2_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(25),
O => \i__carry__2_i_13_n_0\
);
\i__carry__2_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(31),
O => \i__carry__2_i_14_n_0\
);
\i__carry__2_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(30),
O => \i__carry__2_i_15_n_0\
);
\i__carry__2_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(29),
O => \i__carry__2_i_16_n_0\
);
\i__carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(28),
I1 => p_0_in(29),
O => \i__carry__2_i_2_n_0\
);
\i__carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(26),
I1 => p_0_in(27),
O => \i__carry__2_i_3_n_0\
);
\i__carry__2_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__1_i_1_n_0\,
CO(3) => \i__carry__2_i_4_n_0\,
CO(2) => \i__carry__2_i_4_n_1\,
CO(1) => \i__carry__2_i_4_n_2\,
CO(0) => \i__carry__2_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(28 downto 25),
S(3) => \i__carry__2_i_10_n_0\,
S(2) => \i__carry__2_i_11_n_0\,
S(1) => \i__carry__2_i_12_n_0\,
S(0) => \i__carry__2_i_13_n_0\
);
\i__carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(30),
I1 => p_0_in(31),
O => \i__carry__2_i_5_n_0\
);
\i__carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(28),
I1 => p_0_in(29),
O => \i__carry__2_i_6_n_0\
);
\i__carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(26),
I1 => p_0_in(27),
O => \i__carry__2_i_7_n_0\
);
\i__carry__2_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(24),
I1 => p_0_in(25),
O => \i__carry__2_i_8_n_0\
);
\i__carry__2_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry__2_i_4_n_0\,
CO(3 downto 2) => \NLW_i__carry__2_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \i__carry__2_i_9_n_2\,
CO(0) => \i__carry__2_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_i__carry__2_i_9_O_UNCONNECTED\(3),
O(2 downto 0) => p_0_in(31 downto 29),
S(3) => '0',
S(2) => \i__carry__2_i_14_n_0\,
S(1) => \i__carry__2_i_15_n_0\,
S(0) => \i__carry__2_i_16_n_0\
);
\i__carry_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \i__carry_i_9_n_0\,
CO(3) => \i__carry_i_1_n_0\,
CO(2) => \i__carry_i_1_n_1\,
CO(1) => \i__carry_i_1_n_2\,
CO(0) => \i__carry_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(8 downto 5),
S(3) => \i__carry_i_10_n_0\,
S(2) => \i__carry_i_11_n_0\,
S(1) => \i__carry_i_12_n_0\,
S(0) => \i__carry_i_13_n_0\
);
\i__carry_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(8),
O => \i__carry_i_10_n_0\
);
\i__carry_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(7),
O => \i__carry_i_11_n_0\
);
\i__carry_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(6),
O => \i__carry_i_12_n_0\
);
\i__carry_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(5),
O => \i__carry_i_13_n_0\
);
\i__carry_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(4),
O => \i__carry_i_14_n_0\
);
\i__carry_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(3),
O => \i__carry_i_15_n_0\
);
\i__carry_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(2),
O => \i__carry_i_16_n_0\
);
\i__carry_i_17\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(1),
O => \i__carry_i_17_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(4),
I1 => p_0_in(5),
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in(2),
I1 => p_0_in(3),
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => counter_reg(0),
I1 => p_0_in(1),
O => \i__carry_i_4_n_0\
);
\i__carry_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_0_in(6),
I1 => p_0_in(7),
O => \i__carry_i_5_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(4),
I1 => p_0_in(5),
O => \i__carry_i_6_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(2),
I1 => p_0_in(3),
O => \i__carry_i_7_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(0),
I1 => p_0_in(1),
O => \i__carry_i_8_n_0\
);
\i__carry_i_9\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \i__carry_i_9_n_0\,
CO(2) => \i__carry_i_9_n_1\,
CO(1) => \i__carry_i_9_n_2\,
CO(0) => \i__carry_i_9_n_3\,
CYINIT => counter_reg(0),
DI(3 downto 0) => B"0000",
O(3 downto 0) => p_0_in(4 downto 1),
S(3) => \i__carry_i_14_n_0\,
S(2) => \i__carry_i_15_n_0\,
S(1) => \i__carry_i_16_n_0\,
S(0) => \i__carry_i_17_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_affine_rotation_generator_0_0 is
port (
clk_25 : in STD_LOGIC;
reset : in STD_LOGIC;
a00 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_affine_rotation_generator_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_affine_rotation_generator_0_0 : entity is "system_affine_rotation_generator_0_0,affine_rotation_generator,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_affine_rotation_generator_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_affine_rotation_generator_0_0 : entity is "affine_rotation_generator,Vivado 2016.4";
end system_affine_rotation_generator_0_0;
architecture STRUCTURE of system_affine_rotation_generator_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^a00\ : STD_LOGIC_VECTOR ( 28 to 28 );
signal \^a01\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \^a11\ : STD_LOGIC_VECTOR ( 25 downto 0 );
begin
a00(31) <= \<const0>\;
a00(30) <= \<const0>\;
a00(29) <= \^a00\(28);
a00(28) <= \^a00\(28);
a00(27) <= \^a00\(28);
a00(26) <= \^a00\(28);
a00(25 downto 0) <= \^a11\(25 downto 0);
a01(31) <= \<const1>\;
a01(30) <= \<const0>\;
a01(29 downto 0) <= \^a01\(29 downto 0);
a10(31) <= \<const0>\;
a10(30) <= \<const0>\;
a10(29 downto 0) <= \^a01\(29 downto 0);
a11(31) <= \<const0>\;
a11(30) <= \<const0>\;
a11(29) <= \^a00\(28);
a11(28) <= \^a00\(28);
a11(27) <= \^a00\(28);
a11(26) <= \^a00\(28);
a11(25 downto 0) <= \^a11\(25 downto 0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_affine_rotation_generator_0_0_affine_rotation_generator
port map (
a00(26) => \^a00\(28),
a00(25 downto 0) => \^a11\(25 downto 0),
a01(29 downto 0) => \^a01\(29 downto 0),
clk_25 => clk_25,
reset => reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 3ab6804a564dac580afa70498b370dcb | 0.486834 | 2.423046 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl | 1 | 805,207 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 02:52:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_i2c_sender : entity is "i2c_sender";
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_zed_hdmi : entity is "zed_hdmi";
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair43";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair43";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair29";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_6\ : label is "lutpair30";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[15]_i_5\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_6\ : label is "lutpair32";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair33";
attribute HLUTNM of \cr_int[19]_i_5\ : label is "lutpair32";
attribute HLUTNM of \cr_int[19]_i_6\ : label is "lutpair34";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair33";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair35";
attribute HLUTNM of \cr_int[23]_i_5\ : label is "lutpair34";
attribute HLUTNM of \cr_int[23]_i_6\ : label is "lutpair36";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair35";
attribute HLUTNM of \cr_int[27]_i_2\ : label is "lutpair36";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair44";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair44";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair39";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair40";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair39";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair38";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair42";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair41";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair40";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair42";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair41";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
| mit | 6dea6901d3949f617fd52f2592e4e907 | 0.480239 | 2.232005 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_split_controller_0_0/sim/system_vga_split_controller_0_0.vhd | 1 | 3,633 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_split_controller:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_split_controller_0_0 IS
PORT (
rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clock : IN STD_LOGIC;
hsync : IN STD_LOGIC;
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_vga_split_controller_0_0;
ARCHITECTURE system_vga_split_controller_0_0_arch OF system_vga_split_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_split_controller IS
GENERIC (
HALF_ROW : INTEGER
);
PORT (
rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clock : IN STD_LOGIC;
hsync : IN STD_LOGIC;
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT vga_split_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clock: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : vga_split_controller
GENERIC MAP (
HALF_ROW => 320
)
PORT MAP (
rgb_0 => rgb_0,
rgb_1 => rgb_1,
clock => clock,
hsync => hsync,
rgb => rgb
);
END system_vga_split_controller_0_0_arch;
| mit | 7fd76c35fcd6eb6a18d10ccfb1dd487b | 0.722819 | 3.9967 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/usb_component.vhd | 1 | 2,339 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb is
port(
--Clock and Reset
clk : in std_logic;
reset_n : in std_logic;
-- USB Conduit interface to DE2 (Export)
USB_DATA : inout std_logic_vector(15 downto 0);
USB_ADDR : out std_logic_vector(1 downto 0);
USB_WR_N : out std_logic := '1';
USB_RD_N : out std_logic := '1';
USB_RST_N : out std_logic := '1';
USB_CS_N : out std_logic := '1';
USB_INT0 : in std_logic; -- Irq 0 DC
USB_INT1 : in std_logic; -- Irq 1 HC
-- Avalon Memory-Mapped-Slave interface Device Controller (DC)
avs_dc_address : in std_logic;
avs_dc_writedata : in std_logic_vector(15 downto 0);
avs_dc_write_n : in std_logic;
avs_dc_read_n : in std_logic;
avs_dc_CS_n : in std_logic;
avs_dc_readdata : out std_logic_vector(15 downto 0);
avs_dc_irq : out std_logic;
-- Avalon Memory-Mapped-Slave interface Host Controller (HC)
-- Probably will not use this interface.
avs_hc_address : in std_logic;
avs_hc_writedata : in std_logic_vector(15 downto 0);
avs_hc_write_n : in std_logic;
avs_hc_read_n : in std_logic;
avs_hc_CS_n : in std_logic;
avs_hc_readdata : out std_logic_vector(15 downto 0);
avs_hc_irq : out std_logic
);
end usb;
architecture connections of usb is
begin
-- Send interrupt from DE2 connection to proper controller
avs_dc_irq <= USB_INT0;
avs_hc_irq <= USB_INT1;
--Two cases possible, using the host controller or the device controller. The github project combines them with when else style assignments
--Device controller signals
USB_DATA <= avs_dc_writedata when avs_dc_write_n = '0' else (others => 'Z'); -- Only does device controller
avs_dc_readdata <= USB_DATA when avs_dc_read_n = '0' else (others => 'Z');
avs_hc_readdata <= USB_DATA when avs_hc_read_n = '0' else (others => 'Z');
USB_CS_N <= '1' when avs_dc_CS_n = '0' and avs_hc_CS_n = '0' else '0';
USB_ADDR(0) <= '1';
USB_ADDR(1) <= avs_dc_address;
USB_RD_N <= avs_dc_read_n; --Just Ignoring the HC controller right now.
USB_WR_N <= avs_dc_write_n;
USB_RST_N <= reset_n;
end architecture connections;
-- If chip_select_n == 1
-- I could probably have processes for chip select for toggling between HC and DC
-- but for now i'm less than interested when I havent gotten DC working
| apache-2.0 | 28387fd30a39740d32434d750291201f | 0.657973 | 2.729288 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_word_align.vhd | 1 | 4,426 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
--MIPI CSI-2 word aligner
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives aligned bytes and status signals from the 4 byte aligners
--and compensates for up to 2 clock cycles of skew between channels. It also
--controls the packet_done input to the byte aligner, resetting byte aligners'
--sync status if all 4 byte aligners fail to find the sync pattern
--Similar to the byte aligner, this locks the alignment once a valid alignment
--has been found until packet_done is asserted
entity csi_rx_word_align is
Port ( word_clock : in STD_LOGIC; --byte/word clock in
reset : in STD_LOGIC; --active high synchronous reset
enable : in STD_LOGIC; --active high enable
packet_done : in STD_LOGIC; --packet done input from packet handler entity
wait_for_sync : in STD_LOGIC; --whether or not to be looking for an alignment
packet_done_out : out STD_LOGIC; --packet done output to byte aligners
word_in : in STD_LOGIC_VECTOR (31 downto 0); --unaligned word from the 4 byte aligners
valid_in : in STD_LOGIC_VECTOR (3 downto 0); --valid_out from the byte aligners (MSB is index 3, LSB index 0)
word_out : out STD_LOGIC_VECTOR (31 downto 0); --aligned word out to packet handler
valid_out : out STD_LOGIC); --goes high once alignment is valid, such that the first word with it high is the CSI packet header
end csi_rx_word_align;
architecture Behavioral of csi_rx_word_align is
signal word_dly_0 : std_logic_vector(31 downto 0);
signal word_dly_1 : std_logic_vector(31 downto 0);
signal word_dly_2 : std_logic_vector(31 downto 0);
signal valid_dly_0 : std_logic_vector (3 downto 0);
signal valid_dly_1 : std_logic_vector (3 downto 0);
signal valid_dly_2 : std_logic_vector (3 downto 0);
type taps_t is array(0 to 3) of std_logic_vector(1 downto 0);
signal taps : taps_t;
signal next_taps : taps_t;
signal valid : std_logic := '0';
signal next_valid : std_logic;
signal invalid_start : std_logic := '0';
signal aligned_word : std_logic_vector(31 downto 0);
begin
process(word_clock)
begin
if rising_edge(word_clock) then
if reset = '1' then
valid <= '0';
taps <= ("00", "00", "00", "00");
elsif enable = '1' then
word_dly_0 <= word_in;
valid_dly_0 <= valid_in;
word_dly_1 <= word_dly_0;
valid_dly_1 <= valid_dly_0;
word_dly_2 <= word_dly_1;
valid_dly_2 <= valid_dly_1;
valid_out <= valid;
word_out <= aligned_word;
if next_valid = '1' and valid = '0' and wait_for_sync = '1' then
valid <= '1';
taps <= next_taps;
elsif packet_done = '1' then
valid <= '0';
end if;
end if;
end if;
end process;
process(valid_dly_0, valid_dly_1, valid_dly_2)
variable next_valid_int : std_logic;
variable is_triggered : std_logic := '0';
begin
next_valid_int := and_reduce(valid_dly_0);
--Reset if all channels fail to sync
is_triggered := '0';
for i in 0 to 3 loop
if valid_dly_0(i) = '1' and valid_dly_1(i) = '1' and valid_dly_2(i) = '1' then
is_triggered := '1';
end if;
end loop;
invalid_start <= (not next_valid_int) and is_triggered;
next_valid <= next_valid_int;
for i in 0 to 3 loop
if valid_dly_2(i) = '1' then
next_taps(i) <= "10";
elsif valid_dly_1(i) = '1' then
next_taps(i) <= "01";
else
next_taps(i) <= "00";
end if;
end loop;
end process;
packet_done_out <= packet_done or invalid_start;
process(word_dly_0, word_dly_1, word_dly_2, taps)
begin
for i in 0 to 3 loop
if taps(i) = "10" then
aligned_word((8*i) + 7 downto 8 * i) <= word_dly_2((8*i) + 7 downto 8 * i);
elsif taps(i) = "01" then
aligned_word((8*i) + 7 downto 8 * i) <= word_dly_1((8*i) + 7 downto 8 * i);
else
aligned_word((8*i) + 7 downto 8 * i) <= word_dly_0((8*i) + 7 downto 8 * i);
end if;
end loop;
end process;
end Behavioral;
| mit | 6d4e585b1c6e92aa8ed3370e600bf7c1 | 0.579756 | 3.449727 | false | false | false | false |
adelapie/xtea | tb_xtea.vhd | 1 | 3,023 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_xtea IS
END tb_xtea;
ARCHITECTURE behavior OF tb_xtea IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xtea
PORT(
clk : IN std_logic;
rst : IN std_logic;
enc : in std_logic;
block_in : IN std_logic_vector(63 downto 0);
key : IN std_logic_vector(127 downto 0);
v_0_out : out std_logic_vector(31 downto 0);
v_1_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal enc : std_logic := '0';
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
signal key : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal v_0_out : std_logic_vector(31 downto 0);
signal v_1_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xtea PORT MAP (
clk => clk,
rst => rst,
enc => enc,
block_in => block_in,
key => key,
v_0_out => v_0_out,
v_1_out => v_1_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
enc <= '0';
rst <= '1';
block_in <= X"bbbbbbbb" & X"aaaaaaaa" ;
key <= X"44444444" & X"33333333" & X"22222222" & X"11111111";
wait for clk_period;
rst <= '0';
wait for 4*64*clk_period;
assert v_0_out = X"3a53039a"
report "ENCRYPT ERROR (v_0)" severity FAILURE;
wait for clk_period;
assert v_1_out = X"fe2d9913"
report "ENCRYPT ERROR (v_1)" severity FAILURE;
wait for clk_period*10;
enc <= '1';
rst <= '1';
block_in <= X"fe2d9913" & X"3a53039a" ;
key <= X"44444444" & X"33333333" & X"22222222" & X"11111111";
wait for clk_period;
rst <= '0';
wait for 4*64*clk_period;
assert v_0_out = X"bbbbbbbb"
report "DECRYPT ERROR (v_0)" severity FAILURE;
wait for clk_period;
assert v_1_out = X"aaaaaaaa"
report "DECRYPT ERROR (v_1)" severity FAILURE;
wait;
end process;
END;
| gpl-3.0 | 9f1e065c0af16e1bf6b7888cba7bc8c1 | 0.620906 | 3.21254 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/mul_trunc_seq-rtl.vhdl | 1 | 1,612 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of mul_trunc_seq is
begin
mul : entity work.mul_trunc_seq_inferred(rtl)
generic map (
latency => latency,
src_bits => src_bits
)
port map (
clk => clk,
rstn => rstn,
en => en,
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
valid => valid,
overflow => overflow,
result => result
);
end;
| apache-2.0 | 8c8775e2d0d7823fc69b8c297388fcb3 | 0.476427 | 5.216828 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl | 1 | 25,036 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:48:14 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_color_test_0_0_vga_color_test : entity is "vga_color_test";
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
| mit | 16f939645b960c1183ab323e85b05f80 | 0.47887 | 2.488173 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl | 1 | 129,288 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zybo_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
shift_blue : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \dc_bias[0]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_2_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[2]_i_2_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[3]_i_2_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[4]_i_2_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[5]_i_2_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_4__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \dc_bias[1]_i_6__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[1]_i_9__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[2]_i_14__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[2]_i_7__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_19__1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[3]_i_26__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[3]_i_29__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \encoded[1]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \encoded[2]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \encoded[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[4]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[6]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[7]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[8]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \shift_blue[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \shift_blue[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[5]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[6]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[7]_i_1\ : label is "soft_lutpair11";
begin
SR(0) <= \^sr\(0);
\dc_bias[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9F90909F909F9F90"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[0]_i_3__1_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[0]_i_1__1_n_0\
);
\dc_bias[0]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[0]_i_2__1_n_0\
);
\dc_bias[0]_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__1_n_0\
);
\dc_bias[0]_i_4__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[0]_i_4__1_n_0\
);
\dc_bias[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6696969999696966"
)
port map (
I0 => rgb(6),
I1 => rgb(4),
I2 => \dc_bias[2]_i_13__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_12__0_n_0\,
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[0]_i_5__0_n_0\
);
\dc_bias[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[1]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[1]_i_3__1_n_0\,
I4 => \dc_bias[1]_i_4__1_n_0\,
I5 => \dc_bias[1]_i_5__1_n_0\,
O => \dc_bias[1]_i_1__0_n_0\
);
\dc_bias[1]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias[1]_i_6__0_n_0\,
I1 => \dc_bias[1]_i_7__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias[1]_i_8_n_0\,
I4 => \dc_bias[1]_i_9__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[1]_i_2__1_n_0\
);
\dc_bias[1]_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5695"
)
port map (
I0 => \dc_bias[1]_i_7__1_n_0\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[1]_i_3__1_n_0\
);
\dc_bias[1]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D7BE2841"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[1]_i_4__1_n_0\
);
\dc_bias[1]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EB7D7DEB7D14147D"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[1]_i_5__1_n_0\
);
\dc_bias[1]_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
O => \dc_bias[1]_i_6__0_n_0\
);
\dc_bias[1]_i_7__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
O => \dc_bias[1]_i_7__1_n_0\
);
\dc_bias[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"14D782BE82BE14D7"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => \dc_bias[3]_i_31__0_n_0\,
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_8_n_0\
);
\dc_bias[1]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A56566A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[1]_i_9__0_n_0\
);
\dc_bias[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A5965A665A69A59"
)
port map (
I0 => \dc_bias[2]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[2]_i_14__0_n_0\,
O => \dc_bias[2]_i_10_n_0\
);
\dc_bias[2]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
O => \dc_bias[2]_i_11__1_n_0\
);
\dc_bias[2]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"022BBFFF"
)
port map (
I0 => \dc_bias[2]_i_15__0_n_0\,
I1 => rgb(0),
I2 => rgb(7),
I3 => \dc_bias[3]_i_29__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
O => \dc_bias[2]_i_12__0_n_0\
);
\dc_bias[2]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"79E9EF7FFFFFFFFF"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[3]_i_29__0_n_0\,
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_15__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
I5 => rgb(0),
O => \dc_bias[2]_i_13__0_n_0\
);
\dc_bias[2]_i_14__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_14__0_n_0\
);
\dc_bias[2]_i_15__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[2]_i_15__0_n_0\
);
\dc_bias[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[2]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_4__1_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[2]_i_6__1_n_0\,
O => \dc_bias[2]_i_1__1_n_0\
);
\dc_bias[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"999999A999A9AAAA"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_21_n_0\,
I2 => \dc_bias[3]_i_20__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[2]_i_2__0_n_0\
);
\dc_bias[2]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6699A5A566995A5A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_14__0_n_0\,
I2 => \dc_bias[3]_i_9__1_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_8__1_n_0\,
O => \dc_bias[2]_i_3__1_n_0\
);
\dc_bias[2]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4BB4B44B"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_14__0_n_0\,
I4 => \dc_bias[3]_i_26__1_n_0\,
O => \dc_bias[2]_i_4__1_n_0\
);
\dc_bias[2]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75F710518A08EFAE"
)
port map (
I0 => \dc_bias[2]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias[2]_i_8__1_n_0\,
I5 => \dc_bias[2]_i_9__0_n_0\,
O => \dc_bias[2]_i_5__1_n_0\
);
\dc_bias[2]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"177E777777777E17"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[2]_i_11__1_n_0\,
I2 => \dc_bias[0]_i_3__1_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => rgb(2),
O => \dc_bias[2]_i_6__1_n_0\
);
\dc_bias[2]_i_7__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
O => \dc_bias[2]_i_7__0_n_0\
);
\dc_bias[2]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DB4B4B42D2D2DB4"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_12__0_n_0\,
I4 => \dc_bias[3]_i_13__0_n_0\,
I5 => \dc_bias[2]_i_13__0_n_0\,
O => \dc_bias[2]_i_8__1_n_0\
);
\dc_bias[2]_i_9__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_9__0_n_0\
);
\dc_bias[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \^sr\(0)
);
\dc_bias[3]_i_10__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"69FFFF69FF6969FF"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \dc_bias[3]_i_29__0_n_0\,
O => \dc_bias[3]_i_10__1_n_0\
);
\dc_bias[3]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"17717117"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[3]_i_11__1_n_0\
);
\dc_bias[3]_i_12__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_12__1_n_0\
);
\dc_bias[3]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_13__0_n_0\
);
\dc_bias[3]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4DDD444D444D2444"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \dc_bias[3]_i_30__0_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_31__0_n_0\,
I5 => \dc_bias[3]_i_19__1_n_0\,
O => \dc_bias[3]_i_14__0_n_0\
);
\dc_bias[3]_i_15__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECFE8FC88FC8ECFE"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_19__1_n_0\,
I3 => \dc_bias[3]_i_20__0_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[3]_i_15__1_n_0\
);
\dc_bias[3]_i_16__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => p_1_in,
O => \dc_bias[3]_i_16__0_n_0\
);
\dc_bias[3]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22D4BB42DD2B44B"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_17__0_n_0\
);
\dc_bias[3]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1D8B8B1D8B1D1D8B"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => rgb(0),
I3 => rgb(6),
I4 => rgb(4),
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[3]_i_18__0_n_0\
);
\dc_bias[3]_i_19__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_19__1_n_0\
);
\dc_bias[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DFF1D001DFF1DFF"
)
port map (
I0 => \dc_bias[3]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_4__1_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \dc_bias[3]_i_6__1_n_0\,
I5 => \dc_bias[3]_i_7__1_n_0\,
O => \dc_bias[3]_i_1__1_n_0\
);
\dc_bias[3]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(6),
I3 => \encoded[7]_i_2__1_n_0\,
I4 => rgb(0),
O => \dc_bias[3]_i_20__0_n_0\
);
\dc_bias[3]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"A20808A2208A8A20"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_21_n_0\
);
\dc_bias[3]_i_22__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBABA22BA22BA22"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_32__0_n_0\,
I2 => \dc_bias[3]_i_33__0_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22__1_n_0\
);
\dc_bias[3]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFFFFEF"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[0]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_11__1_n_0\,
O => \dc_bias[3]_i_23__0_n_0\
);
\dc_bias[3]_i_24__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE7810081000000"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[0]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_11__1_n_0\,
I5 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[3]_i_24__1_n_0\
);
\dc_bias[3]_i_25__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[3]_i_19__1_n_0\,
I1 => \dc_bias[3]_i_31__0_n_0\,
I2 => rgb(0),
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => \dc_bias[3]_i_30__0_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_25__1_n_0\
);
\dc_bias[3]_i_26__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9990F999"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_26__1_n_0\
);
\dc_bias[3]_i_27__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA696955559696AA"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_27__1_n_0\
);
\dc_bias[3]_i_28__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"28882228BEEEBBBE"
)
port map (
I0 => \encoded[4]_i_2_n_0\,
I1 => \encoded[5]_i_2_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_13__0_n_0\,
I5 => \encoded[6]_i_2__1_n_0\,
O => \dc_bias[3]_i_28__0_n_0\
);
\dc_bias[3]_i_29__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_29__0_n_0\
);
\dc_bias[3]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"24DB"
)
port map (
I0 => \dc_bias[3]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_9__1_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_2__1_n_0\
);
\dc_bias[3]_i_30__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BD400FFFF002BD4"
)
port map (
I0 => \dc_bias[2]_i_13__0_n_0\,
I1 => \dc_bias[3]_i_13__0_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => rgb(2),
I5 => rgb(3),
O => \dc_bias[3]_i_30__0_n_0\
);
\dc_bias[3]_i_31__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55F5F5FFAE8A8A08"
)
port map (
I0 => \dc_bias[3]_i_13__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias[3]_i_12__1_n_0\,
I3 => \dc_bias[3]_i_11__1_n_0\,
I4 => \dc_bias[3]_i_10__1_n_0\,
I5 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[3]_i_31__0_n_0\
);
\dc_bias[3]_i_32__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01B00071B20001B0"
)
port map (
I0 => rgb(6),
I1 => rgb(7),
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \encoded[3]_i_2_n_0\,
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_32__0_n_0\
);
\dc_bias[3]_i_33__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9208000059591049"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_33__0_n_0\
);
\dc_bias[3]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2B023F03FFBFFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_10__1_n_0\,
I2 => \dc_bias[3]_i_11__1_n_0\,
I3 => \dc_bias[3]_i_12__1_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_13__0_n_0\,
O => \dc_bias[3]_i_3__1_n_0\
);
\dc_bias[3]_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"65A6"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias[3]_i_14__0_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
O => \dc_bias[3]_i_4__1_n_0\
);
\dc_bias[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAABEABAA"
)
port map (
I0 => \dc_bias[3]_i_16__0_n_0\,
I1 => \dc_bias[3]_i_17__0_n_0\,
I2 => \dc_bias[3]_i_18__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_20__0_n_0\,
I5 => \dc_bias[3]_i_21_n_0\,
O => \dc_bias[3]_i_5_n_0\
);
\dc_bias[3]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228822828288228"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => p_1_in,
I2 => \dc_bias[3]_i_22__1_n_0\,
I3 => \dc_bias[3]_i_23__0_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[3]_i_24__1_n_0\,
O => \dc_bias[3]_i_6__1_n_0\
);
\dc_bias[3]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4F4F0FBFFFFF4"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__1_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_14__0_n_0\,
O => \dc_bias[3]_i_7__1_n_0\
);
\dc_bias[3]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08A28A20AEFBEFBA"
)
port map (
I0 => \dc_bias[3]_i_27__1_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[1]_i_8_n_0\,
O => \dc_bias[3]_i_8__1_n_0\
);
\dc_bias[3]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000099F099FFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_9__1_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => \^sr\(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => \^sr\(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => \^sr\(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
\encoded[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F6FAF5F6060A050"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => active,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[0]_i_1__1_n_0\
);
\encoded[1]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7B33B7CC480084"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[1]_i_2_n_0\,
I5 => hsync,
O => \encoded[1]_i_1__1_n_0\
);
\encoded[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \encoded[1]_i_2_n_0\
);
\encoded[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[2]_i_2_n_0\,
I5 => hsync,
O => \encoded[2]_i_1__1_n_0\
);
\encoded[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \encoded[2]_i_2_n_0\
);
\encoded[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[3]_i_2_n_0\,
I5 => hsync,
O => \encoded[3]_i_1__1_n_0\
);
\encoded[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[3]_i_2_n_0\
);
\encoded[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44C0880C77F3BB3F"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[4]_i_2_n_0\,
I5 => hsync,
O => \encoded[4]_i_1__1_n_0\
);
\encoded[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \encoded[4]_i_2_n_0\
);
\encoded[5]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[5]_i_2_n_0\,
I5 => hsync,
O => \encoded[5]_i_1__1_n_0\
);
\encoded[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => rgb(3),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[5]_i_2_n_0\
);
\encoded[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[6]_i_2__1_n_0\,
I5 => hsync,
O => \encoded[6]_i_1__1_n_0\
);
\encoded[6]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[6]_i_2__1_n_0\
);
\encoded[7]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF337BB7CC004884"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \encoded[7]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[7]_i_1__1_n_0\
);
\encoded[7]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[3]_i_2_n_0\,
O => \encoded[7]_i_2__1_n_0\
);
\encoded[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => hsync,
O => \encoded[8]_i_1__1_n_0\
);
\encoded[9]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5FFC500C500C5FF"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => active,
I4 => hsync,
I5 => vsync,
O => \encoded[9]_i_1__1_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__1_n_0\,
Q => Q(1),
R => '0'
);
\shift_blue[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_blue[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_blue[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_blue[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_blue[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_blue[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_blue[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_blue[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
shift_green : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_0 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_0;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_0 is
signal \dc_bias[0]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_34_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_2_n_0\ : STD_LOGIC;
signal \encoded[8]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_4_n_0\ : STD_LOGIC;
signal \encoded[8]_i_5_n_0\ : STD_LOGIC;
signal \encoded[8]_i_6_n_0\ : STD_LOGIC;
signal \encoded[8]_i_7_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[0]_i_5__1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \dc_bias[0]_i_7\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[1]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_12__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[3]_i_13__1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \dc_bias[3]_i_15__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[3]_i_18__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[3]_i_22__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_23__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[3]_i_24__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[3]_i_2__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[3]_i_33\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \dc_bias[3]_i_7__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \dc_bias[3]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \encoded[0]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[1]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \encoded[2]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \encoded[4]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[5]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \encoded[6]_i_2__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \encoded[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[7]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \encoded[7]_i_3__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \encoded[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[8]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \encoded[8]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \shift_green[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \shift_green[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[5]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[6]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[7]_i_1\ : label is "soft_lutpair34";
begin
\dc_bias[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[0]_i_3__0_n_0\,
I5 => \dc_bias[0]_i_4__0_n_0\,
O => \dc_bias[0]_i_1__0_n_0\
);
\dc_bias[0]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[0]_i_2__0_n_0\
);
\dc_bias[0]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2__0_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__0_n_0\
);
\dc_bias[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \encoded[8]_i_2_n_0\,
O => \dc_bias[0]_i_4__0_n_0\
);
\dc_bias[0]_i_5__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[0]_i_5__1_n_0\
);
\dc_bias[0]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[0]_i_6_n_0\
);
\dc_bias[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[0]_i_7_n_0\
);
\dc_bias[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \dc_bias[1]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[1]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[1]_i_4__0_n_0\,
O => \dc_bias[1]_i_1_n_0\
);
\dc_bias[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"960096FF96FF9600"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_6__1_n_0\,
I2 => \dc_bias[1]_i_7__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[1]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_10__1_n_0\,
O => \dc_bias[1]_i_2__0_n_0\
);
\dc_bias[1]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5965"
)
port map (
I0 => \dc_bias[2]_i_10__1_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[0]_i_2__0_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_3__0_n_0\
);
\dc_bias[1]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56955965A96AA69A"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[0]_i_3__0_n_0\,
I2 => rgb(2),
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_11__0_n_0\,
I5 => \dc_bias[3]_i_12__0_n_0\,
O => \dc_bias[1]_i_4__0_n_0\
);
\dc_bias[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"066090096FF6F99F"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[0]_i_7_n_0\,
I2 => \dc_bias[1]_i_9_n_0\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[1]_i_5_n_0\
);
\dc_bias[1]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"556969AAAA969655"
)
port map (
I0 => \dc_bias[3]_i_27__0_n_0\,
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_6__1_n_0\
);
\dc_bias[1]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9C3939399C9C9C39"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[2]_i_11__0_n_0\,
I2 => rgb(3),
I3 => \dc_bias[3]_i_30_n_0\,
I4 => \encoded[8]_i_6_n_0\,
I5 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[1]_i_7__0_n_0\
);
\dc_bias[1]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[1]_i_8__0_n_0\
);
\dc_bias[1]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_9_n_0\
);
\dc_bias[2]_i_10__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
O => \dc_bias[2]_i_10__1_n_0\
);
\dc_bias[2]_i_11__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \dc_bias[2]_i_11__0_n_0\
);
\dc_bias[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[2]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[2]_i_4_n_0\,
I5 => \dc_bias[2]_i_5__0_n_0\,
O => \dc_bias[2]_i_1__0_n_0\
);
\dc_bias[2]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FF9600960096FF"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_6__0_n_0\,
I2 => \dc_bias[2]_i_7_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_9_n_0\,
O => \dc_bias[2]_i_2__1_n_0\
);
\dc_bias[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04DFFB20FB2004DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[2]_i_10__1_n_0\,
I4 => \dc_bias[3]_i_23__1_n_0\,
I5 => \dc_bias[2]_i_8__0_n_0\,
O => \dc_bias[2]_i_3__0_n_0\
);
\dc_bias[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"711818188EE7E7E7"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_4_n_0\
);
\dc_bias[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB2BB2BBBBBDDBBB"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[3]_i_12__0_n_0\,
I2 => \dc_bias[2]_i_11__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => rgb(2),
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[2]_i_5__0_n_0\
);
\dc_bias[2]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01151501577F7F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[3]_i_27__0_n_0\,
O => \dc_bias[2]_i_6__0_n_0\
);
\dc_bias[2]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"802AA802EABFFEAB"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(3),
I3 => \dc_bias[2]_i_11__0_n_0\,
I4 => rgb(2),
I5 => \dc_bias[1]_i_6__1_n_0\,
O => \dc_bias[2]_i_7_n_0\
);
\dc_bias[2]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[2]_i_8__0_n_0\
);
\dc_bias[2]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"2B22"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[2]_i_9_n_0\
);
\dc_bias[3]_i_10__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => \dc_bias[3]_i_29_n_0\,
I2 => rgb(0),
I3 => \dc_bias[3]_i_28_n_0\,
I4 => \dc_bias[3]_i_27__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_10__0_n_0\
);
\dc_bias[3]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[3]_i_11__0_n_0\
);
\dc_bias[3]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_12__0_n_0\
);
\dc_bias[3]_i_13__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[3]_i_13__1_n_0\
);
\dc_bias[3]_i_14__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_14__1_n_0\
);
\dc_bias[3]_i_15__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_15__0_n_0\
);
\dc_bias[3]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"B42D"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(5),
O => \dc_bias[3]_i_16_n_0\
);
\dc_bias[3]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_17_n_0\
);
\dc_bias[3]_i_18__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"14414114"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[3]_i_18__1_n_0\
);
\dc_bias[3]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"82BE14D714D782BE"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[7]_i_2_n_0\,
I3 => rgb(0),
I4 => \dc_bias[0]_i_7_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_19__0_n_0\
);
\dc_bias[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFAAEB"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__0_n_0\,
I2 => \dc_bias[3]_i_4__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[3]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_7__0_n_0\,
O => \dc_bias[3]_i_1__0_n_0\
);
\dc_bias[3]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"42BDBD42BD4242BD"
)
port map (
I0 => rgb(6),
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_20_n_0\
);
\dc_bias[3]_i_21__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAEEFFBEFFBBAAE"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => rgb(6),
I2 => \encoded[8]_i_2_n_0\,
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_21__1_n_0\
);
\dc_bias[3]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"99F99099"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_22__0_n_0\
);
\dc_bias[3]_i_23__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_23__1_n_0\
);
\dc_bias[3]_i_24__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \dc_bias[3]_i_24__0_n_0\
);
\dc_bias[3]_i_25__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002BD400FFD42BFF"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_7__0_n_0\,
I2 => \dc_bias[1]_i_6__1_n_0\,
I3 => \dc_bias[2]_i_6__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => p_1_in,
O => \dc_bias[3]_i_25__0_n_0\
);
\dc_bias[3]_i_26__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFD4DDD4DD0000"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[3]_i_26__0_n_0\
);
\dc_bias[3]_i_27__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBBEEEB82228882"
)
port map (
I0 => \dc_bias[0]_i_7_n_0\,
I1 => \dc_bias[3]_i_32_n_0\,
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
I5 => \encoded[7]_i_2_n_0\,
O => \dc_bias[3]_i_27__0_n_0\
);
\dc_bias[3]_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \dc_bias[3]_i_30_n_0\,
I1 => \encoded[8]_i_6_n_0\,
I2 => \dc_bias[3]_i_31_n_0\,
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_28_n_0\
);
\dc_bias[3]_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAFB5D45BAFB4504"
)
port map (
I0 => \encoded[8]_i_6_n_0\,
I1 => \encoded[8]_i_5_n_0\,
I2 => \encoded[8]_i_4_n_0\,
I3 => \encoded[8]_i_3_n_0\,
I4 => \dc_bias[0]_i_6_n_0\,
I5 => rgb(0),
O => \dc_bias[3]_i_29_n_0\
);
\dc_bias[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAAE"
)
port map (
I0 => \dc_bias[3]_i_8__0_n_0\,
I1 => \dc_bias[3]_i_9__0_n_0\,
I2 => \dc_bias[3]_i_10__0_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[3]_i_2__0_n_0\
);
\dc_bias[3]_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F6606000FFF6"
)
port map (
I0 => \dc_bias[3]_i_33_n_0\,
I1 => rgb(6),
I2 => rgb(7),
I3 => rgb(0),
I4 => \encoded[8]_i_5_n_0\,
I5 => \dc_bias[3]_i_34_n_0\,
O => \dc_bias[3]_i_30_n_0\
);
\dc_bias[3]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"4008000029610000"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => \encoded[8]_i_7_n_0\,
I3 => \dc_bias[3]_i_34_n_0\,
I4 => rgb(0),
I5 => \encoded[8]_i_5_n_0\,
O => \dc_bias[3]_i_31_n_0\
);
\dc_bias[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(5),
I1 => rgb(4),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => rgb(3),
O => \dc_bias[3]_i_32_n_0\
);
\dc_bias[3]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
O => \dc_bias[3]_i_33_n_0\
);
\dc_bias[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_34_n_0\
);
\dc_bias[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A088A8A8A8AAE8A"
)
port map (
I0 => \dc_bias[2]_i_4_n_0\,
I1 => \dc_bias[3]_i_11__0_n_0\,
I2 => \dc_bias[3]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__1_n_0\,
I4 => \dc_bias[3]_i_14__1_n_0\,
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[3]_i_3__0_n_0\
);
\dc_bias[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56555555AA6A6A56"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_15__0_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias[3]_i_16_n_0\,
I4 => \dc_bias[3]_i_17_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_4__0_n_0\
);
\dc_bias[3]_i_5__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6655555"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_18__1_n_0\,
I2 => \dc_bias[3]_i_19__0_n_0\,
I3 => \dc_bias[3]_i_20_n_0\,
I4 => \dc_bias[3]_i_21__1_n_0\,
O => \dc_bias[3]_i_5__1_n_0\
);
\dc_bias[3]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C40404040CCC0"
)
port map (
I0 => \dc_bias[3]_i_22__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \dc_bias[3]_i_23__1_n_0\,
I3 => \dc_bias[3]_i_24__0_n_0\,
I4 => \dc_bias[3]_i_9__0_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_6__0_n_0\
);
\dc_bias[3]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B08080B0"
)
port map (
I0 => \dc_bias[3]_i_25__0_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__0_n_0\,
I4 => \dc_bias[3]_i_5__1_n_0\,
O => \dc_bias[3]_i_7__0_n_0\
);
\dc_bias[3]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => p_1_in,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_8__0_n_0\
);
\dc_bias[3]_i_9__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D444DDD4DDD4BDDD"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_27__0_n_0\,
I2 => \dc_bias[3]_i_28_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_29_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[3]_i_9__0_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__0_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2__0_n_0\,
O => \encoded[0]_i_1__0_n_0\
);
\encoded[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => rgb(1),
I2 => rgb(0),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[1]_i_1__0_n_0\
);
\encoded[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D7DD7"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2__0_n_0\,
O => \encoded[2]_i_1__0_n_0\
);
\encoded[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882822882282882"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3__0_n_0\,
O => \encoded[3]_i_1__0_n_0\
);
\encoded[4]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2__0_n_0\,
O => \encoded[4]_i_1__0_n_0\
);
\encoded[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"28828228"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => rgb(5),
I4 => \encoded[7]_i_3__0_n_0\,
O => \encoded[5]_i_1__0_n_0\
);
\encoded[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D77D7DD77DD7D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[9]_i_2__0_n_0\,
O => \encoded[6]_i_1__0_n_0\
);
\encoded[6]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2__0_n_0\
);
\encoded[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[7]_i_1__0_n_0\
);
\encoded[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => rgb(6),
I3 => \encoded[6]_i_2__0_n_0\,
O => \encoded[7]_i_2_n_0\
);
\encoded[7]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \encoded[7]_i_3__0_n_0\
);
\encoded[8]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => active,
O => \encoded[8]_i_1__0_n_0\
);
\encoded[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00200000F2FF20F2"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_3_n_0\,
I3 => \encoded[8]_i_4_n_0\,
I4 => \encoded[8]_i_5_n_0\,
I5 => \encoded[8]_i_6_n_0\,
O => \encoded[8]_i_2_n_0\
);
\encoded[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF6969FF69FFFF69"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \encoded[8]_i_7_n_0\,
O => \encoded[8]_i_3_n_0\
);
\encoded[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E88E8EE8"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \encoded[8]_i_4_n_0\
);
\encoded[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E817E8171717"
)
port map (
I0 => rgb(2),
I1 => rgb(3),
I2 => rgb(1),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[8]_i_5_n_0\
);
\encoded[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E800E8000000"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
I3 => rgb(2),
I4 => rgb(3),
I5 => rgb(1),
O => \encoded[8]_i_6_n_0\
);
\encoded[8]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \encoded[8]_i_7_n_0\
);
\encoded[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => active,
I1 => \encoded[9]_i_2__0_n_0\,
O => \encoded[9]_i_1_n_0\
);
\encoded[9]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_5__1_n_0\,
O => \encoded[9]_i_2__0_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__0_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1_n_0\,
Q => Q(1),
R => '0'
);
\shift_green[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_green[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_green[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_green[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_green[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_green[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_green[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_green[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_1 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
data1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_1 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_1;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_1 is
signal \dc_bias[0]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal encoded : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \encoded[6]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[2]_i_12\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \dc_bias[2]_i_13\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_16\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_17\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \dc_bias[2]_i_18\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_19\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_20\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_22\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \dc_bias[3]_i_10\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[3]_i_20__1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[3]_i_25\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[3]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \encoded[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \encoded[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[4]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[6]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \encoded[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[7]_i_2__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \encoded[7]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \encoded[8]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[9]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[9]_i_2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \shift_red[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \shift_red[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[2]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[3]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[4]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[5]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[6]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[7]_i_1\ : label is "soft_lutpair55";
begin
\dc_bias[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_6_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[0]_i_3_n_0\,
I5 => \dc_bias[0]_i_4_n_0\,
O => \dc_bias[0]_i_1_n_0\
);
\dc_bias[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
O => \dc_bias[0]_i_2_n_0\
);
\dc_bias[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3_n_0\
);
\dc_bias[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_4_n_0\
);
\dc_bias[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_5_n_0\
);
\dc_bias[0]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(6),
O => \dc_bias[0]_i_6__0_n_0\
);
\dc_bias[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC3CC3CC55555555"
)
port map (
I0 => \dc_bias[1]_i_4_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[0]_i_2_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[1]_i_2_n_0\
);
\dc_bias[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00F0FF099999999"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[1]_i_6_n_0\,
I3 => \dc_bias[1]_i_7_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[1]_i_3_n_0\
);
\dc_bias[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"95A9A96A569595A9"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[2]_i_16_n_0\,
I2 => \dc_bias[2]_i_17_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[1]_i_4_n_0\
);
\dc_bias[1]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9996699969996669"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[1]_i_5__0_n_0\
);
\dc_bias[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5CC5355335535CC5"
)
port map (
I0 => \dc_bias[0]_i_6__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_6_n_0\
);
\dc_bias[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"A665599A"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[0]_i_5_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_7_n_0\
);
\dc_bias[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_3_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_6_n_0\,
O => \dc_bias[2]_i_1_n_0\
);
\dc_bias[2]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"90060690"
)
port map (
I0 => \dc_bias[0]_i_5_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_10__0_n_0\
);
\dc_bias[2]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"3AA3ACCAACCA3AA3"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_2__0_n_0\,
I4 => \dc_bias[2]_i_22_n_0\,
I5 => rgb(6),
O => \dc_bias[2]_i_11_n_0\
);
\dc_bias[2]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DD2B44B"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_12_n_0\
);
\dc_bias[2]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"A59669A5"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[6]_i_2_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(6),
O => \dc_bias[2]_i_13_n_0\
);
\dc_bias[2]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2_n_0\,
O => \dc_bias[2]_i_14_n_0\
);
\dc_bias[2]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"4BD2"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(5),
O => \dc_bias[2]_i_15_n_0\
);
\dc_bias[2]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[2]_i_16_n_0\
);
\dc_bias[2]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[2]_i_17_n_0\
);
\dc_bias[2]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \dc_bias[2]_i_15_n_0\,
I1 => \dc_bias[2]_i_14_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[2]_i_18_n_0\
);
\dc_bias[2]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(5),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_19_n_0\
);
\dc_bias[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F60606F"
)
port map (
I0 => \dc_bias[2]_i_7__1_n_0\,
I1 => \dc_bias[3]_i_9_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[2]_i_8_n_0\,
I4 => \dc_bias[2]_i_9__1_n_0\,
O => \dc_bias[2]_i_2_n_0\
);
\dc_bias[2]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_20_n_0\
);
\dc_bias[2]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[2]_i_22_n_0\,
I2 => \encoded[7]_i_2__0_n_0\,
I3 => rgb(7),
I4 => rgb(0),
O => \dc_bias[2]_i_21_n_0\
);
\dc_bias[2]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_22_n_0\
);
\dc_bias[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"56569556566A5656"
)
port map (
I0 => \dc_bias[2]_i_8_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_17__1_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => \dc_bias[0]_i_2_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_3_n_0\
);
\dc_bias[2]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5556566A"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[2]_i_10__0_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_12_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[2]_i_4__0_n_0\
);
\dc_bias[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D44242422BBDBDBD"
)
port map (
I0 => \dc_bias[2]_i_14_n_0\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_5_n_0\
);
\dc_bias[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F1F170EFF7F7F1"
)
port map (
I0 => \dc_bias[2]_i_16_n_0\,
I1 => \dc_bias[2]_i_17_n_0\,
I2 => \dc_bias[2]_i_18_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[2]_i_6_n_0\
);
\dc_bias[2]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5565656666A6A6AA"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_13_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_7__1_n_0\
);
\dc_bias[2]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[2]_i_8_n_0\
);
\dc_bias[2]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"41141414417D7D14"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_21_n_0\,
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_9__1_n_0\
);
\dc_bias[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"15017F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_10_n_0\
);
\dc_bias[3]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_11_n_0\
);
\dc_bias[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_12_n_0\
);
\dc_bias[3]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_13_n_0\
);
\dc_bias[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_14_n_0\
);
\dc_bias[3]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE78EEE8EEE888E"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[3]_i_15_n_0\
);
\dc_bias[3]_i_16__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EBBEBEEB"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(3),
I4 => rgb(1),
O => \dc_bias[3]_i_16__1_n_0\
);
\dc_bias[3]_i_17__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F6F66F6F090990"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[0]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_26_n_0\,
O => \dc_bias[3]_i_17__1_n_0\
);
\dc_bias[3]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFF799E799EFFF7"
)
port map (
I0 => \dc_bias[3]_i_25_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_18_n_0\
);
\dc_bias[3]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"E00E0EE00EE0E00E"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[2]_i_10__0_n_0\,
I3 => \dc_bias[2]_i_11_n_0\,
I4 => \dc_bias[3]_i_26_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_19_n_0\
);
\dc_bias[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8FFB8FFB800"
)
port map (
I0 => \dc_bias[3]_i_3_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[3]_i_5__0_n_0\,
I3 => \dc_bias[3]_i_6_n_0\,
I4 => \dc_bias[3]_i_7_n_0\,
I5 => \dc_bias[3]_i_8_n_0\,
O => \dc_bias[3]_i_2_n_0\
);
\dc_bias[3]_i_20__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[3]_i_20__1_n_0\
);
\dc_bias[3]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A96A6A5600000000"
)
port map (
I0 => \dc_bias[3]_i_26_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_21__0_n_0\
);
\dc_bias[3]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAEAE8AAE8AAE8A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias[2]_i_14_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22_n_0\
);
\dc_bias[3]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"02BF002B002B0002"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[2]_i_20_n_0\,
I2 => \dc_bias[2]_i_19_n_0\,
I3 => \dc_bias[2]_i_18_n_0\,
I4 => \dc_bias[2]_i_17_n_0\,
I5 => \dc_bias[2]_i_16_n_0\,
O => \dc_bias[3]_i_23_n_0\
);
\dc_bias[3]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5775D55D"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(2),
I5 => \dc_bias[3]_i_27_n_0\,
O => \dc_bias[3]_i_24_n_0\
);
\dc_bias[3]_i_25\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_25_n_0\
);
\dc_bias[3]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"963CC39669C33C69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_26_n_0\
);
\dc_bias[3]_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBEBEFF"
)
port map (
I0 => \dc_bias[0]_i_4_n_0\,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(7),
O => \dc_bias[3]_i_27_n_0\
);
\dc_bias[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \dc_bias[3]_i_9_n_0\,
I1 => \dc_bias[3]_i_10_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_3_n_0\
);
\dc_bias[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0022AAAA32EAAAAA"
)
port map (
I0 => \dc_bias[3]_i_11_n_0\,
I1 => \dc_bias[3]_i_12_n_0\,
I2 => rgb(0),
I3 => rgb(7),
I4 => \dc_bias[3]_i_13_n_0\,
I5 => \dc_bias[3]_i_14_n_0\,
O => \dc_bias[3]_i_4_n_0\
);
\dc_bias[3]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5656566A566A6A6A"
)
port map (
I0 => \dc_bias[2]_i_4__0_n_0\,
I1 => \dc_bias[3]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_16__1_n_0\,
I4 => \dc_bias[3]_i_17__1_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_5__0_n_0\
);
\dc_bias[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => p_1_in,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias[3]_i_18_n_0\,
O => \dc_bias[3]_i_6_n_0\
);
\dc_bias[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0000400040C0CC"
)
port map (
I0 => \dc_bias[3]_i_19_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_20__1_n_0\,
I3 => \dc_bias[3]_i_21__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[3]_i_7_n_0\
);
\dc_bias[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000096969996"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_22_n_0\,
I2 => \dc_bias[3]_i_23_n_0\,
I3 => \dc_bias[3]_i_24_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[3]_i_8_n_0\
);
\dc_bias[3]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \dc_bias[1]_i_6_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[1]_i_7_n_0\,
O => \dc_bias[3]_i_9_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias_reg[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \dc_bias[1]_i_2_n_0\,
I1 => \dc_bias[1]_i_3_n_0\,
O => \dc_bias_reg[1]_i_1_n_0\,
S => \dc_bias[3]_i_6_n_0\
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_2_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"28"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2_n_0\,
O => encoded(0)
);
\encoded[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_3_n_0\,
I2 => rgb(1),
I3 => rgb(0),
O => encoded(1)
);
\encoded[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7DD7D77D"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2_n_0\,
O => encoded(2)
);
\encoded[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228288228828228"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3_n_0\,
O => encoded(3)
);
\encoded[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7DD7"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2_n_0\,
O => encoded(4)
);
\encoded[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82282882"
)
port map (
I0 => active,
I1 => rgb(4),
I2 => rgb(5),
I3 => \encoded[6]_i_2_n_0\,
I4 => \encoded[7]_i_3_n_0\,
O => encoded(5)
);
\encoded[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7DD7D77DD77D7DD7"
)
port map (
I0 => active,
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2_n_0\,
I5 => \encoded[9]_i_2_n_0\,
O => encoded(6)
);
\encoded[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2_n_0\
);
\encoded[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2__0_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3_n_0\,
O => encoded(7)
);
\encoded[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[7]_i_2__0_n_0\
);
\encoded[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \dc_bias[3]_i_6_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \encoded[7]_i_3_n_0\
);
\encoded[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => active,
O => \encoded[8]_i_1_n_0\
);
\encoded[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[9]_i_2_n_0\,
I1 => active,
O => \encoded[9]_i_1__0_n_0\
);
\encoded[9]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_4__0_n_0\,
O => \encoded[9]_i_2_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(0),
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(1),
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(2),
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(3),
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(4),
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(5),
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(6),
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(7),
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__0_n_0\,
Q => Q(1),
R => '0'
);
\shift_red[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_red[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_red[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_red[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_red[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_red[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_red[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_red[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_dvid is
port (
red_s : out STD_LOGIC;
green_s : out STD_LOGIC;
blue_s : out STD_LOGIC;
clock_s : out STD_LOGIC;
clk_125 : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_dvid : entity is "dvid";
end system_zybo_hdmi_0_0_dvid;
architecture STRUCTURE of system_zybo_hdmi_0_0_dvid is
signal D0 : STD_LOGIC;
signal D1 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_0 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_10 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_9 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_8 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_9 : STD_LOGIC;
signal TMDS_encoder_RED_n_8 : STD_LOGIC;
signal TMDS_encoder_RED_n_9 : STD_LOGIC;
signal clk_dvin : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal shift_blue : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_blue_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_blue_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_blue_reg_n_0_[1]\ : STD_LOGIC;
signal shift_clock : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \shift_clock_reg_n_0_[2]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[3]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[4]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[5]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[6]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[7]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[8]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[9]\ : STD_LOGIC;
signal shift_green : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_green_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_green_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_green_reg_n_0_[1]\ : STD_LOGIC;
signal shift_red : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_red[9]_i_1_n_0\ : STD_LOGIC;
signal \shift_red[9]_i_2_n_0\ : STD_LOGIC;
signal NLW_ODDR2_BLUE_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_BLUE_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_S_UNCONNECTED : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ODDR2_BLUE : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of ODDR2_BLUE : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR2_BLUE : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR2_BLUE : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_CLK : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_CLK : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_CLK : label is "TRUE";
attribute box_type of ODDR2_CLK : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_GREEN : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_GREEN : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_GREEN : label is "TRUE";
attribute box_type of ODDR2_GREEN : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_RED : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_RED : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_RED : label is "TRUE";
attribute box_type of ODDR2_RED : label is "PRIMITIVE";
begin
ODDR2_BLUE: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_blue_reg_n_0_[0]\,
D2 => \shift_blue_reg_n_0_[1]\,
Q => blue_s,
R => NLW_ODDR2_BLUE_R_UNCONNECTED,
S => NLW_ODDR2_BLUE_S_UNCONNECTED
);
ODDR2_CLK: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => shift_clock(0),
D2 => shift_clock(1),
Q => clock_s,
R => NLW_ODDR2_CLK_R_UNCONNECTED,
S => NLW_ODDR2_CLK_S_UNCONNECTED
);
ODDR2_GREEN: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_green_reg_n_0_[0]\,
D2 => \shift_green_reg_n_0_[1]\,
Q => green_s,
R => NLW_ODDR2_GREEN_R_UNCONNECTED,
S => NLW_ODDR2_GREEN_S_UNCONNECTED
);
ODDR2_RED: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => D0,
D2 => D1,
Q => red_s,
R => NLW_ODDR2_RED_R_UNCONNECTED,
S => NLW_ODDR2_RED_S_UNCONNECTED
);
ODDR2_RED_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_125,
O => clk_dvin
);
TMDS_encoder_BLUE: entity work.system_zybo_hdmi_0_0_TMDS_encoder
port map (
D(7 downto 0) => shift_blue_0(7 downto 0),
Q(1) => TMDS_encoder_BLUE_n_9,
Q(0) => TMDS_encoder_BLUE_n_10,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
hsync => hsync,
rgb(7 downto 0) => rgb(7 downto 0),
shift_blue(7 downto 0) => shift_blue(9 downto 2),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
vsync => vsync
);
TMDS_encoder_GREEN: entity work.system_zybo_hdmi_0_0_TMDS_encoder_0
port map (
D(7 downto 0) => shift_green_1(7 downto 0),
Q(1) => TMDS_encoder_GREEN_n_8,
Q(0) => TMDS_encoder_GREEN_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
rgb(7 downto 0) => rgb(15 downto 8),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
shift_green(7 downto 0) => shift_green(9 downto 2)
);
TMDS_encoder_RED: entity work.system_zybo_hdmi_0_0_TMDS_encoder_1
port map (
D(7 downto 0) => shift_red(7 downto 0),
Q(1) => TMDS_encoder_RED_n_8,
Q(0) => TMDS_encoder_RED_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
data1(7 downto 0) => data1(7 downto 0),
rgb(7 downto 0) => rgb(23 downto 16),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(0),
Q => \shift_blue_reg_n_0_[0]\,
R => '0'
);
\shift_blue_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(1),
Q => \shift_blue_reg_n_0_[1]\,
R => '0'
);
\shift_blue_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(2),
Q => shift_blue(2),
R => '0'
);
\shift_blue_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(3),
Q => shift_blue(3),
R => '0'
);
\shift_blue_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(4),
Q => shift_blue(4),
R => '0'
);
\shift_blue_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(5),
Q => shift_blue(5),
R => '0'
);
\shift_blue_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(6),
Q => shift_blue(6),
R => '0'
);
\shift_blue_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(7),
Q => shift_blue(7),
R => '0'
);
\shift_blue_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_10,
Q => shift_blue(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_9,
Q => shift_blue(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_clock_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[2]\,
Q => shift_clock(0),
R => '0'
);
\shift_clock_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[3]\,
Q => shift_clock(1),
R => '0'
);
\shift_clock_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[4]\,
Q => \shift_clock_reg_n_0_[2]\,
R => '0'
);
\shift_clock_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[5]\,
Q => \shift_clock_reg_n_0_[3]\,
R => '0'
);
\shift_clock_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[6]\,
Q => \shift_clock_reg_n_0_[4]\,
R => '0'
);
\shift_clock_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[7]\,
Q => \shift_clock_reg_n_0_[5]\,
R => '0'
);
\shift_clock_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[8]\,
Q => \shift_clock_reg_n_0_[6]\,
R => '0'
);
\shift_clock_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[9]\,
Q => \shift_clock_reg_n_0_[7]\,
R => '0'
);
\shift_clock_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(0),
Q => \shift_clock_reg_n_0_[8]\,
R => '0'
);
\shift_clock_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(1),
Q => \shift_clock_reg_n_0_[9]\,
R => '0'
);
\shift_green_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(0),
Q => \shift_green_reg_n_0_[0]\,
R => '0'
);
\shift_green_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(1),
Q => \shift_green_reg_n_0_[1]\,
R => '0'
);
\shift_green_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(2),
Q => shift_green(2),
R => '0'
);
\shift_green_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(3),
Q => shift_green(3),
R => '0'
);
\shift_green_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(4),
Q => shift_green(4),
R => '0'
);
\shift_green_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(5),
Q => shift_green(5),
R => '0'
);
\shift_green_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(6),
Q => shift_green(6),
R => '0'
);
\shift_green_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(7),
Q => shift_green(7),
R => '0'
);
\shift_green_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_9,
Q => shift_green(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_green_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_8,
Q => shift_green(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFFFFF"
)
port map (
I0 => \shift_red[9]_i_2_n_0\,
I1 => \shift_clock_reg_n_0_[5]\,
I2 => \shift_clock_reg_n_0_[4]\,
I3 => \shift_clock_reg_n_0_[2]\,
I4 => \shift_clock_reg_n_0_[3]\,
O => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \shift_clock_reg_n_0_[8]\,
I1 => \shift_clock_reg_n_0_[9]\,
I2 => \shift_clock_reg_n_0_[6]\,
I3 => \shift_clock_reg_n_0_[7]\,
I4 => shift_clock(1),
I5 => shift_clock(0),
O => \shift_red[9]_i_2_n_0\
);
\shift_red_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(0),
Q => D0,
R => '0'
);
\shift_red_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(1),
Q => D1,
R => '0'
);
\shift_red_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(2),
Q => data1(0),
R => '0'
);
\shift_red_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(3),
Q => data1(1),
R => '0'
);
\shift_red_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(4),
Q => data1(2),
R => '0'
);
\shift_red_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(5),
Q => data1(3),
R => '0'
);
\shift_red_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(6),
Q => data1(4),
R => '0'
);
\shift_red_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(7),
Q => data1(5),
R => '0'
);
\shift_red_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_9,
Q => data1(6),
R => \shift_red[9]_i_1_n_0\
);
\shift_red_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_8,
Q => data1(7),
R => \shift_red[9]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_zybo_hdmi is
port (
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_zybo_hdmi : entity is "zybo_hdmi";
end system_zybo_hdmi_0_0_zybo_hdmi;
architecture STRUCTURE of system_zybo_hdmi_0_0_zybo_hdmi is
signal blue_s : STD_LOGIC;
signal clock_s : STD_LOGIC;
signal green_s : STD_LOGIC;
signal red_s : STD_LOGIC;
attribute CAPACITANCE : string;
attribute CAPACITANCE of OBUFDS_blue : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of OBUFDS_blue : label is "OBUFDS";
attribute box_type : string;
attribute box_type of OBUFDS_blue : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_clock : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_clock : label is "OBUFDS";
attribute box_type of OBUFDS_clock : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_green : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_green : label is "OBUFDS";
attribute box_type of OBUFDS_green : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_red : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_red : label is "OBUFDS";
attribute box_type of OBUFDS_red : label is "PRIMITIVE";
begin
DVID: entity work.system_zybo_hdmi_0_0_dvid
port map (
active => active,
blue_s => blue_s,
clk_125 => clk_125,
clk_25 => clk_25,
clock_s => clock_s,
green_s => green_s,
hsync => hsync,
red_s => red_s,
rgb(23 downto 0) => rgb(23 downto 0),
vsync => vsync
);
OBUFDS_blue: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => blue_s,
O => tmds(0),
OB => tmdsb(0)
);
OBUFDS_clock: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clock_s,
O => tmds(3),
OB => tmdsb(3)
);
OBUFDS_green: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => red_s,
O => tmds(2),
OB => tmdsb(2)
);
OBUFDS_red: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => green_s,
O => tmds(1),
OB => tmdsb(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zybo_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zybo_hdmi_0_0 : entity is "system_zybo_hdmi_0_0,zybo_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zybo_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zybo_hdmi_0_0 : entity is "zybo_hdmi,Vivado 2016.4";
end system_zybo_hdmi_0_0;
architecture STRUCTURE of system_zybo_hdmi_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
hdmi_out_en <= \<const1>\;
U0: entity work.system_zybo_hdmi_0_0_zybo_hdmi
port map (
active => active,
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
rgb(23 downto 0) => rgb(23 downto 0),
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync => vsync
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 916c29d4e634737bffaa3f55cd37533c | 0.48484 | 2.424483 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_sim_netlist.vhdl | 1 | 14,590 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:33:31 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_sim_netlist.vhdl
-- Design : system_comparator_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_comparator_0_0_comparator is
port (
z : out STD_LOGIC;
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
x : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_comparator_0_0_comparator : entity is "comparator";
end system_comparator_0_0_comparator;
architecture STRUCTURE of system_comparator_0_0_comparator is
signal z1 : STD_LOGIC;
signal \z1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z1_carry__0_n_0\ : STD_LOGIC;
signal \z1_carry__0_n_1\ : STD_LOGIC;
signal \z1_carry__0_n_2\ : STD_LOGIC;
signal \z1_carry__0_n_3\ : STD_LOGIC;
signal \z1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \z1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \z1_carry__1_n_0\ : STD_LOGIC;
signal \z1_carry__1_n_1\ : STD_LOGIC;
signal \z1_carry__1_n_2\ : STD_LOGIC;
signal \z1_carry__1_n_3\ : STD_LOGIC;
signal \z1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \z1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \z1_carry__2_n_1\ : STD_LOGIC;
signal \z1_carry__2_n_2\ : STD_LOGIC;
signal \z1_carry__2_n_3\ : STD_LOGIC;
signal z1_carry_i_1_n_0 : STD_LOGIC;
signal z1_carry_i_2_n_0 : STD_LOGIC;
signal z1_carry_i_3_n_0 : STD_LOGIC;
signal z1_carry_i_4_n_0 : STD_LOGIC;
signal z1_carry_i_5_n_0 : STD_LOGIC;
signal z1_carry_i_6_n_0 : STD_LOGIC;
signal z1_carry_i_7_n_0 : STD_LOGIC;
signal z1_carry_i_8_n_0 : STD_LOGIC;
signal z1_carry_n_0 : STD_LOGIC;
signal z1_carry_n_1 : STD_LOGIC;
signal z1_carry_n_2 : STD_LOGIC;
signal z1_carry_n_3 : STD_LOGIC;
signal NLW_z1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z1_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
begin
z1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z1_carry_n_0,
CO(2) => z1_carry_n_1,
CO(1) => z1_carry_n_2,
CO(0) => z1_carry_n_3,
CYINIT => '0',
DI(3) => z1_carry_i_1_n_0,
DI(2) => z1_carry_i_2_n_0,
DI(1) => z1_carry_i_3_n_0,
DI(0) => z1_carry_i_4_n_0,
O(3 downto 0) => NLW_z1_carry_O_UNCONNECTED(3 downto 0),
S(3) => z1_carry_i_5_n_0,
S(2) => z1_carry_i_6_n_0,
S(1) => z1_carry_i_7_n_0,
S(0) => z1_carry_i_8_n_0
);
\z1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z1_carry_n_0,
CO(3) => \z1_carry__0_n_0\,
CO(2) => \z1_carry__0_n_1\,
CO(1) => \z1_carry__0_n_2\,
CO(0) => \z1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \z1_carry__0_i_1_n_0\,
DI(2) => \z1_carry__0_i_2_n_0\,
DI(1) => \z1_carry__0_i_3_n_0\,
DI(0) => \z1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_z1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \z1_carry__0_i_5_n_0\,
S(2) => \z1_carry__0_i_6_n_0\,
S(1) => \z1_carry__0_i_7_n_0\,
S(0) => \z1_carry__0_i_8_n_0\
);
\z1_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(14),
I1 => x(14),
I2 => x(15),
I3 => y(15),
O => \z1_carry__0_i_1_n_0\
);
\z1_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(12),
I1 => x(12),
I2 => x(13),
I3 => y(13),
O => \z1_carry__0_i_2_n_0\
);
\z1_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(10),
I1 => x(10),
I2 => x(11),
I3 => y(11),
O => \z1_carry__0_i_3_n_0\
);
\z1_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(8),
I1 => x(8),
I2 => x(9),
I3 => y(9),
O => \z1_carry__0_i_4_n_0\
);
\z1_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(14),
I1 => x(14),
I2 => y(15),
I3 => x(15),
O => \z1_carry__0_i_5_n_0\
);
\z1_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(12),
I1 => x(12),
I2 => y(13),
I3 => x(13),
O => \z1_carry__0_i_6_n_0\
);
\z1_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(10),
I1 => x(10),
I2 => y(11),
I3 => x(11),
O => \z1_carry__0_i_7_n_0\
);
\z1_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(8),
I1 => x(8),
I2 => y(9),
I3 => x(9),
O => \z1_carry__0_i_8_n_0\
);
\z1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \z1_carry__0_n_0\,
CO(3) => \z1_carry__1_n_0\,
CO(2) => \z1_carry__1_n_1\,
CO(1) => \z1_carry__1_n_2\,
CO(0) => \z1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \z1_carry__1_i_1_n_0\,
DI(2) => \z1_carry__1_i_2_n_0\,
DI(1) => \z1_carry__1_i_3_n_0\,
DI(0) => \z1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_z1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \z1_carry__1_i_5_n_0\,
S(2) => \z1_carry__1_i_6_n_0\,
S(1) => \z1_carry__1_i_7_n_0\,
S(0) => \z1_carry__1_i_8_n_0\
);
\z1_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => x(23),
I3 => y(23),
O => \z1_carry__1_i_1_n_0\
);
\z1_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => x(21),
I3 => y(21),
O => \z1_carry__1_i_2_n_0\
);
\z1_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => x(19),
I3 => y(19),
O => \z1_carry__1_i_3_n_0\
);
\z1_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => x(17),
I3 => y(17),
O => \z1_carry__1_i_4_n_0\
);
\z1_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => y(23),
I3 => x(23),
O => \z1_carry__1_i_5_n_0\
);
\z1_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => y(21),
I3 => x(21),
O => \z1_carry__1_i_6_n_0\
);
\z1_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => y(19),
I3 => x(19),
O => \z1_carry__1_i_7_n_0\
);
\z1_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => y(17),
I3 => x(17),
O => \z1_carry__1_i_8_n_0\
);
\z1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \z1_carry__1_n_0\,
CO(3) => z1,
CO(2) => \z1_carry__2_n_1\,
CO(1) => \z1_carry__2_n_2\,
CO(0) => \z1_carry__2_n_3\,
CYINIT => '0',
DI(3) => \z1_carry__2_i_1_n_0\,
DI(2) => \z1_carry__2_i_2_n_0\,
DI(1) => \z1_carry__2_i_3_n_0\,
DI(0) => \z1_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_z1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \z1_carry__2_i_5_n_0\,
S(2) => \z1_carry__2_i_6_n_0\,
S(1) => \z1_carry__2_i_7_n_0\,
S(0) => \z1_carry__2_i_8_n_0\
);
\z1_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(30),
I1 => x(30),
I2 => x(31),
I3 => y(31),
O => \z1_carry__2_i_1_n_0\
);
\z1_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(28),
I1 => x(28),
I2 => x(29),
I3 => y(29),
O => \z1_carry__2_i_2_n_0\
);
\z1_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(26),
I1 => x(26),
I2 => x(27),
I3 => y(27),
O => \z1_carry__2_i_3_n_0\
);
\z1_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => x(25),
I3 => y(25),
O => \z1_carry__2_i_4_n_0\
);
\z1_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(30),
I1 => x(30),
I2 => y(31),
I3 => x(31),
O => \z1_carry__2_i_5_n_0\
);
\z1_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(28),
I1 => x(28),
I2 => y(29),
I3 => x(29),
O => \z1_carry__2_i_6_n_0\
);
\z1_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(26),
I1 => x(26),
I2 => y(27),
I3 => x(27),
O => \z1_carry__2_i_7_n_0\
);
\z1_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => y(25),
I3 => x(25),
O => \z1_carry__2_i_8_n_0\
);
\z1_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => z1,
CO(3 downto 0) => \NLW_z1_carry__3_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_z1_carry__3_O_UNCONNECTED\(3 downto 1),
O(0) => z,
S(3 downto 0) => B"0001"
);
z1_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(6),
I1 => x(6),
I2 => x(7),
I3 => y(7),
O => z1_carry_i_1_n_0
);
z1_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(4),
I1 => x(4),
I2 => x(5),
I3 => y(5),
O => z1_carry_i_2_n_0
);
z1_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(2),
I1 => x(2),
I2 => x(3),
I3 => y(3),
O => z1_carry_i_3_n_0
);
z1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => y(0),
I1 => x(0),
I2 => x(1),
I3 => y(1),
O => z1_carry_i_4_n_0
);
z1_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(6),
I1 => x(6),
I2 => y(7),
I3 => x(7),
O => z1_carry_i_5_n_0
);
z1_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(4),
I1 => x(4),
I2 => y(5),
I3 => x(5),
O => z1_carry_i_6_n_0
);
z1_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(2),
I1 => x(2),
I2 => y(3),
I3 => x(3),
O => z1_carry_i_7_n_0
);
z1_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => y(0),
I1 => x(0),
I2 => y(1),
I3 => x(1),
O => z1_carry_i_8_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_comparator_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_comparator_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_comparator_0_0 : entity is "system_comparator_0_0,comparator,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_comparator_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_comparator_0_0 : entity is "comparator,Vivado 2016.4";
end system_comparator_0_0;
architecture STRUCTURE of system_comparator_0_0 is
begin
U0: entity work.system_comparator_0_0_comparator
port map (
x(31 downto 0) => x(31 downto 0),
y(31 downto 0) => y(31 downto 0),
z => z
);
end STRUCTURE;
| mit | ba12115a802789a1f53b3f7291a3f38c | 0.490267 | 2.462863 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_3/Uart_working/RS232RefComp.vhd | 2 | 10,758 |
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock = 50MHz
DBIN: in std_logic_vector (7 downto 0); --Data Bus in
DBOUT: out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := x"00"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal trainingdone: std_logic:= '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; | mit | e9d5a258a65f6249098d17b949589824 | 0.54499 | 3.086059 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dspalu_acc.vhd | 2 | 13,985 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dsputil_pac.all;
-------------------------------------------------------------------------------
entity dspalu_acc is
generic (
sig_width : integer := 16;
acc_width : integer := 32;
acc_reduce_width : integer := 32);
port (
--@inputs
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : in std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
--@outputs
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end dspalu_acc;
--=----------------------------------------------------------------------------
architecture archi_dspalu_acc of dspalu_acc is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_result1 : signed((2*sig_width - 1) downto 0);
signal s_result2 : signed((2*sig_width - 1) downto 0);
signal s_mul_out1 : signed((2*sig_width - 1) downto 0);
signal s_mul_out2 : signed((2*sig_width - 1) downto 0);
signal s_result_acc1 : signed((acc_width - 1) downto 0);
signal s_result_acc2 : signed((acc_width - 1) downto 0);
signal s_back_acc1 : signed((acc_width - 1) downto 0);
signal s_back_acc2 : signed((acc_width - 1) downto 0);
signal s_cmp_reg : signed((acc_width - 1) downto 0);
signal s_cmp_in : signed((acc_width - 1) downto 0);
signal s_cmp_reg_r : unsigned((acc_reduce_width - 2) downto 0);
signal s_cmp_in_r : unsigned((acc_reduce_width - 2) downto 0);
signal s_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode1_n1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2_n1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode1_inreg : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_acc_mode2_inreg : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_cmul_acc_mode1 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_cmul_acc_mode2 : std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
signal s_mul_a1 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a2 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b1 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a1_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_a2_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b1_in : std_logic_vector((sig_width - 1) downto 0);
signal s_mul_b2_in : std_logic_vector((sig_width - 1) downto 0);
type t_cmul_state is (cmul_step, cmul_end);
signal s_cmul_state : t_cmul_state;
signal s_cmp_greater : std_logic;
signal s_cmp_greater_inreg : std_logic;
signal s_b2 : std_logic_vector((sig_width - 1) downto 0);
signal s_cmp_store : std_logic;
begin -- archs_dspalu_acc
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- First accumulator
-------------------------------------------------------------------------------
p_acc1 : process (clk)
variable v_tmp_acc1 : signed((acc_width - 1) downto 0);
begin -- process p_acc
if rising_edge(clk) then -- rising clock edge
if(clr_acc = '1') then
s_result_acc1 <= (others => '0');
else
v_tmp_acc1 := resize(s_result1, acc_width);
-- Accumulation mode
case s_acc_mode1 is
when acc_store =>
s_result_acc1 <= v_tmp_acc1;
when acc_sumstore =>
s_result_acc1 <= resize(signed(s_result1) + signed(s_result2), acc_width);
when acc_add =>
s_result_acc1 <= s_result_acc1 + v_tmp_acc1;
when acc_sub =>
s_result_acc1 <= s_result_acc1 - v_tmp_acc1;
when acc_back_add =>
s_result_acc1 <= s_back_acc1 + v_tmp_acc1;
when acc_minback_sub =>
s_result_acc1 <= - v_tmp_acc1 - s_back_acc1;
when others =>
s_result_acc1 <= (others => '0');
end case;
-- backup of accumulator content
s_back_acc1 <= s_result_acc1;
end if;
end if;
end process p_acc1;
-------------------------------------------------------------------------------
-- Second accumulator
-------------------------------------------------------------------------------
p_acc2 : process (clk)
variable v_tmp_acc2 : signed((acc_width - 1) downto 0);
begin -- process p_acc
if rising_edge(clk) then -- rising clock edge
if(clr_acc = '1') then
s_result_acc2 <= (others => '0');
else
v_tmp_acc2 := resize(s_result2, acc_width);
-- Accumulation mode
case s_acc_mode2 is
when acc_store =>
s_result_acc2 <= v_tmp_acc2;
when acc_diff =>
-- s_result_acc2 <= resize(signed(a2) + signed(b2), acc_width);
s_result_acc2 <= s_result_acc2 - s_result_acc1;
when acc_abs =>
s_result_acc2 <= s_result_acc2 + dsp_abs(s_result_acc1);
when acc_add =>
s_result_acc2 <= s_result_acc2 + v_tmp_acc2;
when acc_sub =>
s_result_acc2 <= s_result_acc2 - v_tmp_acc2;
when acc_back_add =>
s_result_acc2 <= s_back_acc2 + v_tmp_acc2;
when acc_minback_sub =>
s_result_acc2 <= - v_tmp_acc2 - s_back_acc2;
when others =>
s_result_acc2 <= (others => '0');
end case;
-- backup of accumulator content
s_back_acc2 <= s_result_acc2;
end if;
end if;
end process p_acc2;
-------------------------------------------------------------------------------
-- Comparator
-------------------------------------------------------------------------------
-- p_cmp_in : process (cmp_mode, s_result_acc1, s_result_acc2, s_cmp_reg, s_cmp_in)
p_cmp_in : process (clk)
begin -- process p_cmp_in
if rising_edge(clk) then
case cmp_mode is
when cmp_acc1 =>
if(s_result_acc1(acc_width - 1) = '0') then
s_cmp_in <= s_result_acc1;
else
s_cmp_in <= not s_result_acc1;
end if;
when cmp_acc2 =>
if(s_result_acc2(acc_width - 1) = '0') then
s_cmp_in <= s_result_acc2;
else
s_cmp_in <= not s_result_acc2;
end if;
when others =>
s_cmp_in <= (others => '0');
end case;
s_cmp_greater <= s_cmp_greater_inreg;
end if;
end process p_cmp_in;
s_cmp_reg_r <= unsigned(s_cmp_reg((acc_width - 2) downto (acc_width - acc_reduce_width))) ;
s_cmp_in_r <= unsigned(s_cmp_in((acc_width - 2) downto (acc_width - acc_reduce_width)));
s_cmp_greater_inreg <= '1' when s_cmp_reg_r < s_cmp_in_r else '0';
-- s_cmp_greater_inreg <= '1' when s_cmp_reg < s_cmp_in else '0';
p_cmp : process (clk)
begin -- process p_cmp_in
if rising_edge(clk) then -- rising clock edge
s_cmp_store <= cmp_store;
-- if(((s_cmp_greater_inreg xor cmp_pol) or s_cmp_store) = '1') then
if(s_cmp_store = '1') then
s_cmp_reg <= s_cmp_in;
elsif(s_cmp_greater_inreg = '1') then
s_cmp_reg <= s_cmp_in;
else
s_cmp_reg <= s_cmp_reg;
end if;
end if;
end process p_cmp;
-------------------------------------------------------------------------------
-- Operation controller (manage the complex multiplication)
-------------------------------------------------------------------------------
p_alu_ctrl : process (clk)
begin -- process p_alu_ctrl
if rising_edge(clk) then -- rising clock edge
if (alu_select = alu_mul or alu_select = alu_none) then
s_cmul_state <= cmul_end;
elsif (s_cmul_state = cmul_step) then
s_cmul_state <= cmul_end;
else
s_cmul_state <= cmul_step;
end if;
end if;
end process p_alu_ctrl;
p_mul_reg : process (clk)
begin -- process p_mul_reg
if rising_edge(clk) then -- rising clock edge
s_result1 <= s_mul_out1;
s_result2 <= s_mul_out2;
s_acc_mode1 <= s_acc_mode1_n1;
s_acc_mode2 <= s_acc_mode2_n1;
s_acc_mode1_n1 <= s_acc_mode1_inreg;
s_acc_mode2_n1 <= s_acc_mode2_inreg;
end if;
end process p_mul_reg;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
result1 <= std_logic_vector(s_result1((2*sig_width - 2) downto (sig_width - 1)));
result2 <= std_logic_vector(s_result2((2*sig_width - 2) downto (sig_width - 1)));
s_mul_out1 <= signed(s_mul_a1) * signed(s_mul_b1);
s_mul_out2 <= signed(s_mul_a2) * signed(s_mul_b2);
result_acc1 <= std_logic_vector(s_result_acc1);
result_acc2 <= std_logic_vector(s_result_acc2);
-- accumulation mode is given by acc_modex except during complex multiplication (modified for step 2)
s_cmul_acc_mode1 <= acc_add when acc_mode1 = acc_sub else acc_sub;
s_cmul_acc_mode2 <= acc_sub when acc_mode1 = acc_sub else acc_add;
-- TODO move the mux to s_acc_modeX_n1!!!!
s_acc_mode1_inreg <= s_cmul_acc_mode1 when s_cmul_state = cmul_step else acc_mode1;
s_acc_mode2_inreg <= s_cmul_acc_mode2 when s_cmul_state = cmul_step else acc_mode2;
-- multipliers inputs (special selection during complex multiplication)
p_mul_in_reg : process (clk)
begin -- process p_mul_reg
if rising_edge(clk) then -- rising clock edge
s_mul_a1 <= s_mul_a1_in;
s_mul_a2 <= s_mul_a2_in;
s_mul_b1 <= s_mul_b1_in;
s_mul_b2 <= s_mul_b2_in;
end if;
end process p_mul_in_reg;
s_mul_a1_in <= a2 when s_cmul_state = cmul_step else a1;
s_mul_a2_in <= a1 when s_cmul_state = cmul_step else a2;
s_mul_b1_in <= s_b2 when s_cmul_state = cmul_step else b1;
-- ! can be more time critical than other entries because depends on alu_select
s_mul_b2_in <= b1 when (s_cmul_state = cmul_end and (alu_select = alu_cmul or alu_select = alu_cmul_conj)) else s_b2;
-- ------------------------------------------------------------------------------------------------------------------------
s_b2 <= std_logic_vector(-signed(b2)) when alu_select = alu_cmul_conj else b2;
cmp_reg <= std_logic_vector(s_cmp_reg);
cmp_greater <= s_cmp_greater;
end archi_dspalu_acc;
-------------------------------------------------------------------------------
| gpl-3.0 | e986c43b10255417bcfdd5dad175ba2c | 0.486593 | 3.524446 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/hdl/reg_file.vhd | 1 | 3,485 | -------------------------------------------------------------------------------
-- Title : Register File
-- Project :
-------------------------------------------------------------------------------
-- File : reg_file.vhd
-- Author : Calle <calle@Alukiste>
-- Created : 2012-03-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Multiple 16-bit registers at the internal parallel data bus with address
-- decoding.
-------------------------------------------------------------------------------
-- Copyright (c) 2012, 2016
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.reset_pkg.all;
entity reg_file is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#; -- Base address of the registers
REG_ADDR_BIT : natural := 0; -- number of bits not to compare in
-- address. Gives 2**n registers
RESET_IMPL : reset_type := none
);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reg_o : out reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reg_i : in reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reset : in std_logic;
clk : in std_logic);
end reg_file;
-------------------------------------------------------------------------------
architecture str of reg_file is
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) := std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
type reg_file_state_type is record
reg : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
constant reg_file_state_type_initial : reg_file_state_type := (reg => (others => (others => '0')), data_out => (others => '0'));
signal r, rin : reg_file_state_type := reg_file_state_type_initial;
begin -- str
bus_o.data <= r.data_out;
reg_o <= r.reg;
comb : process (bus_i.addr, bus_i.data, bus_i.re, bus_i.we, r, reg_i, reset) is
variable v : reg_file_state_type;
variable index : integer := 0;
begin -- process comb
v := r;
index := to_integer(unsigned(bus_i.addr(REG_ADDR_BIT-1 downto 0)));
if bus_i.addr(14 downto REG_ADDR_BIT) = BASE_ADDRESS_VECTOR(14 downto REG_ADDR_BIT) then
if bus_i.we = '1' then
v.reg(index) := bus_i.data;
end if;
end if;
if (bus_i.addr(14 downto REG_ADDR_BIT) = BASE_ADDRESS_VECTOR(14 downto REG_ADDR_BIT)) and bus_i.re = '1' then
v.data_out := reg_i(index);
else
v.data_out := (others => '0');
end if;
-- sync reset
if RESET_IMPL = sync and reset = '1' then
v := reg_file_state_type_initial;
end if;
rin <= v;
end process comb;
async_reset : if RESET_IMPL = async generate
seq : process (clk, reset) is
begin -- process seq
if reset = '0' then -- asynchronous reset (active low)
r <= reg_file_state_type_initial;
elsif clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
sync_reset : if RESET_IMPL /= async generate
seq : process (clk) is
begin -- process seq
if clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
end str;
| bsd-3-clause | 0cb9c670d647a536796833b7d2a70856 | 0.523386 | 3.556122 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/sim/system_zybo_hdmi_0_0.vhd | 3 | 3,818 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
| mit | 071a42bd3530469d837b65962ff345ba | 0.699843 | 3.833333 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/axi_vga_framebuffer_1.0/hdl/axi_vga_framebuffer_v1_0.vhd | 1 | 4,600 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end axi_vga_framebuffer_v1_0;
architecture arch_imp of axi_vga_framebuffer_v1_0 is
-- component declaration
component axi_vga_framebuffer_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- user ports
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
--
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_vga_framebuffer_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
axi_vga_framebuffer_v1_0_S_AXI_inst : axi_vga_framebuffer_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
clk => clk,
active => active,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| mit | 0519427a31d396f2838dccf68f92399a | 0.64 | 2.483801 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_1_0/sim/system_util_vector_logic_1_0.vhd | 1 | 3,426 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY system_util_vector_logic_1_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_vector_logic_1_0;
ARCHITECTURE system_util_vector_logic_1_0_arch OF system_util_vector_logic_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_vector_logic_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "or",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END system_util_vector_logic_1_0_arch;
| mit | 54ba9558bab0365509bcedd34fcf99f1 | 0.725628 | 3.937931 | false | false | false | false |
loa-org/loa-hdl | modules/uart/hdl/uart_tx.vhd | 1 | 4,673 | -------------------------------------------------------------------------------
-- Title : UART Transmitter with Odd-Parity
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
--
-- Data is send with LSB (Least Significat Bit) first.
-- Odd-parity. Example:
--
-- 0000 0000 => parity 1
-- 0000 0001 => parity 0
-- 0000 0010 => parity 0
-- 0000 0011 => parity 1
-- ...
-- 1111 1111 => parity 1
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.uart_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
entity uart_tx is
generic (
RESET_IMPL : reset_type := none
);
port (
txd_p : out std_logic;
busy_p : out std_logic;
data_p : in std_logic_vector(7 downto 0);
empty_p : in std_logic;
re_p : out std_logic;
clk_tx_en : in std_logic;
reset : in std_logic;
clk : in std_logic);
end uart_tx;
-------------------------------------------------------------------------------
architecture behavioural of uart_tx is
type transmit_states is (IDLE, START, WAITSTATE, WAITSTATE2, DATA, PARITY, STOP);
type uart_tx_type is record
state : transmit_states;
bitcount : integer range 0 to 8;
parity : std_logic;
txd : std_logic; -- Output pin
-- Input FIFO
shift_reg : std_logic_vector(7 downto 0);
fifo_re : std_logic;
end record;
constant uart_tx_type_initial : uart_tx_type := (
state => IDLE,
bitcount => 0,
parity => '0',
txd => '1',
shift_reg => (others => '0'),
fifo_re => '0');
signal r, rin : uart_tx_type := uart_tx_type_initial;
begin
-- Connections between ports and signals
txd_p <= r.txd;
re_p <= r.fifo_re;
busy_p <= '0' when ((r.state = IDLE) and (empty_p = '1')) else '1';
-- Combinatorial part of FSM
comb_proc : process(clk_tx_en, data_p, empty_p, r, reset)
variable v : uart_tx_type;
begin
v := r;
v.fifo_re := '0';
case r.state is
when IDLE =>
if empty_p = '0' then
v.fifo_re := '1';
v.state := WAITSTATE;
end if;
when WAITSTATE =>
v.state := WAITSTATE2;
when WAITSTATE2 =>
v.shift_reg := data_p;
v.state := START;
when START =>
if clk_tx_en = '1' then
v.txd := '0';
v.state := DATA;
v.bitcount := 0;
v.parity := '0';
end if;
when DATA =>
if clk_tx_en = '1' then
-- Send data with LSB first
v.txd := r.shift_reg(0);
-- data parity
-- 0 + 0 => 0
-- 0 + 1 => 1
-- 1 + 0 => 1
-- 1 + 1 => 0
-- => xor
v.parity := r.parity xor r.shift_reg(0);
v.shift_reg := '0' & r.shift_reg(7 downto 1);
if r.bitcount = 7 then
v.state := PARITY;
else
v.bitcount := r.bitcount + 1;
end if;
end if;
when PARITY =>
if clk_tx_en = '1' then
v.txd := not r.parity;
v.state := STOP;
end if;
when STOP =>
if clk_tx_en = '1' then
v.txd := '1';
v.state := IDLE;
end if;
end case;
-- sync reset
if RESET_IMPL = sync then
if reset = '1' then
v := uart_tx_type_initial;
end if;
end if;
rin <= v;
end process comb_proc;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
reset_async : if RESET_IMPL = async generate
seq_proc : process(clk, reset)
begin
if reset = '1' then
r <= uart_tx_type_initial; -- async reset
elsif rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
end generate reset_async;
reset_sync : if not (RESET_IMPL = async) generate
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
end generate reset_sync;
-- Component instantiations
end behavioural;
| bsd-3-clause | 924a61a54323c5644d5cf21e611c9a76 | 0.430773 | 3.900668 | false | false | false | false |
loa-org/loa-hdl | modules/dds/tb/dds_module_tb.vhd | 1 | 4,280 | -------------------------------------------------------------------------------
-- Title : Testbench for design "dds_module"
-------------------------------------------------------------------------------
-- Author : Carl Treudler
-- Standard :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dds_module_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
entity dds_module_tb is
end dds_module_tb;
-------------------------------------------------------------------------------
architecture tb of dds_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#400#;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal dout : std_logic_vector(15 downto 0);
signal reset : std_logic;
signal clk : std_logic := '1';
begin
dds_module_1 : entity work.dds_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
RESET_IMPL => none)
port map (
bus_o => bus_o,
bus_i => bus_i,
dout => dout,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- reset generation
reset <= '1', '0' after 50 ns;
waveform : process
begin
wait until falling_edge(reset);
wait for 20 us;
---------------------------------------------------------------------------
-- load some data into waveform ram
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#400#, 15));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#401#, 15));
bus_i.data <= x"0124";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#402#, 15));
bus_i.data <= x"0125";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 1 us;
---------------------------------------------------------------------------
-- Set Phase increment
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#801#, 15));
bus_i.data <= x"0001";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#802#, 15));
bus_i.data <= x"0020";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
---------------------------------------------------------------------------
-- Set Phase -- 0°
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#803#, 15));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#804#, 15));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
---------------------------------------------------------------------------
-- set Control Register
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#800#, 15));
bus_i.data <= x"0002"; -- load accu0
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#800#, 15));
bus_i.data <= x"0001"; -- enable nco0
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 us;
end process waveform;
end tb;
| bsd-3-clause | 589e2bca8cacec0ad6f6882bb54e38f3 | 0.404534 | 4.098659 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0_1/system_vga_color_test_0_0_sim_netlist.vhdl | 1 | 24,812 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:08 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_color_test_0_0 -prefix
-- system_vga_color_test_0_0_ system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
| mit | 8563fd6aaf3b6fca18f88e021d3b8a6d | 0.47606 | 2.484679 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/src/colour_space_conversion.vhd | 1 | 43,843 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Module Name: colour_space_conversion - Behavioral
--
-- Description: Convert the input pixel data into YCbCr 422 values
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity colour_space_conversion is
Port ( clk : in STD_LOGIC;
r1_in : IN std_logic_vector(8 downto 0);
g1_in : IN std_logic_vector(8 downto 0);
b1_in : IN std_logic_vector(8 downto 0);
r2_in : IN std_logic_vector(8 downto 0);
g2_in : IN std_logic_vector(8 downto 0);
b2_in : IN std_logic_vector(8 downto 0);
pair_start_in: IN std_logic;
de_in : IN std_logic;
vsync_in : IN std_logic;
hsync_in : IN std_logic;
y_out : OUT std_logic_vector(7 downto 0);
c_out : OUT std_logic_vector(7 downto 0);
de_out : OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic
);
end colour_space_conversion;
architecture Behavioral of colour_space_conversion is
signal d_a : std_logic;
signal h_a : std_logic;
signal v_a : std_logic;
signal c1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal a_r1, a_g1, a_b1 : STD_LOGIC_VECTOR(29 DOWNTO 0);
signal b_r1, b_g1, b_b1 : STD_LOGIC_VECTOR(17 DOWNTO 0);
signal pc_r1, pc_g1, p_b1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal c2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal a_r2, a_g2 , a_b2 : STD_LOGIC_VECTOR(29 DOWNTO 0);
signal b_r2, b_g2, b_b2 : STD_LOGIC_VECTOR(17 DOWNTO 0);
signal pc_r2, pc_g2, p_b2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal hs_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
signal vs_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
signal de_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
begin
-- y = ( 8432 * r + 16425 * g + 3176 * B) / 32768 + 16;
-- cb = (-4818 * r - 9527 * g + 14345 * B) / 32768 + 128;
-- cr = (14345 * r - 12045 * g - 2300 * B) / 32768 + 128;
c1 <= x"002000000000";
a_r1 <= "000000" & r1_in & x"000" & "000";
a_g1 <= "000000" & g1_in & x"000" & "000";
a_b1 <= "000000" & b1_in & x"000" & "000";
c2 <= x"010000000000";
a_r2 <= "000000" & r2_in & x"000" & "000";
a_g2 <= "000000" & g2_in & x"000" & "000";
a_b2 <= "000000" & b2_in & x"000" & "000";
b_r1 <= x"20F0"&"00";
b_g1 <= x"4029"&"00";
b_b1 <= x"0C68"&"00";
b_r2 <= x"ED2E"&"00" when pair_start_in = '1' else x"3809"&"00";
b_g2 <= x"DAC9"&"00" when pair_start_in = '1' else x"D0F3"&"00";
b_b2 <= x"3809"&"00" when pair_start_in = '1' else x"F704"&"00";
process(clk)
begin
if rising_edge(clk) then
hsync_out <= hs_delay(hs_delay'high);
vsync_out <= vs_delay(vs_delay'high);
de_out <= de_delay(de_delay'high);
de_delay <= de_delay(de_delay'high-1 downto 0) & de_in;
vs_delay <= vs_delay(de_delay'high-1 downto 0) & vsync_in;
hs_delay <= hs_delay(de_delay'high-1 downto 0) & hsync_in;
y_out <= p_b1(40 downto 33);
c_out <= p_b2(40 downto 33);
end if;
end process;
mult_r1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_r1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_r1, -- 30-bit input: A data input
B => b_r1, -- 18-bit input: B data input
C => c1, -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_g1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) input: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_g1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_r1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_g1, -- 30-bit input: A data input
B => b_g1, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_b1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 2, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 2, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_b1, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others =>'0'), -- 30-bit input: A cascade data input
BCIN => (others =>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_g1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_b1, -- 30-bit input: A data input
B => b_b1, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
-----------------------------------------
mult_r2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_r2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_r2, -- 30-bit input: A data input
B => b_r2, -- 18-bit input: B data input
C => c2, -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_g2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_g2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'), -- 30-bit input: A cascade data input
BCIN => (others=>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_r2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_g2, -- 30-bit input: A data input
B => b_g2, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_b2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 2, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 2, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 2, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 2, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_b2, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others =>'0'), -- 30-bit input: A cascade data input
BCIN => (others =>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_g2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_b2, -- 30-bit input: A data input
B => b_b2, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
end Behavioral; | mit | b157662095b37d6bf46175512bda80bb | 0.520699 | 4.126012 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 33,348 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_reg28_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
component superip_internal is
port(
-- Outputs
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : out STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg26 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when "00000000000000000000000000001000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000010" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000001" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when others => null;
end case;
slv_reg28 <= slv_reg28_internal;
slv_reg29 <= slv_reg29_internal;
slv_reg30 <= slv_reg30_internal;
slv_reg31 <= slv_reg31_internal;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31 ) is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= slv_reg0;
when "01000000000000000000000000000000" => slv_ip2bus_data <= slv_reg1;
when "00100000000000000000000000000000" => slv_ip2bus_data <= slv_reg2;
when "00010000000000000000000000000000" => slv_ip2bus_data <= slv_reg3;
when "00001000000000000000000000000000" => slv_ip2bus_data <= slv_reg4;
when "00000100000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "00000010000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "00000001000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "00000000100000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "00000000010000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "00000000000010000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "00000000000001000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "00000000000000100000000000000000" => slv_ip2bus_data <= slv_reg14;
when "00000000000000010000000000000000" => slv_ip2bus_data <= slv_reg15;
when "00000000000000001000000000000000" => slv_ip2bus_data <= slv_reg16;
when "00000000000000000100000000000000" => slv_ip2bus_data <= slv_reg17;
when "00000000000000000010000000000000" => slv_ip2bus_data <= slv_reg18;
when "00000000000000000001000000000000" => slv_ip2bus_data <= slv_reg19;
when "00000000000000000000100000000000" => slv_ip2bus_data <= slv_reg20;
when "00000000000000000000010000000000" => slv_ip2bus_data <= slv_reg21;
when "00000000000000000000001000000000" => slv_ip2bus_data <= slv_reg22;
when "00000000000000000000000100000000" => slv_ip2bus_data <= slv_reg23;
when "00000000000000000000000010000000" => slv_ip2bus_data <= slv_reg24;
when "00000000000000000000000001000000" => slv_ip2bus_data <= slv_reg25;
when "00000000000000000000000000100000" => slv_ip2bus_data <= slv_reg26;
when "00000000000000000000000000010000" => slv_ip2bus_data <= slv_reg27;
when "00000000000000000000000000001000" => slv_ip2bus_data <= slv_reg28;
when "00000000000000000000000000000100" => slv_ip2bus_data <= slv_reg29;
when "00000000000000000000000000000010" => slv_ip2bus_data <= slv_reg30;
when "00000000000000000000000000000001" => slv_ip2bus_data <= slv_reg31;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
SIP : superip_internal port map (
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left_out,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right_out,
slv_reg28 => slv_reg28_internal ,
slv_reg29 => slv_reg29_internal ,
slv_reg30 => slv_reg30_internal ,
slv_reg31 => slv_reg31_internal ,
CLK_48_in => CLK_48_in ,
CLK_100M_in => CLK_100M_in ,
Audio_Left_in => Audio_Left_in ,
Audio_Right_in => Audio_Right_in ,
slv_reg0 => slv_reg0 ,
slv_reg1 => slv_reg1 ,
slv_reg2 => slv_reg2 ,
slv_reg3 => slv_reg3 ,
slv_reg4 => slv_reg4 ,
slv_reg5 => slv_reg5 ,
slv_reg6 => slv_reg6 ,
slv_reg7 => slv_reg7 ,
slv_reg8 => slv_reg8 ,
slv_reg9 => slv_reg9 ,
slv_reg10 => slv_reg10 ,
slv_reg11 => slv_reg11 ,
slv_reg12 => slv_reg12 ,
slv_reg13 => slv_reg13 ,
slv_reg14 => slv_reg14 ,
slv_reg15 => slv_reg15 ,
slv_reg16 => slv_reg16 ,
slv_reg17 => slv_reg17 ,
slv_reg18 => slv_reg18 ,
slv_reg19 => slv_reg19 ,
slv_reg20 => slv_reg20 ,
slv_reg21 => slv_reg21 ,
slv_reg22 => slv_reg22 ,
slv_reg23 => slv_reg23 ,
slv_reg24 => slv_reg24 ,
slv_reg25 => slv_reg25 ,
slv_reg26 => slv_reg26 ,
slv_reg27 => slv_reg27
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 33711a2c871f8ba130037370dacfbfc5 | 0.518832 | 3.675116 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd | 3 | 142,619 | `protect begin_protected
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`protect end_protected
| mit | be7f3e558a8d014390063c4be7cd0a26 | 0.953926 | 1.811426 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/new/svd_2x2.vhd | 1 | 4,974 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity svd_2x2 is
port (
clk : in std_logic;
start : in std_logic;
ready : out std_logic;
m_00 : in std_logic_vector(15 downto 0);
m_01 : in std_logic_vector(15 downto 0);
m_10 : in std_logic_vector(15 downto 0);
m_11 : in std_logic_vector(15 downto 0);
s_x : out std_logic_vector(15 downto 0);
s_y : out std_logic_vector(15 downto 0);
phi : out std_logic_vector(15 downto 0);
theta : out std_logic_vector(15 downto 0)
);
end svd_2x2;
architecture Behavioral of svd_2x2 is
component sqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END component;
component arctan IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END component;
signal m_00_2, m_01_2, m_10_2, m_11_2 : unsigned(15 downto 0);
signal e, f, g, h, q_2, r_2 : unsigned(15 downto 0);
signal q, r, a1, a2 : std_logic_vector(15 downto 0);
signal e_2, h_2, f_2, g_2 : unsigned(31 downto 0);
signal start_sqrt, start_atan, ready_sqrt_q, ready_sqrt_r, ready_atan_1, ready_atan_2 : std_logic := '0';
signal running : std_logic := '0';
signal cycle : std_logic_vector(1 downto 0) := "00";
begin
process(clk)
begin
if rising_edge(clk) then
if start = '1' and running = '0' then
running <= '1';
start_sqrt <= '0';
start_atan <= '0';
elsif running = '1' then
if cycle = "00" then
m_00_2 <= unsigned(m_00) srl 1;
m_01_2 <= unsigned(m_01) srl 1;
m_10_2 <= unsigned(m_10) srl 1;
m_11_2 <= unsigned(m_11) srl 1;
cycle <= "01";
elsif cycle = "01" then
e <= m_00_2 + m_11_2;
f <= m_00_2 - m_11_2;
g <= m_10_2 + m_01_2;
h <= m_10_2 - m_01_2;
cycle <= "10";
elsif cycle = "10" then
start_atan <= '1';
e_2 <= (e * e) srl 15; -- shift right by 16-1 since sqrt only has a single radix point
f_2 <= (f * f) srl 15;
g_2 <= (g * g) srl 15;
h_2 <= (h * h) srl 15;
cycle <= "11";
elsif cycle = "11" then
if start_sqrt = '0' then
q_2 <= e_2(15 downto 0) + h_2(15 downto 0);
r_2 <= f_2(15 downto 0) + g_2(15 downto 0);
start_sqrt <= '1';
elsif ready_sqrt_q = '1' and ready_sqrt_r = '1' and ready_atan_1 = '1' and ready_atan_2 = '1' then
s_x <= std_logic_vector(unsigned(q) + unsigned(r));
s_y <= std_logic_vector(signed(q) - signed(r));
theta <= std_logic_vector(signed(a2) - signed(a1));
phi <= std_logic_vector(unsigned(a2) + unsigned(a1));
running <= '0';
end if;
end if;
end if;
end if;
end process;
ready <= not running;
SQRT_q : sqrt port map (
aclk => clk,
s_axis_cartesian_tvalid => start_sqrt,
s_axis_cartesian_tdata => std_logic_vector(q_2),
m_axis_dout_tvalid => ready_sqrt_q,
m_axis_dout_tdata => q
);
SQRT_r : sqrt port map (
aclk => clk,
s_axis_cartesian_tvalid => start_sqrt,
s_axis_cartesian_tdata => std_logic_vector(r_2),
m_axis_dout_tvalid => ready_sqrt_r,
m_axis_dout_tdata => r
);
ATAN_a1 : arctan port map (
aclk => clk,
s_axis_cartesian_tvalid => start_atan,
s_axis_cartesian_tdata(31 downto 16) => std_logic_vector(g),
s_axis_cartesian_tdata(15 downto 0) => std_logic_vector(f),
m_axis_dout_tvalid => ready_atan_1,
m_axis_dout_tdata => a1
);
ATAN_a2 : arctan port map (
aclk => clk,
s_axis_cartesian_tvalid => start_atan,
s_axis_cartesian_tdata(31 downto 16) => std_logic_vector(h),
s_axis_cartesian_tdata(15 downto 0) => std_logic_vector(e),
m_axis_dout_tvalid => ready_atan_2,
m_axis_dout_tdata => a2
);
end Behavioral;
| mit | a737676ab386ff555a773e67e5b64d87 | 0.477483 | 3.446985 | false | false | false | false |
loa-org/loa-hdl | modules/adc_mcp3008/hdl/adc_mcp3008.vhd | 2 | 7,071 | -------------------------------------------------------------------------------
-- Title : Interface for Microchip MCP3008 ADC
-- Project : Loa
-------------------------------------------------------------------------------
-- Description: Interface to Microchip's 8 channel 10-bit ADC (MCP3008).
-- Converversion started by logical 1 on start_p. '1' on done_p
-- signals completetd conversion.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.adc_mcp3008_pkg.all;
-------------------------------------------------------------------------------
entity adc_mcp3008 is
generic (
DELAY : natural := 39 -- waitstates between toggling the
-- SCK line (MCP3008 max: about 1.3
-- MHz)
);
port (
adc_out : out adc_mcp3008_spi_out_type;
adc_in : in adc_mcp3008_spi_in_type;
start_p : in std_logic; -- starts the acquisition cycle
adc_mode_p : in std_logic; -- single-ended or differential mode of ADC
channel_p : in std_logic_vector(2 downto 0); -- select channel of ADC
value_p : out std_logic_vector(9 downto 0); -- last value from ADC
done_p : out std_logic; -- conversion reads
clk : in std_logic
);
end adc_mcp3008;
-------------------------------------------------------------------------------
architecture behavioral of adc_mcp3008 is
-----------------------------------------------------------------------------
-- FSM Type declaration
-----------------------------------------------------------------------------
type adc_mcp3008_state_type is (IDLE, SCK_LOW, SCK_HIGH, HOLD_OFF);
type adc_mcp3008_type is record
state : adc_mcp3008_state_type;
csn : std_logic;
sck : std_logic;
din : std_logic_vector(9 downto 0);
done : std_logic;
countdown_delay : integer range 0 to (DELAY * 16);
countdown_bit : integer range 0 to 16;
dout : std_logic_vector(4 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_mcp3008_type := (state => IDLE,
csn => '1',
sck => '0',
dout => "11111",
din => (others => '0'),
done => '0',
countdown_bit => 0,
countdown_delay => DELAY);
begin
-----------------------------------------------------------------------------
-- patch signals to outside of module
-----------------------------------------------------------------------------
-- outputs to adc
adc_out.cs_n <= r.csn;
adc_out.sck <= r.sck;
adc_out.mosi <= r.dout(4);
-- outputs
done_p <= r.done; -- signals valid data on value_p
value_p <= r.din; -- value of the last conversion fetched
-- from the ADC
-----------------------------------------------------------------------------
-- Sequential proc of FSM
-----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- Transitons and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(adc_in.miso, adc_mode_p, channel_p, r, r.countdown_bit,
r.countdown_delay, r.din(8 downto 0),
r.dout(3 downto 0), r.state, start_p)
variable v : adc_mcp3008_type;
begin
v := r;
case r.state is
-------------------------------------------------------------------------
-- Idle State
-------------------------------------------------------------------------
when IDLE =>
v.csn := '1';
v.done := '0';
if start_p = '1' then
v.state := SCK_LOW;
v.sck := '0';
v.countdown_delay := DELAY;
v.countdown_bit := 16;
v.dout := '1' & adc_mode_p & channel_p;
end if;
-------------------------------------------------------------------------
-- Low period of SCK cycle
-------------------------------------------------------------------------
when SCK_LOW =>
v.csn := '0';
if r.countdown_delay = 0 then
v.state := SCK_HIGH;
v.sck := '1';
v.countdown_delay := DELAY;
-- shift in data from ADC
-- miso is an external signal but is assumed to be in sync with SCK
-- so no synchronization needed here.
v.din := r.din(8 downto 0) & adc_in.miso;
else
v.countdown_delay := v.countdown_delay -1;
end if;
-------------------------------------------------------------------------
-- High period of SCK cycle
-------------------------------------------------------------------------
when SCK_HIGH =>
if r.countdown_delay = 0 then
v.state := SCK_LOW;
v.sck := '0';
v.countdown_delay := DELAY;
v.dout := r.dout(3 downto 0) & '0';
if r.countdown_bit = 0 then
v.state := HOLD_OFF;
v.sck := '0';
v.countdown_delay := DELAY * 4;
else
v.countdown_bit := v.countdown_bit - 1;
end if;
else
v.countdown_delay := v.countdown_delay -1;
end if;
-----------------------------------------------------------------------
-- Hold Off State
-----------------------------------------------------------------------
when HOLD_OFF =>
-- this state is required as the ADC can't handle a 20ns pulse on chipselect
v.csn := '1';
if r.countdown_delay = 0 then
v.state := IDLE;
v.done := '1';
else
v.countdown_delay := v.countdown_delay -1;
end if;
end case;
rin <= v;
end process comb_proc;
end behavioral;
| bsd-3-clause | 28f13c6442920459094b94c62cd132eb | 0.332626 | 5.43505 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/globalmixer_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 28,660 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Fri May 29 17:58:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
GM_Left_in_0 : in std_logic_vector(23 downto 0);
GM_Right_in_0 : in std_logic_vector(23 downto 0);
GM_Left_in_1 : in std_logic_vector(23 downto 0);
GM_Right_in_1 : in std_logic_vector(23 downto 0);
GM_Left_in_2 : in std_logic_vector(23 downto 0);
GM_Right_in_2 : in std_logic_vector(23 downto 0);
GM_Left_in_3 : in std_logic_vector(23 downto 0);
GM_Right_in_3 : in std_logic_vector(23 downto 0);
GM_Left_out : out std_logic_vector(23 downto 0);
GM_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
alias selected_channel : std_logic_vector is slv_reg0(1 downto 0);
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31 ) is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= slv_reg0;
when "01000000000000000000000000000000" => slv_ip2bus_data <= slv_reg1;
when "00100000000000000000000000000000" => slv_ip2bus_data <= slv_reg2;
when "00010000000000000000000000000000" => slv_ip2bus_data <= slv_reg3;
when "00001000000000000000000000000000" => slv_ip2bus_data <= slv_reg4;
when "00000100000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "00000010000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "00000001000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "00000000100000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "00000000010000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "00000000000010000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "00000000000001000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "00000000000000100000000000000000" => slv_ip2bus_data <= slv_reg14;
when "00000000000000010000000000000000" => slv_ip2bus_data <= slv_reg15;
when "00000000000000001000000000000000" => slv_ip2bus_data <= slv_reg16;
when "00000000000000000100000000000000" => slv_ip2bus_data <= slv_reg17;
when "00000000000000000010000000000000" => slv_ip2bus_data <= slv_reg18;
when "00000000000000000001000000000000" => slv_ip2bus_data <= slv_reg19;
when "00000000000000000000100000000000" => slv_ip2bus_data <= slv_reg20;
when "00000000000000000000010000000000" => slv_ip2bus_data <= slv_reg21;
when "00000000000000000000001000000000" => slv_ip2bus_data <= slv_reg22;
when "00000000000000000000000100000000" => slv_ip2bus_data <= slv_reg23;
when "00000000000000000000000010000000" => slv_ip2bus_data <= slv_reg24;
when "00000000000000000000000001000000" => slv_ip2bus_data <= slv_reg25;
when "00000000000000000000000000100000" => slv_ip2bus_data <= slv_reg26;
when "00000000000000000000000000010000" => slv_ip2bus_data <= slv_reg27;
when "00000000000000000000000000001000" => slv_ip2bus_data <= slv_reg28;
when "00000000000000000000000000000100" => slv_ip2bus_data <= slv_reg29;
when "00000000000000000000000000000010" => slv_ip2bus_data <= slv_reg30;
when "00000000000000000000000000000001" => slv_ip2bus_data <= slv_reg31;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
process(selected_channel)
begin
case(selected_channel) is
when "00" => GM_Left_out <= GM_Left_in_0;
GM_Right_out <= GM_Right_in_0;
when "01" => GM_Left_out <= GM_Left_in_1;
GM_Right_out <= GM_Right_in_1;
when "10" => GM_Left_out <= GM_Left_in_2;
GM_Right_out <= GM_Right_in_2;
when "11" => GM_Left_out <= GM_Left_in_3;
GM_Right_out <= GM_Right_in_3;
when others => GM_Left_out <= GM_Left_in_0;
GM_Right_out <= GM_Right_in_0;
end case;
end process;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | ec8b72637509147deec9099a7a3838e6 | 0.538835 | 3.63475 | false | false | false | false |
loa-org/loa-hdl | modules/onewire/hdl/onewire.vhd | 1 | 6,397 | -------------------------------------------------------------------------------
-- Title : Onewire Master
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description: This is an Onewire Master, intended for use with dedicated
-- protocol FSMs.
--
-- Timing constants are defined in onwire_cfg_pkg.vhd
--
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.onewire_pkg.all;
use work.onewire_cfg_pkg.all;
entity onewire is
port (
onewire_in : in onewire_in_type;
onewire_out : out onewire_out_type;
onewire_bus_in : in onewire_bus_in_type;
onewire_bus_out : out onewire_bus_out_type;
clk : in std_logic);
end onewire;
architecture rtl of onewire is
type onewire_states is (idle, reset1, reset2, reset3, write1, write2, write3, read1, read2, read3, read4);
type onewire_state_type is record
timer : integer range 0 to 25000;
bus_o : onewire_bus_out_type;
o : onewire_out_type;
sr : std_logic_vector(7 downto 0);
bit_cnt : integer range 0 to 7;
sync : std_logic_vector(1 downto 0);
state : onewire_states;
end record;
signal r, rin : onewire_state_type := (
timer => 0,
bus_o => (d => '0', en_driver => '0'),
o => (d => (others => '0'), busy => '1', err => '0'),
sr => (others => '0'),
bit_cnt => 0,
sync => "11",
state => idle);
begin -- onewire
onewire_bus_out <= r.bus_o;
onewire_out <= r.o;
comb : process(onewire_bus_in, onewire_in, r)
variable v : onewire_state_type;
variable bus_d_sync : std_logic := '1';
begin
v := r;
v.bus_o.d := '0'; -- not used, devices don't used
-- parasitic power (yet!).
bus_d_sync := v.sync(1);
v.sync(1) := v.sync(0);
v.sync(0) := onewire_bus_in.d;
case v.state is
when idle =>
v.o.busy := '0';
if onewire_in.reset_bus = '1' then
v.state := reset1;
v.timer := bus_reset_cycles;
v.o.busy := '1';
end if;
if onewire_in.we = '1' then
v.sr := onewire_in.d;
v.bit_cnt := 0;
v.state := write1;
v.o.busy := '1';
end if;
if onewire_in.re = '1' then
v.state := read1;
v.bit_cnt := 0;
v.o.busy := '1';
end if;
-----------------------------------------------------------------------
-- reset sequence
-- samples response from bus
-----------------------------------------------------------------------
when reset1 =>
v.bus_o.en_driver := '1';
v.timer := v.timer - 1;
if v.timer = 0 then
v.bus_o.en_driver := '0';
v.timer := bus_reset_wait_for_response;
v.state := reset2;
end if;
when reset2 =>
v.timer := v.timer - 1;
if v.timer = 0 then
v.o.err := bus_d_sync;
v.timer := bus_reset_cycles;
v.state := reset3;
end if;
when reset3 =>
v.timer := v.timer - 1;
if v.timer = 0 then
v.state := idle;
end if;
-------------------------------------------------------------------------
-- Write loop sequence
-- lsb first
-------------------------------------------------------------------------
when write1 =>
if v.sr(0) = '0' then
v.timer := bus_write_zero;
else
v.timer := bus_write_one;
end if;
v.state := write2;
when write2 =>
v.bus_o.en_driver := '1';
if v.timer = 0 then
if v.sr(0) = '0' then
v.timer := bus_write_zero_gap;
else
v.timer := bus_write_one_gap;
end if;
v.state := write3;
else
v.timer := v.timer - 1;
end if;
when write3 =>
v.bus_o.en_driver := '0';
v.timer := v.timer - 1;
if v.timer = 0 then
v.sr := "0" & v.sr(7 downto 1);
if v.bit_cnt = 7 then
v.state := idle;
else
v.state := write1;
v.bit_cnt := v.bit_cnt + 1;
end if;
end if;
-----------------------------------------------------------------------
-- Read loop Sequence
-----------------------------------------------------------------------
when read1 =>
v.timer := bus_read_pulse;
v.state := read2;
when read2 =>
v.bus_o.en_driver := '1';
v.timer := v.timer - 1;
if v.timer = 0 then
v.state := read3;
v.timer := bus_read_delay;
end if;
when read3 =>
v.bus_o.en_driver := '0';
v.timer := v.timer - 1;
if v.timer = 0 then
v.sr := bus_d_sync & v.sr(7 downto 1);
v.state := read4;
v.timer := bus_read_gap;
end if;
when read4 =>
v.timer := v.timer - 1;
if v.timer = 0 then
if v.bit_cnt = 7 then
v.state := idle;
else
v.state := read1;
v.bit_cnt := v.bit_cnt + 1;
end if;
end if;
when others => null;
end case;
v.o.d := v.sr; -- output register could be optimised
-- away ...
rin <= v;
end process comb;
seq : process (clk)
begin -- process seq
if rising_edge(clk) then
r <= rin;
end if;
end process seq;
end rtl;
| bsd-3-clause | 6c9ca58d170e1f0e222101da171fc23e | 0.399562 | 3.898233 | false | false | false | false |
loa-org/loa-hdl | modules/onewire/tb/onewire_read_tb.vhd | 1 | 2,959 | -------------------------------------------------------------------------------
-- Title : Onewire Master Testbench - Read Operation
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.onewire_pkg.all;
use work.onewire_cfg_pkg.all;
-------------------------------------------------------------------------------
entity onewire_read_tb is
end onewire_read_tb;
-------------------------------------------------------------------------------
architecture tb of onewire_read_tb is
component onewire
port (
onewire_in : in onewire_in_type;
onewire_out : out onewire_out_type;
onewire_bus_in : in onewire_bus_in_type;
onewire_bus_out : out onewire_bus_out_type;
clk : in std_logic);
end component;
-- component ports
signal onewire_in : onewire_in_type;
signal onewire_out : onewire_out_type;
signal onewire_bus_in : onewire_bus_in_type;
signal onewire_bus_out : onewire_bus_out_type;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : onewire
port map (
onewire_in => onewire_in,
onewire_out => onewire_out,
onewire_bus_in => onewire_bus_in,
onewire_bus_out => onewire_bus_out,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns; -- 50MHz Clock
-- waveform generation
WaveGen_Proc : process
begin
onewire_in.d <= (others => '0');
onewire_in.re <= '0';
onewire_in.we <= '0';
onewire_in.reset_bus <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
onewire_in.re <= '1';
wait until Clk = '1';
onewire_in.re <= '0';
wait for 2.5 ms;
end process WaveGen_Proc;
WaveGen_onewire_device : process
variable device_response : std_logic := '0';
begin
onewire_bus_in.d <= device_response;
device_response := not device_response;
wait until onewire_bus_out.en_driver = '1';
end process WaveGen_onewire_device;
end tb;
-------------------------------------------------------------------------------
configuration onewire_read_tb_tb_cfg of onewire_read_tb is
for tb
end for;
end onewire_read_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | c7c1a54968072a262d45b782a24e0030 | 0.466712 | 4.357879 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_buffer_register_1_0/system_buffer_register_1_0_sim_netlist.vhdl | 1 | 7,575 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:30:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_1_0 -prefix
-- system_buffer_register_1_0_ system_buffer_register_1_0_sim_netlist.vhdl
-- Design : system_buffer_register_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_1_0_buffer_register is
port (
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
clk : in STD_LOGIC
);
end system_buffer_register_1_0_buffer_register;
architecture STRUCTURE of system_buffer_register_1_0_buffer_register is
begin
\val_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(0),
Q => val_out(0),
R => '0'
);
\val_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(10),
Q => val_out(10),
R => '0'
);
\val_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(11),
Q => val_out(11),
R => '0'
);
\val_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(12),
Q => val_out(12),
R => '0'
);
\val_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(13),
Q => val_out(13),
R => '0'
);
\val_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(14),
Q => val_out(14),
R => '0'
);
\val_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(15),
Q => val_out(15),
R => '0'
);
\val_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(16),
Q => val_out(16),
R => '0'
);
\val_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(17),
Q => val_out(17),
R => '0'
);
\val_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(18),
Q => val_out(18),
R => '0'
);
\val_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(19),
Q => val_out(19),
R => '0'
);
\val_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(1),
Q => val_out(1),
R => '0'
);
\val_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(20),
Q => val_out(20),
R => '0'
);
\val_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(21),
Q => val_out(21),
R => '0'
);
\val_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(22),
Q => val_out(22),
R => '0'
);
\val_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(23),
Q => val_out(23),
R => '0'
);
\val_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(24),
Q => val_out(24),
R => '0'
);
\val_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(25),
Q => val_out(25),
R => '0'
);
\val_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(26),
Q => val_out(26),
R => '0'
);
\val_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(27),
Q => val_out(27),
R => '0'
);
\val_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(28),
Q => val_out(28),
R => '0'
);
\val_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(29),
Q => val_out(29),
R => '0'
);
\val_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(2),
Q => val_out(2),
R => '0'
);
\val_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(30),
Q => val_out(30),
R => '0'
);
\val_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(31),
Q => val_out(31),
R => '0'
);
\val_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(3),
Q => val_out(3),
R => '0'
);
\val_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(4),
Q => val_out(4),
R => '0'
);
\val_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(5),
Q => val_out(5),
R => '0'
);
\val_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(6),
Q => val_out(6),
R => '0'
);
\val_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(7),
Q => val_out(7),
R => '0'
);
\val_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(8),
Q => val_out(8),
R => '0'
);
\val_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(9),
Q => val_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_1_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_buffer_register_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_buffer_register_1_0 : entity is "system_buffer_register_1_0,buffer_register,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_buffer_register_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_buffer_register_1_0 : entity is "buffer_register,Vivado 2016.4";
end system_buffer_register_1_0;
architecture STRUCTURE of system_buffer_register_1_0 is
begin
U0: entity work.system_buffer_register_1_0_buffer_register
port map (
clk => clk,
val_in(31 downto 0) => val_in(31 downto 0),
val_out(31 downto 0) => val_out(31 downto 0)
);
end STRUCTURE;
| mit | e5bce443f8a0980532fc157f599b6c2d | 0.486865 | 3.101966 | false | false | false | false |
ashikpoojari/Hardware-Security | RC5 CryptoCore/Rc5 Codes/RC5_enc_full.vhd | 2 | 2,330 | Library IEEE;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_arith.All;
Use IEEE.std_logic_unsigned.All;
Use Work.RC5_pkg.All;
Entity rc5_Struct is
Port
(
clr : in std_logic;
clk : in std_logic;
enc : in std_logic;
key_vld : in std_logic;
key : in std_logic_vector (127 downto 0);
data_vld : in std_logic;
din : in std_logic_vector (63 downto 0);
dout : out std_logic_vector (63 downto 0);
data_rdy : out std_logic
);
End rc5_Struct;
--Architecture
Architecture struct of rc5_Struct is
--Key Expansion Module
Component rc5_rnd_key
Port
(
clr : in std_logic;
clk : in std_logic;
key_vld : in std_logic;
key_in : in Std_logic_vector (127 downto 0);
skey : out rom;
key_rdy : out std_logic
);
End Component;
--Encryption Module
Component rc5_enc
Port
(
clr : in std_logic;
clk : in std_logic;
din : in std_logic_vector(63 downto 0);
di_vld : in std_logic;
key_rdy : in std_logic;
skey : in rom;
dout : out std_logic_vector(63 downto 0);
do_rdy : out std_logic
);
End Component;
--Decryption Module
Component rc5_dec
Port
(
clr : In std_logic;
clk : In std_logic;
din : In std_logic_vector(63 downto 0);
din_vld : In std_logic;
key_rdy : In std_logic;
skey : In rom;
dout : Out std_logic_vector(63 downto 0);
dout_rdy : Out std_logic
);
End Component;
--Signals
Signal skey : rom;
Signal key_rdy : std_logic;
Signal dout_enc : std_logic_vector (63 downto 0);
Signal dout_dec : std_logic_vector (63 downto 0);
Signal enc_rdy : std_logic;
Signal dec_rdy : std_logic;
Signal i_cnt : std_logic_vector (3 downto 0);
Begin
--Port Maps
U1 : rc5_rnd_key Port Map (clr => clr, clk => clk, key_in => key, key_vld => key_vld, skey => skey, key_rdy => key_rdy);
U2 : rc5_enc Port Map (clr => clr, clk => clk, din => din, di_vld => key_rdy, skey => skey, dout => dout_enc, do_rdy => enc_rdy, key_rdy => key_rdy);
U3 : rc5_dec Port Map (clr => clr, clk => clk, din => din, din_vld => key_rdy, skey => skey, dout => dout_dec, dout_rdy => dec_rdy, key_rdy => key_rdy);
--Select
With enc select
dout <= dout_enc when '1',
dout_dec when others;
With enc select
data_rdy <= enc_rdy when '1',
dec_rdy when others;
--End structure
End struct;
| mit | 85b92df71d7b137136d8498b2da82f4e | 0.618884 | 2.540894 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/signal_sources.vhd | 2 | 1,547 | -------------------------------------------------------------------------------
-- Title : Common Signal Sources for Testbenches
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Signal sources for test benches, not synthesizable.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signal_sources_pkg.all;
entity source_sine is
generic (
DATA_WIDTH : positive := 10;
AMPLITUDE : real := 1.0;
SIGNAL_FREQUENCY : real := 16000.0;
SAMPLING_FREQUENCY : real := 75000.0);
port (
start_i : in std_logic;
signal_o : out signed(DATA_WIDTH-1 downto 0));
end entity source_sine;
architecture behavourial of source_sine is
begin -- architecture behavourial
WaveGen: process
variable phase : real := 0.0;
variable phase_increment : real := MATH_2_PI * SIGNAL_FREQUENCY / SAMPLING_FREQUENCY;
begin -- process WaveGen
phase := phase + phase_increment;
signal_o <= to_signed(integer(AMPLITUDE * sin(phase)), DATA_WIDTH);
wait until start_i = '1';
end process WaveGen;
end architecture behavourial;
| bsd-3-clause | 82ec35c5aa7d2738f4d2b287aa06d4b5 | 0.481577 | 4.834375 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_sim_netlist.vhdl | 1 | 18,213 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_sim_netlist.vhdl
-- Design : system_debounce_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0_debounce is
port (
signal_out : out STD_LOGIC;
clk : in STD_LOGIC;
signal_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_debounce_0_0_debounce : entity is "debounce";
end system_debounce_0_0_debounce;
architecture STRUCTURE of system_debounce_0_0_debounce is
signal \c[0]_i_3_n_0\ : STD_LOGIC;
signal \c[0]_i_4_n_0\ : STD_LOGIC;
signal \c[0]_i_5_n_0\ : STD_LOGIC;
signal \c[0]_i_6_n_0\ : STD_LOGIC;
signal \c[12]_i_2_n_0\ : STD_LOGIC;
signal \c[12]_i_3_n_0\ : STD_LOGIC;
signal \c[12]_i_4_n_0\ : STD_LOGIC;
signal \c[12]_i_5_n_0\ : STD_LOGIC;
signal \c[16]_i_2_n_0\ : STD_LOGIC;
signal \c[16]_i_3_n_0\ : STD_LOGIC;
signal \c[16]_i_4_n_0\ : STD_LOGIC;
signal \c[16]_i_5_n_0\ : STD_LOGIC;
signal \c[20]_i_2_n_0\ : STD_LOGIC;
signal \c[20]_i_3_n_0\ : STD_LOGIC;
signal \c[20]_i_4_n_0\ : STD_LOGIC;
signal \c[20]_i_5_n_0\ : STD_LOGIC;
signal \c[4]_i_2_n_0\ : STD_LOGIC;
signal \c[4]_i_3_n_0\ : STD_LOGIC;
signal \c[4]_i_4_n_0\ : STD_LOGIC;
signal \c[4]_i_5_n_0\ : STD_LOGIC;
signal \c[8]_i_2_n_0\ : STD_LOGIC;
signal \c[8]_i_3_n_0\ : STD_LOGIC;
signal \c[8]_i_4_n_0\ : STD_LOGIC;
signal \c[8]_i_5_n_0\ : STD_LOGIC;
signal c_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \c_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_7\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal signal_out_i_1_n_0 : STD_LOGIC;
signal signal_out_i_2_n_0 : STD_LOGIC;
signal signal_out_i_3_n_0 : STD_LOGIC;
signal signal_out_i_4_n_0 : STD_LOGIC;
signal signal_out_i_5_n_0 : STD_LOGIC;
signal \NLW_c_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\c[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => signal_in,
O => clear
);
\c[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(3),
O => \c[0]_i_3_n_0\
);
\c[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(2),
O => \c[0]_i_4_n_0\
);
\c[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(1),
O => \c[0]_i_5_n_0\
);
\c[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => c_reg(0),
O => \c[0]_i_6_n_0\
);
\c[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(15),
O => \c[12]_i_2_n_0\
);
\c[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(14),
O => \c[12]_i_3_n_0\
);
\c[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(13),
O => \c[12]_i_4_n_0\
);
\c[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(12),
O => \c[12]_i_5_n_0\
);
\c[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(19),
O => \c[16]_i_2_n_0\
);
\c[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(18),
O => \c[16]_i_3_n_0\
);
\c[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(17),
O => \c[16]_i_4_n_0\
);
\c[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(16),
O => \c[16]_i_5_n_0\
);
\c[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(23),
O => \c[20]_i_2_n_0\
);
\c[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(22),
O => \c[20]_i_3_n_0\
);
\c[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(21),
O => \c[20]_i_4_n_0\
);
\c[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(20),
O => \c[20]_i_5_n_0\
);
\c[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(7),
O => \c[4]_i_2_n_0\
);
\c[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(6),
O => \c[4]_i_3_n_0\
);
\c[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(5),
O => \c[4]_i_4_n_0\
);
\c[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(4),
O => \c[4]_i_5_n_0\
);
\c[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(11),
O => \c[8]_i_2_n_0\
);
\c[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(10),
O => \c[8]_i_3_n_0\
);
\c[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(9),
O => \c[8]_i_4_n_0\
);
\c[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(8),
O => \c[8]_i_5_n_0\
);
\c_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_7\,
Q => c_reg(0),
R => clear
);
\c_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \c_reg[0]_i_2_n_0\,
CO(2) => \c_reg[0]_i_2_n_1\,
CO(1) => \c_reg[0]_i_2_n_2\,
CO(0) => \c_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \c_reg[0]_i_2_n_4\,
O(2) => \c_reg[0]_i_2_n_5\,
O(1) => \c_reg[0]_i_2_n_6\,
O(0) => \c_reg[0]_i_2_n_7\,
S(3) => \c[0]_i_3_n_0\,
S(2) => \c[0]_i_4_n_0\,
S(1) => \c[0]_i_5_n_0\,
S(0) => \c[0]_i_6_n_0\
);
\c_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_5\,
Q => c_reg(10),
R => clear
);
\c_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_4\,
Q => c_reg(11),
R => clear
);
\c_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_7\,
Q => c_reg(12),
R => clear
);
\c_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[8]_i_1_n_0\,
CO(3) => \c_reg[12]_i_1_n_0\,
CO(2) => \c_reg[12]_i_1_n_1\,
CO(1) => \c_reg[12]_i_1_n_2\,
CO(0) => \c_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[12]_i_1_n_4\,
O(2) => \c_reg[12]_i_1_n_5\,
O(1) => \c_reg[12]_i_1_n_6\,
O(0) => \c_reg[12]_i_1_n_7\,
S(3) => \c[12]_i_2_n_0\,
S(2) => \c[12]_i_3_n_0\,
S(1) => \c[12]_i_4_n_0\,
S(0) => \c[12]_i_5_n_0\
);
\c_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_6\,
Q => c_reg(13),
R => clear
);
\c_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_5\,
Q => c_reg(14),
R => clear
);
\c_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_4\,
Q => c_reg(15),
R => clear
);
\c_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_7\,
Q => c_reg(16),
R => clear
);
\c_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[12]_i_1_n_0\,
CO(3) => \c_reg[16]_i_1_n_0\,
CO(2) => \c_reg[16]_i_1_n_1\,
CO(1) => \c_reg[16]_i_1_n_2\,
CO(0) => \c_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[16]_i_1_n_4\,
O(2) => \c_reg[16]_i_1_n_5\,
O(1) => \c_reg[16]_i_1_n_6\,
O(0) => \c_reg[16]_i_1_n_7\,
S(3) => \c[16]_i_2_n_0\,
S(2) => \c[16]_i_3_n_0\,
S(1) => \c[16]_i_4_n_0\,
S(0) => \c[16]_i_5_n_0\
);
\c_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_6\,
Q => c_reg(17),
R => clear
);
\c_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_5\,
Q => c_reg(18),
R => clear
);
\c_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_4\,
Q => c_reg(19),
R => clear
);
\c_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_6\,
Q => c_reg(1),
R => clear
);
\c_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_7\,
Q => c_reg(20),
R => clear
);
\c_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[16]_i_1_n_0\,
CO(3) => \NLW_c_reg[20]_i_1_CO_UNCONNECTED\(3),
CO(2) => \c_reg[20]_i_1_n_1\,
CO(1) => \c_reg[20]_i_1_n_2\,
CO(0) => \c_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[20]_i_1_n_4\,
O(2) => \c_reg[20]_i_1_n_5\,
O(1) => \c_reg[20]_i_1_n_6\,
O(0) => \c_reg[20]_i_1_n_7\,
S(3) => \c[20]_i_2_n_0\,
S(2) => \c[20]_i_3_n_0\,
S(1) => \c[20]_i_4_n_0\,
S(0) => \c[20]_i_5_n_0\
);
\c_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_6\,
Q => c_reg(21),
R => clear
);
\c_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_5\,
Q => c_reg(22),
R => clear
);
\c_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_4\,
Q => c_reg(23),
R => clear
);
\c_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_5\,
Q => c_reg(2),
R => clear
);
\c_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_4\,
Q => c_reg(3),
R => clear
);
\c_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_7\,
Q => c_reg(4),
R => clear
);
\c_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[0]_i_2_n_0\,
CO(3) => \c_reg[4]_i_1_n_0\,
CO(2) => \c_reg[4]_i_1_n_1\,
CO(1) => \c_reg[4]_i_1_n_2\,
CO(0) => \c_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[4]_i_1_n_4\,
O(2) => \c_reg[4]_i_1_n_5\,
O(1) => \c_reg[4]_i_1_n_6\,
O(0) => \c_reg[4]_i_1_n_7\,
S(3) => \c[4]_i_2_n_0\,
S(2) => \c[4]_i_3_n_0\,
S(1) => \c[4]_i_4_n_0\,
S(0) => \c[4]_i_5_n_0\
);
\c_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_6\,
Q => c_reg(5),
R => clear
);
\c_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_5\,
Q => c_reg(6),
R => clear
);
\c_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_4\,
Q => c_reg(7),
R => clear
);
\c_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_7\,
Q => c_reg(8),
R => clear
);
\c_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[4]_i_1_n_0\,
CO(3) => \c_reg[8]_i_1_n_0\,
CO(2) => \c_reg[8]_i_1_n_1\,
CO(1) => \c_reg[8]_i_1_n_2\,
CO(0) => \c_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[8]_i_1_n_4\,
O(2) => \c_reg[8]_i_1_n_5\,
O(1) => \c_reg[8]_i_1_n_6\,
O(0) => \c_reg[8]_i_1_n_7\,
S(3) => \c[8]_i_2_n_0\,
S(2) => \c[8]_i_3_n_0\,
S(1) => \c[8]_i_4_n_0\,
S(0) => \c[8]_i_5_n_0\
);
\c_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_6\,
Q => c_reg(9),
R => clear
);
signal_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => signal_out_i_2_n_0,
I1 => signal_out_i_3_n_0,
I2 => signal_out_i_4_n_0,
I3 => c_reg(0),
I4 => signal_out_i_5_n_0,
O => signal_out_i_1_n_0
);
signal_out_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(3),
I1 => c_reg(4),
I2 => c_reg(1),
I3 => c_reg(2),
I4 => c_reg(6),
I5 => c_reg(5),
O => signal_out_i_2_n_0
);
signal_out_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(21),
I1 => c_reg(22),
I2 => c_reg(19),
I3 => c_reg(20),
I4 => signal_in,
I5 => c_reg(23),
O => signal_out_i_3_n_0
);
signal_out_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(15),
I1 => c_reg(16),
I2 => c_reg(13),
I3 => c_reg(14),
I4 => c_reg(18),
I5 => c_reg(17),
O => signal_out_i_4_n_0
);
signal_out_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(9),
I1 => c_reg(10),
I2 => c_reg(7),
I3 => c_reg(8),
I4 => c_reg(12),
I5 => c_reg(11),
O => signal_out_i_5_n_0
);
signal_out_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => signal_out_i_1_n_0,
Q => signal_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_debounce_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_debounce_0_0 : entity is "system_debounce_0_0,debounce,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_debounce_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_debounce_0_0 : entity is "debounce,Vivado 2016.4";
end system_debounce_0_0;
architecture STRUCTURE of system_debounce_0_0 is
begin
U0: entity work.system_debounce_0_0_debounce
port map (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
end STRUCTURE;
| mit | d719c683f758e3e8d6da38e206b6edc5 | 0.464064 | 2.373957 | false | false | false | false |
loa-org/loa-hdl | modules/uart/tb/uart_rx_tb.vhd | 1 | 2,829 | -------------------------------------------------------------------------------
-- Title : Testbench for design "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx_tb is
end entity uart_rx_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_rx_tb is
-- component ports
signal rxd : std_logic := '1';
signal disable : std_logic := '0';
signal data : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_rx
port map (
rxd_p => rxd,
disable_p => disable,
data_p => data,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
reset => '0',
clk => clk);
-- clock generation
clk <= not clk after 20 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_rx_en <= '1';
wait until rising_edge(clk);
clk_rx_en <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
end process bitclock;
-- waveform generation
waveform : process
begin
wait for 100 ns;
wait until rising_edge(clk);
-- glitch
rxd <= '0';
wait until rising_edge(clk);
rxd <= '1';
wait for 100 ns;
-- correct transmission
uart_transmit(rxd, "001111100", 10000000);
--wait for 200 ns;
wait for 800 ns;
-- correct transmission, odd parity in MSB
uart_transmit(rxd, "111111111", 1000000);
uart_transmit(rxd, "111111111", 1000000);
--wait for 200 ns;
---- check slightly off baudrates
uart_transmit(rxd, "001111100", 10500000);
--wait for 200 ns;
uart_transmit(rxd, "001111100", 9700000);
--wait for 200 ns;
-- send a wrong parity bit
uart_transmit(rxd, "101111100", 10000000);
wait for 200 ns;
wait;
end process waveform;
end architecture behavourial;
| bsd-3-clause | 27e69e62b1543c11c910b6c70e8d3546 | 0.455992 | 4.490476 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_feature_transform/vga_feature_transform.srcs/sources_1/new/feature_buffer_match_block.vhd | 1 | 5,844 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feature_buffer_match_block is
generic (
PARITY : std_logic := '0'
);
port (
clk : in std_logic;
mode : in std_logic_vector(1 downto 0);
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_in_match_0 : in std_logic_vector(9 downto 0);
y_in_match_0 : in std_logic_vector(9 downto 0);
x_in_match_1 : in std_logic_vector(9 downto 0);
y_in_match_1 : in std_logic_vector(9 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end feature_buffer_match_block;
architecture Behavioral of feature_buffer_match_block is
signal hessian : unsigned(31 downto 0) := x"00000000";
signal x : std_logic_vector(9 downto 0) := "0000000000";
signal y : std_logic_vector(9 downto 0) := "0000000000";
begin
hessian_out_left <= std_logic_vector(hessian);
x_out_left <= x;
y_out_left <= y;
hessian_out_right <= std_logic_vector(hessian);
x_out_right <= x;
y_out_right <= y;
process(clk)
variable x_diff_0, x_diff_1, y_diff_0, y_diff_1 : signed(9 downto 0);
variable distance_0, distance_1 : unsigned(19 downto 0);
begin
if rising_edge(clk) then
if mode = "01" then
if PARITY = '0' then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
elsif mode = "10" then
if PARITY = '0' then
x_diff_0 := signed(x_in_match_0) - signed(x);
y_diff_0 := signed(y_in_match_0) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_0) - signed(x_in_right);
y_diff_1 := signed(y_in_match_0) - signed(y_in_right);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_right;
y <= y_in_right;
end if;
else
x_diff_0 := signed(x_in_match_1) - signed(x);
y_diff_0 := signed(y_in_match_1) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_1) - signed(x_in_left);
y_diff_1 := signed(y_in_match_1) - signed(y_in_left);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_left;
y <= y_in_left;
end if;
end if;
end if;
end if;
if falling_edge(clk) then
if mode = "01" then
if PARITY = '1' then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
elsif mode = "10" then
if PARITY = '1' then
x_diff_0 := signed(x_in_match_0) - signed(x);
y_diff_0 := signed(y_in_match_0) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_0) - signed(x_in_right);
y_diff_1 := signed(y_in_match_0) - signed(y_in_right);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_right;
y <= y_in_right;
end if;
else
x_diff_0 := signed(x_in_match_1) - signed(x);
y_diff_0 := signed(y_in_match_1) - signed(y);
distance_0 := unsigned(x_diff_0 * x_diff_0 + y_diff_0 * y_diff_0);
x_diff_1 := signed(x_in_match_1) - signed(x_in_left);
y_diff_1 := signed(y_in_match_1) - signed(y_in_left);
distance_1 := unsigned(x_diff_1 * x_diff_1 + y_diff_1 * y_diff_1);
if distance_1 < distance_0 then
x <= x_in_left;
y <= y_in_left;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | e6b3156afca235ce8a215ba75ef47509 | 0.459788 | 3.466192 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_sim_netlist.vhdl | 1 | 506,454 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:17:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_sim_netlist.vhdl
-- Design : system_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd : entity is "axi_protocol_converter_v2_1_11_b2s_incr_cmd";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd is
signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair107";
begin
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \cnt_read_reg[1]_rep__0\,
O => \axaddr_incr[0]_i_1_n_0\
);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A9A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \m_payload_i_reg[46]\(5),
I3 => \m_payload_i_reg[46]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"009A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"0009"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(0),
Q => \axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(1),
Q => \axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(2),
Q => \axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(3),
Q => \axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \^axlen_cnt_reg[0]_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(6),
O => \axlen_cnt[0]_i_1__1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(7),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => p_1_in(1)
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_1_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[6]_i_1_n_0\
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[7]_i_2_n_0\
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(1),
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[0]_0\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[5]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[0]_0\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[6]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[0]_0\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[7]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[0]_0\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[5]\,
I4 => next_pending_r_i_5_n_0,
O => \^axlen_cnt_reg[0]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[1]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_11_b2s_incr_cmd";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[1]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
signal next_pending_r_i_4_n_0 : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \next_pending_r_i_2__1\ : label is "soft_lutpair5";
begin
Q(0) <= \^q\(0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axlen_cnt_reg[1]_0\ <= \^axlen_cnt_reg[1]_0\;
incr_next_pending <= \^incr_next_pending\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A2A262A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A060A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0202010202020202"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(6),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \^axlen_cnt_reg[1]_0\,
O => \axlen_cnt[1]_i_1__1_n_0\
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[1]_0\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \^axlen_cnt_reg[1]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_4_n_0,
O => \^axlen_cnt_reg[1]_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \^q\(0),
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \axlen_cnt_reg_n_0_[5]\,
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \^q\(0),
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[1]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF505C"
)
port map (
I0 => \next_pending_r_i_2__1_n_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => E(0),
I4 => \m_payload_i_reg[44]\,
O => \^incr_next_pending\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => next_pending_r_i_4_n_0,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
O => \next_pending_r_i_2__1_n_0\
);
next_pending_r_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
O => next_pending_r_i_4_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[44]_0\ : in STD_LOGIC;
\state_reg[0]_0\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm : entity is "axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair1";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair0";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[0]\(0) <= \^axaddr_offset_r_reg[0]\(0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]\(1 downto 0) <= \^wrap_second_len_r_reg[3]\(1 downto 0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]_0\,
I2 => \^m_payload_i_reg[0]\,
I3 => m_axi_arready,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[0]_0\(0),
I1 => \m_payload_i_reg[44]\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \^q\(1),
I5 => \m_payload_i_reg[3]\,
O => \^axaddr_offset_r_reg[0]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[44]\(1),
I4 => \axlen_cnt_reg[0]_0\(0),
I5 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[0]\(0)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0E02"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]_0\,
I2 => \^m_payload_i_reg[0]\,
I3 => m_axi_arready,
O => \axlen_cnt_reg[3]\(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002320"
)
port map (
I0 => m_axi_arready,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
O => \m_payload_i_reg[0]_1\(0)
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => m_valid_i0
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFABEEAA"
)
port map (
I0 => \m_payload_i_reg[44]_0\,
I1 => \^r_push_r_reg\,
I2 => \^e\(0),
I3 => \state_reg[0]_0\,
I4 => next_pending_r_reg,
O => \^wrap_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => m_axi_arready,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCFFFFFCCCCCCEE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]\,
I4 => \^m_payload_i_reg[0]_0\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000033333FFF2222"
)
port map (
I0 => si_rs_arvalid,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => s_axburst_eq1_reg_0,
I3 => m_axi_arready,
I4 => \^q\(0),
I5 => \^q\(1),
O => next_state(0)
);
\state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FC00040"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
I4 => \cnt_read_reg[1]_rep__0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5575AA8A5545AA8A"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => D(0)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[2]\(0),
I2 => \wrap_cnt_r[3]_i_2__0_n_0\,
I3 => \wrap_second_len_r_reg[2]\(1),
O => D(1)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD11DD11DD11DDF1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset_r_reg[0]\(0),
I4 => \m_payload_i_reg[47]\(0),
I5 => \m_payload_i_reg[47]\(1),
O => \wrap_cnt_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAABAAA8A"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \axaddr_offset_r_reg[3]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4FF44444444"
)
port map (
I0 => \^e\(0),
I1 => \wrap_second_len_r_reg[3]_0\(1),
I2 => \^axaddr_offset_r_reg[0]\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[47]\(0),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_second_len_r_reg[3]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
\state_reg[0]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
\cnt_read_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo : entity is "axi_protocol_converter_v2_1_11_b2s_simple_fifo";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo is
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 to 1 );
signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC;
signal cnt_read_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_3\ : label is "soft_lutpair110";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
attribute SOFT_HLUTNM of \state[0]_i_2\ : label is "soft_lutpair110";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => areset_d1,
I1 => \^bresp_push\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => si_rs_bready,
I2 => si_rs_bvalid,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
I2 => shandshake_r,
I3 => \cnt_read_reg[1]_0\(1),
I4 => \cnt_read_reg[1]_0\(0),
I5 => si_rs_bvalid,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => cnt_read(1)
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => cnt_read_0(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => cnt_read(1),
Q => cnt_read_0(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => cnt_read(1),
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => cnt_read(1),
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000082"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
I1 => \memory_reg[3][1]_srl4_n_0\,
I2 => Q(1),
I3 => Q(7),
I4 => \memory_reg[3][0]_srl4_i_3_n_0\,
I5 => \memory_reg[3][0]_srl4_i_4_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04000004"
)
port map (
I0 => Q(5),
I1 => mhandshake_r,
I2 => Q(4),
I3 => \memory_reg[3][3]_srl4_n_0\,
I4 => Q(3),
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFAEAEAE"
)
port map (
I0 => Q(6),
I1 => \memory_reg[3][0]_srl4_n_0\,
I2 => Q(0),
I3 => \^cnt_read_reg[1]_rep__0_0\,
I4 => \^cnt_read_reg[0]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FF2"
)
port map (
I0 => Q(0),
I1 => \memory_reg[3][0]_srl4_n_0\,
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => Q(2),
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read_0(0),
A1 => cnt_read_0(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \out\(1)
);
\state[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
O => \state_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
mhandshake : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
bresp_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_11_b2s_simple_fifo";
end \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair114";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair113";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
attribute SOFT_HLUTNM of mhandshake_r_i_1 : label is "soft_lutpair113";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^q\(0),
I1 => bresp_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^q\(0),
I1 => bresp_push,
I2 => shandshake_r,
I3 => \^q\(1),
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => bresp_push,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => bresp_push,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[1]_rep__3_0\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\cnt_read_reg[2]_rep__0_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_11_b2s_simple_fifo";
end \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__3_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[3]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair10";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__3\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__3\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__3\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
begin
\cnt_read_reg[1]_rep__3_0\ <= \^cnt_read_reg[1]_rep__3_0\;
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \^cnt_read_reg[1]_rep__3_0\,
I2 => \cnt_read[3]_i_2_n_0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \^cnt_read_reg[1]_rep__3_0\,
I2 => \cnt_read[3]_i_2_n_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE7F0180"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^cnt_read_reg[1]_rep__3_0\,
I3 => \cnt_read[3]_i_2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFB20000004"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read[3]_i_2_n_0\,
I2 => \^cnt_read_reg[1]_rep__3_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[3]_rep__2_n_0\,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"08808880FFFFFFFF"
)
port map (
I0 => \cnt_read_reg[4]_rep__2_n_0\,
I1 => \cnt_read_reg[3]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__3_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__3_n_0\,
I5 => m_axi_rvalid,
O => \cnt_read[3]_i_2_n_0\
);
\cnt_read[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
O => \^cnt_read_reg[1]_rep__3_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AA69AAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__2_n_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \cnt_read_reg[3]_rep__2_n_0\,
I4 => \cnt_read[4]_i_3_n_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7F77"
)
port map (
I0 => \cnt_read_reg[1]_rep__3_n_0\,
I1 => \cnt_read_reg[0]_rep__3_n_0\,
I2 => \^m_valid_i_reg\,
I3 => si_rs_rready,
I4 => \cnt_read[3]_i_2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => \cnt_read[3]_i_2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__3_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__3\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__3_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__2_n_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \cnt_read_reg[4]_rep__2_n_0\,
I1 => \cnt_read_reg[3]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF80000000"
)
port map (
I0 => \cnt_read_reg[3]_rep__2_n_0\,
I1 => \cnt_read_reg[4]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__3_n_0\,
I3 => \cnt_read_reg[0]_rep__3_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[2]_rep__0_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"800AAAAAAAAAAAAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \cnt_read_reg[0]_rep__3_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \cnt_read_reg[1]_rep__3_n_0\,
I4 => \cnt_read_reg[3]_rep__2_n_0\,
I5 => \cnt_read_reg[4]_rep__2_n_0\,
O => wr_en0
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => wr_en0,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => wr_en0,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__3_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__3_n_0\,
I3 => \cnt_read_reg[3]_rep__2_n_0\,
I4 => \cnt_read_reg[4]_rep__2_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
s_ready_i_reg : in STD_LOGIC;
r_push_r : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__3\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_11_b2s_simple_fifo";
end \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => r_push_r,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFE8001"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFE80000001"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AA69AAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[3]_rep__0_n_0\,
I4 => \cnt_read[4]_i_3__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5DFFFFFF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[3]_rep__2\,
I3 => r_push_r,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => r_push_r,
I2 => si_rs_rready,
I3 => \cnt_read_reg[3]_rep__2\,
I4 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__1_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[4]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
O => m_valid_i_reg
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFEEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__3\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
I3 => \cnt_read_reg[2]_rep__0_n_0\,
I4 => \cnt_read_reg[4]_rep__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
sel_first_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[7]_0\ : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm : entity is "axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \^sel_first_reg\ : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^wrap_next_pending\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair106";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair105";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair105";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair106";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
sel_first_i <= \^sel_first_i\;
sel_first_reg <= \^sel_first_reg\;
\wrap_boundary_axaddr_r_reg[0]\(0) <= \^wrap_boundary_axaddr_r_reg[0]\(0);
wrap_next_pending <= \^wrap_next_pending\;
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"04FF"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^sel_first_reg\,
O => E(0)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000004FF"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^sel_first_reg\,
I4 => \axlen_cnt_reg[7]_0\,
O => \axlen_cnt_reg[7]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A0A0A800A8A8"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready,
I2 => \^q\(1),
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__0_0\,
I5 => s_axburst_eq1_reg_0,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg,
I3 => \^sel_first_reg\,
I4 => \axlen_cnt_reg[7]_0\,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg_0,
I3 => \^sel_first_reg\,
I4 => \axlen_cnt_reg[3]\,
O => \^wrap_next_pending\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0CAE0CFF00FF00FF"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__0_0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => \^q\(1),
I4 => m_axi_awready,
I5 => \^q\(0),
O => \^sel_first_reg\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF04FF04FF04"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => areset_d1,
I4 => \^sel_first_reg\,
I5 => sel_first_reg_2,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^sel_first_reg\,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^sel_first_reg\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_1
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F232FE32FE3EFE3E"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \cnt_read_reg[1]_rep__0\,
I4 => s_axburst_eq1_reg_0,
I5 => m_axi_awready,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"20E0202000E00000"
)
port map (
I0 => m_axi_awready,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__0_0\,
I5 => s_axburst_eq1_reg_0,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
O => \^wrap_boundary_axaddr_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd : entity is "axi_protocol_converter_v2_1_11_b2s_wrap_cmd";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_3\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair109";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(0),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(0),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(10),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(10),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(11),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(11),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \axaddr_wrap[11]_i_8_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_3_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => wrap_cnt_r(1),
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => wrap_cnt_r(0),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(1),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(2),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(3),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(3),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(4),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(4),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(5),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(6),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(6),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(7),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(7),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(8),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(8),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[47]\(9),
I1 => \cnt_read_reg[1]_rep__0\,
I2 => axaddr_wrap0(9),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_4_n_0\,
S(2) => \axaddr_wrap[11]_i_5_n_0\,
S(1) => \axaddr_wrap[11]_i_6_n_0\,
S(0) => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF555400005554"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(15),
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC3AAC3AAC3AAC0"
)
port map (
I0 => \m_payload_i_reg[47]\(16),
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => E(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAACCC3AAAACCC0"
)
port map (
I0 => \m_payload_i_reg[47]\(17),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => E(0),
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(1),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_11_b2s_wrap_cmd";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[47]_0\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[47]_0\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[47]_0\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[47]_0\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_8__0_n_0\,
O => \axaddr_wrap[11]_i_3__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_2__0_n_7\,
S(3) => \axaddr_wrap[11]_i_4__0_n_0\,
S(2) => \axaddr_wrap[11]_i_5__0_n_0\,
S(1) => \axaddr_wrap[11]_i_6__0_n_0\,
S(0) => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAC3AAC3AAC3AAC0"
)
port map (
I0 => \m_payload_i_reg[47]\(16),
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => E(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAACCC3AAAACCC0"
)
port map (
I0 => \m_payload_i_reg[47]\(17),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => E(0),
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[2]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[5]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_arvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"13D320E0"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1_n_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_cnt_r_reg[2]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
sel_first_1 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[38]\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[2]_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair12";
begin
Q(53 downto 0) <= \^q\(53 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axaddr_offset_r_reg[3]\(1 downto 0) <= \^axaddr_offset_r_reg[3]\(1 downto 0);
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[2]_0\ <= \^wrap_cnt_r_reg[2]_0\;
\wrap_second_len_r_reg[2]\(1 downto 0) <= \^wrap_second_len_r_reg[2]\(1 downto 0);
\wrap_second_len_r_reg[3]\ <= \^wrap_second_len_r_reg[3]\;
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_1,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_1,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_1,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_1,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_1,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_1,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_1,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_1,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1FDF00001FDFFFFF"
)
port map (
I0 => \axaddr_offset_r[1]_i_3_n_0\,
I1 => \^q\(35),
I2 => \^q\(39),
I3 => \axaddr_offset_r[2]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(41),
I1 => \axaddr_offset_r[3]_i_2__0_n_0\,
I2 => \state_reg[1]_rep_0\,
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[0]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^axaddr_offset_r_reg[3]\(1)
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(41),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \m_payload_i_reg_n_0_[38]\,
I1 => sel_first_1,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \m_payload_i_reg_n_0_[38]\,
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[52]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(38),
I2 => \^q\(41),
I3 => \^q\(39),
I4 => \^q\(40),
O => next_pending_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[1]_rep_0\,
I3 => \state_reg[0]_rep\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(38),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(38),
I3 => \^q\(35),
I4 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888082AAAAA082A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(39),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(38),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(39),
I4 => \^q\(35),
I5 => \^q\(38),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(40),
I1 => \^q\(35),
I2 => \^q\(41),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002AA02A0A2AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(39),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(40),
I3 => \^q\(35),
I4 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A656AAAAAAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[2]\(1),
I1 => \wrap_second_len_r_reg[2]_0\(0),
I2 => \state_reg[1]_rep\,
I3 => axaddr_offset_0(0),
I4 => \^wrap_cnt_r_reg[2]_0\,
I5 => \^wrap_second_len_r_reg[2]\(0),
O => \wrap_cnt_r_reg[2]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBAFFFFFFFF"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_0\(2),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => axaddr_offset_0(0),
I5 => \^axaddr_offset_r_reg[1]\,
O => \^wrap_cnt_r_reg[2]_0\
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0EF0FFFF0EF00000"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \^axaddr_offset_r_reg[3]\(1),
I2 => axaddr_offset_0(0),
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(1),
O => \^wrap_second_len_r_reg[2]\(0)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D2D0FFFFD2D00000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => axaddr_offset_0(0),
I2 => \^axaddr_offset_r_reg[2]\,
I3 => \^axaddr_offset_r_reg[3]\(1),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(2),
O => \^wrap_second_len_r_reg[2]\(1)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \^wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0 : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0;
architecture STRUCTURE of system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[38]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[0]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_4\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_2\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_5\ : label is "soft_lutpair44";
begin
Q(53 downto 0) <= \^q\(53 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
wrap_second_len(2 downto 0) <= \^wrap_second_len\(2 downto 0);
\wrap_second_len_r_reg[1]\ <= \^wrap_second_len_r_reg[1]\;
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
O => axaddr_offset(0)
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000700FFFFF7FF"
)
port map (
I0 => \^q\(38),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]_0\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]_0\(0),
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_3_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \state_reg[1]_0\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]_0\(0),
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(35),
I3 => \^q\(3),
I4 => \^q\(36),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
O => axaddr_offset(1)
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03FFF3FF55555555"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(2),
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \axaddr_offset_r[2]_i_4_n_0\,
I5 => \state_reg[1]\,
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_4_n_0\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(41),
I1 => \axaddr_offset_r[3]_i_2_n_0\,
I2 => \state_reg[1]_0\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]_0\(0),
I5 => \axaddr_offset_r_reg[3]_0\(3),
O => \^axaddr_offset_r_reg[3]\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2_n_0\
);
\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(41),
I1 => \state_reg[1]_0\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_0\(1),
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \m_payload_i_reg_n_0_[38]\,
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \m_payload_i_reg_n_0_[38]\,
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(40),
I1 => \^q\(39),
I2 => \^q\(41),
I3 => \^q\(38),
O => next_pending_r_reg
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(38),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(38),
I3 => \^q\(35),
I4 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A002A2AAAA02A2"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(39),
I4 => \^q\(36),
I5 => \^q\(38),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(39),
I4 => \^q\(35),
I5 => \^q\(38),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(40),
I1 => \^q\(35),
I2 => \^q\(41),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A0A2AA02AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(40),
I3 => \^q\(35),
I4 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDD8DDAAAAA8AA"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r[0]_i_3_n_0\,
I2 => \state_reg[1]_0\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]_0\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => D(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\,
I1 => \wrap_cnt_r[3]_i_2_n_0\,
O => D(1)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len\(1),
I1 => \wrap_cnt_r[3]_i_2_n_0\,
I2 => \^wrap_second_len_r_reg[1]\,
O => D(2)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len\(2),
I1 => \^wrap_second_len_r_reg[1]\,
I2 => \wrap_cnt_r[3]_i_2_n_0\,
I3 => \^wrap_second_len\(1),
O => D(3)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[3]\,
O => \wrap_cnt_r[3]_i_2_n_0\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800FFFFF8FF"
)
port map (
I0 => \^q\(38),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]_0\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]_0\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000CCCCCACC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]\(0),
I2 => \state_reg[1]_0\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]_0\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF2FFFFFF"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(3),
I1 => \state_reg[1]\,
I2 => \wrap_second_len_r[3]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \axaddr_offset_r[0]_i_2_n_0\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(2),
I3 => \^q\(35),
I4 => \wrap_second_len_r[0]_i_4_n_0\,
I5 => \wrap_second_len_r[0]_i_5_n_0\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(38),
I1 => \state_reg[1]_0\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_0\(1),
O => \wrap_second_len_r[0]_i_5_n_0\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2EE22E222EE22EE2"
)
port map (
I0 => \wrap_second_len_r_reg[3]\(1),
I1 => \state_reg[1]\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[3]\,
I5 => \axaddr_offset_r[2]_i_2_n_0\,
O => \^wrap_second_len_r_reg[1]\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08F3FFFF08F30000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \^axaddr_offset_r_reg[1]\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \state_reg[1]\,
I5 => \wrap_second_len_r_reg[3]\(2),
O => \^wrap_second_len\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00FFFFBF00BF00"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \axaddr_offset_r[2]_i_2_n_0\,
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]\,
I5 => \wrap_second_len_r_reg[3]\(3),
O => \^wrap_second_len\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_4_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
shandshake : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\;
architecture STRUCTURE of \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair73";
attribute SOFT_HLUTNM of shandshake_r_i_1 : label is "soft_lutpair73";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => si_rs_bvalid,
O => shandshake
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair99";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \^skid_buffer_reg[0]_0\,
I3 => \cnt_read_reg[3]_rep__2\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__2\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
\state_reg[0]\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
shandshake : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel : entity is "axi_protocol_converter_v2_1_11_b2s_b_channel";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel is
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair116";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo
port map (
Q(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_5,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_0\(1 downto 0) => cnt_read(1 downto 0),
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(15 downto 0) => \in\(15 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready,
si_rs_bvalid => \^si_rs_bvalid\,
\state_reg[0]\ => \state_reg[0]\
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
I1 => \bresp_cnt_reg__0\(1),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized0\
port map (
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
bresp_push => bresp_push,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_5,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => '0'
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACECCCC"
)
port map (
I0 => m_axi_bresp(0),
I1 => \s_bresp_acc_reg_n_0_[0]\,
I2 => \s_bresp_acc_reg_n_0_[1]\,
I3 => m_axi_bresp(1),
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[1]\,
I1 => m_axi_bresp(1),
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\state_reg[0]\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\state_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_1\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator : entity is "axi_protocol_converter_v2_1_11_b2s_cmd_translator";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd
port map (
CO(0) => CO(0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[46]\(8 downto 6) => \m_payload_i_reg[47]_0\(17 downto 15),
\m_payload_i_reg[46]\(5 downto 4) => \m_payload_i_reg[47]_0\(13 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]_0\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]_0\(0),
\state_reg[0]_0\ => \state_reg[0]_1\
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[47]_0\(14),
I2 => s_axburst_eq0,
O => \state_reg[0]\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 0) => \m_payload_i_reg[47]_0\(18 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\(0) => \state_reg[0]_0\(0),
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1 is
port (
incr_next_pending : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[1]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_0\ : in STD_LOGIC;
\m_payload_i_reg[47]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_11_b2s_cmd_translator";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair8";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(0) => D(0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(0) => Q(0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[1]_0\ => \axlen_cnt_reg[1]\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\(7 downto 6) => \m_payload_i_reg[47]_0\(17 downto 16),
\m_payload_i_reg[46]\(5 downto 4) => \m_payload_i_reg[47]_0\(13 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]_0\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[1]\ => \state_reg[1]_0\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[47]_0\(14),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[47]_0\(14),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 0) => \m_payload_i_reg[47]_0\(18 downto 0),
\m_payload_i_reg[47]_0\(3 downto 0) => \m_payload_i_reg[47]_1\(3 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
si_rs_arvalid => si_rs_arvalid,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel : entity is "axi_protocol_converter_v2_1_11_b2s_r_channel";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_push,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[1]_rep__3_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[2]_rep__0_0\ => transaction_fifo_0_n_1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \^m_valid_i_reg\,
\out\(33 downto 0) => \out\(33 downto 0),
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_3
);
transaction_fifo_0: entity work.\system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => \^m_valid_i_reg\,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => transaction_fifo_0_n_1,
r_push_r => r_push_r,
s_ready_i_reg => rd_data_fifo_0_n_0,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 53 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
shandshake : out STD_LOGIC;
\wrap_cnt_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_cnt_r_reg[2]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
aresetn : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_92 : STD_LOGIC;
begin
ar_pipe: entity work.system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice
port map (
Q(53 downto 0) => \s_arid_r_reg[11]\(53 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_92,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
axaddr_offset_0(0) => axaddr_offset_0(0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\,
\axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[3]\(1),
\axaddr_offset_r_reg[3]\(1) => \axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(0) => \axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i0 => m_valid_i0,
m_valid_i_reg_0 => ar_pipe_n_2,
next_pending_r_reg => next_pending_r_reg_0,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_1 => sel_first_1,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\state_reg[1]_rep_1\(0) => \state_reg[1]_rep_1\(0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[2]\(0) => \wrap_cnt_r_reg[2]\(0),
\wrap_cnt_r_reg[2]_0\ => \wrap_cnt_r_reg[2]_0\,
\wrap_second_len_r_reg[2]\(1 downto 0) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[2]_0\(2 downto 0) => \wrap_second_len_r_reg[2]_0\(2 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\
);
aw_pipe: entity work.system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice_0
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(53 downto 0) => Q(53 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_92,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
axaddr_offset(1) => axaddr_offset(2),
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[3]\ => axaddr_offset(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[1]\ => \state_reg[1]\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
wrap_second_len(2 downto 1) => wrap_second_len(3 downto 2),
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[1]\ => wrap_second_len(1),
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
);
b_pipe: entity work.\system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
shandshake => shandshake,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\system_auto_pc_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__2\ => \cnt_read_reg[3]_rep__2\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
r_push : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[61]\ : in STD_LOGIC_VECTOR ( 30 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel : entity is "axi_protocol_converter_v2_1_11_b2s_ar_channel";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_10 : STD_LOGIC;
signal ar_cmd_fsm_0_n_13 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_18 : STD_LOGIC;
signal ar_cmd_fsm_0_n_22 : STD_LOGIC;
signal ar_cmd_fsm_0_n_23 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_4 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^r_push\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal wrap_next_pending : STD_LOGIC;
begin
Q(2 downto 0) <= \^q\(2 downto 0);
axaddr_offset(0) <= \^axaddr_offset\(0);
r_push <= \^r_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
ar_cmd_fsm_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_rd_cmd_fsm
port map (
D(1) => ar_cmd_fsm_0_n_3,
D(0) => ar_cmd_fsm_0_n_4,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => state(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_18,
\axaddr_offset_r_reg[0]\(0) => \^axaddr_offset\(0),
\axaddr_offset_r_reg[0]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[0]\(0) => ar_cmd_fsm_0_n_6,
\axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_9,
\axlen_cnt_reg[3]\(0) => ar_cmd_fsm_0_n_17,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_10,
\axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[44]\(1 downto 0) => \m_payload_i_reg[61]\(15 downto 14),
\m_payload_i_reg[44]_0\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(1 downto 0) => \m_payload_i_reg[47]_0\(2 downto 1),
m_valid_i0 => m_valid_i0,
next_pending_r_reg => cmd_translator_0_n_1,
r_push_r_reg => \^r_push\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_10,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_13,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => s_ready_i_reg,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_22,
sel_first_reg_0 => ar_cmd_fsm_0_n_23,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_0\ => cmd_translator_0_n_11,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[2]\(1 downto 0) => D(1 downto 0),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(1) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]_0\(0) => \^q\(0)
);
cmd_translator_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(0) => ar_cmd_fsm_0_n_6,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(0) => cmd_translator_0_n_9,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 1) => \axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[1]\ => cmd_translator_0_n_10,
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_10,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_13,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\(18 downto 0) => \m_payload_i_reg[61]\(18 downto 0),
\m_payload_i_reg[47]_1\(3 downto 1) => \m_payload_i_reg[47]_0\(2 downto 0),
\m_payload_i_reg[47]_1\(0) => \^axaddr_offset\(0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_17,
next_pending_r_reg => cmd_translator_0_n_1,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_18,
sel_first_reg_3 => ar_cmd_fsm_0_n_22,
sel_first_reg_4 => ar_cmd_fsm_0_n_23,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[1]\(1 downto 0) => state(1 downto 0),
\state_reg[1]_0\ => ar_cmd_fsm_0_n_0,
\state_reg[1]_rep\ => \^r_push\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]\(2 downto 0) => \^q\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(3) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(1) => \wrap_second_len_r_reg[0]\(0),
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_4
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(19),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(29),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(30),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(20),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(21),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(22),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(23),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(24),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(25),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(26),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(27),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(28),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\m_payload_i_reg[61]\ : in STD_LOGIC_VECTOR ( 30 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel : entity is "axi_protocol_converter_v2_1_11_b2s_aw_channel";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_10 : STD_LOGIC;
signal aw_cmd_fsm_0_n_14 : STD_LOGIC;
signal aw_cmd_fsm_0_n_15 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
signal aw_cmd_fsm_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[0]\ <= \^wrap_boundary_axaddr_r_reg[0]\;
aw_cmd_fsm_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_wr_cmd_fsm
port map (
E(0) => aw_cmd_fsm_0_n_0,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_11,
\axlen_cnt_reg[7]\ => aw_cmd_fsm_0_n_5,
\axlen_cnt_reg[7]_0\ => cmd_translator_0_n_9,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0_0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[39]\(0) => \m_payload_i_reg[61]\(14),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_6,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_10,
s_axburst_eq1_reg_0 => cmd_translator_0_n_10,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_3,
sel_first_reg_0 => aw_cmd_fsm_0_n_14,
sel_first_reg_1 => aw_cmd_fsm_0_n_15,
sel_first_reg_2 => cmd_translator_0_n_2,
sel_first_reg_3 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\(0) => \^wrap_boundary_axaddr_r_reg[0]\,
wrap_next_pending => wrap_next_pending
);
cmd_translator_0: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[0]\,
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => \^q\(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axlen_cnt_reg[0]\ => cmd_translator_0_n_9,
\cnt_read_reg[1]_rep__0\ => aw_cmd_fsm_0_n_3,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_6,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_10,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\(18 downto 0) => \m_payload_i_reg[61]\(18 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_11,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_14,
sel_first_reg_2 => aw_cmd_fsm_0_n_15,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\ => cmd_translator_0_n_10,
\state_reg[0]_0\(0) => aw_cmd_fsm_0_n_0,
\state_reg[0]_1\ => aw_cmd_fsm_0_n_5,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(19),
Q => \in\(4),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(29),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(30),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(20),
Q => \in\(5),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(21),
Q => \in\(6),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(22),
Q => \in\(7),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(23),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(24),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(25),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(26),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(27),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(28),
Q => \in\(13),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(15),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(16),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(17),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(18),
Q => \in\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s : entity is "axi_protocol_converter_v2_1_11_b2s";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_14\ : STD_LOGIC;
signal \RD.ar_channel_0_n_15\ : STD_LOGIC;
signal \RD.ar_channel_0_n_44\ : STD_LOGIC;
signal \RD.ar_channel_0_n_45\ : STD_LOGIC;
signal \RD.ar_channel_0_n_46\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_5\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_10 : STD_LOGIC;
signal SI_REG_n_132 : STD_LOGIC;
signal SI_REG_n_133 : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_155 : STD_LOGIC;
signal SI_REG_n_157 : STD_LOGIC;
signal SI_REG_n_160 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_168 : STD_LOGIC;
signal SI_REG_n_169 : STD_LOGIC;
signal SI_REG_n_170 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_172 : STD_LOGIC;
signal SI_REG_n_173 : STD_LOGIC;
signal SI_REG_n_174 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal \WR.aw_channel_0_n_47\ : STD_LOGIC;
signal \WR.aw_channel_0_n_48\ : STD_LOGIC;
signal \WR.aw_channel_0_n_49\ : STD_LOGIC;
signal \WR.aw_channel_0_n_50\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \WR.b_channel_0_n_3\ : STD_LOGIC;
signal \ar_pipe/m_valid_i0\ : STD_LOGIC;
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_push : STD_LOGIC;
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
s_axi_arready <= \^s_axi_arready\;
\RD.ar_channel_0\: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_ar_channel
port map (
CO(0) => SI_REG_n_145,
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_146,
O(2) => SI_REG_n_147,
O(1) => SI_REG_n_148,
O(0) => SI_REG_n_149,
Q(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 0),
S(3) => \RD.ar_channel_0_n_44\,
S(2) => \RD.ar_channel_0_n_45\,
S(1) => \RD.ar_channel_0_n_46\,
S(0) => \RD.ar_channel_0_n_47\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_160,
\cnt_read_reg[1]_rep__0\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_14\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_15\,
\m_payload_i_reg[11]\(3) => SI_REG_n_141,
\m_payload_i_reg[11]\(2) => SI_REG_n_142,
\m_payload_i_reg[11]\(1) => SI_REG_n_143,
\m_payload_i_reg[11]\(0) => SI_REG_n_144,
\m_payload_i_reg[35]\ => SI_REG_n_164,
\m_payload_i_reg[35]_0\ => SI_REG_n_165,
\m_payload_i_reg[38]\ => SI_REG_n_184,
\m_payload_i_reg[3]\ => SI_REG_n_175,
\m_payload_i_reg[3]_0\(3) => SI_REG_n_137,
\m_payload_i_reg[3]_0\(2) => SI_REG_n_138,
\m_payload_i_reg[3]_0\(1) => SI_REG_n_139,
\m_payload_i_reg[3]_0\(0) => SI_REG_n_140,
\m_payload_i_reg[44]\ => SI_REG_n_166,
\m_payload_i_reg[47]\ => SI_REG_n_167,
\m_payload_i_reg[47]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\m_payload_i_reg[61]\(30 downto 19) => s_arid(11 downto 0),
\m_payload_i_reg[61]\(18 downto 15) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[61]\(14) => si_rs_arburst(1),
\m_payload_i_reg[61]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[61]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\(6) => SI_REG_n_168,
\m_payload_i_reg[6]\(5) => SI_REG_n_169,
\m_payload_i_reg[6]\(4) => SI_REG_n_170,
\m_payload_i_reg[6]\(3) => SI_REG_n_171,
\m_payload_i_reg[6]\(2) => SI_REG_n_172,
\m_payload_i_reg[6]\(1) => SI_REG_n_173,
\m_payload_i_reg[6]\(0) => SI_REG_n_174,
m_valid_i0 => \ar_pipe/m_valid_i0\,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => \^s_axi_arready\,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_5\,
\wrap_second_len_r_reg[0]\(0) => SI_REG_n_157
);
\RD.r_channel_0\: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_push => r_push,
r_rlast => r_rlast,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\
);
SI_REG: entity work.system_auto_pc_0_axi_register_slice_v2_1_11_axi_register_slice
port map (
CO(0) => SI_REG_n_132,
D(3 downto 2) => wrap_cnt(3 downto 2),
D(1) => SI_REG_n_10,
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_133,
O(2) => SI_REG_n_134,
O(1) => SI_REG_n_135,
O(0) => SI_REG_n_136,
Q(53 downto 42) => s_awid(11 downto 0),
Q(41 downto 38) => si_rs_awlen(3 downto 0),
Q(37) => si_rs_awburst(1),
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_47\,
S(2) => \WR.aw_channel_0_n_48\,
S(1) => \WR.aw_channel_0_n_49\,
S(0) => \WR.aw_channel_0_n_50\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_141,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_142,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_144,
\axaddr_incr_reg[3]\(3) => SI_REG_n_146,
\axaddr_incr_reg[3]\(2) => SI_REG_n_147,
\axaddr_incr_reg[3]\(1) => SI_REG_n_148,
\axaddr_incr_reg[3]\(0) => SI_REG_n_149,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_137,
\axaddr_incr_reg[7]\(2) => SI_REG_n_138,
\axaddr_incr_reg[7]\(1) => SI_REG_n_139,
\axaddr_incr_reg[7]\(0) => SI_REG_n_140,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_145,
axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
axaddr_offset_0(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[0]\ => SI_REG_n_175,
\axaddr_offset_r_reg[1]\ => SI_REG_n_164,
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\axlen_cnt_reg[3]\ => SI_REG_n_154,
\axlen_cnt_reg[3]_0\ => SI_REG_n_167,
b_push => b_push,
\cnt_read_reg[3]_rep__2\ => \RD.r_channel_0_n_0\,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\m_axi_araddr[10]\ => SI_REG_n_184,
\m_axi_awaddr[10]\ => SI_REG_n_183,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_44\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_45\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_46\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_47\,
m_valid_i0 => \ar_pipe/m_valid_i0\,
next_pending_r_reg => SI_REG_n_155,
next_pending_r_reg_0 => SI_REG_n_166,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(53 downto 42) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(41 downto 38) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(37) => si_rs_arburst(1),
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => \^s_axi_arready\,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_1 => \cmd_translator_0/incr_cmd_0/sel_first\,
shandshake => shandshake,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \RD.ar_channel_0_n_15\,
\state_reg[1]\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \RD.ar_channel_0_n_5\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_14\,
\state_reg[1]_rep_1\(0) => \ar_pipe/p_1_in\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_168,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_169,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_170,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_171,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_172,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_173,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_174,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182,
\wrap_cnt_r_reg[2]\(0) => SI_REG_n_157,
\wrap_cnt_r_reg[2]_0\ => SI_REG_n_160,
wrap_second_len(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
\wrap_second_len_r_reg[2]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 0),
\wrap_second_len_r_reg[3]\ => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0)
);
\WR.aw_channel_0\: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_aw_channel
port map (
CO(0) => SI_REG_n_132,
D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_133,
O(2) => SI_REG_n_134,
O(1) => SI_REG_n_135,
O(0) => SI_REG_n_136,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_47\,
S(2) => \WR.aw_channel_0_n_48\,
S(1) => \WR.aw_channel_0_n_49\,
S(0) => \WR.aw_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_3\,
\cnt_read_reg[1]_rep__0_0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[38]\ => SI_REG_n_183,
\m_payload_i_reg[46]\ => SI_REG_n_155,
\m_payload_i_reg[47]\ => SI_REG_n_154,
\m_payload_i_reg[61]\(30 downto 19) => s_awid(11 downto 0),
\m_payload_i_reg[61]\(18 downto 15) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[61]\(14) => si_rs_awburst(1),
\m_payload_i_reg[61]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\(6) => SI_REG_n_176,
\m_payload_i_reg[6]\(5) => SI_REG_n_177,
\m_payload_i_reg[6]\(4) => SI_REG_n_178,
\m_payload_i_reg[6]\(3) => SI_REG_n_179,
\m_payload_i_reg[6]\(2) => SI_REG_n_180,
\m_payload_i_reg[6]\(1) => SI_REG_n_181,
\m_payload_i_reg[6]\(0) => SI_REG_n_182,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(1) => SI_REG_n_10,
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
shandshake => shandshake,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
\state_reg[0]\ => \WR.b_channel_0_n_3\
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_11_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter : entity is "2'b10";
end system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter;
architecture STRUCTURE of system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_pc_0 : entity is "system_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_pc_0 : entity is "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4";
end system_auto_pc_0;
architecture STRUCTURE of system_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.system_auto_pc_0_axi_protocol_converter_v2_1_11_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 45f01e858a0f7532647a56ef0206a191 | 0.532635 | 2.539979 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_1/synth/system_ov7670_vga_0_1.vhd | 1 | 3,723 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_0_1 IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_0_1;
ARCHITECTURE system_ov7670_vga_0_1_arch OF system_ov7670_vga_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_0_1_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_0_1_arch : ARCHITECTURE IS "system_ov7670_vga_0_1,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_0_1_arch: ARCHITECTURE IS "system_ov7670_vga_0_1,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ov7670_vga
PORT MAP (
pclk => pclk,
data => data,
rgb => rgb
);
END system_ov7670_vga_0_1_arch;
| mit | 5827d8db9f72e97270f257a0a86d5d3f | 0.7408 | 3.834192 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/synth/system_c_addsub_0_0.vhd | 1 | 6,392 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:c_addsub:12.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY c_addsub_v12_0_10;
USE c_addsub_v12_0_10.c_addsub_v12_0_10;
ENTITY system_c_addsub_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_c_addsub_0_0;
ARCHITECTURE system_c_addsub_0_0_arch OF system_c_addsub_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_c_addsub_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT c_addsub_v12_0_10 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_XDEVICEFAMILY : STRING;
C_IMPLEMENTATION : INTEGER;
C_A_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_OUT_WIDTH : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_A_TYPE : INTEGER;
C_B_TYPE : INTEGER;
C_LATENCY : INTEGER;
C_ADD_MODE : INTEGER;
C_B_CONSTANT : INTEGER;
C_B_VALUE : STRING;
C_AINIT_VAL : STRING;
C_SINIT_VAL : STRING;
C_CE_OVERRIDES_BYPASS : INTEGER;
C_BYPASS_LOW : INTEGER;
C_SCLR_OVERRIDES_SSET : INTEGER;
C_HAS_C_IN : INTEGER;
C_HAS_C_OUT : INTEGER;
C_BORROW_LOW : INTEGER;
C_HAS_CE : INTEGER;
C_HAS_BYPASS : INTEGER;
C_HAS_SCLR : INTEGER;
C_HAS_SSET : INTEGER;
C_HAS_SINIT : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK : IN STD_LOGIC;
ADD : IN STD_LOGIC;
C_IN : IN STD_LOGIC;
CE : IN STD_LOGIC;
BYPASS : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
SSET : IN STD_LOGIC;
SINIT : IN STD_LOGIC;
C_OUT : OUT STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT c_addsub_v12_0_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_c_addsub_0_0_arch: ARCHITECTURE IS "c_addsub_v12_0_10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_c_addsub_0_0_arch : ARCHITECTURE IS "system_c_addsub_0_0,c_addsub_v12_0_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_c_addsub_0_0_arch: ARCHITECTURE IS "system_c_addsub_0_0,c_addsub_v12_0_10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=c_addsub,x_ipVersion=12.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_XDEVICEFAMILY=zynq,C_IMPLEMENTATION=0,C_A_WIDTH=10,C_B_WIDTH=10,C_OUT_WIDTH=10,C_CE_OVERRIDES_SCLR=0,C_A_TYPE=0,C_B_TYPE=0,C_LATENCY=0,C_ADD_MODE=0,C_B_CONSTANT=0,C_B_VALUE=0000000000,C_AINIT_VAL=0,C_SINIT_VAL=0,C_CE_OVERRIDES_BYPASS=1,C_BYPASS_LOW=0,C_SCLR_OVERRIDES_SSET=1,C_HAS_C_IN=0" &
",C_HAS_C_OUT=0,C_BORROW_LOW=1,C_HAS_CE=0,C_HAS_BYPASS=0,C_HAS_SCLR=0,C_HAS_SSET=0,C_HAS_SINIT=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA";
BEGIN
U0 : c_addsub_v12_0_10
GENERIC MAP (
C_VERBOSITY => 0,
C_XDEVICEFAMILY => "zynq",
C_IMPLEMENTATION => 0,
C_A_WIDTH => 10,
C_B_WIDTH => 10,
C_OUT_WIDTH => 10,
C_CE_OVERRIDES_SCLR => 0,
C_A_TYPE => 0,
C_B_TYPE => 0,
C_LATENCY => 0,
C_ADD_MODE => 0,
C_B_CONSTANT => 0,
C_B_VALUE => "0000000000",
C_AINIT_VAL => "0",
C_SINIT_VAL => "0",
C_CE_OVERRIDES_BYPASS => 1,
C_BYPASS_LOW => 0,
C_SCLR_OVERRIDES_SSET => 1,
C_HAS_C_IN => 0,
C_HAS_C_OUT => 0,
C_BORROW_LOW => 1,
C_HAS_CE => 0,
C_HAS_BYPASS => 0,
C_HAS_SCLR => 0,
C_HAS_SSET => 0,
C_HAS_SINIT => 0
)
PORT MAP (
A => A,
B => B,
CLK => '0',
ADD => '1',
C_IN => '0',
CE => '1',
BYPASS => '0',
SCLR => '0',
SSET => '0',
SINIT => '0',
S => S
);
END system_c_addsub_0_0_arch;
| mit | 471386237997476ae5a48dced5871ff4 | 0.660044 | 3.241379 | false | false | false | false |
sbourdeauducq/dspunit | rtl/bit_manipulation.vhdl | 2 | 12,347 | -- bit_manipulation.vhdl - miscellaneous bit manipulation functions
-- Copyright (C) 2001, 2002 Michael Riepe <[email protected]>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- $Id: bit_manipulation.vhdl,v 1.10 2002/07/05 21:36:57 michael Exp $
-- url : http://f-cpu.seul.org/whygee/f-cpu/f-cpu/vhdl/common/bit_manipulation.vhdl
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
package Bit_Manipulation is
-- reverse bits in a vector
function bit_reverse (A : in signed) return signed;
function bit_reverse (A : in unsigned) return unsigned;
function bit_reverse (A : in std_logic_vector) return std_logic_vector;
-- extract 1 bit of N, starting at offset O
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector;
-- duplicate all bits in a vector
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- duplicate vector
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector;
-- AND cascade
function cascade_and (A : in std_logic_vector) return std_logic_vector;
-- OR cascade
function cascade_or (A : in std_logic_vector) return std_logic_vector;
-- n:1 AND
function reduce_and (A : in std_logic_vector) return std_logic;
-- n:1 XOR
function reduce_xor (A : in std_logic_vector) return std_logic;
-- n:1 OR
function reduce_or (A : in std_logic_vector) return std_logic;
-- left shift w/ carry-in
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- left shift w/o carry-in
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic left shift
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right shift w/ carry-in
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector;
-- right shift w/o carry-in
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- arithmetic right shift
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- left rotate
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- right rotate
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned;
-- function bitbit_and(A : in signed; B : in signed) return signed;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector;
end Bit_Manipulation;
package body Bit_Manipulation is
function bit_reverse (A : in signed) return signed is
begin
return signed(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in unsigned) return unsigned is
begin
return unsigned(bit_reverse(std_logic_vector(A)));
end bit_reverse;
function bit_reverse (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, yy : std_logic_vector(L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in aa'range loop
yy(i) := aa(L - 1 - i);
end loop;
return yy;
end bit_reverse;
function bit_extract (A : in std_logic_vector;
N : in positive;
O : in natural := 0) return std_logic_vector is
constant L : natural := A'length;
constant L2 : natural := (L - O + N - 1) / N;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L2-1 downto 0);
begin
--pragma synthesis_off
assert L > O;
--pragma synthesis_on
for i in L2-1 downto 0 loop
yy(i) := aa(N*i+O);
end loop;
return yy;
end bit_extract;
function bit_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i/N);
end loop;
return yy;
end bit_duplicate;
function vector_duplicate (A : in std_logic_vector;
N : in positive) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(N*L-1 downto 0);
begin
--pragma synthesis_off
assert L > 0;
assert N > 0;
--pragma synthesis_on
for i in N*L-1 downto 0 loop
yy(i) := aa(i rem L);
end loop;
return yy;
end vector_duplicate;
function cascade_and (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) and aa(k1) and aa(k2) and aa(k3);
when 2 =>
bb(j) := aa(j) and aa(k1) and aa(k2);
when 1 =>
bb(j) := aa(j) and aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_and;
function cascade_or (A : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
variable aa, bb : std_logic_vector(L-1 downto 0);
variable k1, k2, k3 : integer;
variable step : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
for i in 0 to 15 loop -- should be enough
step := 4 ** i;
exit when step >= L;
for j in aa'range loop
k1 := j - j mod (4 * step) + step - 1;
k2 := k1 + step;
k3 := k2 + step;
case (j / step) mod 4 is
when 3 =>
bb(j) := aa(j) or aa(k1) or aa(k2) or aa(k3);
when 2 =>
bb(j) := aa(j) or aa(k1) or aa(k2);
when 1 =>
bb(j) := aa(j) or aa(k1);
when others =>
bb(j) := aa(j);
end case;
end loop;
aa := bb;
end loop;
return aa;
end cascade_or;
function reduce_and (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) and aa(4*i+1) and aa(4*i+2) and aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) and aa(4*k+1) and aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) and aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_and;
function reduce_xor (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 31 loop -- should be enough
exit when len = 1;
k := len / 2;
for i in 0 to k-1 loop
aa(i) := aa(2*i+0) xor aa(2*i+1);
end loop;
case len mod 2 is
when 1 => aa(k) := aa(2*k+0);
when others => null;
end case;
len := (len + 1) / 2;
end loop;
return aa(0);
end reduce_xor;
function reduce_or (A : in std_logic_vector) return std_logic is
constant L : natural := A'length;
variable aa : std_logic_vector(L-1 downto 0);
variable k, len : natural;
begin
--pragma synthesis_off
assert L > 0;
--pragma synthesis_on
aa := A;
len := L;
for j in 0 to 15 loop -- should be enough
exit when len = 1;
k := len / 4;
for i in 0 to k-1 loop
aa(i) := aa(4*i+0) or aa(4*i+1) or aa(4*i+2) or aa(4*i+3);
end loop;
case len mod 4 is
when 3 => aa(k) := aa(4*k+0) or aa(4*k+1) or aa(4*k+2);
when 2 => aa(k) := aa(4*k+0) or aa(4*k+1);
when 1 => aa(k) := aa(4*k+0);
when others => null;
end case;
len := (len + 3) / 4;
end loop;
return aa(0);
end reduce_or;
function lshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-1 downto N) := aa(L-N-1 downto 0);
end if;
return yy;
end lshift;
function lshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, '0');
end lshift;
function lshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return lshift(A, N, A(A'right));
end lshifta;
function rshift (A : in std_logic_vector;
N : in natural;
C : in std_logic) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
yy := (others => C);
if N < L then
yy(L-N-1 downto 0) := aa(L-1 downto N);
end if;
return yy;
end rshift;
function rshift (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, '0');
end rshift;
function rshifta (A : in std_logic_vector;
N : in natural) return std_logic_vector is
begin
return rshift(A, N, A(A'left));
end rshifta;
function lrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + L - N) rem L);
end loop;
return yy;
end lrotate;
function rrotate (A : in std_logic_vector;
N : in natural) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector(L-1 downto 0) is A;
variable yy : std_logic_vector(L-1 downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa((i + N) rem L);
end loop;
return yy;
end rrotate;
-- function bitbit_and(A : in signed; B : in signed) return signed is
-- begin
-- return signed(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
-- function bitbit_and(A : in unsigned; B : in unsigned) return unsigned is
-- begin
-- return unsigned(bitbit_and(std_logic_vector(A), std_logic_vector(B)));
-- end bitbit_and;
function bitbit_and(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) and bb(i);
end loop;
return yy;
end bitbit_and;
function bitbit_or(A : in std_logic_vector; B : in std_logic_vector) return std_logic_vector is
constant L : natural := A'length;
alias aa : std_logic_vector((L - 1) downto 0) is A;
alias bb : std_logic_vector((L - 1) downto 0) is B;
variable yy : std_logic_vector((L - 1) downto 0);
begin
for i in L-1 downto 0 loop
yy(i) := aa(i) or bb(i);
end loop;
return yy;
end bitbit_or;
end Bit_Manipulation;
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please
| gpl-3.0 | 5b163aa24c052fc3938dc88bab8b890d | 0.634729 | 2.81702 | false | false | false | false |
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