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loa-org/loa-hdl | modules/ram/tb/xilinx_block_ram_tb.vhd | 2 | 3,663 | -------------------------------------------------------------------------------
-- Title : Testbench for design "xilinx_block_ram"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xilinx_block_ram_pkg.all;
-------------------------------------------------------------------------------
entity xilinx_block_ram_tb is
end xilinx_block_ram_tb;
-------------------------------------------------------------------------------
architecture tb of xilinx_block_ram_tb is
-- component generics
constant ADDR_A_WIDTH : positive := 11;
constant ADDR_B_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 8;
constant DATA_B_WIDTH : positive := 16;
-- component ports
signal addr_a : std_logic_vector(ADDR_A_WIDTH-1 downto 0) := (others => '0');
signal addr_b : std_logic_vector(ADDR_B_WIDTH-1 downto 0) := (others => '0');
signal din_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal din_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal dout_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal dout_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal we_a : std_logic := '0';
signal we_b : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => addr_a,
addr_b => addr_b,
din_a => din_a,
din_b => din_b,
dout_a => dout_a,
dout_b => dout_b,
we_a => we_a,
we_b => we_b,
en_a => '1',
en_b => '1',
ssr_a => '0',
ssr_b => '0',
clk_a => clk,
clk_b => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
-- write Port A 0xfe at 0x20
addr_a <= std_logic_vector(unsigned'(resize(x"0020", addr_a'length)));
din_a <= std_logic_vector(unsigned'(resize(x"00fe", din_a'length)));
we_a <= '1';
wait until clk = '0';
we_a <= '0';
-- write Port A 0xab at 0x21
addr_a <= std_logic_vector(unsigned'(resize(x"0021", addr_a'length)));
din_a <= std_logic_vector(unsigned'(resize(x"00ab", din_a'length)));
we_a <= '1';
-- read Port B 0x20 / 2
addr_b <= std_logic_vector(unsigned'(resize(x"0010", addr_b'length)));
wait until clk = '0';
we_a <= '0';
-- Remember the effect of "read-first":
-- When 0x21 is addressed the memory cell is read before 0xab is
-- written to that cell. Thus 0x00 will appear at the output of dout_a.
-- 0xab will appear with the next rising clock edge on the output dout_a.
wait until clk = '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
| bsd-3-clause | ae5f2c5c541d159b7a3013dbc2a50db0 | 0.454818 | 3.788004 | false | false | false | false |
ErikAndren/SramTest-IS61LV25616AL | SramController.vhd | 1 | 3,273 | -- Controller implementation for the IS61LV25616-10 memory
-- Copyright [email protected] 2014
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity SramController is
generic (
AddrW : positive := 18;
DataW : positive := 16
);
port (
Clk : in bit1;
RstN : in bit1;
--
AddrIn : in word(AddrW-1 downto 0);
WrData : in word(DataW-1 downto 0);
RdData : out word(DataW-1 downto 0);
We : in bit1;
Re : in bit1;
--
D : inout word(DataW-1 downto 0);
AddrOut : out word(AddrW-1 downto 0);
CeN : out bit1;
OeN : out bit1;
WeN : out bit1;
UbN : out bit1;
LbN : out bit1
);
end entity;
architecture rtl of SramController is
-- The Is61LV25616-10 is asynchronous
-- tWC = Write Cycle Time = 10 ns min
-- tSA = Address Setup Time = 8 ns min
-- tSCE = CeN to Write End = 8 ns min
-- tHA = Address Hold from Write End = 0 ns min
-- tAW = Address Setup Time to Write End = 8 ns min
-- tPWE = WeN Pulse Width = 8 ns min
-- tPWB = LbN, UbN valid to end of write = 8 ns
-- tHZWE = WeN low to High-Z output = 5 ns max
-- tLZWE = WeN high to low-Z output = 3 ns min
-- tSD = Data Setup to Write End = 5 ns min
-- tHD = Data Hold from Write End = 0 ns min
-- tRC = Read Cycle Time = 10 ns min
type SramFSM is (IDLE, WR0, WR1, RE0);
signal SramFSM_N, SramFSM_D : SramFSM;
signal Addr_N, Addr_D : word(AddrW-1 downto 0);
signal Data_N, Data_D : word(DataW-1 downto 0);
begin
FSMSyncRst : process (Clk, RstN)
begin
if RstN = '0' then
SramFSM_D <= IDLE;
elsif rising_edge(Clk) then
SramFSM_D <= SramFSM_N;
end if;
end process;
FSMSyncNoRst : process (Clk)
begin
if rising_edge(Clk) then
Addr_D <= Addr_N;
Data_D <= Data_N;
end if;
end process;
FSMASync : process (SramFSM_D, We, Re, Addr_D, Data_D, AddrIn, WrData, D)
begin
SramFSM_N <= SramFSM_D;
Addr_N <= Addr_D;
AddrOut <= Addr_D;
Data_N <= Data_D;
--
D <= (others => 'Z');
WeN <= '1';
-- FIXME: Tie these to 0
UbN <= '1';
LbN <= '1';
CeN <= '1';
OeN <= '1';
case SramFsm_D is
when WR0 =>
SramFSM_N <= IDLE;
--
D <= Data_D;
CeN <= '0';
WeN <= '0';
UbN <= '0';
LbN <= '0';
when RE0 =>
SramFSM_N <= IDLE;
--
Data_N <= D;
when others =>
if (We = '1') then
SramFSM_N <= WR0;
--
Data_N <= WrData;
Addr_N <= AddrIn;
AddrOut <= AddrIn;
elsif Re = '1' then
SramFSM_N <= RE0;
--
CeN <= '0';
OeN <= '0';
UbN <= '0';
LbN <= '0';
--
Addr_N <= AddrIn;
AddrOut <= AddrIn;
-- FIXME: Potentially change this to sample the line instead
Data_N <= (others => '1');
end if;
end case;
end process;
RdData <= Data_D;
end architecture;
| gpl-2.0 | dcfaafa1d8873597fdd4ca311f8e18fc | 0.498014 | 3.227811 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_0/synth/affine_block_uint_to_ieee754_fp_0_0.vhd | 2 | 3,943 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:uint_to_ieee754_fp:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_uint_to_ieee754_fp_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_uint_to_ieee754_fp_0_0;
ARCHITECTURE affine_block_uint_to_ieee754_fp_0_0_arch OF affine_block_uint_to_ieee754_fp_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_uint_to_ieee754_fp_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT uint_to_ieee754_fp IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT uint_to_ieee754_fp;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_uint_to_ieee754_fp_0_0_arch: ARCHITECTURE IS "uint_to_ieee754_fp,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_uint_to_ieee754_fp_0_0_arch : ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_0,uint_to_ieee754_fp,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_uint_to_ieee754_fp_0_0_arch: ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_0,uint_to_ieee754_fp,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=uint_to_ieee754_fp,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=10}";
BEGIN
U0 : uint_to_ieee754_fp
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_uint_to_ieee754_fp_0_0_arch;
| mit | e5f08a2a313737de43978c34be723172 | 0.739031 | 3.644177 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_1rw_inferred-rtl-sim.vhdl | 1 | 3,505 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.numeric_pkg.all;
use util.logic_pkg.all;
use util.names_pkg.all;
use std.textio.all;
architecture rtl of syncram_1rw_inferred is
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
-- fill the memory with pseudo-random (but reproduceable) data
pure function memory_init return memory_type is
constant lfsr_bits : natural := addr_bits + log2ceil(data_bits) + 1;
variable lfsr : std_ulogic_vector(lfsr_bits-1 downto 0);
constant taps : std_ulogic_vector(lfsr_bits-1 downto 0) := lfsr_taps(lfsr_bits);
variable ret : memory_type;
variable initial_bit : integer;
variable name : line;
begin
name := new string'(entity_path_name(syncram_1rw_inferred'path_name));
for n in name.all'range loop
initial_bit := (initial_bit + character'pos(name.all(n))) mod lfsr_bits;
end loop;
deallocate(name);
lfsr := (others => '0');
lfsr(0) := '1';
lfsr(initial_bit) := '1';
for n in 0 to memory_size-1 loop
for m in data_bits-1 downto 0 loop
ret(n)(m) := lfsr(0);
lfsr(lfsr_bits-1 downto 0) := lfsr(0) & (lfsr(lfsr_bits-1 downto 1) xor ((lfsr_bits-2 downto 0 => lfsr(0)) and taps(lfsr_bits-2 downto 0)));
end loop;
end loop;
return ret;
end;
signal memory : memory_type := memory_init;
begin
main : process(clk)
begin
if rising_edge(clk) then
assert not is_x(en) report "en is invalid" severity warning;
if en = '1' then
assert not is_x(we) report "ew is invalid" severity warning;
assert not is_x(addr) report "addr is invalid" severity warning;
if we = '1' then
if not is_x(addr) then
memory(conv_addr(addr)) <= wdata;
end if;
rdata <= (others => 'X');
else
rdata <= memory(conv_addr(addr));
end if;
end if;
end if;
end process;
end;
| apache-2.0 | f10066b5351e739713a0c2db01b1a195 | 0.568616 | 3.978434 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_1_0/system_util_ds_buf_1_0_sim_netlist.vhdl | 1 | 6,355 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 11:21:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_util_ds_buf_1_0 -prefix
-- system_util_ds_buf_1_0_ system_util_ds_buf_0_0_sim_netlist.vhdl
-- Design : system_util_ds_buf_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_util_ds_buf_1_0_util_ds_buf is
port (
IBUF_DS_P : in STD_LOGIC_VECTOR ( 0 to 0 );
IBUF_DS_N : in STD_LOGIC_VECTOR ( 0 to 0 );
IBUF_OUT : out STD_LOGIC_VECTOR ( 0 to 0 );
IBUF_DS_ODIV2 : out STD_LOGIC_VECTOR ( 0 to 0 );
OBUF_IN : in STD_LOGIC_VECTOR ( 0 to 0 );
OBUF_DS_P : out STD_LOGIC_VECTOR ( 0 to 0 );
OBUF_DS_N : out STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_DS_P : inout STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_DS_N : inout STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_IO_T : in STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_IO_I : in STD_LOGIC_VECTOR ( 0 to 0 );
IOBUF_IO_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFGCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFGCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFGCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFH_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFH_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFHCE_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFHCE_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFHCE_O : out STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CEMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CLR : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_CLRMASK : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_GT_DIV : in STD_LOGIC_VECTOR ( 2 downto 0 );
BUFG_GT_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUF_TYPE : string;
attribute C_BUF_TYPE of system_util_ds_buf_1_0_util_ds_buf : entity is "BUFG";
attribute C_SIZE : integer;
attribute C_SIZE of system_util_ds_buf_1_0_util_ds_buf : entity is 1;
end system_util_ds_buf_1_0_util_ds_buf;
architecture STRUCTURE of system_util_ds_buf_1_0_util_ds_buf is
signal \<const0>\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \USE_BUFG.GEN_BUFG[0].BUFG_U\ : label is "PRIMITIVE";
begin
BUFGCE_O(0) <= \<const0>\;
BUFG_GT_O(0) <= \<const0>\;
BUFHCE_O(0) <= \<const0>\;
BUFH_O(0) <= \<const0>\;
IBUF_DS_ODIV2(0) <= \<const0>\;
IBUF_OUT(0) <= \<const0>\;
IOBUF_IO_O(0) <= \<const0>\;
OBUF_DS_N(0) <= \<const0>\;
OBUF_DS_P(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\USE_BUFG.GEN_BUFG[0].BUFG_U\: unisim.vcomponents.BUFG
port map (
I => BUFG_I(0),
O => BUFG_O(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_util_ds_buf_1_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_util_ds_buf_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_util_ds_buf_1_0 : entity is "system_util_ds_buf_0_0,util_ds_buf,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_util_ds_buf_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_util_ds_buf_1_0 : entity is "util_ds_buf,Vivado 2016.4";
end system_util_ds_buf_1_0;
architecture STRUCTURE of system_util_ds_buf_1_0 is
signal NLW_U0_BUFGCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_BUFG_GT_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_BUFHCE_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_BUFH_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IBUF_DS_ODIV2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IBUF_OUT_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IOBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IOBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_IOBUF_IO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_OBUF_DS_N_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_OBUF_DS_P_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BUF_TYPE : string;
attribute C_BUF_TYPE of U0 : label is "BUFG";
attribute C_SIZE : integer;
attribute C_SIZE of U0 : label is 1;
begin
U0: entity work.system_util_ds_buf_1_0_util_ds_buf
port map (
BUFGCE_CE(0) => '0',
BUFGCE_I(0) => '0',
BUFGCE_O(0) => NLW_U0_BUFGCE_O_UNCONNECTED(0),
BUFG_GT_CE(0) => '0',
BUFG_GT_CEMASK(0) => '0',
BUFG_GT_CLR(0) => '0',
BUFG_GT_CLRMASK(0) => '0',
BUFG_GT_DIV(2 downto 0) => B"000",
BUFG_GT_I(0) => '0',
BUFG_GT_O(0) => NLW_U0_BUFG_GT_O_UNCONNECTED(0),
BUFG_I(0) => BUFG_I(0),
BUFG_O(0) => BUFG_O(0),
BUFHCE_CE(0) => '0',
BUFHCE_I(0) => '0',
BUFHCE_O(0) => NLW_U0_BUFHCE_O_UNCONNECTED(0),
BUFH_I(0) => '0',
BUFH_O(0) => NLW_U0_BUFH_O_UNCONNECTED(0),
IBUF_DS_N(0) => '0',
IBUF_DS_ODIV2(0) => NLW_U0_IBUF_DS_ODIV2_UNCONNECTED(0),
IBUF_DS_P(0) => '0',
IBUF_OUT(0) => NLW_U0_IBUF_OUT_UNCONNECTED(0),
IOBUF_DS_N(0) => NLW_U0_IOBUF_DS_N_UNCONNECTED(0),
IOBUF_DS_P(0) => NLW_U0_IOBUF_DS_P_UNCONNECTED(0),
IOBUF_IO_I(0) => '0',
IOBUF_IO_O(0) => NLW_U0_IOBUF_IO_O_UNCONNECTED(0),
IOBUF_IO_T(0) => '0',
OBUF_DS_N(0) => NLW_U0_OBUF_DS_N_UNCONNECTED(0),
OBUF_DS_P(0) => NLW_U0_OBUF_DS_P_UNCONNECTED(0),
OBUF_IN(0) => '0'
);
end STRUCTURE;
| mit | 57b3c22f7c73e5c9f3653a27fe86517b | 0.604721 | 2.840858 | false | false | false | false |
loa-org/loa-hdl | modules/dds/hdl/nco.vhd | 1 | 3,016 | -------------------------------------------------------------------------------
-- Title : Numerically controlled oscillator - NCO
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2015-08-24
-------------------------------------------------------------------------------
-- Copyright (c) 2015, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.nco_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
entity nco is
generic (
ACCU_WIDTH : natural := 16;
PHASE_WIDTH : natural := 8;
RESET_IMPL : reset_type := none);
port (
en : in std_logic;
phase_increment : in std_logic_vector(ACCU_WIDTH-1 downto 0);
phase : out std_logic_vector(PHASE_WIDTH-1 downto 0);
load : in std_logic;
accu_load : in std_logic_vector(ACCU_WIDTH-1 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity nco;
architecture behavioral of nco is
type nco_state_type is record
accu : std_logic_vector(ACCU_WIDTH-1 downto 0);
end record nco_state_type;
constant nco_state_initial : nco_state_type := (accu => (others => '0'));
signal r, rin : nco_state_type := nco_state_initial;
begin -- architecture behaviorall
phase <= r.accu(ACCU_WIDTH-1 downto (ACCU_WIDTH - PHASE_WIDTH));
comb : process (accu_load, en, load, phase_increment, r, reset) is
variable v : nco_state_type;
begin -- process comb
v := r;
-- here usually goes the case statement for the FSMs state .. but not today
if load = '1' then
v.accu := accu_load;
elsif en = '1' then
v.accu :=
std_logic_vector(
resize(unsigned(r.accu) +unsigned(phase_increment), ACCU_WIDTH)
); -- numeric_std loves you
end if;
-- sync reset
if RESET_IMPL = sync and reset = '1' then
v := nco_state_initial;
end if;
rin <= v;
end process comb;
async_reset : if RESET_IMPL = async generate
seq : process (clk, reset) is
begin -- process seq
if reset = '0' then -- asynchronous reset (active low)
r <= nco_state_initial;
elsif clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
sync_reset : if RESET_IMPL /= async generate
seq : process (clk) is
begin -- process seq
if clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
end architecture behavioral;
| bsd-3-clause | 9f635caefcdfd0277b059e4b9759d82c | 0.528846 | 3.989418 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/mux_1hot-rtl.vhdl | 1 | 1,470 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of mux_1hot is
begin
mux : entity work.mux_1hot_inferred(rtl)
generic map (
data_bits => data_bits,
sel_bits => sel_bits
)
port map (
din => din,
sel => sel,
dout => dout
);
end;
| apache-2.0 | 2e77e21bd38fd7490231f536ca80e87a | 0.47483 | 5.306859 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl | 3 | 70,090 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_0_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_0_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_0_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_0_0 : entity is "system_vga_sync_ref_0_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_0_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_0_0;
architecture STRUCTURE of system_vga_sync_ref_0_0 is
begin
U0: entity work.system_vga_sync_ref_0_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 61804a0cc0aabcc54b0cbfdfd48de67a | 0.486104 | 2.524583 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0_1/sim/system_vga_sync_0_0.vhd | 3 | 4,025 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit | 069b942340724f4c9165061d399074f2 | 0.691429 | 3.866475 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/synth/system_rgb888_to_rgb565_0_0.vhd | 4 | 3,795 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb888_to_rgb565:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb888_to_rgb565_0_0 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_rgb888_to_rgb565_0_0;
ARCHITECTURE system_rgb888_to_rgb565_0_0_arch OF system_rgb888_to_rgb565_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb888_to_rgb565 IS
PORT (
rgb_888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_565 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT rgb888_to_rgb565;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "rgb888_to_rgb565,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb888_to_rgb565_0_0_arch : ARCHITECTURE IS "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb888_to_rgb565_0_0_arch: ARCHITECTURE IS "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb888_to_rgb565,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : rgb888_to_rgb565
PORT MAP (
rgb_888 => rgb_888,
rgb_565 => rgb_565
);
END system_rgb888_to_rgb565_0_0_arch;
| mit | 1da6cd40d2afcbd3dd82b9a0c0e8a440 | 0.74809 | 3.709677 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/synth/affine_block_ieee754_fp_adder_subtractor_0_1.vhd | 2 | 4,122 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_adder_subtractor:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_adder_subtractor_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_adder_subtractor_0_1;
ARCHITECTURE affine_block_ieee754_fp_adder_subtractor_0_1_arch OF affine_block_ieee754_fp_adder_subtractor_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_adder_subtractor IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_adder_subtractor;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "ieee754_fp_adder_subtractor,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_adder_subtractor_0_1_arch : ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_adder_subtractor_0_1_arch: ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_adder_subtractor,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_adder_subtractor
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_adder_subtractor_0_1_arch;
| mit | e47c842fa2ac226c61ffa292ceb944b8 | 0.751577 | 3.774725 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/synth/system_vga_hessian_0_0.vhd | 1 | 4,403 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_0_0_arch : ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=41,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit | 6bf272885ea8c157d88ceccff3a7feeb | 0.719509 | 3.678363 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 26,705 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Wed Mar 01 10:29:47 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished_0 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
href_0 : in STD_LOGIC;
href_1 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
resend : in STD_LOGIC;
scl_0 : out STD_LOGIC;
scl_1 : out STD_LOGIC;
sda_0 : inout STD_LOGIC;
sda_1 : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=16,numReposBlks=16,numNonXlnxBlks=3,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_ov7670_vga_0_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_ov7670_vga_1_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_1_0;
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_1_0;
component system_rgb565_to_rgb888_0_0 is
port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_rgb565_to_rgb888_1_0 is
port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_1_0;
component system_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
end component system_zybo_hdmi_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_inverter_1_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_1_0;
component system_util_vector_logic_1_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_vector_logic_1_0;
component system_inverter_2_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_2_0;
component system_vga_gaussian_blur_0_0 is
port (
clk_25 : in STD_LOGIC;
hsync_in : in STD_LOGIC;
vsync_in : in STD_LOGIC;
rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
hsync_out : out STD_LOGIC;
vsync_out : out STD_LOGIC;
rgb_blur : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_gaussian_blur_0_0;
component system_vga_gaussian_blur_1_0 is
port (
clk_25 : in STD_LOGIC;
hsync_in : in STD_LOGIC;
vsync_in : in STD_LOGIC;
rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
hsync_out : out STD_LOGIC;
vsync_out : out STD_LOGIC;
rgb_blur : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_gaussian_blur_1_0;
component system_vga_laplacian_fusion_0_0 is
port (
clk_25 : in STD_LOGIC;
rgb_blur_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_blur_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_out : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_laplacian_fusion_0_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal \^data_1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data_1_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal hdmi_cec_1 : STD_LOGIC;
signal hdmi_hpd_1 : STD_LOGIC;
signal href_0_1 : STD_LOGIC;
signal href_1_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal inverter_1_x_not : STD_LOGIC;
signal inverter_2_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_controller_0_xclk : STD_LOGIC;
signal ov7670_controller_1_config_finished : STD_LOGIC;
signal ov7670_controller_1_sioc : STD_LOGIC;
signal ov7670_controller_1_xclk : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ov7670_vga_1_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^pclk_1\ : STD_LOGIC;
signal pclk_1_1 : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal resend_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb565_to_rgb888_1_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal util_vector_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_gaussian_blur_0_rgb_blur : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_gaussian_blur_0_rgb_pass : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_gaussian_blur_1_rgb_blur : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_gaussian_blur_1_rgb_pass : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_laplacian_fusion_0_rgb_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vsync_0_1 : STD_LOGIC;
signal vsync_1_1 : STD_LOGIC;
signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC;
signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_reset_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_vga_gaussian_blur_0_hsync_out_UNCONNECTED : STD_LOGIC;
signal NLW_vga_gaussian_blur_0_vsync_out_UNCONNECTED : STD_LOGIC;
signal NLW_vga_gaussian_blur_1_hsync_out_UNCONNECTED : STD_LOGIC;
signal NLW_vga_gaussian_blur_1_vsync_out_UNCONNECTED : STD_LOGIC;
begin
\^data_1\(7 downto 0) <= data_0(7 downto 0);
\^pclk_1\ <= pclk_0;
config_finished_0 <= ov7670_controller_0_config_finished;
config_finished_1 <= ov7670_controller_1_config_finished;
data_1_1(7 downto 0) <= data_1(7 downto 0);
hdmi_cec_1 <= hdmi_cec;
hdmi_hpd_1 <= hdmi_hpd;
hdmi_out_en <= zybo_hdmi_0_hdmi_out_en;
href_0_1 <= href_0;
href_1_1 <= href_1;
pclk_1_1 <= pclk_1;
resend_1 <= resend;
scl_0 <= ov7670_controller_0_sioc;
scl_1 <= ov7670_controller_1_sioc;
tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0);
tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0);
vsync_0_1 <= vsync_0;
vsync_1_1 <= vsync_1;
xclk_0 <= ov7670_controller_0_xclk;
xclk_1 <= ov7670_controller_1_xclk;
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => href_0_1,
x_not => inverter_0_x_not
);
inverter_1: component system_inverter_1_0
port map (
x => href_1_1,
x_not => inverter_1_x_not
);
inverter_2: component system_inverter_2_0
port map (
x => util_vector_logic_1_Res(0),
x_not => inverter_2_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => clk_wiz_0_clk_out1,
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => resend_1,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => sda_0,
xclk => ov7670_controller_0_xclk
);
ov7670_controller_1: component system_ov7670_controller_1_0
port map (
clk => clk_wiz_0_clk_out1,
config_finished => ov7670_controller_1_config_finished,
pwdn => NLW_ov7670_controller_1_pwdn_UNCONNECTED,
resend => resend_1,
reset => NLW_ov7670_controller_1_reset_UNCONNECTED,
sioc => ov7670_controller_1_sioc,
siod => sda_1,
xclk => ov7670_controller_1_xclk
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
data(7 downto 0) => \^data_1\(7 downto 0),
pclk => \^pclk_1\,
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
ov7670_vga_1: component system_ov7670_vga_1_0
port map (
data(7 downto 0) => data_1_1(7 downto 0),
pclk => pclk_1_1,
rgb(15 downto 0) => ov7670_vga_1_rgb(15 downto 0)
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb565_to_rgb888_1: component system_rgb565_to_rgb888_1_0
port map (
rgb_565(15 downto 0) => ov7670_vga_1_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_1_rgb_888(23 downto 0)
);
util_vector_logic_1: component system_util_vector_logic_1_0
port map (
Op1(0) => inverter_0_x_not,
Op2(0) => vsync_0_1,
Res(0) => util_vector_logic_1_Res(0)
);
vga_gaussian_blur_0: component system_vga_gaussian_blur_0_0
port map (
clk_25 => clk_wiz_0_clk_out1,
hsync_in => inverter_0_x_not,
hsync_out => NLW_vga_gaussian_blur_0_hsync_out_UNCONNECTED,
rgb_blur(23 downto 0) => vga_gaussian_blur_0_rgb_blur(23 downto 0),
rgb_in(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
rgb_pass(23 downto 0) => vga_gaussian_blur_0_rgb_pass(23 downto 0),
vsync_in => vsync_0_1,
vsync_out => NLW_vga_gaussian_blur_0_vsync_out_UNCONNECTED
);
vga_gaussian_blur_1: component system_vga_gaussian_blur_1_0
port map (
clk_25 => clk_wiz_0_clk_out1,
hsync_in => inverter_1_x_not,
hsync_out => NLW_vga_gaussian_blur_1_hsync_out_UNCONNECTED,
rgb_blur(23 downto 0) => vga_gaussian_blur_1_rgb_blur(23 downto 0),
rgb_in(23 downto 0) => rgb565_to_rgb888_1_rgb_888(23 downto 0),
rgb_pass(23 downto 0) => vga_gaussian_blur_1_rgb_pass(23 downto 0),
vsync_in => vsync_1_1,
vsync_out => NLW_vga_gaussian_blur_1_vsync_out_UNCONNECTED
);
vga_laplacian_fusion_0: component system_vga_laplacian_fusion_0_0
port map (
clk_25 => clk_wiz_0_clk_out1,
rgb_blur_0(23 downto 0) => vga_gaussian_blur_0_rgb_blur(23 downto 0),
rgb_blur_1(23 downto 0) => vga_gaussian_blur_1_rgb_blur(23 downto 0),
rgb_out(23 downto 0) => vga_laplacian_fusion_0_rgb_out(23 downto 0),
rgb_pass_0(23 downto 0) => vga_gaussian_blur_0_rgb_pass(23 downto 0),
rgb_pass_1(23 downto 0) => vga_gaussian_blur_1_rgb_pass(23 downto 0)
);
zybo_hdmi_0: component system_zybo_hdmi_0_0
port map (
active => inverter_2_x_not,
clk_125 => processing_system7_0_FCLK_CLK0,
clk_25 => clk_wiz_0_clk_out1,
hdmi_cec => hdmi_cec_1,
hdmi_hpd => hdmi_hpd_1,
hdmi_out_en => zybo_hdmi_0_hdmi_out_en,
hsync => inverter_0_x_not,
rgb(23 downto 0) => vga_laplacian_fusion_0_rgb_out(23 downto 0),
tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0),
tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0),
vsync => vsync_0_1
);
end STRUCTURE;
| mit | fcbbc124288cbc15ecdcba03e45c7c22 | 0.65894 | 2.886403 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_1/synth/system_vga_buffer_1_1.vhd | 1 | 4,630 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_1_1 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_1_1;
ARCHITECTURE system_vga_buffer_1_1_arch OF system_vga_buffer_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_buffer_1_1_arch: ARCHITECTURE IS "vga_buffer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_buffer_1_1_arch : ARCHITECTURE IS "system_vga_buffer_1_1,vga_buffer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_buffer_1_1_arch: ARCHITECTURE IS "system_vga_buffer_1_1,vga_buffer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_buffer,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE_POW2=12}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 12
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_1_1_arch;
| mit | f7fa72b8a7864f869a64b6425b639135 | 0.707127 | 3.58082 | false | false | false | false |
sbourdeauducq/dspunit | rtl/sigshift.vhd | 2 | 15,849 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
use work.Bit_Manipulation.all;
-------------------------------------------------------------------------------
entity sigshift is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
shift_reg : in std_logic_vector((cmdreg_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end sigshift;
--=----------------------------------------------------------------------------
architecture archi_sigshift of sigshift is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_addr_pipe_depth : integer := 3;
constant c_data_pipe_depth : integer := 6;
constant c_ind_width : integer := cmdreg_width - 2;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_sigshift_state is (st_init, st_cycle, st_cycleend);
signal s_state : t_sigshift_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_shift : unsigned((cmdreg_width - 1) downto 0);
signal s_length_moins : unsigned((cmdreg_width - 1) downto 0);
type t_addr_pipe is array(0 to c_addr_pipe_depth - 1) of unsigned((cmdreg_width - 1) downto 0);
type t_data_pipe is array(0 to c_data_pipe_depth - 1) of std_logic_vector((sig_width - 1) downto 0);
type t_wr_pipe is array(0 to c_addr_pipe_depth - 1) of std_logic;
signal s_addr_pipe : t_addr_pipe;
signal s_data_pipe : t_data_pipe;
signal s_data_bis : std_logic_vector((sig_width - 1) downto 0);
signal s_wr_pipe : t_wr_pipe;
signal s_next_index : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index_rev : unsigned((c_ind_width - 2) downto 0);
signal s_sample_index_w : unsigned((c_ind_width - 1) downto 0);
signal s_sample_index_w_rev : unsigned((c_ind_width - 2) downto 0);
signal s_addr_r_m0_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_w_m0_tmp : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r_tmp : unsigned((cmdreg_width - 1) downto 0);
begin -- archs_sigshift
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_sigshift : process (clk)
begin -- process p_sigshift
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
if s_dsp_bus.op_done = '0' then
s_state <= st_cycle;
end if;
when st_cycle =>
if s_sample_index = s_length_moins + c_data_pipe_depth then
s_state <= st_cycleend;
end if;
when st_cycleend =>
if s_wr_pipe(c_addr_pipe_depth - 1) = '0' then
-- cycle terminates when writing is about to stop
s_state <= st_init;
s_dsp_bus.op_done <= '1';
end if;
when others =>
s_state <= st_init;
end case;
end if;
end if;
end process p_sigshift;
-------------------------------------------------------------------------------
-- Compute address of reading words
-------------------------------------------------------------------------------
p_addr_comput : process (clk)
begin -- process p_addr_comput
if rising_edge(clk) then -- rising clock edge
if(s_state = st_cycle) then
s_sample_index <= s_next_index((c_ind_width - 1) downto 0);
else
s_sample_index <= to_unsigned(0, c_ind_width);
end if;
end if;
end process p_addr_comput;
s_next_index <= s_sample_index + 1;
-------------------------------------------------------------------------------
-- address pipe : output is writting address
-------------------------------------------------------------------------------
p_addr_pipe : process (clk)
begin -- process p_addr_pipe
if rising_edge(clk) then -- rising clock edge
s_addr_pipe(0) <= s_addr_w_m0_tmp;
if(s_state = st_cycle) then
s_wr_pipe(0) <= '1';
else
s_wr_pipe(0) <= '0';
end if;
for i in 0 to c_addr_pipe_depth - 2 loop
s_addr_pipe(i + 1) <= s_addr_pipe(i);
s_wr_pipe(i + 1) <= s_wr_pipe(i);
end loop;
end if;
end process p_addr_pipe;
s_addr_r_tmp <= zeros(cmdreg_width - c_ind_width) & s_sample_index;
p_data_pipe : process (clk)
begin -- process p_data_pipe
if rising_edge(clk) then -- rising clock edge
s_data_pipe(0) <= data_in_m0;
for i in 0 to c_data_pipe_depth - 2 loop
s_data_pipe(i + 1) <= s_data_pipe(i);
end loop;
end if;
end process p_data_pipe;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.c_en_m0 <= '1';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
-- s_dsp_bus.data_out_m0 <= data_in_m0;
s_data_bis <= s_data_pipe(c_data_pipe_depth - 1)(sig_width - 1) & s_data_pipe(c_data_pipe_depth - 1)((sig_width - 1) downto 1);
-- Writing and reading address of the memory
process (clk)
begin -- process
if rising_edge(clk) then -- rising clock edge
-- One register just after address computation
s_dsp_bus.addr_r_m0 <= s_addr_r_m0_tmp and s_length_moins;
s_dsp_bus.data_out_m0 <= std_logic_vector(signed(data_in_m0) + signed(s_data_bis));
s_dsp_bus.addr_w_m0 <= s_addr_pipe(c_addr_pipe_depth - 1) + s_length;
s_dsp_bus.wr_en_m0 <= s_wr_pipe(c_addr_pipe_depth - 1);
end if;
end process;
-- s_dsp_bus.addr_w_m0 <= (s_addr_pipe(c_addr_pipe_depth - 1) + s_shift) and s_length_moins;
-- s_dsp_bus.addr_w_m0 <= s_addr_pipe(0) + s_length;
-- Writing and reading address of the memory
s_sample_index_rev <= bit_reverse(s_sample_index((c_ind_width - 1) downto 1));
s_sample_index_w <= (s_sample_index + s_shift((c_ind_width - 1) downto 0)) and s_length_moins((c_ind_width - 1) downto 0);
s_sample_index_w_rev <= bit_reverse(s_sample_index_w((c_ind_width - 1) downto 1));
-- index with bit reverse if needed
s_addr_r_m0_tmp((cmdreg_width - 1) downto c_ind_width) <= (others => '0');
s_addr_r_m0_tmp((c_ind_width - 1) downto 1) <= s_sample_index((c_ind_width - 1) downto 1) when opflag_select(opflagbit_bitrev) = '0' else
zeros(c_ind_width - 4) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 4))
when s_length(4) = '1' else
zeros(c_ind_width - 5) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 5))
when s_length(5) = '1' else
zeros(c_ind_width - 6) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 6))
when s_length(6) = '1' else
zeros(c_ind_width - 7) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 7))
when s_length(7) = '1' else
zeros(c_ind_width - 8) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 8))
when s_length(8) = '1' else
zeros(c_ind_width - 9) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 9))
when s_length(9) = '1' else
zeros(c_ind_width - 10) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 10))
when s_length(10) = '1' else
zeros(c_ind_width - 11) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 11))
when s_length(11) = '1' else
zeros(c_ind_width - 12) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 12))
when s_length(12) = '1' else
zeros(c_ind_width - 13) &
s_sample_index_rev((c_ind_width - 2) downto (c_ind_width - 13))
when s_length(13) = '1' else
s_sample_index_rev;
s_addr_r_m0_tmp(0) <= s_sample_index(0);
-- index with bit reverse if needed
s_addr_w_m0_tmp((cmdreg_width - 1) downto c_ind_width) <= (others => '0');
s_addr_w_m0_tmp((c_ind_width - 1) downto 1) <= s_sample_index_w((c_ind_width - 1) downto 1) when opflag_select(opflagbit_bitrev) = '0' else
zeros(c_ind_width - 4) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 4))
when s_length(4) = '1' else
zeros(c_ind_width - 5) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 5))
when s_length(5) = '1' else
zeros(c_ind_width - 6) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 6))
when s_length(6) = '1' else
zeros(c_ind_width - 7) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 7))
when s_length(7) = '1' else
zeros(c_ind_width - 8) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 8))
when s_length(8) = '1' else
zeros(c_ind_width - 9) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 9))
when s_length(9) = '1' else
zeros(c_ind_width - 10) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 10))
when s_length(10) = '1' else
zeros(c_ind_width - 11) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 11))
when s_length(11) = '1' else
zeros(c_ind_width - 12) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 12))
when s_length(12) = '1' else
zeros(c_ind_width - 13) &
s_sample_index_w_rev((c_ind_width - 2) downto (c_ind_width - 13))
when s_length(13) = '1' else
s_sample_index_w_rev;
s_addr_w_m0_tmp(0) <= s_sample_index_w(0);
s_shift <= unsigned(shift_reg);
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= '0';
s_dsp_bus.addr_m2 <= to_unsigned(0, cmdreg_width);
-- specific index relations
s_length <= unsigned(length_reg);
s_length_moins <= s_length - 1;
end archi_sigshift;
| gpl-3.0 | 7f382b8d9430d642076462853a7da956 | 0.395924 | 4.143529 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_clock_det.vhd | 1 | 1,968 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--Simple Clock Detector for CSI-2 Rx
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This is designed to hold the ISERDES in reset until at least 3 byte clock
--cycles have been detected; to ensure proper ISERDES behaviour
--It will reassert reset once the byte clock has not toggled compared to the reference clock
--for at least 200 reference clock cycles
entity csi_rx_clock_det is
port ( ref_clock : in std_logic; --reference clock in; must not be synchronised to ext_clock
ext_clock : in STD_LOGIC; --external byte clock input for detection
enable : in STD_LOGIC; --active high enable
reset_in : in STD_LOGIC; --active high asynchronous reset in
reset_out : out STD_LOGIC); --active high reset out to ISERDESs
end csi_rx_clock_det;
architecture Behavioral of csi_rx_clock_det is
signal count_value : unsigned(3 downto 0);
signal clk_fail : std_logic;
signal ext_clk_lat : std_logic;
signal last_ext_clk : std_logic;
signal clk_fail_count : unsigned(7 downto 0);
begin
process(ext_clock, reset_in, clk_fail)
begin
if reset_in = '1' or clk_fail = '1' then
count_value <= x"0";
elsif rising_edge(ext_clock) then
if enable = '1' then
if count_value < 3 then
count_value <= count_value + 1;
end if;
end if;
end if;
end process;
--Reset in between frames, by detecting the loss of the high speed clock
process(ref_clock)
begin
if rising_edge(ref_clock) then
ext_clk_lat <= ext_clock;
last_ext_clk <= ext_clk_lat;
if last_ext_clk /= ext_clk_lat then
clk_fail_count <= (others => '0');
else
if clk_fail_count < 250 then
clk_fail_count <= clk_fail_count + 1;
end if;
end if;
end if;
end process;
clk_fail <= '1' when clk_fail_count >= 200 else '0';
reset_out <= '0' when count_value >= 2 else '1';
end Behavioral;
| mit | e48a5b5b7deddcdae2409e7ee0ef1b35 | 0.667175 | 3.369863 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/ov7670_vga/ov7670_vga.srcs/sources_1/new/ov7670_vga.vhd | 6 | 1,332 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: ov7670_vga - Structural
-- Description: The ov7670 can produce 8-bits of data - pclk runs two cycles to produce RGB565
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ov7670_vga is
port(
clk_x2 : in std_logic;
active : in std_logic;
data : in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(15 downto 0)
);
end ov7670_vga;
architecture Structural of ov7670_vga is
signal data_pair : std_logic_vector(15 downto 0);
signal cycle : std_logic := '0';
begin
process(clk_x2)
begin
if rising_edge(clk_x2) then
if active = '0' then
cycle <= '0';
else
if cycle = '0' then
data_pair(7 downto 0) <= data;
cycle <= '1';
else
data_pair(15 downto 8) <= data;
cycle <= '0';
end if;
end if;
end if;
if falling_edge(clk_x2) and cycle = '1' then
rgb <= data_pair;
end if;
end process;
end Structural;
| mit | 846c6d52b7db45b710c41c2cd0db2bf3 | 0.459459 | 4.269231 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 20,687 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 20 15:33:27 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=8,numReposBlks=8,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
end component system_zybo_hdmi_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_affine_transform_0_1 is
port (
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_affine_transform_0_1;
component system_affine_rotation_generator_0_0 is
port (
clk_25 : in STD_LOGIC;
reset : in STD_LOGIC;
a00 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_affine_rotation_generator_0_0;
signal VDDMinus : STD_LOGIC;
signal affine_rotation_generator_0_a00 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal affine_rotation_generator_0_a01 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal affine_rotation_generator_0_a10 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal affine_rotation_generator_0_a11 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal affine_transform_0_x_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal affine_transform_0_y_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal hdmi_cec_1 : STD_LOGIC;
signal hdmi_hpd_1 : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC;
signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
hdmi_cec_1 <= hdmi_cec;
hdmi_hpd_1 <= hdmi_hpd;
hdmi_out_en <= zybo_hdmi_0_hdmi_out_en;
tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0);
tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0);
affine_rotation_generator_0: component system_affine_rotation_generator_0_0
port map (
a00(31 downto 0) => affine_rotation_generator_0_a00(31 downto 0),
a01(31 downto 0) => affine_rotation_generator_0_a01(31 downto 0),
a10(31 downto 0) => affine_rotation_generator_0_a10(31 downto 0),
a11(31 downto 0) => affine_rotation_generator_0_a11(31 downto 0),
clk_25 => clk_wiz_0_clk_out1,
reset => VDDMinus
);
affine_transform_0: component system_affine_transform_0_1
port map (
a00(31 downto 0) => affine_rotation_generator_0_a00(31 downto 0),
a01(31 downto 0) => affine_rotation_generator_0_a10(31 downto 0),
a10(31 downto 0) => affine_rotation_generator_0_a01(31 downto 0),
a11(31 downto 0) => affine_rotation_generator_0_a11(31 downto 0),
x_in(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
x_out(9 downto 0) => affine_transform_0_x_out(9 downto 0),
y_in(9 downto 0) => vga_sync_0_yaddr(9 downto 0),
y_out(9 downto 0) => affine_transform_0_y_out(9 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => processing_system7_0_FCLK_RESET0_N,
x_not => VDDMinus
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => clk_wiz_0_clk_out1,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => affine_transform_0_x_out(9 downto 0),
yaddr(9 downto 0) => affine_transform_0_y_out(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk_25 => clk_wiz_0_clk_out1,
hsync => vga_sync_0_hsync,
rst => VDDMinus,
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zybo_hdmi_0: component system_zybo_hdmi_0_0
port map (
active => vga_sync_0_active,
clk_125 => processing_system7_0_FCLK_CLK0,
clk_25 => clk_wiz_0_clk_out1,
hdmi_cec => hdmi_cec_1,
hdmi_hpd => hdmi_hpd_1,
hdmi_out_en => zybo_hdmi_0_hdmi_out_en,
hsync => vga_sync_0_hsync,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0),
tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0),
vsync => vga_sync_0_vsync
);
end STRUCTURE;
| mit | 99175a4b910f22099a43aa62110c5640 | 0.662783 | 2.913252 | false | false | false | false |
sbourdeauducq/dspunit | rtl/cpmem.vhd | 2 | 8,357 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity cpmem is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end cpmem;
--=----------------------------------------------------------------------------
architecture archi_cpmem of cpmem is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_cpmem_state is (st_init, st_startpipe, st_copy);
signal s_state : t_cpmem_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_real_r : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_real_w : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_w : unsigned((cmdreg_width - 1) downto 0);
signal s_wr_en : std_logic;
begin -- archs_cpmem
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_cpmem : process (clk)
begin -- process p_cpmem
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
s_dsp_bus.op_done <= '0';
s_addr_r <= (others => '0');
s_addr_w <= (others => '0');
s_wr_en <= '0';
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
s_dsp_bus.alu_select <= alu_mul;
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_addr_w <= (others => '0');
s_addr_r <= (others => '0');
s_wr_en <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_startpipe;
end if;
when st_startpipe =>
if s_addr_r = 2 then
s_wr_en <= '1';
s_state <= st_copy;
end if;
-- index increment
s_addr_r <= s_addr_r + 1;
when st_copy =>
s_wr_en <= '1';
if(s_addr_w = s_length) then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
else
s_addr_r <= s_addr_r + 1;
s_addr_w <= (s_addr_w + 1) and s_length;
end if;
when others => null;
end case;
end if;
end if;
end process p_cpmem;
p_data_select : process (clk)
begin -- process p_data_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.data_out_m0 <= (others => '0');
s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.data_out_m2 <= (others => '0');
elsif opflag_select(opflagbit_srcm0) = '1' then
s_dsp_bus.data_out_m0 <= data_in_m0;
s_dsp_bus.data_out_m1 <= data_in_m0;
s_dsp_bus.data_out_m2 <= data_in_m0;
elsif opflag_select(opflagbit_srcm1) = '1' then
s_dsp_bus.data_out_m0 <= data_in_m1;
s_dsp_bus.data_out_m1 <= data_in_m1;
s_dsp_bus.data_out_m2 <= data_in_m1;
elsif opflag_select(opflagbit_srcm2) = '1' then
s_dsp_bus.data_out_m0 <= data_in_m2;
s_dsp_bus.data_out_m1 <= data_in_m2;
s_dsp_bus.data_out_m2 <= data_in_m2;
end if;
end if;
end process p_data_select;
p_out_select : process (clk)
begin -- process p_out_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m0) = '1' then
s_dsp_bus.wr_en_m0 <= s_wr_en;
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m1) = '1' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= s_wr_en;
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m2) = '1' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= s_wr_en;
end if;
end if;
end process p_out_select;
p_adr_select : process (clk)
begin -- process p_adr_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.addr_r_m0 <= (others => '0');
s_dsp_bus.addr_w_m0 <= (others => '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.c_en_m0 <= '0';
s_dsp_bus.c_en_m1 <= '0';
s_dsp_bus.c_en_m2 <= '0';
else
s_dsp_bus.addr_w_m0 <= s_addr_real_w;
s_dsp_bus.addr_r_m0 <= s_addr_real_r;
if opflag_select(opflagbit_srcm1) = '1' then
s_dsp_bus.addr_m1 <= s_addr_real_r;
else
s_dsp_bus.addr_m1 <= s_addr_real_w;
end if;
if opflag_select(opflagbit_srcm2) = '1' then
s_dsp_bus.addr_m2 <= s_addr_real_r;
else
s_dsp_bus.addr_m2 <= s_addr_real_w;
end if;
s_dsp_bus.c_en_m0 <= opflag_select(opflagbit_srcm0) or opflag_select(opflagbit_m0);
s_dsp_bus.c_en_m1 <= opflag_select(opflagbit_srcm1) or opflag_select(opflagbit_m1);
s_dsp_bus.c_en_m2 <= opflag_select(opflagbit_srcm2) or opflag_select(opflagbit_m2);
end if;
end if;
end process p_adr_select;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
s_addr_real_w <= s_addr_w when opflag_select(opflagbit_tocomplex) = '0' else
s_addr_w((cmdreg_width - 2) downto 0) & '0';
s_addr_real_r <= s_addr_r when opflag_select(opflagbit_fromcomplex) = '0' else
s_addr_r((cmdreg_width - 2) downto 0) & '0';
end archi_cpmem;
| gpl-3.0 | fadf3d8a0755b201f5c19ebbef0e0b65 | 0.457461 | 3.43768 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/sim/system_vga_pll_0_0.vhd | 3 | 3,216 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_pll:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_pll_0_0 IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END system_vga_pll_0_0;
ARCHITECTURE system_vga_pll_0_0_arch OF system_vga_pll_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_pll_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_pll IS
PORT (
clk_100 : IN STD_LOGIC;
clk_50 : OUT STD_LOGIC;
clk_25 : OUT STD_LOGIC;
clk_12_5 : OUT STD_LOGIC;
clk_6_25 : OUT STD_LOGIC
);
END COMPONENT vga_pll;
BEGIN
U0 : vga_pll
PORT MAP (
clk_100 => clk_100,
clk_50 => clk_50,
clk_25 => clk_25,
clk_12_5 => clk_12_5,
clk_6_25 => clk_6_25
);
END system_vga_pll_0_0_arch;
| mit | 9079da7b29416e073d570e89dfa6cb55 | 0.718905 | 3.870036 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/cpu_types_pkg.vhdl | 1 | 3,219 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library isa;
use isa.or1k_pkg.all;
library util;
use util.types_pkg.all;
use work.cpu_or1knd_i5_pkg.all;
package cpu_types_pkg is
constant cpu_vaddr_bits : natural := or1k_vaddr_bits;
constant cpu_paddr_bits : natural := or1k_paddr_bits;
constant cpu_poffset_bits : natural := or1k_poffset_bits;
constant cpu_ppn_bits : natural := or1k_ppn_bits;
constant cpu_vpn_bits : natural := or1k_vpn_bits;
constant cpu_ivaddr_bits : natural := or1k_ivaddr_bits;
constant cpu_ipaddr_bits : natural := or1k_ipaddr_bits;
constant cpu_wvaddr_bits : natural := or1k_wvaddr_bits;
constant cpu_wpaddr_bits : natural := or1k_wpaddr_bits;
constant cpu_ipoffset_bits : natural := or1k_ipoffset_bits;
constant cpu_wpoffset_bits : natural := or1k_wpoffset_bits;
constant cpu_word_bits : natural := or1k_word_bits;
constant cpu_log2_word_bytes : natural := or1k_log2_word_bytes;
constant cpu_word_bytes : natural := or1k_word_bytes;
constant cpu_log2_inst_bytes : natural := or1k_log2_inst_bytes;
constant cpu_inst_bits : natural := or1k_inst_bits;
constant cpu_inst_endianness : endianness_type := or1k_inst_endianness;
subtype cpu_vaddr_type is or1k_vaddr_type;
subtype cpu_paddr_type is or1k_paddr_type;
subtype cpu_poffset_type is or1k_poffset_type;
subtype cpu_vpn_type is or1k_vpn_type;
subtype cpu_ppn_type is or1k_ppn_type;
subtype cpu_ivaddr_type is or1k_ivaddr_type;
subtype cpu_ipaddr_type is or1k_ipaddr_type;
subtype cpu_wvaddr_type is or1k_wvaddr_type;
subtype cpu_wpaddr_type is or1k_wpaddr_type;
subtype cpu_ipoffset_type is or1k_ipoffset_type;
subtype cpu_wpoffset_type is or1k_wpoffset_type;
subtype cpu_word_type is or1k_word_type;
subtype cpu_word_bytes_type is or1k_word_bytes_type;
subtype cpu_inst_type is or1k_inst_type;
subtype cpu_inst_bytes_type is or1k_inst_bytes_type;
constant cpu_data_size_bits : natural := cpu_or1knd_i5_data_size_bits;
subtype cpu_data_size_type is cpu_or1knd_i5_data_size_type;
end package;
| apache-2.0 | c6cbbb4b7a0d57b5136ac84b56e2e17c | 0.633116 | 3.514192 | false | false | false | false |
sbourdeauducq/dspunit | top/dspunit.vhd | 2 | 20,739 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dspunit is
port (
--@inputs
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
--@outputs;
-- memory 0
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
-- memory 1
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
-- memory 2
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
-- cmd registers
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end dspunit;
--=----------------------------------------------------------------------------
architecture archi_dspunit of dspunit is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_refresh_cmdreg_length : integer := 10;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspalu_acc
generic (
sig_width : integer;
acc_width : integer
);
port (
a1 : in std_logic_vector((sig_width - 1) downto 0);
b1 : in std_logic_vector((sig_width - 1) downto 0);
a2 : in std_logic_vector((sig_width - 1) downto 0);
b2 : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
clr_acc : in std_logic;
acc_mode1 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
acc_mode2 : in std_logic_vector((acc_mode_width - 1) downto 0); -- t_acc_mode;
alu_select : in std_logic_vector((alu_select_width - 1) downto 0); -- t_alu_select;
cmp_mode : in std_logic_vector((cmp_mode_width - 1) downto 0); -- t_cmp_mode;
cmp_pol : in std_logic;
cmp_store : in std_logic;
chain_acc : in std_logic;
result1 : out std_logic_vector((sig_width - 1) downto 0);
result_acc1 : out std_logic_vector((acc_width - 1) downto 0);
result2 : out std_logic_vector((sig_width - 1) downto 0);
result_acc2 : out std_logic_vector((acc_width - 1) downto 0);
cmp_reg : out std_logic_vector((acc_width - 1) downto 0);
cmp_greater : out std_logic;
cmp_out : out std_logic
);
end component;
component dsp_cmdregs
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
op_done : in std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
offset_0 : out unsigned((cmdreg_width - 1) downto 0);
offset_1 : out unsigned((cmdreg_width - 1) downto 0);
offset_2 : out unsigned((cmdreg_width - 1) downto 0);
length0 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length1 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length2 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : out std_logic_vector((opflag_width - 1) downto 0);
opcode_select : out std_logic_vector((opcode_width - 1) downto 0);
irq : out std_logic;
debug : out std_logic_vector(15 downto 0)
);
end component;
component cpflip
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component cpmem
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component fft
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
shift_flags_reg : in std_logic_vector((cmdreg_width - 1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector(sig_width downto 0);
result2 : in std_logic_vector(sig_width downto 0);
lut_out : in std_logic_vector((lut_out_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component dotcmul
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_width -1) downto 0);
length_kern_reg : in std_logic_vector((cmdreg_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((sig_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
component dsplut
port (
clk : in std_logic;
lut_in : in std_logic_vector((lut_in_width - 1) downto 0);
lut_select : in std_logic_vector((lut_sel_width - 1) downto 0);
lut_out : out std_logic_vector((lut_out_width - 1) downto 0)
);
end component;
component dotopnorm
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_params : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_result : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((2*sig_width - 1) downto 0);
cmp_greater : in std_logic;
dsp_bus : out t_dsp_bus
);
end component;
component dspdiv
generic (
sig_width : integer
);
port (
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end component;
component dotdiv
port (
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_result : in std_logic_vector((cmdreg_data_width -1) downto 0);
num_shift : in std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
div_q : in std_logic_vector((sig_width - 1) downto 0);
dsp_bus : out t_dsp_bus
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clr_acc : std_logic;
signal s_alu_result1 : std_logic_vector((sig_width - 1) downto 0);
signal s_alu_result_acc1 : std_logic_vector((acc_width - 1) downto 0);
signal s_alu_result2 : std_logic_vector((sig_width - 1) downto 0);
signal s_alu_result_acc2 : std_logic_vector((acc_width - 1) downto 0);
signal s_opflag_select : std_logic_vector((opflag_width - 1) downto 0);
signal s_opcode_select : std_logic_vector((opcode_width - 1) downto 0);
signal s_offset_0 : unsigned((cmdreg_width - 1) downto 0);
signal s_offset_1 : unsigned((cmdreg_width - 1) downto 0);
signal s_offset_2 : unsigned((cmdreg_width - 1) downto 0);
signal s_length0 : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_length1 : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_length2 : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_gcount : unsigned(15 downto 0);
signal s_dsp_bus : t_dsp_bus;
signal s_op_cpflip_en : std_logic;
signal s_dsp_bus_cpflip : t_dsp_bus;
signal s_op_cpmem_en : std_logic;
signal s_dsp_bus_cpmem : t_dsp_bus;
signal s_op_fft_en : std_logic;
signal s_op_dotcmul_en : std_logic;
signal s_dsp_bus_fft : t_dsp_bus;
signal s_dsp_bus_dotcmul : t_dsp_bus;
signal s_lut_out : std_logic_vector((lut_out_width - 1) downto 0);
signal s_alu_cmp_reg : std_logic_vector((acc_width - 1) downto 0);
signal s_alu_cmp_out : std_logic;
signal s_cmp_greater : std_logic;
signal s_dsp_bus_dotopnorm : t_dsp_bus;
signal s_op_dotopnorm_en : std_logic;
signal s_dsp_bus_dotdiv : t_dsp_bus;
signal s_op_dotdiv_en : std_logic;
signal s_chain_acc : std_logic;
signal s_div_q : std_logic_vector((sig_width - 1) downto 0);
signal s_div_r : std_logic_vector((2*sig_width - 3) downto 0);
begin -- archs_dspunit
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspalu_acc_1 : dspalu_acc
generic map (
sig_width => sig_width,
acc_width => acc_width)
port map (
a1 => s_dsp_bus.mul_in_a1,
b1 => s_dsp_bus.mul_in_b1,
a2 => s_dsp_bus.mul_in_a2,
b2 => s_dsp_bus.mul_in_b2,
clk => clk,
clr_acc => s_clr_acc,
acc_mode1 => s_dsp_bus.acc_mode1,
acc_mode2 => s_dsp_bus.acc_mode2,
alu_select => s_dsp_bus.alu_select,
cmp_mode => s_dsp_bus.cmp_mode,
cmp_pol => s_dsp_bus.cmp_pol,
cmp_store => s_dsp_bus.cmp_store,
chain_acc => s_chain_acc,
result1 => s_alu_result1,
result_acc1 => s_alu_result_acc1,
result2 => s_alu_result2,
result_acc2 => s_alu_result_acc2,
cmp_reg => s_alu_cmp_reg,
cmp_greater => s_cmp_greater,
cmp_out => s_alu_cmp_out);
dsp_cmdregs_1 : dsp_cmdregs
port map (
clk => clk,
clk_cpu => clk_cpu,
reset => reset,
op_done => s_dsp_bus.op_done,
addr_cmdreg => addr_cmdreg,
data_in_cmdreg => data_in_cmdreg,
wr_en_cmdreg => wr_en_cmdreg,
data_out_cmdreg => data_out_cmdreg,
offset_0 => s_offset_0,
offset_1 => s_offset_1,
offset_2 => s_offset_2,
length0 => s_length0,
length1 => s_length1,
length2 => s_length2,
opflag_select => s_opflag_select,
opcode_select => s_opcode_select,
irq => irq,
debug => open);
dsplut_1 : dsplut
port map (
clk => clk,
lut_in => s_dsp_bus.lut_in,
lut_select => s_dsp_bus.lut_select,
lut_out => s_lut_out);
cpflip_1 : cpflip
port map (
clk => clk,
op_en => s_op_cpflip_en,
data_in_m2 => data_in_m2,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
dsp_bus => s_dsp_bus_cpflip);
cpmem_1 : cpmem
port map (
clk => clk,
op_en => s_op_cpmem_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
data_in_m2 => data_in_m2,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
opflag_select => s_opflag_select,
dsp_bus => s_dsp_bus_cpmem);
fft_1 : fft
port map (
clk => clk,
op_en => s_op_fft_en,
data_in_m0 => data_in_m0,
data_in_m2 => data_in_m2,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
shift_flags_reg => s_length1, --s_dsp_cmdregs(DSPADDR_LENGTH1),
opflag_select => s_opflag_select,
result1 => s_alu_result_acc1((2*sig_width - 1) downto (sig_width - 1)),
result2 => s_alu_result_acc2((2*sig_width - 1) downto (sig_width - 1)),
lut_out => s_lut_out,
dsp_bus => s_dsp_bus_fft);
dotcmul_1 : dotcmul
port map (
clk => clk,
op_en => s_op_dotcmul_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
length_reg => s_length0, --s_dsp_cmdregs(DSPADDR_LENGTH0),
length_kern_reg => s_length1, --s_dsp_cmdregs(DSPADDR_LENGTH1),
opflag_select => s_opflag_select,
result1 => s_alu_result_acc1((2*sig_width - 1) downto sig_width),
result2 => s_alu_result_acc2((2*sig_width - 1) downto sig_width),
dsp_bus => s_dsp_bus_dotcmul);
dotopnorm_1 : dotopnorm
port map (
clk => clk,
op_en => s_op_dotopnorm_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
data_in_m2 => data_in_m2,
length_reg => s_length0,
offset_params => s_length1,
offset_result => s_length2,
opflag_select => s_opflag_select,
result1 => s_alu_result_acc1((2*sig_width - 2) downto (sig_width - 1)),
result2 => s_alu_result_acc2((acc_width - 1) downto (acc_width - 2*sig_width)),
cmp_greater => s_cmp_greater,
dsp_bus => s_dsp_bus_dotopnorm);
dspdiv_1 : dspdiv
generic map (
sig_width => sig_width)
port map (
num => s_dsp_bus.div_num,
den => s_dsp_bus.div_den,
clk => clk,
q => s_div_q,
r => s_div_r);
dotdiv_1 : dotdiv
port map (
clk => clk,
op_en => s_op_dotdiv_en,
data_in_m0 => data_in_m0,
data_in_m1 => data_in_m1,
data_in_m2 => data_in_m2,
length_reg => s_length0,
offset_result => s_length1,
num_shift => s_length2,
opflag_select => s_opflag_select,
div_q => s_div_q,
dsp_bus => s_dsp_bus_dotdiv);
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Global counter
-------------------------------------------------------------------------------
p_count : process (clk)
begin -- process p_count
if rising_edge(clk) then -- rising clock edge
if s_dsp_bus.gcounter_reset = '1' then
s_gcount <= (others => '0');
else
s_gcount <= s_gcount + 1;
end if;
end if;
end process p_count;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- reading of config registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- multiplexer of the dsp unit bus
-------------------------------------------------------------------------------
s_op_cpflip_en <= '1' when s_opcode_select = opcode_cpflip else '0';
s_op_cpmem_en <= '1' when s_opcode_select = opcode_cpmem else '0';
s_op_fft_en <= '1' when s_opcode_select = opcode_fft else '0';
s_op_dotcmul_en <= '1' when s_opcode_select = opcode_dotcmul else '0';
s_op_dotopnorm_en <= '1' when s_opcode_select = opcode_dotopnorm else '0';
s_op_dotdiv_en <= '1' when s_opcode_select = opcode_dotdiv else '0';
s_dsp_bus <=
s_dsp_bus_cpflip when s_opcode_select = opcode_cpflip else
s_dsp_bus_cpmem when s_opcode_select = opcode_cpmem else
s_dsp_bus_fft when s_opcode_select = opcode_fft else
s_dsp_bus_dotcmul when s_opcode_select = opcode_dotcmul else
s_dsp_bus_dotopnorm when s_opcode_select = opcode_dotopnorm else
s_dsp_bus_dotdiv when s_opcode_select = opcode_dotdiv else
c_dsp_bus_init;
-------------------------------------------------------------------------------
-- bus to output ports
-------------------------------------------------------------------------------
-- memory 0
data_out_m0 <= s_dsp_bus.data_out_m0;
addr_r_m0 <= std_logic_vector(s_dsp_bus.addr_r_m0 + s_offset_0);
addr_w_m0 <= std_logic_vector(s_dsp_bus.addr_w_m0 + s_offset_0);
wr_en_m0 <= s_dsp_bus.wr_en_m0;
c_en_m0 <= s_dsp_bus.c_en_m0;
-- memory 1
data_out_m1 <= s_dsp_bus.data_out_m1;
addr_m1 <= std_logic_vector(s_dsp_bus.addr_m1 + s_offset_1);
wr_en_m1 <= s_dsp_bus.wr_en_m1;
c_en_m1 <= s_dsp_bus.c_en_m1;
-- memory 2
data_out_m2 <= s_dsp_bus.data_out_m2;
addr_m2 <= std_logic_vector(s_dsp_bus.addr_m2 + s_offset_2);
wr_en_m2 <= s_dsp_bus.wr_en_m2;
c_en_m2 <= s_dsp_bus.c_en_m2;
op_done <= s_dsp_bus.op_done;
s_clr_acc <= not reset;
end archi_dspunit;
-------------------------------------------------------------------------------
| gpl-3.0 | 5c7d20fb1bc3eb25c36a954f5d805607 | 0.504364 | 3.276303 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/hdl/reg_file_bram_double_buffered.vhd | 2 | 10,020 | -------------------------------------------------------------------------------
-- Title : reg_file_bram_double_buffered.vhd
-- Project :
-------------------------------------------------------------------------------
-- File : reg_file_bram_double_buffered.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-22
-- Platform : Xilinx Spartan 3A
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A Larger Register File Using Block RAM.
--
-- A dual port block RAM is interfaced to the internal parallel
-- bus and double buffering is implemented. Double buffering
-- guarantees that the data read by the SPI slave is not
-- comprimised while new data is written to the block RAM by the
-- other component.
-- If no double buffering was implemented new and old data may get
-- mixed up.
--
-- This register file was designed for the Goertzel algorithm.
-- It was implemented with a calc width of 18 bits (because the
-- mulipliers are 18 bits wide). The result and the intermediate
-- data are two words of 18 bits so a data width of 36 bits was
-- chosen. This fits perfectly well to the Block RAM.
--
-- Each SelectRAM in Spartan-3(A/E/AN) has 18432 data bits and can
-- be configured as 512 address x 36 data bits.
--
-- Double buffering is implemented by toggeling the MSB of the
-- address.
--
-- Port A: parallel bus:
-- 2 x 512 addresses of 18 bits, lower two data bits are discarded
-- 512 address = 9 bits (8 downto 0)
--
-- Port B: Goertzel Algorithm:
-- 2 x 256 addresses of 36 bits
-- 256 addresses = 8 bits (7 downto 0)
--
-------------------------------------------------------------------------------
-- Todo: * Generic widths
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.xilinx_block_ram_pkg.all;
use work.utils_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram_double_buffered is
generic (
-- The module uses 9 bits for 512 addresses and the base address must be aligned.
-- Valid BASE_ADDRESSes are 0x0000, 0x0200, 0x0400, 0x0600, ...
BASE_ADDRESS : integer range 0 to 2**15-1);
port (
-- Interface to the internal parallel bus.
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- Read and write interface to the block RAM for the application.
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_addr_i : in std_logic_vector(7 downto 0);
bram_we_p : in std_logic;
-- Inform the STM that new results are ready to be fetched.
irq_o : out std_logic;
-- Get an acknowledge from the STM that all results are fetched.
ack_i : in std_logic;
-- Get informed by the application that it has written a new set of results
-- to the block RAM.
ready_i : in std_logic;
-- Allow the application to write new data to the block RAM.
enable_o : out std_logic;
-- Show to which bank the application writes at the moment
bank_x_o : out std_logic; -- The bank that is currently mapped to
-- the bus.
bank_y_o : out std_logic; -- The bank that is currently mapped to
-- the application.
-- No reset, all signals are initialised.
clk : in std_logic);
end reg_file_bram_double_buffered;
-------------------------------------------------------------------------------
architecture str of reg_file_bram_double_buffered is
----------------------------------------------------------------------------
-- Configuration
----------------------------------------------------------------------------
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
-- Port A to bus
constant ADDR_A_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 18;
-- Port B to application
constant ADDR_B_WIDTH : positive := 9;
constant DATA_B_WIDTH : positive := 36;
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type ram_a_in_type is record
addr : std_logic_vector(ADDR_A_WIDTH-1 downto 0);
data : std_logic_vector(DATA_A_WIDTH-1 downto 0);
we : std_logic;
en : std_logic;
ssr : std_logic;
end record;
type ram_a_out_type is record
data : std_logic_vector(DATA_A_WIDTH-1 downto 0);
end record;
type ram_b_in_type is record
addr : std_logic_vector(ADDR_B_WIDTH-1 downto 0);
data : std_logic_vector(DATA_B_WIDTH-1 downto 0);
we : std_logic;
en : std_logic;
ssr : std_logic;
end record;
type ram_b_out_type is record
data : std_logic_vector(DATA_B_WIDTH-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal ram_a_in : ram_a_in_type;
signal ram_a_out : ram_a_out_type;
signal ram_b_in : ram_b_in_type;
signal ram_b_out : ram_b_out_type;
signal data_bus_out : std_logic_vector(15 downto 0) := (others => '0');
signal bank : std_logic := '0';
signal bank_x : std_logic;
signal bank_y : std_logic;
signal addr_match_a : std_logic;
begin -- str
----------------------------------------------------------------------------
-- Connections
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Bank switching
-- Call the banks X and Y to not confuse with Port A and B of the Dual port
-- RAM.
--
-- Signals:
-- ----------------
-- irq_p to bus
-- ack_p form bus
-- ready_p from app
-- enable_p to app
--
---------------------------------------------------------------------------
bank_x <= bank;
bank_y <= not bank;
-- Output the current bank information for use by other double buffering registers.
bank_x_o <= bank_x;
bank_y_o <= bank_y;
double_buffering_1 : entity work.double_buffering
port map (
ready_p => ready_i,
enable_p => enable_o,
irq_p => irq_o,
ack_p => ack_i,
bank_p => bank,
clk => clk);
----------------------------------------------------------------------------
-- Block RAM as dual port RAM with asymmetrical port widths.
----------------------------------------------------------------------------
dp_1 : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => ram_a_in.addr,
addr_b => ram_b_in.addr,
din_a => ram_a_in.data,
din_b => ram_b_in.data,
dout_a => ram_a_out.data,
dout_b => ram_b_out.data,
we_a => ram_a_in.we,
we_b => ram_b_in.we,
en_a => ram_a_in.en,
en_b => ram_b_in.en,
ssr_a => ram_a_in.ssr,
ssr_b => ram_b_in.ssr,
clk_a => clk,
clk_b => clk);
----------------------------------------------------------------------------
-- Port B
----------------------------------------------------------------------------
-- Transfer data to and from the application to and from the RAM
-- Do the bank switching here.
-- 9 = 1 + 8
ram_b_in.addr <= bank_y & bram_addr_i;
ram_b_in.data <= bram_data_i;
ram_b_in.en <= '1';
ram_b_in.we <= bram_we_p;
ram_b_in.ssr <= '0';
bram_data_o <= ram_b_out.data;
-----------------------------------------------------------------------------
-- Port A: parallel data bus
----------------------------------------------------------------------------
-- enable
ram_a_in.en <= '1';
-- Always present the address from the parallel bus to the block RAM.
-- When the bus address matches the address range of the block RAM
-- route the result of the Block RAM to the parallel bus.
-- Do the bank switching here.
-----------------------------------------------------------------------------
-- 10 = 1 + 9
ram_a_in.addr <= bank_x & bus_i.addr(8 downto 0);
ram_a_in.data <= "00" & bus_i.data;
addr_match_a <= '1' when (bus_i.addr(14 downto 9) = BASE_ADDRESS_VECTOR(14 downto 9)) else '0';
-- The block RAM keeps its output latches when EN is '0'. This behaviour is
-- not compatible with the parallel bus where the bus output must be 0 when
-- the device is not selected.
-- Solution: Use Synchronous Reset of the output latches:
ram_a_in.ssr <= '0' when (addr_match_a = '1') and (bus_i.re = '1') else '1';
-- Write enable
ram_a_in.we <= '1' when (addr_match_a = '1') and (bus_i.we = '1') else '0';
-- upper 16 bits of RAM (most significant bits of Q13 number)
bus_o.data <= ram_a_out.data(17 downto 2);
end str;
-------------------------------------------------------------------------------
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`protect end_protected
| mit | 1cf8942f8cc76b1eb9982ff65cf3a6a7 | 0.951741 | 1.815853 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_axi_dma_0_0/sim/system_axi_dma_0_0.vhd | 1 | 30,349 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_12;
USE axi_dma_v7_1_12.axi_dma;
ENTITY system_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_axi_dma_0_0;
ARCHITECTURE system_axi_dma_0_0_arch OF system_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END system_axi_dma_0_0_arch;
| mit | f6bd99726f4ce1c79cb7ca91e6be2baa | 0.678704 | 2.783801 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_1_0/synth/system_vga_gaussian_blur_1_0.vhd | 1 | 4,598 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
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-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_1_0 IS
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_1_0;
ARCHITECTURE system_vga_gaussian_blur_1_0_arch OF system_vga_gaussian_blur_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_1_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_1_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_1_0,vga_gaussian_blur,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
clk_25 => clk_25,
hsync_in => hsync_in,
vsync_in => vsync_in,
rgb_in => rgb_in,
hsync_out => hsync_out,
vsync_out => vsync_out,
rgb_blur => rgb_blur,
rgb_pass => rgb_pass
);
END system_vga_gaussian_blur_1_0_arch;
| mit | 33f479a605bf4e7e11e330f8be0b0482 | 0.714441 | 3.550579 | false | false | false | false |
sbourdeauducq/dspunit | sim/clock_gen.vhd | 2 | 3,063 | --------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: clock_gen.vhdl,v $ $Revision: 2.1 $ Date: 1993/10/31 20:20:50 $
--
--------------------------------------------------------------------------
--
-- Entity declaration for clock generator
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_gen is
generic (
Tpw : Time;
Tps : Time);
port (
--@inputs
--@outputs;
clk : out std_logic;
reset : out std_logic
);
end clock_gen;
--=----------------------------------------------------------------------------
architecture archi_clock_gen of clock_gen is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant clock_period : Time := 2*(Tpw+Tps);
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
begin -- archs_clock_gen
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_gen_clk : process
begin -- process p_gen_clk
clk <= '1', '0' after Tpw;
wait for clock_period;
end process p_gen_clk;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
reset_driver:
reset <= '0', '1' after 10*clock_period + Tpw+Tps;
end archi_clock_gen;
-------------------------------------------------------------------------------
| gpl-3.0 | b9e1c9aa249a9faafa2ef03ce135ad78 | 0.38459 | 5.518919 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/cpu_or1knd_i5_pipe_dp-rtl.vhdl | 1 | 64,192 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.numeric_pkg.all;
use util.types_pkg.all;
-- pragma translate_off
use util.names_pkg.all;
-- pragma translate_on
library isa;
use isa.or1k_pkg.all;
-- pragma translate_off
library sim;
use sim.monitor_pkg.all;
-- pragma translate_on
use work.cpu_or1knd_i5_pkg.all;
use work.cpu_or1knd_i5_config_pkg.all;
use work.cpu_or1knd_i5_pipe_pkg.all;
use work.cpu_bpb_pkg.all;
use work.cpu_btb_pkg.all;
architecture rtl of cpu_or1knd_i5_pipe_dp is
type spr_type is record
sys_eear0 : or1k_vaddr_type;
sys_epcr0 : or1k_ivaddr_type;
mac_maclo : or1k_spr_data_type;
mac_machi : or1k_spr_data_type;
end record;
constant spr_init : spr_type := (
sys_eear0 => (others => '0'),
sys_epcr0 => (others => '0'),
mac_maclo => (others => '0'),
mac_machi => (others => '0')
);
type reg_f_type is record
pc : or1k_ivaddr_type;
end record;
type reg_d_type is record
pc : or1k_ivaddr_type;
pc_incr : or1k_ivaddr_type;
inst_bus_error_eear : or1k_ipaddr_type;
inst : or1k_inst_type;
bpb_state : cpu_bpb_state_type;
btb_state : cpu_btb_state_type;
btb_target : or1k_ivaddr_type;
end record;
constant reg_d_x : reg_d_type := (
pc => (others => 'X'),
pc_incr => (others => 'X'),
inst_bus_error_eear => (others => 'X'),
inst => (others => 'X'),
bpb_state => (others => 'X'),
btb_state => (others => 'X'),
btb_target => (others => 'X')
);
type reg_e_type is record
pc : or1k_ivaddr_type;
pc_incr : or1k_ivaddr_type;
inst_bus_error_eear : or1k_ipaddr_type;
inst : or1k_inst_type;
bpb_state : cpu_bpb_state_type;
btb_state : cpu_btb_state_type;
btb_target : or1k_ivaddr_type;
ra : or1k_rfaddr_type;
rb : or1k_rfaddr_type;
rd : or1k_rfaddr_type;
alu_src1 : or1k_word_type;
alu_src2 : or1k_word_type;
st_data : or1k_word_type;
end record;
constant reg_e_x : reg_e_type := (
pc => (others => 'X'),
pc_incr => (others => 'X'),
inst_bus_error_eear => (others => 'X'),
inst => (others => 'X'),
bpb_state => (others => 'X'),
btb_state => (others => 'X'),
btb_target => (others => 'X'),
ra => (others => 'X'),
rb => (others => 'X'),
rd => (others => 'X'),
alu_src1 => (others => 'X'),
alu_src2 => (others => 'X'),
st_data => (others => 'X')
);
type reg_m_type is record
pc : or1k_ivaddr_type;
pc_incr : or1k_ivaddr_type;
inst_bus_error_eear : or1k_ipaddr_type;
inst : or1k_inst_type;
ra : or1k_rfaddr_type;
rb : or1k_rfaddr_type;
rd : or1k_rfaddr_type;
addr : or1k_vaddr_type;
alu_result : or1k_word_type;
mtspr_data : or1k_spr_data_type;
end record;
constant reg_m_x : reg_m_type := (
pc => (others => 'X'),
pc_incr => (others => 'X'),
inst_bus_error_eear => (others => 'X'),
inst => (others => 'X'),
ra => (others => 'X'),
rb => (others => 'X'),
rd => (others => 'X'),
addr => (others => 'X'),
alu_result => (others => 'X'),
mtspr_data => (others => 'X')
);
type reg_w_type is record
rd_data : or1k_word_type;
end record;
constant reg_w_x : reg_w_type := (
rd_data => (others => 'X')
);
type reg_p_type is record
spr : spr_type;
f_btb_target_buffer : or1k_ivaddr_type;
f_inst_buffer : or1k_inst_type;
f_btb_state_buffer : cpu_btb_state_type;
f_bpb_state_buffer : cpu_bpb_state_type;
f_inst_bus_error_eear_buffer : or1k_ipaddr_type;
m_load_buffer : or1k_word_type;
m_data_bus_error_eear_buffer : or1k_paddr_type;
end record;
constant reg_p_init : reg_p_type := (
spr => (
sys_eear0 => (others => '0'),
sys_epcr0 => (others => '0'),
mac_maclo => (others => 'X'),
mac_machi => (others => 'X')
),
f_btb_target_buffer => (others => 'X'),
f_inst_buffer => (others => 'X'),
f_btb_state_buffer => (others => 'X'),
f_bpb_state_buffer => (others => 'X'),
f_inst_bus_error_eear_buffer => (others => 'X'),
m_load_buffer => (others => 'X'),
m_data_bus_error_eear_buffer => (others => 'X')
);
type reg_type is record
f : reg_f_type;
d : reg_d_type;
e : reg_e_type;
m : reg_m_type;
w : reg_w_type;
p : reg_p_type;
end record;
type comb_type is record
bf_pc : or1k_ivaddr_type;
f_pc_incr : or1k_ivaddr_type;
f_btb_target : or1k_ivaddr_type;
f_btb_state : cpu_btb_state_type;
f_bpb_state : cpu_bpb_state_type;
f_inst : or1k_inst_type;
f_ra : or1k_rfaddr_type;
f_rb : or1k_rfaddr_type;
f_inst_bus_error_eear : or1k_ipaddr_type;
d_ra : or1k_rfaddr_type;
d_rb : or1k_rfaddr_type;
d_rd : or1k_rfaddr_type;
d_ra_data : or1k_word_type;
d_rb_data : or1k_word_type;
d_depends_ra_e : std_ulogic;
d_depends_rb_e : std_ulogic;
d_depends_ra_m : std_ulogic;
d_depends_rb_m : std_ulogic;
d_imm_contig : or1k_imm_type;
d_imm_split : or1k_imm_type;
d_imm_toc_offset : or1k_toc_offset_type;
d_imm : or1k_word_type;
d_alu_src1 : or1k_word_type;
d_alu_src2 : or1k_word_type;
d_st_data : or1k_word_type;
e_alu_src1 : or1k_word_type;
e_alu_src2 : or1k_word_type;
e_cmov_result : or1k_word_type;
e_ff1_result : or1k_word_type;
e_fl1_result : or1k_word_type;
e_ext_result : or1k_word_type;
e_alu_result : or1k_word_type;
e_ldst_size : cpu_or1knd_i5_data_size_type;
e_ldst_addr : or1k_vaddr_type;
e_ldst_misaligned : std_ulogic;
e_madd_acc : or1k_dword_type;
e_st_data : or1k_word_type;
e_not_equal : std_ulogic;
e_lt_tmp : std_ulogic;
e_lts : std_ulogic;
e_ltu : std_ulogic;
e_direct_toc_target : or1k_ivaddr_type;
e_indir_toc_target : or1k_ivaddr_type;
e_toc_target : or1k_ivaddr_type;
e_toc_target_misaligned : std_ulogic;
e_btb_mispred : std_ulogic;
e_mtspr_data : or1k_spr_data_type;
e_addr : or1k_vaddr_type;
e_spr_addr : or1k_word_type;
e_spr_group : or1k_spr_group_type;
e_spr_index : or1k_spr_index_type;
e_spr_group_sys : std_ulogic;
e_spr_group_dmmu : std_ulogic;
e_spr_group_immu : std_ulogic;
e_spr_group_dcache : std_ulogic;
e_spr_group_icache : std_ulogic;
e_spr_group_mac : std_ulogic;
e_spr_index_sys_vr : std_ulogic;
e_spr_index_sys_upr : std_ulogic;
e_spr_index_sys_cpucfgr : std_ulogic;
e_spr_index_sys_dmmucfgr : std_ulogic;
e_spr_index_sys_immucfgr : std_ulogic;
e_spr_index_sys_dccfgr : std_ulogic;
e_spr_index_sys_iccfgr : std_ulogic;
e_spr_index_sys_dcfgr : std_ulogic;
e_spr_index_sys_pccfgr : std_ulogic;
e_spr_index_sys_npc : std_ulogic;
e_spr_index_sys_aecr : std_ulogic;
e_spr_index_sys_aesr : std_ulogic;
e_spr_index_sys_sr : std_ulogic;
e_spr_index_sys_ppc : std_ulogic;
e_spr_index_sys_fpcsr : std_ulogic;
e_spr_index_sys_epcr0 : std_ulogic;
e_spr_index_sys_eear0 : std_ulogic;
e_spr_index_sys_esr0 : std_ulogic;
e_spr_index_sys_gpr : std_ulogic;
e_spr_index_dmmu_dmmucr : std_ulogic;
e_spr_index_dmmu_dmmupr : std_ulogic;
e_spr_index_dmmu_dtlbeir : std_ulogic;
e_spr_index_dmmu_datbmr : std_ulogic;
e_spr_index_dmmu_datbtr : std_ulogic;
e_spr_index_dmmu_dtlbwmr_way : std_ulogic_vector(or1k_tlb_ways-1 downto 0);
e_spr_index_dmmu_dtlbwtr_way : std_ulogic_vector(or1k_tlb_ways-1 downto 0);
e_spr_index_dmmu_dtlbwmr : std_ulogic;
e_spr_index_dmmu_dtlbwtr : std_ulogic;
e_spr_index_immu_immucr : std_ulogic;
e_spr_index_immu_immupr : std_ulogic;
e_spr_index_immu_itlbeir : std_ulogic;
e_spr_index_immu_iatbmr : std_ulogic;
e_spr_index_immu_iatbtr : std_ulogic;
e_spr_index_immu_itlbwmr_way : std_ulogic_vector(or1k_tlb_ways-1 downto 0);
e_spr_index_immu_itlbwtr_way : std_ulogic_vector(or1k_tlb_ways-1 downto 0);
e_spr_index_immu_itlbwmr : std_ulogic;
e_spr_index_immu_itlbwtr : std_ulogic;
e_spr_index_dcache_dcbfr : std_ulogic;
e_spr_index_dcache_dcbir : std_ulogic;
e_spr_index_dcache_dcbwr : std_ulogic;
e_spr_index_icache_icbir : std_ulogic;
e_spr_index_mac_maclo : std_ulogic;
e_spr_index_mac_machi : std_ulogic;
e_spr_atb_index : or1k_atb_index_type;
e_spr_tlb_way : or1k_tlb_way_type;
e_spr_addr_sel : cpu_or1knd_i5_spr_addr_sel_type;
e_spr_addr_valid : std_ulogic;
m_load_data : or1k_word_type;
m_load_data_prebuffer : or1k_word_type;
m_data_bus_error_eear : or1k_paddr_type;
m_rd_data : or1k_word_type;
m_spr_sys_eear0 : or1k_vaddr_type;
m_spr_sys_epcr0 : or1k_ivaddr_type;
m_spr_mac_maclo : or1k_spr_data_type;
m_spr_mac_machi : or1k_spr_data_type;
m_madd_result_hi_zeros : std_ulogic;
m_madd_result_hi_ones : std_ulogic;
m_mul_result_msb : std_ulogic;
m_mfspr_data : or1k_spr_data_type;
m_exception : or1k_exception_type;
m_exception_pc : or1k_ivaddr_type;
regfile_raddr1 : or1k_rfaddr_type;
regfile_raddr2 : or1k_rfaddr_type;
regfile_waddr : or1k_rfaddr_type;
regfile_wdata : or1k_word_type;
l1mem_inst_vaddr : or1k_ivaddr_type;
l1mem_data_vaddr : or1k_vaddr_type;
l1mem_data_size : cpu_or1knd_i5_data_size_type;
end record;
signal r, r_next : reg_type;
signal c : comb_type;
pure function ff1(v : or1k_word_type) return or1k_word_type is
variable ret : or1k_word_type;
begin
ret := std_ulogic_vector(to_unsigned(0, or1k_word_bits));
for n in 0 to or1k_word_bits-1 loop
case v(n) is
when '0' =>
when '1' =>
ret := std_ulogic_vector(to_unsigned(n+1, or1k_word_bits));
exit;
when others =>
ret := (others => 'X');
exit;
end case;
end loop;
return ret;
end function;
pure function fl1(v : or1k_word_type) return or1k_word_type is
variable ret : or1k_word_type;
begin
ret := std_ulogic_vector(to_unsigned(0, or1k_word_bits));
for n in or1k_word_bits-1 downto 0 loop
case v(n) is
when '0' =>
when '1' =>
ret := std_ulogic_vector(to_unsigned(n+1, or1k_word_bits));
exit;
when others =>
ret := (others => 'X');
exit;
end case;
end loop;
return ret;
end function;
begin
------------------
-- memory stage --
------------------
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_exception_sel select
c.m_exception <= or1k_exception_reset when cpu_or1knd_i5_m_exception_sel_reset,
or1k_exception_bus when cpu_or1knd_i5_m_exception_sel_bus,
or1k_exception_dpf when cpu_or1knd_i5_m_exception_sel_dpf,
or1k_exception_ipf when cpu_or1knd_i5_m_exception_sel_ipf,
or1k_exception_tti when cpu_or1knd_i5_m_exception_sel_tti,
or1k_exception_align when cpu_or1knd_i5_m_exception_sel_align,
or1k_exception_ill when cpu_or1knd_i5_m_exception_sel_ill,
or1k_exception_ext when cpu_or1knd_i5_m_exception_sel_ext,
or1k_exception_dtlbmiss when cpu_or1knd_i5_m_exception_sel_dtlbmiss,
or1k_exception_itlbmiss when cpu_or1knd_i5_m_exception_sel_itlbmiss,
or1k_exception_range when cpu_or1knd_i5_m_exception_sel_range,
or1k_exception_syscall when cpu_or1knd_i5_m_exception_sel_syscall,
or1k_exception_fp when cpu_or1knd_i5_m_exception_sel_fp,
or1k_exception_trap when cpu_or1knd_i5_m_exception_sel_trap,
(others => 'X') when others;
c.m_exception_pc <= ((29 => cpu_or1knd_i5_pipe_dp_in_ctrl.p_spr_sys_sr_eph,
28 downto 10 => '0'
) &
c.m_exception &
(5 downto 0 => '0')
);
m_mfspr_data_madd_enable_gen : if cpu_or1knd_i5_madd_enable generate
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_mfspr_data_sel select
c.m_mfspr_data <= cpu_or1knd_i5_pipe_dp_in_ctrl.m_mfspr_data when cpu_or1knd_i5_m_mfspr_data_sel_ctrl,
cpu_or1knd_i5_spr_sys_vr when cpu_or1knd_i5_m_mfspr_data_sel_sys_vr,
cpu_or1knd_i5_spr_sys_upr when cpu_or1knd_i5_m_mfspr_data_sel_sys_upr,
cpu_or1knd_i5_spr_sys_cpucfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_cpucfgr,
cpu_or1knd_i5_spr_sys_dmmucfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_dmmucfgr,
cpu_or1knd_i5_spr_sys_immucfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_immucfgr,
cpu_or1knd_i5_spr_sys_dccfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_dccfgr,
cpu_or1knd_i5_spr_sys_iccfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_iccfgr,
r.p.spr.sys_eear0 when cpu_or1knd_i5_m_mfspr_data_sel_sys_eear0,
r.p.spr.sys_epcr0 & (or1k_log2_inst_bytes-1 downto 0 => '0') when cpu_or1knd_i5_m_mfspr_data_sel_sys_epcr0,
cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata1 when cpu_or1knd_i5_m_mfspr_data_sel_sys_gpr,
r.p.spr.mac_maclo when cpu_or1knd_i5_m_mfspr_data_sel_mac_maclo,
r.p.spr.mac_machi when cpu_or1knd_i5_m_mfspr_data_sel_mac_machi,
(others => 'X') when others;
end generate;
m_mfspr_data_madd_disable_gen : if not cpu_or1knd_i5_madd_enable generate
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_mfspr_data_sel select
c.m_mfspr_data <= cpu_or1knd_i5_pipe_dp_in_ctrl.m_mfspr_data when cpu_or1knd_i5_m_mfspr_data_sel_ctrl,
cpu_or1knd_i5_spr_sys_vr when cpu_or1knd_i5_m_mfspr_data_sel_sys_vr,
cpu_or1knd_i5_spr_sys_upr when cpu_or1knd_i5_m_mfspr_data_sel_sys_upr,
cpu_or1knd_i5_spr_sys_cpucfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_cpucfgr,
cpu_or1knd_i5_spr_sys_dmmucfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_dmmucfgr,
cpu_or1knd_i5_spr_sys_immucfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_immucfgr,
cpu_or1knd_i5_spr_sys_dccfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_dccfgr,
cpu_or1knd_i5_spr_sys_iccfgr when cpu_or1knd_i5_m_mfspr_data_sel_sys_iccfgr,
r.p.spr.sys_eear0 when cpu_or1knd_i5_m_mfspr_data_sel_sys_eear0,
r.p.spr.sys_epcr0 & (or1k_log2_inst_bytes-1 downto 0 => '0') when cpu_or1knd_i5_m_mfspr_data_sel_sys_epcr0,
cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata1 when cpu_or1knd_i5_m_mfspr_data_sel_sys_gpr,
(others => 'X') when others;
end generate;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_data_size_sel select
c.m_load_data_prebuffer <= ((31 downto 8 => cpu_l1mem_data_dp_out.data(7) and cpu_or1knd_i5_pipe_dp_in_ctrl.m_sext) &
cpu_l1mem_data_dp_out.data(7 downto 0)
) when cpu_or1knd_i5_data_size_sel_byte,
((31 downto 16 => cpu_l1mem_data_dp_out.data(15) and cpu_or1knd_i5_pipe_dp_in_ctrl.m_sext) &
cpu_l1mem_data_dp_out.data(15 downto 0)
) when cpu_or1knd_i5_data_size_sel_half,
cpu_l1mem_data_dp_out.data when cpu_or1knd_i5_data_size_sel_word,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_load_data_buffered select
c.m_load_data <= c.m_load_data_prebuffer when '0',
r.p.m_load_buffer when '1',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_load_data_buffered select
c.m_data_bus_error_eear <= cpu_l1mem_data_dp_out.paddr when '0',
r.p.m_data_bus_error_eear_buffer when '1',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_rd_data_sel select
c.m_rd_data <= r.m.alu_result when cpu_or1knd_i5_rd_data_sel_alu,
c.m_load_data when cpu_or1knd_i5_rd_data_sel_load,
c.m_mfspr_data when cpu_or1knd_i5_rd_data_sel_mfspr,
cpu_or1knd_i5_pipe_dp_in_misc.m_mul_result when cpu_or1knd_i5_rd_data_sel_mul,
cpu_or1knd_i5_pipe_dp_in_misc.m_div_result when cpu_or1knd_i5_rd_data_sel_div,
r.m.pc_incr & (or1k_log2_inst_bytes-1 downto 0 => '0') when cpu_or1knd_i5_rd_data_sel_pc_incr,
r.p.spr.mac_maclo when cpu_or1knd_i5_rd_data_sel_maclo,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_sys_eear0_sel select
c.m_spr_sys_eear0 <= (others => '0') when cpu_or1knd_i5_m_spr_sys_eear0_sel_init,
r.m.mtspr_data when cpu_or1knd_i5_m_spr_sys_eear0_sel_mtspr,
r.m.pc & (or1k_log2_inst_bytes-1 downto 0 => '0') when cpu_or1knd_i5_m_spr_sys_eear0_sel_pc,
r.m.addr when cpu_or1knd_i5_m_spr_sys_eear0_sel_addr,
(c.f_inst_bus_error_eear(or1k_spr_data_bits-or1k_log2_inst_bytes-1 downto 0) &
(or1k_log2_inst_bytes-1 downto 0 => '0')) when cpu_or1knd_i5_m_spr_sys_eear0_sel_inst_bus_error_eear,
c.m_data_bus_error_eear(or1k_spr_data_bits-1 downto 0) when cpu_or1knd_i5_m_spr_sys_eear0_sel_data_bus_error_eear,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_sys_epcr0_sel select
c.m_spr_sys_epcr0 <= (others => '0') when cpu_or1knd_i5_m_spr_sys_epcr0_sel_init,
r.m.mtspr_data(or1k_word_bits-1 downto or1k_log2_inst_bytes) when cpu_or1knd_i5_m_spr_sys_epcr0_sel_mtspr,
r.f.pc when cpu_or1knd_i5_m_spr_sys_epcr0_sel_f_pc,
r.d.pc when cpu_or1knd_i5_m_spr_sys_epcr0_sel_d_pc,
r.e.pc when cpu_or1knd_i5_m_spr_sys_epcr0_sel_e_pc,
r.m.pc when cpu_or1knd_i5_m_spr_sys_epcr0_sel_m_pc,
(others => 'X') when others;
m_madd_result_enabled_gen : if cpu_or1knd_i5_madd_enable generate
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_mac_maclo_sel select
c.m_spr_mac_maclo <= r.m.mtspr_data when cpu_or1knd_i5_m_spr_mac_maclo_sel_mtspr,
(others => '0') when cpu_or1knd_i5_m_spr_mac_maclo_sel_clear,
cpu_or1knd_i5_pipe_dp_in_misc.m_mul_result when cpu_or1knd_i5_m_spr_mac_maclo_sel_madd,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_mac_machi_sel select
c.m_spr_mac_machi <= r.m.mtspr_data when cpu_or1knd_i5_m_spr_mac_machi_sel_mtspr,
(others => '0') when cpu_or1knd_i5_m_spr_mac_machi_sel_clear,
cpu_or1knd_i5_pipe_dp_in_misc.m_madd_result_hi when cpu_or1knd_i5_m_spr_mac_machi_sel_madd,
(others => 'X') when others;
c.m_madd_result_hi_zeros <= all_zeros(cpu_or1knd_i5_pipe_dp_in_misc.m_madd_result_hi);
c.m_madd_result_hi_ones <= all_ones(cpu_or1knd_i5_pipe_dp_in_misc.m_madd_result_hi);
c.m_mul_result_msb <= cpu_or1knd_i5_pipe_dp_in_misc.m_mul_result(or1k_word_bits-1);
end generate;
-------------------
-- execute stage --
-------------------
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_fwd_alu_src1_sel select
c.e_alu_src1 <= r.e.alu_src1 when cpu_or1knd_i5_e_fwd_alu_src_sel_none,
r.m.alu_result when cpu_or1knd_i5_e_fwd_alu_src_sel_m_alu_result,
r.w.rd_data when cpu_or1knd_i5_e_fwd_alu_src_sel_w_rd_data,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_fwd_alu_src2_sel select
c.e_alu_src2 <= r.e.alu_src2 when cpu_or1knd_i5_e_fwd_alu_src_sel_none,
r.m.alu_result when cpu_or1knd_i5_e_fwd_alu_src_sel_m_alu_result,
r.w.rd_data when cpu_or1knd_i5_e_fwd_alu_src_sel_w_rd_data,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_fwd_st_data_sel select
c.e_st_data <= r.e.st_data when cpu_or1knd_i5_e_fwd_st_data_sel_none,
c.m_rd_data when cpu_or1knd_i5_e_fwd_st_data_sel_m_rd_data,
r.w.rd_data when cpu_or1knd_i5_e_fwd_st_data_sel_w_rd_data,
(others => 'X') when others;
c.e_cmov_result <= logic_if(cpu_or1knd_i5_pipe_dp_in_ctrl.e_spr_sys_sr_f, c.e_alu_src1, c.e_alu_src2);
c.e_ff1_result <= ff1(c.e_alu_src1);
c.e_fl1_result <= fl1(c.e_alu_src1);
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_data_size_sel select
c.e_ext_result <= ((31 downto 8 => cpu_or1knd_i5_pipe_dp_in_ctrl.e_sext and c.e_alu_src1(7)) &
c.e_alu_src1(7 downto 0)
) when cpu_or1knd_i5_data_size_sel_byte,
((31 downto 16 => cpu_or1knd_i5_pipe_dp_in_ctrl.e_sext and c.e_alu_src1(15)) &
c.e_alu_src1(15 downto 0)
) when cpu_or1knd_i5_data_size_sel_half,
c.e_alu_src1 when cpu_or1knd_i5_data_size_sel_word,
(others => 'X') when others;
c.e_not_equal <= any_ones(c.e_alu_src1 xor c.e_alu_src2);
c.e_lt_tmp <= (not (c.e_alu_src1(or1k_word_bits-1) xor c.e_alu_src2(or1k_word_bits-1))) and cpu_or1knd_i5_pipe_dp_in_misc.e_addsub_result(or1k_word_bits-1);
c.e_ltu <= ((not c.e_alu_src1(or1k_word_bits-1)) and c.e_alu_src2(or1k_word_bits-1)) or c.e_lt_tmp;
c.e_lts <= (c.e_alu_src1(or1k_word_bits-1) and (not c.e_alu_src2(or1k_word_bits-1))) or c.e_lt_tmp;
-- need to drop the *top* two bits from the adder result, because we
-- dropped the bottom two bits *before* feeding into the adder
c.e_direct_toc_target <= cpu_or1knd_i5_pipe_dp_in_misc.e_addsub_result(or1k_ivaddr_bits-1 downto 0);
c.e_indir_toc_target <= c.e_alu_src2(or1k_vaddr_bits-1 downto or1k_log2_inst_bytes);
c.e_toc_target_misaligned <= cpu_or1knd_i5_pipe_dp_in_ctrl.e_toc_indir and any_ones(c.e_alu_src2(or1k_log2_inst_bytes-1 downto 0));
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_toc_indir select
c.e_toc_target <= c.e_direct_toc_target when '0',
c.e_indir_toc_target when '1',
(others => 'X') when others;
c.e_btb_mispred <= logic_ne(r.e.btb_target, c.e_toc_target);
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_alu_result_sel select
c.e_alu_result <= cpu_or1knd_i5_pipe_dp_in_misc.e_addsub_result when cpu_or1knd_i5_alu_result_sel_addsub,
cpu_or1knd_i5_pipe_dp_in_misc.e_shifter_result when cpu_or1knd_i5_alu_result_sel_shifter,
c.e_alu_src1 and c.e_alu_src2 when cpu_or1knd_i5_alu_result_sel_and,
c.e_alu_src1 or c.e_alu_src2 when cpu_or1knd_i5_alu_result_sel_or,
c.e_alu_src1 xor c.e_alu_src2 when cpu_or1knd_i5_alu_result_sel_xor,
c.e_cmov_result when cpu_or1knd_i5_alu_result_sel_cmov,
c.e_ff1_result when cpu_or1knd_i5_alu_result_sel_ff1,
c.e_fl1_result when cpu_or1knd_i5_alu_result_sel_fl1,
c.e_ext_result when cpu_or1knd_i5_alu_result_sel_ext,
r.e.alu_src2(15 downto 0) & (15 downto 0 => '0') when cpu_or1knd_i5_alu_result_sel_movhi,
(others => 'X') when others;
-- load/store always uses immediate second argument, no forwarding
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_data_size_sel select
c.e_ldst_size <= "00" when cpu_or1knd_i5_data_size_sel_byte,
"01" when cpu_or1knd_i5_data_size_sel_half,
"10" when cpu_or1knd_i5_data_size_sel_word,
"XX" when others;
c.e_ldst_addr <= std_ulogic_vector(signed(c.e_alu_src1) + signed((or1k_word_bits-1 downto 16 => r.e.alu_src2(15)) & r.e.alu_src2(15 downto 0)));
c.e_ldst_misaligned <= (
(cpu_or1knd_i5_pipe_dp_in_ctrl.e_data_size_sel(cpu_or1knd_i5_data_size_sel_index_half) and c.e_ldst_addr(0)) or
(cpu_or1knd_i5_pipe_dp_in_ctrl.e_data_size_sel(cpu_or1knd_i5_data_size_sel_index_word) and (c.e_ldst_addr(0) or c.e_ldst_addr(1)))
);
-- SPR access always uses immediate second argument, no forwarding
c.e_spr_addr <= c.e_alu_src1 or ((or1k_word_bits-1 downto 16 => '0') & r.e.alu_src2(15 downto 0));
c.e_spr_group <= c.e_spr_addr(or1k_spr_addr_bits-1 downto or1k_spr_index_bits);
c.e_spr_index <= c.e_spr_addr(or1k_spr_index_bits-1 downto 0);
-- decode SPR address
c.e_spr_group_sys <= logic_eq(c.e_spr_group, or1k_spr_group_sys);
c.e_spr_group_dmmu <= logic_eq(c.e_spr_group, or1k_spr_group_dmmu);
c.e_spr_group_immu <= logic_eq(c.e_spr_group, or1k_spr_group_immu);
c.e_spr_group_dcache <= logic_eq(c.e_spr_group, or1k_spr_group_dcache);
c.e_spr_group_icache <= logic_eq(c.e_spr_group, or1k_spr_group_icache);
c.e_spr_group_mac <= logic_eq(c.e_spr_group, or1k_spr_group_mac);
c.e_spr_index_sys_vr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_vr);
c.e_spr_index_sys_upr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_upr);
c.e_spr_index_sys_cpucfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_cpucfgr);
c.e_spr_index_sys_dmmucfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_dmmucfgr);
c.e_spr_index_sys_immucfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_immucfgr);
c.e_spr_index_sys_dccfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_dccfgr);
c.e_spr_index_sys_iccfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_iccfgr);
c.e_spr_index_sys_dcfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_dcfgr);
c.e_spr_index_sys_pccfgr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_pccfgr);
c.e_spr_index_sys_aecr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_aecr);
c.e_spr_index_sys_aesr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_aesr);
c.e_spr_index_sys_npc <= logic_eq(c.e_spr_index, or1k_spr_index_sys_npc);
c.e_spr_index_sys_sr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_sr);
c.e_spr_index_sys_ppc <= logic_eq(c.e_spr_index, or1k_spr_index_sys_ppc);
c.e_spr_index_sys_fpcsr <= logic_eq(c.e_spr_index, or1k_spr_index_sys_fpcsr);
c.e_spr_index_sys_epcr0 <= logic_eq(c.e_spr_index,
(or1k_spr_index_sys_epcr_base(or1k_spr_index_bits-1 downto or1k_spr_index_sys_epcr_index_bits) &
std_ulogic_vector(to_unsigned(0, or1k_spr_index_sys_epcr_index_bits))));
c.e_spr_index_sys_eear0 <= logic_eq(c.e_spr_index,
(or1k_spr_index_sys_eear_base(or1k_spr_index_bits-1 downto or1k_spr_index_sys_eear_index_bits) &
std_ulogic_vector(to_unsigned(0, or1k_spr_index_sys_eear_index_bits))));
c.e_spr_index_sys_esr0 <= logic_eq(c.e_spr_index,
(or1k_spr_index_sys_esr_base(or1k_spr_index_bits-1 downto or1k_spr_index_sys_esr_index_bits) &
std_ulogic_vector(to_unsigned(0, or1k_spr_index_sys_esr_index_bits))));
c.e_spr_index_sys_gpr <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_rfaddr_bits),
(or1k_spr_index_sys_gpr_base(or1k_spr_index_bits-1 downto or1k_spr_index_sys_gpr_index_bits) &
(or1k_spr_index_sys_gpr_index_bits-1 downto or1k_rfaddr_bits => '0')));
c.e_spr_index_dmmu_dmmucr <= logic_eq(c.e_spr_index, or1k_spr_index_dmmu_dmmucr);
c.e_spr_index_dmmu_dmmupr <= logic_eq(c.e_spr_index, or1k_spr_index_dmmu_dmmupr);
c.e_spr_index_dmmu_dtlbeir <= logic_eq(c.e_spr_index, or1k_spr_index_dmmu_dtlbeir);
c.e_spr_index_dmmu_datbmr <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_datbmr_index_bits),
or1k_spr_index_dmmu_datbmr_base(or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_datbmr_index_bits));
c.e_spr_index_dmmu_datbtr <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_datbtr_index_bits),
or1k_spr_index_dmmu_datbtr_base(or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_datbtr_index_bits));
spr_dmmu_loop : for w in 0 to or1k_tlb_ways-1 generate
c.e_spr_index_dmmu_dtlbwmr_way(w) <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_dtlbwmr_index_bits),
std_ulogic_vector(unsigned(or1k_spr_index_dmmu_dtlbwmr_base(or1k_spr_index_bits-1 downto or1k_tlb_index_bits)) +
unsigned((or1k_spr_index_bits-1 downto or1k_tlb_way_bits+or1k_tlb_index_bits+1 => '0') &
to_unsigned(w, or1k_tlb_way_bits) &
'0')));
c.e_spr_index_dmmu_dtlbwtr_way(w) <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_dtlbwtr_index_bits),
std_ulogic_vector(unsigned(or1k_spr_index_dmmu_dtlbwtr_base(or1k_spr_index_bits-1 downto or1k_tlb_index_bits)) +
unsigned((or1k_spr_index_bits-1 downto or1k_tlb_way_bits+or1k_tlb_index_bits+1 => '0') &
to_unsigned(w, or1k_tlb_way_bits) &
'0')));
end generate;
c.e_spr_index_dmmu_dtlbwmr <= reduce_or(c.e_spr_index_dmmu_dtlbwmr_way);
c.e_spr_index_dmmu_dtlbwtr <= reduce_or(c.e_spr_index_dmmu_dtlbwtr_way);
c.e_spr_index_immu_immucr <= logic_eq(c.e_spr_index, or1k_spr_index_immu_immucr);
c.e_spr_index_immu_immupr <= logic_eq(c.e_spr_index, or1k_spr_index_immu_immupr);
c.e_spr_index_immu_itlbeir <= logic_eq(c.e_spr_index, or1k_spr_index_immu_itlbeir);
c.e_spr_index_immu_iatbmr <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_immu_iatbmr_index_bits),
or1k_spr_index_immu_iatbmr_base(or1k_spr_index_bits-1 downto or1k_spr_index_immu_iatbmr_index_bits));
c.e_spr_index_immu_iatbtr <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_immu_iatbtr_index_bits),
or1k_spr_index_immu_iatbtr_base(or1k_spr_index_bits-1 downto or1k_spr_index_immu_iatbtr_index_bits));
spr_immu_loop : for w in 0 to or1k_tlb_ways-1 generate
c.e_spr_index_immu_itlbwmr_way(w) <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_immu_itlbwmr_index_bits),
std_ulogic_vector(unsigned(or1k_spr_index_immu_itlbwmr_base(or1k_spr_index_bits-1 downto or1k_tlb_index_bits)) +
unsigned((or1k_spr_index_bits-1 downto or1k_tlb_way_bits+or1k_tlb_index_bits+1 => '0') &
to_unsigned(w, or1k_tlb_way_bits) &
'0')));
c.e_spr_index_immu_itlbwtr_way(w) <= logic_eq(c.e_spr_index(or1k_spr_index_bits-1 downto or1k_spr_index_immu_itlbwtr_index_bits),
std_ulogic_vector(unsigned(or1k_spr_index_immu_itlbwtr_base(or1k_spr_index_bits-1 downto or1k_tlb_index_bits)) +
unsigned((or1k_spr_index_bits-1 downto or1k_tlb_way_bits+or1k_tlb_index_bits+1 => '0') &
to_unsigned(w, or1k_tlb_way_bits) &
'0')));
end generate;
c.e_spr_index_immu_itlbwmr <= reduce_or(c.e_spr_index_immu_itlbwmr_way);
c.e_spr_index_immu_itlbwtr <= reduce_or(c.e_spr_index_immu_itlbwtr_way);
c.e_spr_index_dcache_dcbfr <= logic_eq(c.e_spr_index, or1k_spr_index_dcache_dcbfr);
c.e_spr_index_dcache_dcbir <= logic_eq(c.e_spr_index, or1k_spr_index_dcache_dcbir);
c.e_spr_index_dcache_dcbwr <= logic_eq(c.e_spr_index, or1k_spr_index_dcache_dcbwr);
c.e_spr_index_icache_icbir <= logic_eq(c.e_spr_index, or1k_spr_index_icache_icbir);
e_spr_index_mac_gen : if cpu_or1knd_i5_madd_enable generate
c.e_spr_index_mac_maclo <= logic_eq(c.e_spr_index, or1k_spr_index_mac_maclo);
c.e_spr_index_mac_machi <= logic_eq(c.e_spr_index, or1k_spr_index_mac_machi);
end generate;
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_vr) <= (c.e_spr_group_sys and c.e_spr_index_sys_vr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_upr) <= (c.e_spr_group_sys and c.e_spr_index_sys_upr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_cpucfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_cpucfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dmmucfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_dmmucfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_immucfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_immucfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dccfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_dccfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_iccfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_iccfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dcfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_dcfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_pccfgr) <= (c.e_spr_group_sys and c.e_spr_index_sys_pccfgr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_aecr) <= (c.e_spr_group_sys and c.e_spr_index_sys_aecr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_aesr) <= (c.e_spr_group_sys and c.e_spr_index_sys_aesr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_npc) <= (c.e_spr_group_sys and c.e_spr_index_sys_npc);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_sr) <= (c.e_spr_group_sys and c.e_spr_index_sys_sr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_ppc) <= (c.e_spr_group_sys and c.e_spr_index_sys_ppc);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_fpcsr) <= (c.e_spr_group_sys and c.e_spr_index_sys_fpcsr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_epcr0) <= (c.e_spr_group_sys and c.e_spr_index_sys_epcr0);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_eear0) <= (c.e_spr_group_sys and c.e_spr_index_sys_eear0);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_esr0) <= (c.e_spr_group_sys and c.e_spr_index_sys_esr0);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_gpr) <= (c.e_spr_group_sys and c.e_spr_index_sys_gpr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmucr) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_dmmucr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmupr) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_dmmupr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbeir) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_dtlbeir);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbmr) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_datbmr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbtr) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_datbtr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwmr) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_dtlbwmr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwtr) <= (c.e_spr_group_dmmu and c.e_spr_index_dmmu_dtlbwtr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_immucr) <= (c.e_spr_group_immu and c.e_spr_index_immu_immucr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_immupr) <= (c.e_spr_group_immu and c.e_spr_index_immu_immupr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbeir) <= (c.e_spr_group_immu and c.e_spr_index_immu_itlbeir);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_iatbmr) <= (c.e_spr_group_immu and c.e_spr_index_immu_iatbmr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_iatbtr) <= (c.e_spr_group_immu and c.e_spr_index_immu_iatbtr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwmr) <= (c.e_spr_group_immu and c.e_spr_index_immu_itlbwmr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwtr) <= (c.e_spr_group_immu and c.e_spr_index_immu_itlbwtr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbfr) <= (c.e_spr_group_dcache and c.e_spr_index_dcache_dcbfr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbir) <= (c.e_spr_group_dcache and c.e_spr_index_dcache_dcbir);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbwr) <= (c.e_spr_group_dcache and c.e_spr_index_dcache_dcbwr);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_icache_icbir) <= (c.e_spr_group_icache and c.e_spr_index_icache_icbir);
e_spr_addr_sel_madd_enable_gen : if cpu_or1knd_i5_madd_enable generate
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_mac_maclo) <= (c.e_spr_group_mac and c.e_spr_index_mac_maclo);
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_mac_machi) <= (c.e_spr_group_mac and c.e_spr_index_mac_machi);
c.e_spr_addr_valid <= (all_zeros(c.e_spr_addr(or1k_word_bits-1 downto or1k_spr_addr_bits)) and
(c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_vr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_upr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_cpucfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dmmucfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_immucfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dccfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_iccfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dcfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_pccfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_npc) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_sr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_ppc) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_fpcsr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_epcr0) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_eear0) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_esr0) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_gpr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmucr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmupr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbeir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_immucr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_immupr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbeir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_iatbmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_iatbtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbfr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbwr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_icache_icbir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_mac_maclo) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_mac_machi)
));
end generate;
e_spr_addr_sel_madd_disable_gen : if not cpu_or1knd_i5_madd_enable generate
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_mac_maclo) <= '0';
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_mac_machi) <= '0';
c.e_spr_addr_valid <= (all_zeros(c.e_spr_addr(or1k_word_bits-1 downto or1k_spr_addr_bits)) and
(c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_vr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_upr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_cpucfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dmmucfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_immucfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dccfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_iccfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_dcfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_pccfgr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_npc) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_sr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_ppc) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_fpcsr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_epcr0) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_eear0) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_esr0) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_sys_gpr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmucr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dmmupr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbeir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_datbtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dmmu_dtlbwtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_immucr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_immupr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbeir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_iatbmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_iatbtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwmr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_immu_itlbwtr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbfr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbir) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_dcache_dcbwr) or
c.e_spr_addr_sel(cpu_or1knd_i5_spr_addr_sel_index_icache_icbir)
));
end generate;
c.e_mtspr_data <= c.e_st_data;
with cpu_or1knd_i5_pipe_dp_in_ctrl.e_addr_sel select
c.e_addr <= c.e_ldst_addr when cpu_or1knd_i5_e_addr_sel_ldst,
c.e_spr_addr when cpu_or1knd_i5_e_addr_sel_spr,
(others => 'X') when others;
e_madd_acc_gen : if cpu_or1knd_i5_madd_enable generate
c.e_madd_acc <= ((r.p.spr.mac_machi & r.p.spr.mac_maclo) and
(2*or1k_word_bits-1 downto 0 => not cpu_or1knd_i5_pipe_dp_in_ctrl.e_madd_acc_zero));
end generate;
------------------
-- decode stage --
------------------
c.d_ra <= or1k_inst_ra(r.d.inst);
c.d_rb <= or1k_inst_rb(r.d.inst);
with cpu_or1knd_i5_pipe_dp_in_ctrl.d_rd_link select
c.d_rd <= "01001" when '1',
or1k_inst_rd(r.d.inst) when '0',
(others => 'X') when others;
c.d_ra_data <= cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata1;
c.d_rb_data <= cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata2;
c.d_depends_ra_e <= not reduce_or(c.d_ra xor r.e.rd);
c.d_depends_rb_e <= not reduce_or(c.d_rb xor r.e.rd);
c.d_depends_ra_m <= not reduce_or(c.d_ra xor r.m.rd);
c.d_depends_rb_m <= not reduce_or(c.d_rb xor r.m.rd);
c.d_imm_contig <= or1k_inst_imm_contig(r.d.inst);
c.d_imm_split <= or1k_inst_imm_split(r.d.inst);
c.d_imm_toc_offset <= or1k_inst_toc_offset(r.d.inst);
with cpu_or1knd_i5_pipe_dp_in_ctrl.d_imm_sel select
c.d_imm <= ((or1k_word_bits-1 downto or1k_imm_bits => cpu_or1knd_i5_pipe_dp_in_ctrl.d_imm_sext and c.d_imm_contig(or1k_imm_bits-1)) &
c.d_imm_contig
) when cpu_or1knd_i5_imm_sel_contig,
((or1k_word_bits-1 downto or1k_imm_bits => cpu_or1knd_i5_pipe_dp_in_ctrl.d_imm_sext and c.d_imm_split(or1k_imm_bits-1)) &
c.d_imm_split
) when cpu_or1knd_i5_imm_sel_split,
((or1k_word_bits-1 downto or1k_shift_bits => '0') &
or1k_inst_shift(r.d.inst)
) when cpu_or1knd_i5_imm_sel_shift,
((or1k_word_bits-1 downto or1k_word_bits-or1k_log2_inst_bytes => '0') &
(or1k_word_bits-or1k_log2_inst_bytes-1 downto or1k_toc_offset_bits => c.d_imm_toc_offset(or1k_toc_offset_bits-1)) &
c.d_imm_toc_offset
) when cpu_or1knd_i5_imm_sel_toc_offset,
(others => 'X') when others;
-- PC and TOC offset are fed to ALU, with the bottom 2 zeros dropped, and
-- with 2 zeros appended to the top.
-- this seems counterintuitive but may improve timing
with cpu_or1knd_i5_pipe_dp_in_ctrl.d_alu_src1_sel select
c.d_alu_src1 <= c.d_ra_data when cpu_or1knd_i5_alu_src1_sel_ra,
"00" & r.d.pc when cpu_or1knd_i5_alu_src1_sel_pc,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.d_alu_src2_sel select
c.d_alu_src2 <= c.d_rb_data when cpu_or1knd_i5_alu_src2_sel_rb,
c.d_imm when cpu_or1knd_i5_alu_src2_sel_imm,
(others => 'X') when others;
c.d_st_data <= c.d_rb_data;
-----------------
-- fetch stage --
-----------------
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_inst_buffered select
c.f_inst <= cpu_l1mem_inst_dp_out.data when '0',
r.p.f_inst_buffer when '1',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_inst_buffered select
c.f_inst_bus_error_eear <= cpu_l1mem_inst_dp_out.paddr when '0',
r.p.f_inst_bus_error_eear_buffer when '1',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_bpred_buffered select
c.f_btb_target <= cpu_btb_dp_out.rtarget when '0',
r.p.f_btb_target_buffer when '1',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_bpred_buffered select
c.f_btb_state <= cpu_btb_dp_out.rstate when '0',
r.p.f_btb_state_buffer when '1',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_bpred_buffered select
c.f_bpb_state <= cpu_bpb_dp_out.rstate when '0',
r.p.f_bpb_state_buffer when '1',
(others => 'X') when others;
c.f_ra <= or1k_inst_ra(c.f_inst);
c.f_rb <= or1k_inst_rb(c.f_inst);
c.f_pc_incr <= std_ulogic_vector(unsigned(r.f.pc) + to_unsigned(1, or1k_ivaddr_bits));
------------------------
-- before fetch stage --
------------------------
with cpu_or1knd_i5_pipe_dp_in_ctrl.bf_pc_sel select
c.bf_pc <= r.f.pc when cpu_or1knd_i5_bf_pc_sel_f,
c.f_pc_incr when cpu_or1knd_i5_bf_pc_sel_f_pc_incr,
c.f_btb_target when cpu_or1knd_i5_bf_pc_sel_btb,
r.d.pc when cpu_or1knd_i5_bf_pc_sel_d,
r.e.pc when cpu_or1knd_i5_bf_pc_sel_e,
r.e.pc_incr when cpu_or1knd_i5_bf_pc_sel_e_pc_incr,
c.e_toc_target when cpu_or1knd_i5_bf_pc_sel_e_toc_target,
c.m_exception_pc when cpu_or1knd_i5_bf_pc_sel_m_exception_pc,
r.p.spr.sys_epcr0 when cpu_or1knd_i5_bf_pc_sel_epcr0,
(others => 'X') when others;
---------------
-- registers --
---------------
with cpu_or1knd_i5_pipe_dp_in_ctrl.emw_stall select
r_next.w <= r.w when '1',
(rd_data => c.m_rd_data) when '0',
reg_w_x when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.emw_stall select
r_next.m <= r.m when '1',
(pc => r.e.pc,
pc_incr => r.e.pc_incr,
inst_bus_error_eear => r.e.inst_bus_error_eear,
inst => r.e.inst,
ra => r.e.ra,
rb => r.e.rb,
rd => r.e.rd,
addr => c.e_addr,
alu_result => c.e_alu_result,
mtspr_data => c.e_mtspr_data
) when '0',
reg_m_x when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.emw_stall select
r_next.e <= r.e when '1',
(pc => r.d.pc,
pc_incr => r.d.pc_incr,
inst_bus_error_eear => r.d.inst_bus_error_eear,
inst => r.d.inst,
bpb_state => r.d.bpb_state,
btb_state => r.d.btb_state,
btb_target => r.d.btb_target,
ra => c.d_ra,
rb => c.d_rb,
rd => c.d_rd,
alu_src1 => c.d_alu_src1,
alu_src2 => c.d_alu_src2,
st_data => c.d_st_data
) when '0',
reg_e_x when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.fd_stall select
r_next.d <= r.d when '1',
(inst => c.f_inst,
pc => r.f.pc,
pc_incr => c.f_pc_incr,
inst_bus_error_eear => c.f_inst_bus_error_eear,
bpb_state => c.f_bpb_state,
btb_state => c.f_btb_state,
btb_target => c.f_btb_target
) when '0',
reg_d_x when others;
r_next.f <= (
pc => c.bf_pc
);
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_sys_eear0_write select
r_next.p.spr.sys_eear0 <= c.m_spr_sys_eear0 when '1',
r.p.spr.sys_eear0 when '0',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_sys_epcr0_write select
r_next.p.spr.sys_epcr0 <= c.m_spr_sys_epcr0 when '1',
r.p.spr.sys_epcr0 when '0',
(others => 'X') when others;
r_next_madd_gen : if cpu_or1knd_i5_madd_enable generate
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_mac_maclo_write select
r_next.p.spr.mac_maclo <= c.m_spr_mac_maclo when '1',
r.p.spr.mac_maclo when '0',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_spr_mac_machi_write select
r_next.p.spr.mac_machi <= c.m_spr_mac_machi when '1',
r.p.spr.mac_machi when '0',
(others => 'X') when others;
end generate;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_bpred_buffer_write select
r_next.p.f_btb_target_buffer <= cpu_btb_dp_out.rtarget when '1',
r.p.f_btb_target_buffer when '0',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_bpred_buffer_write select
r_next.p.f_btb_state_buffer <= cpu_btb_dp_out.rstate when '1',
r.p.f_btb_state_buffer when '0',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_bpred_buffer_write select
r_next.p.f_bpb_state_buffer <= cpu_bpb_dp_out.rstate when '1',
r.p.f_bpb_state_buffer when '0',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.f_inst_buffer_write select
r_next.p.f_inst_buffer <= cpu_l1mem_inst_dp_out.data when '1',
r.p.f_inst_buffer when '0',
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.m_load_buffer_write select
r_next.p.m_load_buffer <= c.m_load_data_prebuffer when '1',
r.p.m_load_buffer when '0',
(others => 'X') when others;
-------------------
-- register file --
-------------------
with cpu_or1knd_i5_pipe_dp_in_ctrl.regfile_raddr1_sel select
c.regfile_raddr1 <= c.f_ra when cpu_or1knd_i5_regfile_raddr1_sel_f_ra,
c.d_ra when cpu_or1knd_i5_regfile_raddr1_sel_d_ra,
r.m.addr(or1k_rfaddr_bits-1 downto 0) when cpu_or1knd_i5_regfile_raddr1_sel_m_mfspr_sys_gpr,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.regfile_raddr2_sel select
c.regfile_raddr2 <= c.f_rb when cpu_or1knd_i5_regfile_raddr2_sel_f_rb,
c.d_rb when cpu_or1knd_i5_regfile_raddr2_sel_d_rb,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.regfile_w_sel select
c.regfile_waddr <= r.m.rd when cpu_or1knd_i5_regfile_w_sel_m_rd,
r.m.addr(or1k_rfaddr_bits-1 downto 0) when cpu_or1knd_i5_regfile_w_sel_m_mtspr_sys_gpr,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.regfile_w_sel select
c.regfile_wdata <= c.m_rd_data when cpu_or1knd_i5_regfile_w_sel_m_rd,
r.m.mtspr_data when cpu_or1knd_i5_regfile_w_sel_m_mtspr_sys_gpr,
(others => 'X') when others;
with cpu_or1knd_i5_pipe_dp_in_ctrl.l1mem_inst_vaddr_sel select
c.l1mem_inst_vaddr <= c.bf_pc when cpu_or1knd_i5_l1mem_inst_vaddr_sel_bf_pc,
r.m.mtspr_data(or1k_vaddr_bits-1 downto or1k_log2_inst_bytes) when cpu_or1knd_i5_l1mem_inst_vaddr_sel_m_mtspr_data,
(others => 'X') when others;
c.l1mem_data_size <= c.e_ldst_size;
with cpu_or1knd_i5_pipe_dp_in_ctrl.l1mem_data_vaddr_sel select
c.l1mem_data_vaddr <= c.e_ldst_addr when cpu_or1knd_i5_l1mem_data_vaddr_sel_e_ldst_addr,
r.m.mtspr_data when cpu_or1knd_i5_l1mem_data_vaddr_sel_m_mtspr_data,
(others => 'X') when others;
-------------
-- outputs --
-------------
cpu_bpb_dp_in <= (
raddr => c.bf_pc,
waddr => r.e.pc,
wstate => r.e.bpb_state
);
cpu_btb_dp_in <= (
raddr => c.bf_pc,
waddr => r.e.pc,
wstate => r.e.btb_state,
wtarget => c.e_direct_toc_target
);
cpu_or1knd_i5_pipe_dp_out_ctrl <= (
f_inst => c.f_inst,
d_depends_ra_e => c.d_depends_ra_e,
d_depends_rb_e => c.d_depends_rb_e,
d_depends_ra_m => c.d_depends_ra_m,
d_depends_rb_m => c.d_depends_rb_m,
e_not_equal => c.e_not_equal,
e_lts => c.e_lts,
e_ltu => c.e_ltu,
e_spr_addr_sel => c.e_spr_addr_sel,
e_spr_addr_valid => c.e_spr_addr_valid,
e_ldst_misaligned => c.e_ldst_misaligned,
e_toc_target_misaligned => c.e_toc_target_misaligned,
e_btb_mispred => c.e_btb_mispred,
m_mtspr_data => r.m.mtspr_data,
m_madd_result_hi_zeros => c.m_madd_result_hi_zeros,
m_madd_result_hi_ones => c.m_madd_result_hi_ones,
m_mul_result_msb => c.m_mul_result_msb
);
cpu_or1knd_i5_pipe_dp_out_misc <= (
e_alu_src1 => c.e_alu_src1,
e_alu_src2 => c.e_alu_src2,
e_madd_acc => c.e_madd_acc,
regfile_waddr => c.regfile_waddr,
regfile_wdata => c.regfile_wdata,
regfile_raddr1 => c.regfile_raddr1,
regfile_raddr2 => c.regfile_raddr2
);
cpu_l1mem_inst_dp_in <= (
vaddr => c.l1mem_inst_vaddr
);
cpu_l1mem_data_dp_in <= (
size => c.l1mem_data_size,
vaddr => c.l1mem_data_vaddr,
data => c.e_st_data
);
seq : process (clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
-- pragma translate_off
monitor : block
begin
m_pc_watch : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_pipe_dp'path_name),
name => "m_pc",
data_bits => or1k_ivaddr_bits
)
port map (
clk => clk,
data => r.m.pc
);
m_inst_watch : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_pipe_dp'path_name),
name => "m_inst",
data_bits => or1k_inst_bits
)
port map (
clk => clk,
data => r.m.inst
);
end block;
-- pragma translate_on
end;
| apache-2.0 | e866743a177eadb9e5541b5bf079f41f | 0.531546 | 2.7436 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_2/UART_Sample_Usage.vhd | 2 | 4,692 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:34:48 11/23/2016
-- Design Name:
-- Module Name: SERIAL_PORT - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SERIAL_PORT is
port (CLK : in std_logic;
UART_RXD : in std_logic;
UART_TXD : out std_logic;
IM_WRITE_EN : in std_logic;
reset : in std_logic;
IM_WR_EN_from_UART : out std_logic;
MEM_ADDRESS : out std_logic_vector(31 downto 0);
LED_1 : out std_logic;
LED_2 : out std_logic;
count_sig : out std_logic_vector(2 downto 0);
Ins_Data : out std_logic_vector(31 downto 0));
end SERIAL_PORT;
architecture behaviour of SERIAL_PORT is
component UART_RX_CTRL is
port ( UART_RX : in STD_LOGIC;
CLK : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA : out STD_LOGIC := '0';
RESET_READ: in STD_LOGIC);
end component;
component UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
signal uart_data_in: std_logic_vector(7 downto 0);
signal uart_data_out: std_logic_vector(7 downto 0);
signal data_available: std_logic;
signal reset_read: std_logic := '0';
signal tx_is_ready: std_logic;
signal send_data: std_logic := '0';
type SEND_STATE_TYPE is (READY, SENT, WAITING);
signal SEND_STATE : SEND_STATE_TYPE := READY;
signal last_six_chars: std_logic_vector(47 downto 0) := (others => '0');
signal count : std_logic_vector(2 downto 0) := (others => '0');
begin
count_sig <= count;
inst_UART_RX_CTRL: UART_RX_CTRL
port map( UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => data_available,
RESET_READ => reset_read);
inst_UART_TX_CTRL: UART_TX_CTRL
port map( SEND => send_data,
CLK => CLK,
DATA => uart_data_out,
READY => tx_is_ready,
UART_TX => UART_TXD);
uart_receive: process(CLK, SEND_STATE, data_available)
begin
if (rising_edge(CLK)) then
if reset = '1' then last_six_chars(47 downto 0) <= x"000000000000";
MEM_ADDRESS <= x"00000000";
count <= "000";
LED_2 <= '0';
LED_1 <= '0';
else
case SEND_STATE is
when READY => if (data_available = '1' and tx_is_ready = '1') then
last_six_chars(47 downto 8) <= last_six_chars(39 downto 0);
last_six_chars(7 downto 0) <= uart_data_in;
count <= count + 1;
if count = "110" then
LED_2 <= '1';
if (last_six_chars(47 downto 40) = x"04") then --write
if IM_WRITE_EN = '1' then
LED_1 <= '1';
IM_WR_EN_from_UART <= '1';
MEM_ADDRESS <= x"000000" & last_six_chars(39 downto 32);
Ins_Data <= last_six_chars(31 downto 0);
-- else
-- IM_WR_EN_from_UART <= '0';
-- MEM_ADDRESS <= x"000000FF";
-- Ins_Data <= x"00000000";
end if;
else
IM_WR_EN_from_UART <= '0';
MEM_ADDRESS <= x"000000FF";
Ins_Data <= x"00000000";
end if;
count <= "000";
uart_data_out <= x"01";
send_data <= '1';
--count_output <= count;
else
IM_WR_EN_from_UART <= '0';
--count <= count + 1;
send_data <= '0';
LED_2 <= '0';
LED_1 <= '0';
--count_output <= count;
end if;
SEND_STATE <= SENT;
end if;
when SENT => reset_read <= '1';
send_data <= '0';
SEND_STATE <= WAITING;
when WAITING => if (data_available = '0') then
reset_read <= '0';
SEND_STATE <= READY;
end if;
end case;
end if;
end if;
end process;
end architecture;
| mit | ba19bb181e4aff1f77e787ccf492d38f | 0.474211 | 3.397538 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_altpll_0_pll_slave_translator.vhd | 1 | 14,520 | -- niosii_system_altpll_0_pll_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(3 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_altpll_0_pll_slave_translator;
architecture rtl of niosii_system_altpll_0_pll_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
altpll_0_pll_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_altpll_0_pll_slave_translator
| apache-2.0 | 55d636bac7fc63528c45da9e9a0da7c7 | 0.430854 | 4.32529 | false | false | false | false |
loa-org/loa-hdl | modules/spislave/hdl/spislave.vhd | 2 | 6,327 | -------------------------------------------------------------------------------
-- Title : SPI Slave, synchronous
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description: This is an SPI slave that is a busmaster to the local bus.
-- Data can be transfered to and from the bus slaves on the bus.
--
-- This modules uses some black magic:
-- * On the detection of the rising edge of SCK the input is
-- sampled and the output is set. This violates the SPI protocol
-- which expects setting the MISO at one edge and sampling the
-- MOSI at the other edge.
--
-- * Due to the synchronisation of the asynchronous external SCK
-- signal The detection of the falling edge of SCK is delayed by
-- 3 internal clock cycles. At 50 MHz this leads to a delay of
-- 60 usec which fulfills the setup and hold times of the
-- SPI master.
--
-- Protocol: The SPI transfers are always 32 bits
-- SPI mode 0, CPOL = 0, CPAH = 0
-- The first 16 bits are the address and the second 16 bits are
-- the data.
--
-- If the MSB of the address is not set (MSB = '0') a read access
-- to the parallel bus is performed. The result of this read access
-- is retrieved while sending the next 16 bits. The contents of
-- these bits can be used as the address for the next access (read
-- or write).
--
-- If the MSB of the address is set (MSB = '1') a write access to
-- the parallel bus is performed.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.spislave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spi_slave is
port (
miso_p : out std_logic;
mosi_p : in std_logic;
sck_p : in std_logic;
csn_p : in std_logic;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic
);
end spi_slave;
-------------------------------------------------------------------------------
architecture behavioral of spi_slave is
type spi_slave_states is (IDLE, SEL, WAIT_RD, RD, WR);
type spi_slave_state_type is record
ireg : std_logic_vector(31 downto 0);
oreg : std_logic_vector(31 downto 0);
mosi : std_logic_vector(1 downto 0);
miso : std_logic;
sck : std_logic_vector(2 downto 0);
csn : std_logic_vector(2 downto 0);
bit_cnt : integer range 0 to 31;
bus_addr : std_logic_vector(14 downto 0);
bus_do : std_logic_vector(15 downto 0);
bus_re : std_logic;
bus_we : std_logic;
state : spi_slave_states;
end record;
signal r, rin : spi_slave_state_type := (
ireg => (others => '0'),
oreg => (others => '0'),
mosi => (others => '0'),
miso => '0',
sck => (others => '0'),
csn => (others => '0'),
bit_cnt => 31,
bus_addr => (others => '0'),
bus_do => (others => '0'),
bus_re => '0',
bus_we => '0',
state => IDLE
);
begin
spi_cmb : process (bus_i.data, csn_p, mosi_p, r, r.csn(1 downto 0),
r.mosi(0), r.sck(1 downto 0), r.state, sck_p)
variable v : spi_slave_state_type;
variable rising_sck, falling_csn : std_logic;
begin
v := r;
v.mosi := r.mosi(0) & mosi_p;
v.sck := r.sck(1 downto 0) & sck_p;
v.csn := r.csn(1 downto 0) & csn_p;
rising_sck := v.sck(1) and not v.sck(2);
falling_csn := v.csn(2) and not v.csn(1);
v.bus_we := '0';
v.bus_re := '0';
v.bus_addr := (others => '0');
case r.state is
when IDLE =>
-- falling chip select
if falling_csn = '1' then
v.state := SEL;
v.bit_cnt := 31;
end if;
when SEL =>
v.miso := v.oreg(v.bit_cnt);
if rising_sck = '1' then
v.ireg(v.bit_cnt) := v.mosi(1);
-- MSB = '0' => read
if v.ireg(31) = '0' and v.bit_cnt = 16 then
v.bus_addr := v.ireg(30 downto 16);
v.bus_re := '1';
v.state := WAIT_RD;
end if;
-- MSB = '1' => write
if v.ireg(31) = '1' and v.bit_cnt = 0 then
v.bus_addr := v.ireg(30 downto 16);
v.bus_do := v.ireg(15 downto 0);
v.bus_we := '1';
v.state := WR;
end if;
if not (v.bit_cnt = 0) then
v.bit_cnt := v.bit_cnt - 1;
end if;
end if;
-- delay for one clock cycle to give the devices on the bus
-- some time to output their data
when WAIT_RD =>
v.state := RD;
when RD =>
v.oreg(31 downto 16) := bus_i.data;
-- reset the bit counter to 31 to make sequential reads possible.
v.state := SEL;
v.bit_cnt := 31;
when WR =>
-- reset the bit counter to 31 to make sequential writes possible.
v.state := SEL;
v.bit_cnt := 31;
end case;
if v.csn(1) = '1' then
v.state := IDLE;
end if;
rin <= v;
end process spi_cmb;
-- trisate output is generated comb., to reduce risk of external bus hazard
miso_p <= r.miso when csn_p = '0' else 'Z';
bus_o.addr <= r.bus_addr;
bus_o.data <= r.bus_do;
bus_o.we <= r.bus_we;
bus_o.re <= r.bus_re;
spi_seq : process (clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process spi_seq;
end behavioral;
| bsd-3-clause | 6c34cf1a6bdbf96dc7aff26d10ef7c8e | 0.450609 | 3.853228 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 19,047 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 669eae056167158e081782044ac3897e | 0.491521 | 2.733496 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_hdr_ecc.vhd | 1 | 1,480 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--MIPI CSI-2 Header ECC calculation
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
entity csi_rx_hdr_ecc is
Port ( data : in STD_LOGIC_VECTOR (23 downto 0);
ecc : out STD_LOGIC_VECTOR (7 downto 0));
end csi_rx_hdr_ecc;
architecture Behavioral of csi_rx_hdr_ecc is
begin
ecc(7) <= '0';
ecc(6) <= '0';
ecc(5) <= data(10) xor data(11) xor data(12) xor data(13) xor data(14) xor data(15) xor data(16) xor data(17) xor data(18) xor data(19) xor data(21) xor data(22) xor data(23);
ecc(4) <= data(4) xor data(5) xor data(6) xor data(7) xor data(8) xor data(9) xor data(16) xor data(17) xor data(18) xor data(19) xor data(20) xor data(22) xor data(23);
ecc(3) <= data(1) xor data(2) xor data(3) xor data(7) xor data(8) xor data(9) xor data(13) xor data(14) xor data(15) xor data(19) xor data(20) xor data(21) xor data(23);
ecc(2) <= data(0) xor data(2) xor data(3) xor data(5) xor data(6) xor data(9) xor data(11) xor data(12) xor data(15) xor data(18) xor data(20) xor data(21) xor data(22);
ecc(1) <= data(0) xor data(1) xor data(3) xor data(4) xor data(6) xor data(8) xor data(10) xor data(12) xor data(14) xor data(17) xor data(20) xor data(21) xor data(22) xor data(23);
ecc(0) <= data(0) xor data(1) xor data(2) xor data(4) xor data(5) xor data(7) xor data(10) xor data(11) xor data(13) xor data(16) xor data(20) xor data(21) xor data(22) xor data(23);
end Behavioral;
| mit | 2f09db985432dea178d106abca8b9e7f | 0.652027 | 2.638146 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_banked_1rw_inferred-rtl.vhdl | 1 | 2,177 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of syncram_banked_1rw_inferred is
constant banks : natural := 2**log2_banks;
type bank_data_type is array(banks-1 downto 0) of std_ulogic_vector(word_bits-1 downto 0);
type comb_type is record
bank_en : std_ulogic_vector(banks-1 downto 0);
bank_rdata, bank_wdata : bank_data_type;
end record;
signal c : comb_type;
begin
bank_loop : for n in 0 to banks-1 generate
c.bank_en(n) <= en and banken(n);
word_bit_loop : for m in word_bits-1 downto 0 generate
c.bank_wdata(n)(m) <= wdata(n, m);
rdata(n, m) <= c.bank_rdata(n)(m);
end generate;
syncram : entity work.syncram_1rw(rtl)
generic map (
addr_bits => addr_bits,
data_bits => word_bits
)
port map (
clk => clk,
en => c.bank_en(n),
we => we,
addr => addr,
wdata => c.bank_wdata(n),
rdata => c.bank_rdata(n)
);
end generate;
end;
| apache-2.0 | 67b61d06f1284265e09aa98006792235 | 0.512173 | 4.310891 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ltc2351/hdl/adc_ltc2351.vhd | 2 | 6,547 | -------------------------------------------------------------------------------
-- Title : 1.5Msps 6-channel synchronously sampling ADC LTC2351
-- Project :
-------------------------------------------------------------------------------
-- Created : 2012-04-10
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
entity adc_ltc2351 is
generic (
RESOLUTION : natural := 14 -- resolution of the ADC
);
port (
-- signal to and from real hardware
adc_out : out adc_ltc2351_spi_out_type;
adc_in : in adc_ltc2351_spi_in_type;
-- signals to other logic in FPGA
start_p : in std_logic;
values_p : out adc_ltc2351_values_type(5 downto 0);
done_p : out std_logic;
-- clock
clk : in std_logic
);
end adc_ltc2351;
-------------------------------------------------------------------------------
architecture behavioral of adc_ltc2351 is
constant BITCOUNT : natural := 98; -- Number of bits in one response of ADC
constant CHANNEL_COUNT : natural := 6; -- Number of channels in ADC
type adc_ltc2351_state_type is (IDLE, SCK_LOW, SCK_HIGH);
type adc_ltc2351_type is record
state : adc_ltc2351_state_type;
sck : std_logic;
conv : std_logic;
done : std_logic;
-- 96 data bits and two bit times for CONV accordingly to datasheet
din : std_logic_vector(1 to BITCOUNT);
count_bit : integer range 1 to BITCOUNT + 1;
countdown_delay : integer range 0 to 1;
-- register results of last conversion
values : adc_ltc2351_values_type(CHANNEL_COUNT-1 downto 0);
end record;
-- -----------------------------------------------------------------------------
-- Internal signal declarations
-- -----------------------------------------------------------------------------
signal r, rin : adc_ltc2351_type := (state => IDLE,
sck => '0',
conv => '0',
done => '0',
din => (others => '0'),
count_bit => 1,
countdown_delay => 0,
values => (others => (others => '0')));
-- -----------------------------------------------------------------------------
-- Component declarations
-- -----------------------------------------------------------------------------
begin
-- -----------------------------------------------------------------------------
-- connect internal signals to out
-- -----------------------------------------------------------------------------
-- output to ADC
adc_out.sck <= r.sck;
adc_out.conv <= r.conv;
-- outputs of this entity
done_p <= r.done; -- signals valid data on value_p
-- values of the last conversion
values_p <= r.values;
-- -----------------------------------------------------------------------------
-- Sequential proc of FSM
-- -----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-- -----------------------------------------------------------------------------
-- Transitons and actions of FSM
-- -----------------------------------------------------------------------------
comb_proc : process(adc_in.sdo, r, start_p)
variable v : adc_ltc2351_type;
begin
v := r;
case v.state is
-- -------------------------------------------------------------------------
-- Idle State
-- Wait until a start of conversion was requested by start_p
-- -------------------------------------------------------------------------
when IDLE =>
v.done := '0';
if start_p = '1' then
v.state := SCK_LOW;
v.sck := '0';
v.conv := '1';
v.count_bit := 1;
v.countdown_delay := 1;
-- v.din := r.din(2 to BITCOUNT) & adc_in.sdo;
else
-- keep sck running
v.sck := not r.sck;
end if; -- start_p
-- -------------------------------------------------------------------------
-- Low period of SCK
-- -------------------------------------------------------------------------
when SCK_LOW =>
v.state := SCK_HIGH;
v.sck := '1';
-- -------------------------------------------------------------------------
-- High period of SCK
-- -------------------------------------------------------------------------
when SCK_HIGH =>
v.state := SCK_LOW;
v.sck := '0';
v.conv := '0';
-- sample v.din on the H->L transition of SCK
v.din := r.din(2 to BITCOUNT) & adc_in.sdo;
if r.count_bit = (BITCOUNT + 1) then
-- last bit received
v.state := IDLE;
v.sck := '0';
v.done := '1';
v.values(0) := r.din(3 to 16);
v.values(1) := r.din(19 to 32);
v.values(2) := r.din(35 to 48);
v.values(3) := r.din(51 to 64);
v.values(4) := r.din(67 to 80);
v.values(5) := r.din(83 to 96);
else
v.count_bit := r.count_bit + 1;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
end behavioral;
| bsd-3-clause | bd0bd8dddd944796bd85b65ad794f8ad | 0.317703 | 5.446755 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/madd_pipe-rtl.vhdl | 1 | 1,633 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of madd_pipe is
begin
madd : entity work.madd_pipe_inferred(rtl)
generic map (
stages => stages,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
unsgnd => unsgnd,
sub => sub,
acc => acc,
src1 => src1,
src2 => src2,
result => result,
overflow => overflow
);
end;
| apache-2.0 | 5149d67efe20eddf8da5d9fcfb9d84d9 | 0.475811 | 5.13522 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/tb/input_capture_tb.vhd | 2 | 2,714 | -------------------------------------------------------------------------------
-- Title : Testbench for design "input_capture"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-------------------------------------------------------------------------------
-- Description:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.input_capture_pkg.all;
-------------------------------------------------------------------------------
entity input_capture_tb is
end input_capture_tb;
-------------------------------------------------------------------------------
architecture tb of input_capture_tb is
-- component ports
signal value : std_logic_vector(15 downto 0);
signal step : std_logic := '0';
signal dir : std_logic := '0';
signal clk_en : std_logic := '1';
signal clk : std_logic := '0';
begin
-- component instantiation
input_capture_1 : input_capture
port map (
value_p => value,
step_p => step,
dir_p => dir,
clk_en_p => clk_en,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 400 NS;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
wait for 400 US;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
wait for 200 US;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
wait for 50 US;
wait until rising_edge(clk);
step <= '1';
dir <= '1';
wait until rising_edge(clk);
step <= '0';
wait for 50 US;
wait until rising_edge(clk);
step <= '1';
dir <= '1';
wait until rising_edge(clk);
step <= '0';
wait for 50 US;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
wait for 1 US;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
wait for 2 MS;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
wait for 20 US;
wait until rising_edge(clk);
step <= '1';
dir <= '0';
wait until rising_edge(clk);
step <= '0';
end process waveform;
end tb;
| bsd-3-clause | 42cc71edc12c07ddd1da78ffa5f360e6 | 0.43773 | 4.099698 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl | 1 | 5,311 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_0_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_0_0;
architecture STRUCTURE of system_ov7670_vga_0_0 is
begin
U0: entity work.system_ov7670_vga_0_0_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | 9348e43a66a459a41dfee0b7f4f6f025 | 0.523254 | 3.184053 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/system_ov7670_controller_1_0_sim_netlist.vhdl | 1 | 70,488 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_1_0 -prefix
-- system_ov7670_controller_1_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_1_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_1_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_1_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_1_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_1_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_1_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_1_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_1_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_1_0;
architecture STRUCTURE of system_ov7670_controller_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_1_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 4e0ba7a5d379cdcbf853abee98f9f464 | 0.531211 | 2.810638 | false | false | false | false |
CampbellGroup/fpga | ltc1450/clock/clock.vhd | 1 | 805 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY signal_generator IS
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC; --unused
led: OUT STD_LOGIC;
clock_out : OUT STD_LOGIC);
END signal_generator;
ARCHITECTURE behavior of signal_generator IS
SIGNAL clk_sig : std_logic;
SIGNAL led_sig : std_logic;
BEGIN
PROCESS(clk)
VARIABLE count1 : integer;
VARIABLE count2 : integer;
BEGIN
IF rising_edge(clk) then
IF (count1=5) THEN
clk_sig<=NOT(clk_sig);
count1:=0;
ELSE
count1:=count1+1;
END IF;
IF (count2=24999999) THEN --((input clock)/2-1)
led_sig<=NOT(led_sig);
count2:=0;
ELSE
count2:=count2+1;
END IF;
END IF;
END PROCESS;
clock_out <= clk_sig;
led <= led_sig;
END behavior; | mit | b364933f675ad8b7c38dd48f7fc5e6d8 | 0.665839 | 2.719595 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_1/system_vga_buffer_1_1_sim_netlist.vhdl | 1 | 23,772 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 00:58:43 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_1/system_vga_buffer_1_1_sim_netlist.vhdl
-- Design : system_vga_buffer_1_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_1_vga_buffer is
port (
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
\y_addr_r[1]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_buffer_1_1_vga_buffer : entity is "vga_buffer";
end system_vga_buffer_1_1_vga_buffer;
architecture STRUCTURE of system_vga_buffer_1_1_vga_buffer is
signal addr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal addr_w : STD_LOGIC_VECTOR ( 11 downto 0 );
signal c_addr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal c_addr_w : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_data_reg_0_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_0_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_0_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_0_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_0_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_0_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_0_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_0_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 8 );
signal NLW_data_reg_0_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_0_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_data_reg_0_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_0_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_data_reg_1_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_1_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_1_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_1_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_1_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_1_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 8 );
signal NLW_data_reg_1_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_1_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_data_reg_1_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_1_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_data_reg_2_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_2_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_2_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_2_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_2_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_2_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_2_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_2_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 6 );
signal NLW_data_reg_2_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_2_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_2_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_2_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of data_reg_0 : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg_0 : label is "p1_d8";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg_0 : label is "p1_d8";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of data_reg_0 : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of data_reg_0 : label is 98304;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of data_reg_0 : label is "data";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of data_reg_0 : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of data_reg_0 : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of data_reg_0 : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of data_reg_0 : label is 8;
attribute CLOCK_DOMAINS of data_reg_1 : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg_1 : label is "p1_d8";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg_1 : label is "p1_d8";
attribute METHODOLOGY_DRC_VIOS of data_reg_1 : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS of data_reg_1 : label is 98304;
attribute RTL_RAM_NAME of data_reg_1 : label is "data";
attribute bram_addr_begin of data_reg_1 : label is 0;
attribute bram_addr_end of data_reg_1 : label is 4095;
attribute bram_slice_begin of data_reg_1 : label is 9;
attribute bram_slice_end of data_reg_1 : label is 17;
attribute CLOCK_DOMAINS of data_reg_2 : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg_2 : label is "p0_d6";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg_2 : label is "p0_d6";
attribute METHODOLOGY_DRC_VIOS of data_reg_2 : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS of data_reg_2 : label is 98304;
attribute RTL_RAM_NAME of data_reg_2 : label is "data";
attribute bram_addr_begin of data_reg_2 : label is 0;
attribute bram_addr_end of data_reg_2 : label is 4095;
attribute bram_slice_begin of data_reg_2 : label is 18;
attribute bram_slice_end of data_reg_2 : label is 23;
begin
\addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(0),
Q => addr_r(0),
R => '0'
);
\addr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(10),
Q => addr_r(10),
R => '0'
);
\addr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(11),
Q => addr_r(11),
R => '0'
);
\addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(1),
Q => addr_r(1),
R => '0'
);
\addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(2),
Q => addr_r(2),
R => '0'
);
\addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(3),
Q => addr_r(3),
R => '0'
);
\addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(4),
Q => addr_r(4),
R => '0'
);
\addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(5),
Q => addr_r(5),
R => '0'
);
\addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(6),
Q => addr_r(6),
R => '0'
);
\addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(7),
Q => addr_r(7),
R => '0'
);
\addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(8),
Q => addr_r(8),
R => '0'
);
\addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(9),
Q => addr_r(9),
R => '0'
);
\addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(0),
Q => addr_w(0),
R => '0'
);
\addr_w_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(10),
Q => addr_w(10),
R => '0'
);
\addr_w_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(11),
Q => addr_w(11),
R => '0'
);
\addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(1),
Q => addr_w(1),
R => '0'
);
\addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(2),
Q => addr_w(2),
R => '0'
);
\addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(3),
Q => addr_w(3),
R => '0'
);
\addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(4),
Q => addr_w(4),
R => '0'
);
\addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(5),
Q => addr_w(5),
R => '0'
);
\addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(6),
Q => addr_w(6),
R => '0'
);
\addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(7),
Q => addr_w(7),
R => '0'
);
\addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(8),
Q => addr_w(8),
R => '0'
);
\addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(9),
Q => addr_w(9),
R => '0'
);
\c_addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(0),
Q => c_addr_r(0),
R => '0'
);
\c_addr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(10),
Q => c_addr_r(10),
R => '0'
);
\c_addr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(11),
Q => c_addr_r(11),
R => '0'
);
\c_addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(1),
Q => c_addr_r(1),
R => '0'
);
\c_addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(2),
Q => c_addr_r(2),
R => '0'
);
\c_addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(3),
Q => c_addr_r(3),
R => '0'
);
\c_addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(4),
Q => c_addr_r(4),
R => '0'
);
\c_addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(5),
Q => c_addr_r(5),
R => '0'
);
\c_addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(6),
Q => c_addr_r(6),
R => '0'
);
\c_addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(7),
Q => c_addr_r(7),
R => '0'
);
\c_addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(8),
Q => c_addr_r(8),
R => '0'
);
\c_addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => \y_addr_r[1]\(9),
Q => c_addr_r(9),
R => '0'
);
\c_addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(0),
Q => c_addr_w(0),
R => '0'
);
\c_addr_w_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(10),
Q => c_addr_w(10),
R => '0'
);
\c_addr_w_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(11),
Q => c_addr_w(11),
R => '0'
);
\c_addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(1),
Q => c_addr_w(1),
R => '0'
);
\c_addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(2),
Q => c_addr_w(2),
R => '0'
);
\c_addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(3),
Q => c_addr_w(3),
R => '0'
);
\c_addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(4),
Q => c_addr_w(4),
R => '0'
);
\c_addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(5),
Q => c_addr_w(5),
R => '0'
);
\c_addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(6),
Q => c_addr_w(6),
R => '0'
);
\c_addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(7),
Q => c_addr_w(7),
R => '0'
);
\c_addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(8),
Q => c_addr_w(8),
R => '0'
);
\c_addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => D(9),
Q => c_addr_w(9),
R => '0'
);
data_reg_0: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addr_w(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addr_r(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_0_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_0_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_0_DBITERR_UNCONNECTED,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => data_w(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000011111111",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => data_w(8),
DIPBDIP(3 downto 0) => B"0001",
DOADO(31 downto 0) => NLW_data_reg_0_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 8) => NLW_data_reg_0_DOBDO_UNCONNECTED(31 downto 8),
DOBDO(7 downto 0) => data_r(7 downto 0),
DOPADOP(3 downto 0) => NLW_data_reg_0_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 1) => NLW_data_reg_0_DOPBDOP_UNCONNECTED(3 downto 1),
DOPBDOP(0) => data_r(8),
ECCPARITY(7 downto 0) => NLW_data_reg_0_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_0_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_0_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_0_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_0_SBITERR_UNCONNECTED,
WEA(3) => wen,
WEA(2) => wen,
WEA(1) => wen,
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
data_reg_1: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addr_w(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addr_r(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_1_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_1_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_1_DBITERR_UNCONNECTED,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => data_w(16 downto 9),
DIBDI(31 downto 0) => B"00000000000000000000000011111111",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => data_w(17),
DIPBDIP(3 downto 0) => B"0001",
DOADO(31 downto 0) => NLW_data_reg_1_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 8) => NLW_data_reg_1_DOBDO_UNCONNECTED(31 downto 8),
DOBDO(7 downto 0) => data_r(16 downto 9),
DOPADOP(3 downto 0) => NLW_data_reg_1_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 1) => NLW_data_reg_1_DOPBDOP_UNCONNECTED(3 downto 1),
DOPBDOP(0) => data_r(17),
ECCPARITY(7 downto 0) => NLW_data_reg_1_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_1_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_1_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_1_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_1_SBITERR_UNCONNECTED,
WEA(3) => wen,
WEA(2) => wen,
WEA(1) => wen,
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
data_reg_2: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addr_w(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addr_r(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_2_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_2_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_2_DBITERR_UNCONNECTED,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => data_w(23 downto 18),
DIBDI(31 downto 0) => B"00000000000000000000000000111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => NLW_data_reg_2_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 6) => NLW_data_reg_2_DOBDO_UNCONNECTED(31 downto 6),
DOBDO(5 downto 0) => data_r(23 downto 18),
DOPADOP(3 downto 0) => NLW_data_reg_2_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_data_reg_2_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_data_reg_2_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_2_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_2_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_2_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_2_SBITERR_UNCONNECTED,
WEA(3) => wen,
WEA(2) => wen,
WEA(1) => wen,
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_1 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_buffer_1_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_buffer_1_1 : entity is "system_vga_buffer_1_1,vga_buffer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_buffer_1_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_buffer_1_1 : entity is "vga_buffer,Vivado 2016.4";
end system_vga_buffer_1_1;
architecture STRUCTURE of system_vga_buffer_1_1 is
begin
U0: entity work.system_vga_buffer_1_1_vga_buffer
port map (
D(11 downto 10) => y_addr_w(1 downto 0),
D(9 downto 0) => x_addr_w(9 downto 0),
clk_r => clk_r,
clk_w => clk_w,
data_r(23 downto 0) => data_r(23 downto 0),
data_w(23 downto 0) => data_w(23 downto 0),
wen => wen,
\y_addr_r[1]\(11 downto 10) => y_addr_r(1 downto 0),
\y_addr_r[1]\(9 downto 0) => x_addr_r(9 downto 0)
);
end STRUCTURE;
| mit | 2d7e462a9ce93266b702672c90c70c19 | 0.554181 | 3.076087 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/dc_motor_module_extended.vhd | 2 | 4,792 | -------------------------------------------------------------------------------
-- Title : Motor control for DC Motors
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a symmetric (center-aligned) PWM without deadtime
--
-- Register Map:
-- Base Address + 0 | W | PWM Halfbridge 1
-- Base Address + 0 | R | unused
-- Base Address + 1 | W | PWM Halfbridge 2
-- Base Address + 1 | R | unused
--
-- The shutdown value (bit 15) is shared between the two PWM registers. The
-- value last set takes precedence.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all;
use work.symmetric_pwm_pkg.all;
entity dc_motor_module_extended is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
WIDTH : positive := 12; -- Number of bits for the PWM generation (e.g. 12 => 0..4095)
PRESCALER : positive
);
port (
pwm1_p : out std_logic; -- Halfbridge 1
pwm2_p : out std_logic; -- Halfbridge 2
sd_p : out std_logic; -- Shutdown
-- Disable switching
break_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end dc_motor_module_extended;
-------------------------------------------------------------------------------
architecture behavioral of dc_motor_module_extended is
-- Base address converted to a logic vector for easier access.
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
type dc_motor_module_type is record
data_out : std_logic_vector(15 downto 0); -- currently not used
-- PWM value for half-bridge 1
pwm_value1 : std_logic_vector(WIDTH - 1 downto 0);
-- PWM value for half-bridge 2
pwm_value2 : std_logic_vector(WIDTH - 1 downto 0);
sd : std_logic; -- Shutdown
end record;
signal clk_en : std_logic := '1';
signal pwm1 : std_logic := '0';
signal pwm2 : std_logic := '0';
signal r, rin : dc_motor_module_type := (
data_out => (others => '0'),
pwm_value1 => (others => '0'),
pwm_value2 => (others => '0'),
sd => '1'
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(break_p, bus_i, pwm1, pwm2, r)
variable v : dc_motor_module_type;
begin
v := r;
-- Set default values
v.data_out := (others => '0');
-- Check Bus Address
if bus_i.addr(14 downto 1) = BASE_ADDRESS_VECTOR(14 downto 1) then
if bus_i.we = '1' then
if bus_i.addr(0) = '0' then
v.pwm_value1 := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
else
v.pwm_value2 := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
end if;
elsif bus_i.re = '1' then
-- v.data_out := r.counter;
end if;
end if;
if r.sd = '1' then
pwm1_p <= '0';
pwm2_p <= '0';
sd_p <= '1';
else
if break_p = '1' then
pwm1_p <= '0';
pwm2_p <= '0';
else
pwm1_p <= pwm1;
pwm2_p <= pwm2;
end if;
sd_p <= '0';
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
pwm_generator1 : symmetric_pwm
generic map (
WIDTH => WIDTH)
port map (
pwm_p => pwm1,
underflow_p => open,
overflow_p => open,
clk_en_p => clk_en,
value_p => r.pwm_value1,
reset => '0',
clk => clk);
pwm_generator2 : symmetric_pwm
generic map (
WIDTH => WIDTH)
port map (
pwm_p => pwm2,
underflow_p => open,
overflow_p => open,
clk_en_p => clk_en,
value_p => r.pwm_value2,
reset => '0',
clk => clk);
end behavioral;
| bsd-3-clause | aee6891a9b9895247c0377e2daf6dc83 | 0.475376 | 3.683321 | false | false | false | false |
loa-org/loa-hdl | modules/ir_rx/hdl/ir_rx_adcs.vhd | 2 | 2,054 | -------------------------------------------------------------------------------
-- Title : Two ADCs
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_adcs.vhd
-- Author : strongly-typed
-- Created : 2012-04-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
entity ir_rx_adcs is
generic (
CHANNELS : positive := 12);
port (
clk_sample_en_i_p : in std_logic;
-- Ports to two ADCs
-- signals to and from real hardware
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
adc_values_o_p : out adc_ltc2351_values_type;
adc_done_o_p : out std_logic;
clk : in std_logic);
end ir_rx_adcs;
architecture structural of ir_rx_adcs is
signal adc_values_s : adc_ltc2351_values_type(CHANNELS-1 downto 0) := (others => (others => '0'));
signal adc_done_s : std_logic;
begin -- structural
adc_values_o_p <= adc_values_s;
adc_done_o_p <= adc_done_s;
-- Two ADCs
adc_ltc2351_0 : adc_ltc2351
port map (
adc_out => adc_o_p(0),
adc_in => adc_i_p(0),
start_p => clk_sample_en_i_p,
values_p => adc_values_s(5 downto 0),
done_p => adc_done_s,
clk => clk
);
adc_ltc2351_1 : adc_ltc2351
port map (
adc_out => adc_o_p(1),
adc_in => adc_i_p(1),
start_p => clk_sample_en_i_p,
values_p => adc_values_s(11 downto 6),
done_p => open,
clk => clk
);
end structural;
| bsd-3-clause | aa1557e0da05149b3778d769611f0b6f | 0.437683 | 3.578397 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_transform_0_1/system_vga_transform_0_1_sim_netlist.vhdl | 1 | 143,471 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 14:49:03 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_transform_0_1 -prefix
-- system_vga_transform_0_1_ system_vga_transform_0_1_sim_netlist.vhdl
-- Design : system_vga_transform_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_transform_0_1_vga_transform is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
enable : in STD_LOGIC;
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_transform_0_1_vga_transform;
architecture STRUCTURE of system_vga_transform_0_1_vga_transform is
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 14 );
signal x_addr_out0 : STD_LOGIC_VECTOR ( 23 downto 14 );
signal \x_addr_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_1\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_2\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_3\ : STD_LOGIC;
signal \x_addr_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__1_n_3\ : STD_LOGIC;
signal x_addr_out0_carry_i_1_n_0 : STD_LOGIC;
signal x_addr_out0_carry_i_2_n_0 : STD_LOGIC;
signal x_addr_out0_carry_i_3_n_0 : STD_LOGIC;
signal x_addr_out0_carry_n_0 : STD_LOGIC;
signal x_addr_out0_carry_n_1 : STD_LOGIC;
signal x_addr_out0_carry_n_2 : STD_LOGIC;
signal x_addr_out0_carry_n_3 : STD_LOGIC;
signal \x_addr_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__8_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__8_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__8_n_3\ : STD_LOGIC;
signal x_addr_out2_carry_i_1_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_2_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_3_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_4_n_0 : STD_LOGIC;
signal x_addr_out2_carry_n_0 : STD_LOGIC;
signal x_addr_out2_carry_n_1 : STD_LOGIC;
signal x_addr_out2_carry_n_2 : STD_LOGIC;
signal x_addr_out2_carry_n_3 : STD_LOGIC;
signal \x_addr_out3__0_n_100\ : STD_LOGIC;
signal \x_addr_out3__0_n_101\ : STD_LOGIC;
signal \x_addr_out3__0_n_102\ : STD_LOGIC;
signal \x_addr_out3__0_n_103\ : STD_LOGIC;
signal \x_addr_out3__0_n_104\ : STD_LOGIC;
signal \x_addr_out3__0_n_105\ : STD_LOGIC;
signal \x_addr_out3__0_n_58\ : STD_LOGIC;
signal \x_addr_out3__0_n_59\ : STD_LOGIC;
signal \x_addr_out3__0_n_60\ : STD_LOGIC;
signal \x_addr_out3__0_n_61\ : STD_LOGIC;
signal \x_addr_out3__0_n_62\ : STD_LOGIC;
signal \x_addr_out3__0_n_63\ : STD_LOGIC;
signal \x_addr_out3__0_n_64\ : STD_LOGIC;
signal \x_addr_out3__0_n_65\ : STD_LOGIC;
signal \x_addr_out3__0_n_66\ : STD_LOGIC;
signal \x_addr_out3__0_n_67\ : STD_LOGIC;
signal \x_addr_out3__0_n_68\ : STD_LOGIC;
signal \x_addr_out3__0_n_69\ : STD_LOGIC;
signal \x_addr_out3__0_n_70\ : STD_LOGIC;
signal \x_addr_out3__0_n_71\ : STD_LOGIC;
signal \x_addr_out3__0_n_72\ : STD_LOGIC;
signal \x_addr_out3__0_n_73\ : STD_LOGIC;
signal \x_addr_out3__0_n_74\ : STD_LOGIC;
signal \x_addr_out3__0_n_75\ : STD_LOGIC;
signal \x_addr_out3__0_n_76\ : STD_LOGIC;
signal \x_addr_out3__0_n_77\ : STD_LOGIC;
signal \x_addr_out3__0_n_78\ : STD_LOGIC;
signal \x_addr_out3__0_n_79\ : STD_LOGIC;
signal \x_addr_out3__0_n_80\ : STD_LOGIC;
signal \x_addr_out3__0_n_81\ : STD_LOGIC;
signal \x_addr_out3__0_n_82\ : STD_LOGIC;
signal \x_addr_out3__0_n_83\ : STD_LOGIC;
signal \x_addr_out3__0_n_84\ : STD_LOGIC;
signal \x_addr_out3__0_n_85\ : STD_LOGIC;
signal \x_addr_out3__0_n_86\ : STD_LOGIC;
signal \x_addr_out3__0_n_87\ : STD_LOGIC;
signal \x_addr_out3__0_n_88\ : STD_LOGIC;
signal \x_addr_out3__0_n_89\ : STD_LOGIC;
signal \x_addr_out3__0_n_90\ : STD_LOGIC;
signal \x_addr_out3__0_n_91\ : STD_LOGIC;
signal \x_addr_out3__0_n_92\ : STD_LOGIC;
signal \x_addr_out3__0_n_93\ : STD_LOGIC;
signal \x_addr_out3__0_n_94\ : STD_LOGIC;
signal \x_addr_out3__0_n_95\ : STD_LOGIC;
signal \x_addr_out3__0_n_96\ : STD_LOGIC;
signal \x_addr_out3__0_n_97\ : STD_LOGIC;
signal \x_addr_out3__0_n_98\ : STD_LOGIC;
signal \x_addr_out3__0_n_99\ : STD_LOGIC;
signal \x_addr_out3__1_n_100\ : STD_LOGIC;
signal \x_addr_out3__1_n_101\ : STD_LOGIC;
signal \x_addr_out3__1_n_102\ : STD_LOGIC;
signal \x_addr_out3__1_n_103\ : STD_LOGIC;
signal \x_addr_out3__1_n_104\ : STD_LOGIC;
signal \x_addr_out3__1_n_105\ : STD_LOGIC;
signal \x_addr_out3__1_n_106\ : STD_LOGIC;
signal \x_addr_out3__1_n_107\ : STD_LOGIC;
signal \x_addr_out3__1_n_108\ : STD_LOGIC;
signal \x_addr_out3__1_n_109\ : STD_LOGIC;
signal \x_addr_out3__1_n_110\ : STD_LOGIC;
signal \x_addr_out3__1_n_111\ : STD_LOGIC;
signal \x_addr_out3__1_n_112\ : STD_LOGIC;
signal \x_addr_out3__1_n_113\ : STD_LOGIC;
signal \x_addr_out3__1_n_114\ : STD_LOGIC;
signal \x_addr_out3__1_n_115\ : STD_LOGIC;
signal \x_addr_out3__1_n_116\ : STD_LOGIC;
signal \x_addr_out3__1_n_117\ : STD_LOGIC;
signal \x_addr_out3__1_n_118\ : STD_LOGIC;
signal \x_addr_out3__1_n_119\ : STD_LOGIC;
signal \x_addr_out3__1_n_120\ : STD_LOGIC;
signal \x_addr_out3__1_n_121\ : STD_LOGIC;
signal \x_addr_out3__1_n_122\ : STD_LOGIC;
signal \x_addr_out3__1_n_123\ : STD_LOGIC;
signal \x_addr_out3__1_n_124\ : STD_LOGIC;
signal \x_addr_out3__1_n_125\ : STD_LOGIC;
signal \x_addr_out3__1_n_126\ : STD_LOGIC;
signal \x_addr_out3__1_n_127\ : STD_LOGIC;
signal \x_addr_out3__1_n_128\ : STD_LOGIC;
signal \x_addr_out3__1_n_129\ : STD_LOGIC;
signal \x_addr_out3__1_n_130\ : STD_LOGIC;
signal \x_addr_out3__1_n_131\ : STD_LOGIC;
signal \x_addr_out3__1_n_132\ : STD_LOGIC;
signal \x_addr_out3__1_n_133\ : STD_LOGIC;
signal \x_addr_out3__1_n_134\ : STD_LOGIC;
signal \x_addr_out3__1_n_135\ : STD_LOGIC;
signal \x_addr_out3__1_n_136\ : STD_LOGIC;
signal \x_addr_out3__1_n_137\ : STD_LOGIC;
signal \x_addr_out3__1_n_138\ : STD_LOGIC;
signal \x_addr_out3__1_n_139\ : STD_LOGIC;
signal \x_addr_out3__1_n_140\ : STD_LOGIC;
signal \x_addr_out3__1_n_141\ : STD_LOGIC;
signal \x_addr_out3__1_n_142\ : STD_LOGIC;
signal \x_addr_out3__1_n_143\ : STD_LOGIC;
signal \x_addr_out3__1_n_144\ : STD_LOGIC;
signal \x_addr_out3__1_n_145\ : STD_LOGIC;
signal \x_addr_out3__1_n_146\ : STD_LOGIC;
signal \x_addr_out3__1_n_147\ : STD_LOGIC;
signal \x_addr_out3__1_n_148\ : STD_LOGIC;
signal \x_addr_out3__1_n_149\ : STD_LOGIC;
signal \x_addr_out3__1_n_150\ : STD_LOGIC;
signal \x_addr_out3__1_n_151\ : STD_LOGIC;
signal \x_addr_out3__1_n_152\ : STD_LOGIC;
signal \x_addr_out3__1_n_153\ : STD_LOGIC;
signal \x_addr_out3__1_n_58\ : STD_LOGIC;
signal \x_addr_out3__1_n_59\ : STD_LOGIC;
signal \x_addr_out3__1_n_60\ : STD_LOGIC;
signal \x_addr_out3__1_n_61\ : STD_LOGIC;
signal \x_addr_out3__1_n_62\ : STD_LOGIC;
signal \x_addr_out3__1_n_63\ : STD_LOGIC;
signal \x_addr_out3__1_n_64\ : STD_LOGIC;
signal \x_addr_out3__1_n_65\ : STD_LOGIC;
signal \x_addr_out3__1_n_66\ : STD_LOGIC;
signal \x_addr_out3__1_n_67\ : STD_LOGIC;
signal \x_addr_out3__1_n_68\ : STD_LOGIC;
signal \x_addr_out3__1_n_69\ : STD_LOGIC;
signal \x_addr_out3__1_n_70\ : STD_LOGIC;
signal \x_addr_out3__1_n_71\ : STD_LOGIC;
signal \x_addr_out3__1_n_72\ : STD_LOGIC;
signal \x_addr_out3__1_n_73\ : STD_LOGIC;
signal \x_addr_out3__1_n_74\ : STD_LOGIC;
signal \x_addr_out3__1_n_75\ : STD_LOGIC;
signal \x_addr_out3__1_n_76\ : STD_LOGIC;
signal \x_addr_out3__1_n_77\ : STD_LOGIC;
signal \x_addr_out3__1_n_78\ : STD_LOGIC;
signal \x_addr_out3__1_n_79\ : STD_LOGIC;
signal \x_addr_out3__1_n_80\ : STD_LOGIC;
signal \x_addr_out3__1_n_81\ : STD_LOGIC;
signal \x_addr_out3__1_n_82\ : STD_LOGIC;
signal \x_addr_out3__1_n_83\ : STD_LOGIC;
signal \x_addr_out3__1_n_84\ : STD_LOGIC;
signal \x_addr_out3__1_n_85\ : STD_LOGIC;
signal \x_addr_out3__1_n_86\ : STD_LOGIC;
signal \x_addr_out3__1_n_87\ : STD_LOGIC;
signal \x_addr_out3__1_n_88\ : STD_LOGIC;
signal \x_addr_out3__1_n_89\ : STD_LOGIC;
signal \x_addr_out3__1_n_90\ : STD_LOGIC;
signal \x_addr_out3__1_n_91\ : STD_LOGIC;
signal \x_addr_out3__1_n_92\ : STD_LOGIC;
signal \x_addr_out3__1_n_93\ : STD_LOGIC;
signal \x_addr_out3__1_n_94\ : STD_LOGIC;
signal \x_addr_out3__1_n_95\ : STD_LOGIC;
signal \x_addr_out3__1_n_96\ : STD_LOGIC;
signal \x_addr_out3__1_n_97\ : STD_LOGIC;
signal \x_addr_out3__1_n_98\ : STD_LOGIC;
signal \x_addr_out3__1_n_99\ : STD_LOGIC;
signal \x_addr_out3__2_n_100\ : STD_LOGIC;
signal \x_addr_out3__2_n_101\ : STD_LOGIC;
signal \x_addr_out3__2_n_102\ : STD_LOGIC;
signal \x_addr_out3__2_n_103\ : STD_LOGIC;
signal \x_addr_out3__2_n_104\ : STD_LOGIC;
signal \x_addr_out3__2_n_105\ : STD_LOGIC;
signal \x_addr_out3__2_n_58\ : STD_LOGIC;
signal \x_addr_out3__2_n_59\ : STD_LOGIC;
signal \x_addr_out3__2_n_60\ : STD_LOGIC;
signal \x_addr_out3__2_n_61\ : STD_LOGIC;
signal \x_addr_out3__2_n_62\ : STD_LOGIC;
signal \x_addr_out3__2_n_63\ : STD_LOGIC;
signal \x_addr_out3__2_n_64\ : STD_LOGIC;
signal \x_addr_out3__2_n_65\ : STD_LOGIC;
signal \x_addr_out3__2_n_66\ : STD_LOGIC;
signal \x_addr_out3__2_n_67\ : STD_LOGIC;
signal \x_addr_out3__2_n_68\ : STD_LOGIC;
signal \x_addr_out3__2_n_69\ : STD_LOGIC;
signal \x_addr_out3__2_n_70\ : STD_LOGIC;
signal \x_addr_out3__2_n_71\ : STD_LOGIC;
signal \x_addr_out3__2_n_72\ : STD_LOGIC;
signal \x_addr_out3__2_n_73\ : STD_LOGIC;
signal \x_addr_out3__2_n_74\ : STD_LOGIC;
signal \x_addr_out3__2_n_75\ : STD_LOGIC;
signal \x_addr_out3__2_n_76\ : STD_LOGIC;
signal \x_addr_out3__2_n_77\ : STD_LOGIC;
signal \x_addr_out3__2_n_78\ : STD_LOGIC;
signal \x_addr_out3__2_n_79\ : STD_LOGIC;
signal \x_addr_out3__2_n_80\ : STD_LOGIC;
signal \x_addr_out3__2_n_81\ : STD_LOGIC;
signal \x_addr_out3__2_n_82\ : STD_LOGIC;
signal \x_addr_out3__2_n_83\ : STD_LOGIC;
signal \x_addr_out3__2_n_84\ : STD_LOGIC;
signal \x_addr_out3__2_n_85\ : STD_LOGIC;
signal \x_addr_out3__2_n_86\ : STD_LOGIC;
signal \x_addr_out3__2_n_87\ : STD_LOGIC;
signal \x_addr_out3__2_n_88\ : STD_LOGIC;
signal \x_addr_out3__2_n_89\ : STD_LOGIC;
signal \x_addr_out3__2_n_90\ : STD_LOGIC;
signal \x_addr_out3__2_n_91\ : STD_LOGIC;
signal \x_addr_out3__2_n_92\ : STD_LOGIC;
signal \x_addr_out3__2_n_93\ : STD_LOGIC;
signal \x_addr_out3__2_n_94\ : STD_LOGIC;
signal \x_addr_out3__2_n_95\ : STD_LOGIC;
signal \x_addr_out3__2_n_96\ : STD_LOGIC;
signal \x_addr_out3__2_n_97\ : STD_LOGIC;
signal \x_addr_out3__2_n_98\ : STD_LOGIC;
signal \x_addr_out3__2_n_99\ : STD_LOGIC;
signal x_addr_out3_n_100 : STD_LOGIC;
signal x_addr_out3_n_101 : STD_LOGIC;
signal x_addr_out3_n_102 : STD_LOGIC;
signal x_addr_out3_n_103 : STD_LOGIC;
signal x_addr_out3_n_104 : STD_LOGIC;
signal x_addr_out3_n_105 : STD_LOGIC;
signal x_addr_out3_n_106 : STD_LOGIC;
signal x_addr_out3_n_107 : STD_LOGIC;
signal x_addr_out3_n_108 : STD_LOGIC;
signal x_addr_out3_n_109 : STD_LOGIC;
signal x_addr_out3_n_110 : STD_LOGIC;
signal x_addr_out3_n_111 : STD_LOGIC;
signal x_addr_out3_n_112 : STD_LOGIC;
signal x_addr_out3_n_113 : STD_LOGIC;
signal x_addr_out3_n_114 : STD_LOGIC;
signal x_addr_out3_n_115 : STD_LOGIC;
signal x_addr_out3_n_116 : STD_LOGIC;
signal x_addr_out3_n_117 : STD_LOGIC;
signal x_addr_out3_n_118 : STD_LOGIC;
signal x_addr_out3_n_119 : STD_LOGIC;
signal x_addr_out3_n_120 : STD_LOGIC;
signal x_addr_out3_n_121 : STD_LOGIC;
signal x_addr_out3_n_122 : STD_LOGIC;
signal x_addr_out3_n_123 : STD_LOGIC;
signal x_addr_out3_n_124 : STD_LOGIC;
signal x_addr_out3_n_125 : STD_LOGIC;
signal x_addr_out3_n_126 : STD_LOGIC;
signal x_addr_out3_n_127 : STD_LOGIC;
signal x_addr_out3_n_128 : STD_LOGIC;
signal x_addr_out3_n_129 : STD_LOGIC;
signal x_addr_out3_n_130 : STD_LOGIC;
signal x_addr_out3_n_131 : STD_LOGIC;
signal x_addr_out3_n_132 : STD_LOGIC;
signal x_addr_out3_n_133 : STD_LOGIC;
signal x_addr_out3_n_134 : STD_LOGIC;
signal x_addr_out3_n_135 : STD_LOGIC;
signal x_addr_out3_n_136 : STD_LOGIC;
signal x_addr_out3_n_137 : STD_LOGIC;
signal x_addr_out3_n_138 : STD_LOGIC;
signal x_addr_out3_n_139 : STD_LOGIC;
signal x_addr_out3_n_140 : STD_LOGIC;
signal x_addr_out3_n_141 : STD_LOGIC;
signal x_addr_out3_n_142 : STD_LOGIC;
signal x_addr_out3_n_143 : STD_LOGIC;
signal x_addr_out3_n_144 : STD_LOGIC;
signal x_addr_out3_n_145 : STD_LOGIC;
signal x_addr_out3_n_146 : STD_LOGIC;
signal x_addr_out3_n_147 : STD_LOGIC;
signal x_addr_out3_n_148 : STD_LOGIC;
signal x_addr_out3_n_149 : STD_LOGIC;
signal x_addr_out3_n_150 : STD_LOGIC;
signal x_addr_out3_n_151 : STD_LOGIC;
signal x_addr_out3_n_152 : STD_LOGIC;
signal x_addr_out3_n_153 : STD_LOGIC;
signal x_addr_out3_n_58 : STD_LOGIC;
signal x_addr_out3_n_59 : STD_LOGIC;
signal x_addr_out3_n_60 : STD_LOGIC;
signal x_addr_out3_n_61 : STD_LOGIC;
signal x_addr_out3_n_62 : STD_LOGIC;
signal x_addr_out3_n_63 : STD_LOGIC;
signal x_addr_out3_n_64 : STD_LOGIC;
signal x_addr_out3_n_65 : STD_LOGIC;
signal x_addr_out3_n_66 : STD_LOGIC;
signal x_addr_out3_n_67 : STD_LOGIC;
signal x_addr_out3_n_68 : STD_LOGIC;
signal x_addr_out3_n_69 : STD_LOGIC;
signal x_addr_out3_n_70 : STD_LOGIC;
signal x_addr_out3_n_71 : STD_LOGIC;
signal x_addr_out3_n_72 : STD_LOGIC;
signal x_addr_out3_n_73 : STD_LOGIC;
signal x_addr_out3_n_74 : STD_LOGIC;
signal x_addr_out3_n_75 : STD_LOGIC;
signal x_addr_out3_n_76 : STD_LOGIC;
signal x_addr_out3_n_77 : STD_LOGIC;
signal x_addr_out3_n_78 : STD_LOGIC;
signal x_addr_out3_n_79 : STD_LOGIC;
signal x_addr_out3_n_80 : STD_LOGIC;
signal x_addr_out3_n_81 : STD_LOGIC;
signal x_addr_out3_n_82 : STD_LOGIC;
signal x_addr_out3_n_83 : STD_LOGIC;
signal x_addr_out3_n_84 : STD_LOGIC;
signal x_addr_out3_n_85 : STD_LOGIC;
signal x_addr_out3_n_86 : STD_LOGIC;
signal x_addr_out3_n_87 : STD_LOGIC;
signal x_addr_out3_n_88 : STD_LOGIC;
signal x_addr_out3_n_89 : STD_LOGIC;
signal x_addr_out3_n_90 : STD_LOGIC;
signal x_addr_out3_n_91 : STD_LOGIC;
signal x_addr_out3_n_92 : STD_LOGIC;
signal x_addr_out3_n_93 : STD_LOGIC;
signal x_addr_out3_n_94 : STD_LOGIC;
signal x_addr_out3_n_95 : STD_LOGIC;
signal x_addr_out3_n_96 : STD_LOGIC;
signal x_addr_out3_n_97 : STD_LOGIC;
signal x_addr_out3_n_98 : STD_LOGIC;
signal x_addr_out3_n_99 : STD_LOGIC;
signal \x_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_1\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_2\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_3\ : STD_LOGIC;
signal \y_addr_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__1_n_3\ : STD_LOGIC;
signal y_addr_out0_carry_i_1_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_2_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_3_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_4_n_0 : STD_LOGIC;
signal y_addr_out0_carry_n_0 : STD_LOGIC;
signal y_addr_out0_carry_n_1 : STD_LOGIC;
signal y_addr_out0_carry_n_2 : STD_LOGIC;
signal y_addr_out0_carry_n_3 : STD_LOGIC;
signal y_addr_out2 : STD_LOGIC_VECTOR ( 37 downto 28 );
signal \y_addr_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__8_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__8_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__8_n_3\ : STD_LOGIC;
signal y_addr_out2_carry_i_1_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_2_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_3_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_4_n_0 : STD_LOGIC;
signal y_addr_out2_carry_n_0 : STD_LOGIC;
signal y_addr_out2_carry_n_1 : STD_LOGIC;
signal y_addr_out2_carry_n_2 : STD_LOGIC;
signal y_addr_out2_carry_n_3 : STD_LOGIC;
signal \y_addr_out3__0_n_100\ : STD_LOGIC;
signal \y_addr_out3__0_n_101\ : STD_LOGIC;
signal \y_addr_out3__0_n_102\ : STD_LOGIC;
signal \y_addr_out3__0_n_103\ : STD_LOGIC;
signal \y_addr_out3__0_n_104\ : STD_LOGIC;
signal \y_addr_out3__0_n_105\ : STD_LOGIC;
signal \y_addr_out3__0_n_58\ : STD_LOGIC;
signal \y_addr_out3__0_n_59\ : STD_LOGIC;
signal \y_addr_out3__0_n_60\ : STD_LOGIC;
signal \y_addr_out3__0_n_61\ : STD_LOGIC;
signal \y_addr_out3__0_n_62\ : STD_LOGIC;
signal \y_addr_out3__0_n_63\ : STD_LOGIC;
signal \y_addr_out3__0_n_64\ : STD_LOGIC;
signal \y_addr_out3__0_n_65\ : STD_LOGIC;
signal \y_addr_out3__0_n_66\ : STD_LOGIC;
signal \y_addr_out3__0_n_67\ : STD_LOGIC;
signal \y_addr_out3__0_n_68\ : STD_LOGIC;
signal \y_addr_out3__0_n_69\ : STD_LOGIC;
signal \y_addr_out3__0_n_70\ : STD_LOGIC;
signal \y_addr_out3__0_n_71\ : STD_LOGIC;
signal \y_addr_out3__0_n_72\ : STD_LOGIC;
signal \y_addr_out3__0_n_73\ : STD_LOGIC;
signal \y_addr_out3__0_n_74\ : STD_LOGIC;
signal \y_addr_out3__0_n_75\ : STD_LOGIC;
signal \y_addr_out3__0_n_76\ : STD_LOGIC;
signal \y_addr_out3__0_n_77\ : STD_LOGIC;
signal \y_addr_out3__0_n_78\ : STD_LOGIC;
signal \y_addr_out3__0_n_79\ : STD_LOGIC;
signal \y_addr_out3__0_n_80\ : STD_LOGIC;
signal \y_addr_out3__0_n_81\ : STD_LOGIC;
signal \y_addr_out3__0_n_82\ : STD_LOGIC;
signal \y_addr_out3__0_n_83\ : STD_LOGIC;
signal \y_addr_out3__0_n_84\ : STD_LOGIC;
signal \y_addr_out3__0_n_85\ : STD_LOGIC;
signal \y_addr_out3__0_n_86\ : STD_LOGIC;
signal \y_addr_out3__0_n_87\ : STD_LOGIC;
signal \y_addr_out3__0_n_88\ : STD_LOGIC;
signal \y_addr_out3__0_n_89\ : STD_LOGIC;
signal \y_addr_out3__0_n_90\ : STD_LOGIC;
signal \y_addr_out3__0_n_91\ : STD_LOGIC;
signal \y_addr_out3__0_n_92\ : STD_LOGIC;
signal \y_addr_out3__0_n_93\ : STD_LOGIC;
signal \y_addr_out3__0_n_94\ : STD_LOGIC;
signal \y_addr_out3__0_n_95\ : STD_LOGIC;
signal \y_addr_out3__0_n_96\ : STD_LOGIC;
signal \y_addr_out3__0_n_97\ : STD_LOGIC;
signal \y_addr_out3__0_n_98\ : STD_LOGIC;
signal \y_addr_out3__0_n_99\ : STD_LOGIC;
signal \y_addr_out3__1_n_100\ : STD_LOGIC;
signal \y_addr_out3__1_n_101\ : STD_LOGIC;
signal \y_addr_out3__1_n_102\ : STD_LOGIC;
signal \y_addr_out3__1_n_103\ : STD_LOGIC;
signal \y_addr_out3__1_n_104\ : STD_LOGIC;
signal \y_addr_out3__1_n_105\ : STD_LOGIC;
signal \y_addr_out3__1_n_106\ : STD_LOGIC;
signal \y_addr_out3__1_n_107\ : STD_LOGIC;
signal \y_addr_out3__1_n_108\ : STD_LOGIC;
signal \y_addr_out3__1_n_109\ : STD_LOGIC;
signal \y_addr_out3__1_n_110\ : STD_LOGIC;
signal \y_addr_out3__1_n_111\ : STD_LOGIC;
signal \y_addr_out3__1_n_112\ : STD_LOGIC;
signal \y_addr_out3__1_n_113\ : STD_LOGIC;
signal \y_addr_out3__1_n_114\ : STD_LOGIC;
signal \y_addr_out3__1_n_115\ : STD_LOGIC;
signal \y_addr_out3__1_n_116\ : STD_LOGIC;
signal \y_addr_out3__1_n_117\ : STD_LOGIC;
signal \y_addr_out3__1_n_118\ : STD_LOGIC;
signal \y_addr_out3__1_n_119\ : STD_LOGIC;
signal \y_addr_out3__1_n_120\ : STD_LOGIC;
signal \y_addr_out3__1_n_121\ : STD_LOGIC;
signal \y_addr_out3__1_n_122\ : STD_LOGIC;
signal \y_addr_out3__1_n_123\ : STD_LOGIC;
signal \y_addr_out3__1_n_124\ : STD_LOGIC;
signal \y_addr_out3__1_n_125\ : STD_LOGIC;
signal \y_addr_out3__1_n_126\ : STD_LOGIC;
signal \y_addr_out3__1_n_127\ : STD_LOGIC;
signal \y_addr_out3__1_n_128\ : STD_LOGIC;
signal \y_addr_out3__1_n_129\ : STD_LOGIC;
signal \y_addr_out3__1_n_130\ : STD_LOGIC;
signal \y_addr_out3__1_n_131\ : STD_LOGIC;
signal \y_addr_out3__1_n_132\ : STD_LOGIC;
signal \y_addr_out3__1_n_133\ : STD_LOGIC;
signal \y_addr_out3__1_n_134\ : STD_LOGIC;
signal \y_addr_out3__1_n_135\ : STD_LOGIC;
signal \y_addr_out3__1_n_136\ : STD_LOGIC;
signal \y_addr_out3__1_n_137\ : STD_LOGIC;
signal \y_addr_out3__1_n_138\ : STD_LOGIC;
signal \y_addr_out3__1_n_139\ : STD_LOGIC;
signal \y_addr_out3__1_n_140\ : STD_LOGIC;
signal \y_addr_out3__1_n_141\ : STD_LOGIC;
signal \y_addr_out3__1_n_142\ : STD_LOGIC;
signal \y_addr_out3__1_n_143\ : STD_LOGIC;
signal \y_addr_out3__1_n_144\ : STD_LOGIC;
signal \y_addr_out3__1_n_145\ : STD_LOGIC;
signal \y_addr_out3__1_n_146\ : STD_LOGIC;
signal \y_addr_out3__1_n_147\ : STD_LOGIC;
signal \y_addr_out3__1_n_148\ : STD_LOGIC;
signal \y_addr_out3__1_n_149\ : STD_LOGIC;
signal \y_addr_out3__1_n_150\ : STD_LOGIC;
signal \y_addr_out3__1_n_151\ : STD_LOGIC;
signal \y_addr_out3__1_n_152\ : STD_LOGIC;
signal \y_addr_out3__1_n_153\ : STD_LOGIC;
signal \y_addr_out3__1_n_58\ : STD_LOGIC;
signal \y_addr_out3__1_n_59\ : STD_LOGIC;
signal \y_addr_out3__1_n_60\ : STD_LOGIC;
signal \y_addr_out3__1_n_61\ : STD_LOGIC;
signal \y_addr_out3__1_n_62\ : STD_LOGIC;
signal \y_addr_out3__1_n_63\ : STD_LOGIC;
signal \y_addr_out3__1_n_64\ : STD_LOGIC;
signal \y_addr_out3__1_n_65\ : STD_LOGIC;
signal \y_addr_out3__1_n_66\ : STD_LOGIC;
signal \y_addr_out3__1_n_67\ : STD_LOGIC;
signal \y_addr_out3__1_n_68\ : STD_LOGIC;
signal \y_addr_out3__1_n_69\ : STD_LOGIC;
signal \y_addr_out3__1_n_70\ : STD_LOGIC;
signal \y_addr_out3__1_n_71\ : STD_LOGIC;
signal \y_addr_out3__1_n_72\ : STD_LOGIC;
signal \y_addr_out3__1_n_73\ : STD_LOGIC;
signal \y_addr_out3__1_n_74\ : STD_LOGIC;
signal \y_addr_out3__1_n_75\ : STD_LOGIC;
signal \y_addr_out3__1_n_76\ : STD_LOGIC;
signal \y_addr_out3__1_n_77\ : STD_LOGIC;
signal \y_addr_out3__1_n_78\ : STD_LOGIC;
signal \y_addr_out3__1_n_79\ : STD_LOGIC;
signal \y_addr_out3__1_n_80\ : STD_LOGIC;
signal \y_addr_out3__1_n_81\ : STD_LOGIC;
signal \y_addr_out3__1_n_82\ : STD_LOGIC;
signal \y_addr_out3__1_n_83\ : STD_LOGIC;
signal \y_addr_out3__1_n_84\ : STD_LOGIC;
signal \y_addr_out3__1_n_85\ : STD_LOGIC;
signal \y_addr_out3__1_n_86\ : STD_LOGIC;
signal \y_addr_out3__1_n_87\ : STD_LOGIC;
signal \y_addr_out3__1_n_88\ : STD_LOGIC;
signal \y_addr_out3__1_n_89\ : STD_LOGIC;
signal \y_addr_out3__1_n_90\ : STD_LOGIC;
signal \y_addr_out3__1_n_91\ : STD_LOGIC;
signal \y_addr_out3__1_n_92\ : STD_LOGIC;
signal \y_addr_out3__1_n_93\ : STD_LOGIC;
signal \y_addr_out3__1_n_94\ : STD_LOGIC;
signal \y_addr_out3__1_n_95\ : STD_LOGIC;
signal \y_addr_out3__1_n_96\ : STD_LOGIC;
signal \y_addr_out3__1_n_97\ : STD_LOGIC;
signal \y_addr_out3__1_n_98\ : STD_LOGIC;
signal \y_addr_out3__1_n_99\ : STD_LOGIC;
signal \y_addr_out3__2_n_100\ : STD_LOGIC;
signal \y_addr_out3__2_n_101\ : STD_LOGIC;
signal \y_addr_out3__2_n_102\ : STD_LOGIC;
signal \y_addr_out3__2_n_103\ : STD_LOGIC;
signal \y_addr_out3__2_n_104\ : STD_LOGIC;
signal \y_addr_out3__2_n_105\ : STD_LOGIC;
signal \y_addr_out3__2_n_58\ : STD_LOGIC;
signal \y_addr_out3__2_n_59\ : STD_LOGIC;
signal \y_addr_out3__2_n_60\ : STD_LOGIC;
signal \y_addr_out3__2_n_61\ : STD_LOGIC;
signal \y_addr_out3__2_n_62\ : STD_LOGIC;
signal \y_addr_out3__2_n_63\ : STD_LOGIC;
signal \y_addr_out3__2_n_64\ : STD_LOGIC;
signal \y_addr_out3__2_n_65\ : STD_LOGIC;
signal \y_addr_out3__2_n_66\ : STD_LOGIC;
signal \y_addr_out3__2_n_67\ : STD_LOGIC;
signal \y_addr_out3__2_n_68\ : STD_LOGIC;
signal \y_addr_out3__2_n_69\ : STD_LOGIC;
signal \y_addr_out3__2_n_70\ : STD_LOGIC;
signal \y_addr_out3__2_n_71\ : STD_LOGIC;
signal \y_addr_out3__2_n_72\ : STD_LOGIC;
signal \y_addr_out3__2_n_73\ : STD_LOGIC;
signal \y_addr_out3__2_n_74\ : STD_LOGIC;
signal \y_addr_out3__2_n_75\ : STD_LOGIC;
signal \y_addr_out3__2_n_76\ : STD_LOGIC;
signal \y_addr_out3__2_n_77\ : STD_LOGIC;
signal \y_addr_out3__2_n_78\ : STD_LOGIC;
signal \y_addr_out3__2_n_79\ : STD_LOGIC;
signal \y_addr_out3__2_n_80\ : STD_LOGIC;
signal \y_addr_out3__2_n_81\ : STD_LOGIC;
signal \y_addr_out3__2_n_82\ : STD_LOGIC;
signal \y_addr_out3__2_n_83\ : STD_LOGIC;
signal \y_addr_out3__2_n_84\ : STD_LOGIC;
signal \y_addr_out3__2_n_85\ : STD_LOGIC;
signal \y_addr_out3__2_n_86\ : STD_LOGIC;
signal \y_addr_out3__2_n_87\ : STD_LOGIC;
signal \y_addr_out3__2_n_88\ : STD_LOGIC;
signal \y_addr_out3__2_n_89\ : STD_LOGIC;
signal \y_addr_out3__2_n_90\ : STD_LOGIC;
signal \y_addr_out3__2_n_91\ : STD_LOGIC;
signal \y_addr_out3__2_n_92\ : STD_LOGIC;
signal \y_addr_out3__2_n_93\ : STD_LOGIC;
signal \y_addr_out3__2_n_94\ : STD_LOGIC;
signal \y_addr_out3__2_n_95\ : STD_LOGIC;
signal \y_addr_out3__2_n_96\ : STD_LOGIC;
signal \y_addr_out3__2_n_97\ : STD_LOGIC;
signal \y_addr_out3__2_n_98\ : STD_LOGIC;
signal \y_addr_out3__2_n_99\ : STD_LOGIC;
signal y_addr_out3_n_100 : STD_LOGIC;
signal y_addr_out3_n_101 : STD_LOGIC;
signal y_addr_out3_n_102 : STD_LOGIC;
signal y_addr_out3_n_103 : STD_LOGIC;
signal y_addr_out3_n_104 : STD_LOGIC;
signal y_addr_out3_n_105 : STD_LOGIC;
signal y_addr_out3_n_106 : STD_LOGIC;
signal y_addr_out3_n_107 : STD_LOGIC;
signal y_addr_out3_n_108 : STD_LOGIC;
signal y_addr_out3_n_109 : STD_LOGIC;
signal y_addr_out3_n_110 : STD_LOGIC;
signal y_addr_out3_n_111 : STD_LOGIC;
signal y_addr_out3_n_112 : STD_LOGIC;
signal y_addr_out3_n_113 : STD_LOGIC;
signal y_addr_out3_n_114 : STD_LOGIC;
signal y_addr_out3_n_115 : STD_LOGIC;
signal y_addr_out3_n_116 : STD_LOGIC;
signal y_addr_out3_n_117 : STD_LOGIC;
signal y_addr_out3_n_118 : STD_LOGIC;
signal y_addr_out3_n_119 : STD_LOGIC;
signal y_addr_out3_n_120 : STD_LOGIC;
signal y_addr_out3_n_121 : STD_LOGIC;
signal y_addr_out3_n_122 : STD_LOGIC;
signal y_addr_out3_n_123 : STD_LOGIC;
signal y_addr_out3_n_124 : STD_LOGIC;
signal y_addr_out3_n_125 : STD_LOGIC;
signal y_addr_out3_n_126 : STD_LOGIC;
signal y_addr_out3_n_127 : STD_LOGIC;
signal y_addr_out3_n_128 : STD_LOGIC;
signal y_addr_out3_n_129 : STD_LOGIC;
signal y_addr_out3_n_130 : STD_LOGIC;
signal y_addr_out3_n_131 : STD_LOGIC;
signal y_addr_out3_n_132 : STD_LOGIC;
signal y_addr_out3_n_133 : STD_LOGIC;
signal y_addr_out3_n_134 : STD_LOGIC;
signal y_addr_out3_n_135 : STD_LOGIC;
signal y_addr_out3_n_136 : STD_LOGIC;
signal y_addr_out3_n_137 : STD_LOGIC;
signal y_addr_out3_n_138 : STD_LOGIC;
signal y_addr_out3_n_139 : STD_LOGIC;
signal y_addr_out3_n_140 : STD_LOGIC;
signal y_addr_out3_n_141 : STD_LOGIC;
signal y_addr_out3_n_142 : STD_LOGIC;
signal y_addr_out3_n_143 : STD_LOGIC;
signal y_addr_out3_n_144 : STD_LOGIC;
signal y_addr_out3_n_145 : STD_LOGIC;
signal y_addr_out3_n_146 : STD_LOGIC;
signal y_addr_out3_n_147 : STD_LOGIC;
signal y_addr_out3_n_148 : STD_LOGIC;
signal y_addr_out3_n_149 : STD_LOGIC;
signal y_addr_out3_n_150 : STD_LOGIC;
signal y_addr_out3_n_151 : STD_LOGIC;
signal y_addr_out3_n_152 : STD_LOGIC;
signal y_addr_out3_n_153 : STD_LOGIC;
signal y_addr_out3_n_58 : STD_LOGIC;
signal y_addr_out3_n_59 : STD_LOGIC;
signal y_addr_out3_n_60 : STD_LOGIC;
signal y_addr_out3_n_61 : STD_LOGIC;
signal y_addr_out3_n_62 : STD_LOGIC;
signal y_addr_out3_n_63 : STD_LOGIC;
signal y_addr_out3_n_64 : STD_LOGIC;
signal y_addr_out3_n_65 : STD_LOGIC;
signal y_addr_out3_n_66 : STD_LOGIC;
signal y_addr_out3_n_67 : STD_LOGIC;
signal y_addr_out3_n_68 : STD_LOGIC;
signal y_addr_out3_n_69 : STD_LOGIC;
signal y_addr_out3_n_70 : STD_LOGIC;
signal y_addr_out3_n_71 : STD_LOGIC;
signal y_addr_out3_n_72 : STD_LOGIC;
signal y_addr_out3_n_73 : STD_LOGIC;
signal y_addr_out3_n_74 : STD_LOGIC;
signal y_addr_out3_n_75 : STD_LOGIC;
signal y_addr_out3_n_76 : STD_LOGIC;
signal y_addr_out3_n_77 : STD_LOGIC;
signal y_addr_out3_n_78 : STD_LOGIC;
signal y_addr_out3_n_79 : STD_LOGIC;
signal y_addr_out3_n_80 : STD_LOGIC;
signal y_addr_out3_n_81 : STD_LOGIC;
signal y_addr_out3_n_82 : STD_LOGIC;
signal y_addr_out3_n_83 : STD_LOGIC;
signal y_addr_out3_n_84 : STD_LOGIC;
signal y_addr_out3_n_85 : STD_LOGIC;
signal y_addr_out3_n_86 : STD_LOGIC;
signal y_addr_out3_n_87 : STD_LOGIC;
signal y_addr_out3_n_88 : STD_LOGIC;
signal y_addr_out3_n_89 : STD_LOGIC;
signal y_addr_out3_n_90 : STD_LOGIC;
signal y_addr_out3_n_91 : STD_LOGIC;
signal y_addr_out3_n_92 : STD_LOGIC;
signal y_addr_out3_n_93 : STD_LOGIC;
signal y_addr_out3_n_94 : STD_LOGIC;
signal y_addr_out3_n_95 : STD_LOGIC;
signal y_addr_out3_n_96 : STD_LOGIC;
signal y_addr_out3_n_97 : STD_LOGIC;
signal y_addr_out3_n_98 : STD_LOGIC;
signal y_addr_out3_n_99 : STD_LOGIC;
signal NLW_x_addr_out0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_x_addr_out0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_x_addr_out0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_x_addr_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_x_addr_out2_carry__8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_x_addr_out3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_x_addr_out3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_y_addr_out0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_addr_out0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_addr_out0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_y_addr_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_addr_out2_carry__8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_y_addr_out3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_y_addr_out3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of x_addr_out3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x_addr_out[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute METHODOLOGY_DRC_VIOS of y_addr_out3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__2\ : label is "{SYNTH-13 {cell *THIS*}}";
begin
x_addr_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => x_addr_out0_carry_n_0,
CO(2) => x_addr_out0_carry_n_1,
CO(1) => x_addr_out0_carry_n_2,
CO(0) => x_addr_out0_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => p_1_in(17 downto 14),
O(3 downto 1) => x_addr_out0(17 downto 15),
O(0) => NLW_x_addr_out0_carry_O_UNCONNECTED(0),
S(3) => x_addr_out0_carry_i_1_n_0,
S(2) => x_addr_out0_carry_i_2_n_0,
S(1) => x_addr_out0_carry_i_3_n_0,
S(0) => x_addr_out0(14)
);
\x_addr_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => x_addr_out0_carry_n_0,
CO(3) => \x_addr_out0_carry__0_n_0\,
CO(2) => \x_addr_out0_carry__0_n_1\,
CO(1) => \x_addr_out0_carry__0_n_2\,
CO(0) => \x_addr_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_1_in(21 downto 18),
O(3 downto 0) => x_addr_out0(21 downto 18),
S(3) => \x_addr_out0_carry__0_i_1_n_0\,
S(2) => \x_addr_out0_carry__0_i_2_n_0\,
S(1) => \x_addr_out0_carry__0_i_3_n_0\,
S(0) => \x_addr_out0_carry__0_i_4_n_0\
);
\x_addr_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(21),
I1 => t_x(7),
O => \x_addr_out0_carry__0_i_1_n_0\
);
\x_addr_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(20),
I1 => t_x(6),
O => \x_addr_out0_carry__0_i_2_n_0\
);
\x_addr_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(19),
I1 => t_x(5),
O => \x_addr_out0_carry__0_i_3_n_0\
);
\x_addr_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(18),
I1 => t_x(4),
O => \x_addr_out0_carry__0_i_4_n_0\
);
\x_addr_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out0_carry__0_n_0\,
CO(3 downto 1) => \NLW_x_addr_out0_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \x_addr_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_1_in(22),
O(3 downto 2) => \NLW_x_addr_out0_carry__1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => x_addr_out0(23 downto 22),
S(3 downto 2) => B"00",
S(1) => \x_addr_out0_carry__1_i_1_n_0\,
S(0) => \x_addr_out0_carry__1_i_2_n_0\
);
\x_addr_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(23),
I1 => t_x(9),
O => \x_addr_out0_carry__1_i_1_n_0\
);
\x_addr_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(22),
I1 => t_x(8),
O => \x_addr_out0_carry__1_i_2_n_0\
);
x_addr_out0_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(17),
I1 => t_x(3),
O => x_addr_out0_carry_i_1_n_0
);
x_addr_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(16),
I1 => t_x(2),
O => x_addr_out0_carry_i_2_n_0
);
x_addr_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(15),
I1 => t_x(1),
O => x_addr_out0_carry_i_3_n_0
);
x_addr_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(14),
I1 => t_x(0),
O => x_addr_out0(14)
);
x_addr_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => x_addr_out2_carry_n_0,
CO(2) => x_addr_out2_carry_n_1,
CO(1) => x_addr_out2_carry_n_2,
CO(0) => x_addr_out2_carry_n_3,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_102\,
DI(2) => \x_addr_out3__1_n_103\,
DI(1) => \x_addr_out3__1_n_104\,
DI(0) => \x_addr_out3__1_n_105\,
O(3 downto 0) => NLW_x_addr_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => x_addr_out2_carry_i_1_n_0,
S(2) => x_addr_out2_carry_i_2_n_0,
S(1) => x_addr_out2_carry_i_3_n_0,
S(0) => x_addr_out2_carry_i_4_n_0
);
\x_addr_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => x_addr_out2_carry_n_0,
CO(3) => \x_addr_out2_carry__0_n_0\,
CO(2) => \x_addr_out2_carry__0_n_1\,
CO(1) => \x_addr_out2_carry__0_n_2\,
CO(0) => \x_addr_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_98\,
DI(2) => \x_addr_out3__1_n_99\,
DI(1) => \x_addr_out3__1_n_100\,
DI(0) => \x_addr_out3__1_n_101\,
O(3 downto 0) => \NLW_x_addr_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__0_i_1_n_0\,
S(2) => \x_addr_out2_carry__0_i_2_n_0\,
S(1) => \x_addr_out2_carry__0_i_3_n_0\,
S(0) => \x_addr_out2_carry__0_i_4_n_0\
);
\x_addr_out2_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_98\,
I1 => x_addr_out3_n_98,
O => \x_addr_out2_carry__0_i_1_n_0\
);
\x_addr_out2_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_99\,
I1 => x_addr_out3_n_99,
O => \x_addr_out2_carry__0_i_2_n_0\
);
\x_addr_out2_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_100\,
I1 => x_addr_out3_n_100,
O => \x_addr_out2_carry__0_i_3_n_0\
);
\x_addr_out2_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_101\,
I1 => x_addr_out3_n_101,
O => \x_addr_out2_carry__0_i_4_n_0\
);
\x_addr_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__0_n_0\,
CO(3) => \x_addr_out2_carry__1_n_0\,
CO(2) => \x_addr_out2_carry__1_n_1\,
CO(1) => \x_addr_out2_carry__1_n_2\,
CO(0) => \x_addr_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_94\,
DI(2) => \x_addr_out3__1_n_95\,
DI(1) => \x_addr_out3__1_n_96\,
DI(0) => \x_addr_out3__1_n_97\,
O(3 downto 0) => \NLW_x_addr_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__1_i_1_n_0\,
S(2) => \x_addr_out2_carry__1_i_2_n_0\,
S(1) => \x_addr_out2_carry__1_i_3_n_0\,
S(0) => \x_addr_out2_carry__1_i_4_n_0\
);
\x_addr_out2_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_94\,
I1 => x_addr_out3_n_94,
O => \x_addr_out2_carry__1_i_1_n_0\
);
\x_addr_out2_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_95\,
I1 => x_addr_out3_n_95,
O => \x_addr_out2_carry__1_i_2_n_0\
);
\x_addr_out2_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_96\,
I1 => x_addr_out3_n_96,
O => \x_addr_out2_carry__1_i_3_n_0\
);
\x_addr_out2_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_97\,
I1 => x_addr_out3_n_97,
O => \x_addr_out2_carry__1_i_4_n_0\
);
\x_addr_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__1_n_0\,
CO(3) => \x_addr_out2_carry__2_n_0\,
CO(2) => \x_addr_out2_carry__2_n_1\,
CO(1) => \x_addr_out2_carry__2_n_2\,
CO(0) => \x_addr_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_90\,
DI(2) => \x_addr_out3__1_n_91\,
DI(1) => \x_addr_out3__1_n_92\,
DI(0) => \x_addr_out3__1_n_93\,
O(3 downto 0) => \NLW_x_addr_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__2_i_1_n_0\,
S(2) => \x_addr_out2_carry__2_i_2_n_0\,
S(1) => \x_addr_out2_carry__2_i_3_n_0\,
S(0) => \x_addr_out2_carry__2_i_4_n_0\
);
\x_addr_out2_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_90\,
I1 => x_addr_out3_n_90,
O => \x_addr_out2_carry__2_i_1_n_0\
);
\x_addr_out2_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_91\,
I1 => x_addr_out3_n_91,
O => \x_addr_out2_carry__2_i_2_n_0\
);
\x_addr_out2_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_92\,
I1 => x_addr_out3_n_92,
O => \x_addr_out2_carry__2_i_3_n_0\
);
\x_addr_out2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_93\,
I1 => x_addr_out3_n_93,
O => \x_addr_out2_carry__2_i_4_n_0\
);
\x_addr_out2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__2_n_0\,
CO(3) => \x_addr_out2_carry__3_n_0\,
CO(2) => \x_addr_out2_carry__3_n_1\,
CO(1) => \x_addr_out2_carry__3_n_2\,
CO(0) => \x_addr_out2_carry__3_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_103\,
DI(2) => \x_addr_out3__2_n_104\,
DI(1) => \x_addr_out3__2_n_105\,
DI(0) => \x_addr_out3__1_n_89\,
O(3 downto 0) => \NLW_x_addr_out2_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__3_i_1_n_0\,
S(2) => \x_addr_out2_carry__3_i_2_n_0\,
S(1) => \x_addr_out2_carry__3_i_3_n_0\,
S(0) => \x_addr_out2_carry__3_i_4_n_0\
);
\x_addr_out2_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_103\,
I1 => \x_addr_out3__0_n_103\,
O => \x_addr_out2_carry__3_i_1_n_0\
);
\x_addr_out2_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_104\,
I1 => \x_addr_out3__0_n_104\,
O => \x_addr_out2_carry__3_i_2_n_0\
);
\x_addr_out2_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_105\,
I1 => \x_addr_out3__0_n_105\,
O => \x_addr_out2_carry__3_i_3_n_0\
);
\x_addr_out2_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_89\,
I1 => x_addr_out3_n_89,
O => \x_addr_out2_carry__3_i_4_n_0\
);
\x_addr_out2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__3_n_0\,
CO(3) => \x_addr_out2_carry__4_n_0\,
CO(2) => \x_addr_out2_carry__4_n_1\,
CO(1) => \x_addr_out2_carry__4_n_2\,
CO(0) => \x_addr_out2_carry__4_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_99\,
DI(2) => \x_addr_out3__2_n_100\,
DI(1) => \x_addr_out3__2_n_101\,
DI(0) => \x_addr_out3__2_n_102\,
O(3 downto 0) => \NLW_x_addr_out2_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__4_i_1_n_0\,
S(2) => \x_addr_out2_carry__4_i_2_n_0\,
S(1) => \x_addr_out2_carry__4_i_3_n_0\,
S(0) => \x_addr_out2_carry__4_i_4_n_0\
);
\x_addr_out2_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_99\,
I1 => \x_addr_out3__0_n_99\,
O => \x_addr_out2_carry__4_i_1_n_0\
);
\x_addr_out2_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_100\,
I1 => \x_addr_out3__0_n_100\,
O => \x_addr_out2_carry__4_i_2_n_0\
);
\x_addr_out2_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_101\,
I1 => \x_addr_out3__0_n_101\,
O => \x_addr_out2_carry__4_i_3_n_0\
);
\x_addr_out2_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_102\,
I1 => \x_addr_out3__0_n_102\,
O => \x_addr_out2_carry__4_i_4_n_0\
);
\x_addr_out2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__4_n_0\,
CO(3) => \x_addr_out2_carry__5_n_0\,
CO(2) => \x_addr_out2_carry__5_n_1\,
CO(1) => \x_addr_out2_carry__5_n_2\,
CO(0) => \x_addr_out2_carry__5_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_95\,
DI(2) => \x_addr_out3__2_n_96\,
DI(1) => \x_addr_out3__2_n_97\,
DI(0) => \x_addr_out3__2_n_98\,
O(3 downto 0) => \NLW_x_addr_out2_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__5_i_1_n_0\,
S(2) => \x_addr_out2_carry__5_i_2_n_0\,
S(1) => \x_addr_out2_carry__5_i_3_n_0\,
S(0) => \x_addr_out2_carry__5_i_4_n_0\
);
\x_addr_out2_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_95\,
I1 => \x_addr_out3__0_n_95\,
O => \x_addr_out2_carry__5_i_1_n_0\
);
\x_addr_out2_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_96\,
I1 => \x_addr_out3__0_n_96\,
O => \x_addr_out2_carry__5_i_2_n_0\
);
\x_addr_out2_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_97\,
I1 => \x_addr_out3__0_n_97\,
O => \x_addr_out2_carry__5_i_3_n_0\
);
\x_addr_out2_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_98\,
I1 => \x_addr_out3__0_n_98\,
O => \x_addr_out2_carry__5_i_4_n_0\
);
\x_addr_out2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__5_n_0\,
CO(3) => \x_addr_out2_carry__6_n_0\,
CO(2) => \x_addr_out2_carry__6_n_1\,
CO(1) => \x_addr_out2_carry__6_n_2\,
CO(0) => \x_addr_out2_carry__6_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_91\,
DI(2) => \x_addr_out3__2_n_92\,
DI(1) => \x_addr_out3__2_n_93\,
DI(0) => \x_addr_out3__2_n_94\,
O(3 downto 0) => p_1_in(17 downto 14),
S(3) => \x_addr_out2_carry__6_i_1_n_0\,
S(2) => \x_addr_out2_carry__6_i_2_n_0\,
S(1) => \x_addr_out2_carry__6_i_3_n_0\,
S(0) => \x_addr_out2_carry__6_i_4_n_0\
);
\x_addr_out2_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_91\,
I1 => \x_addr_out3__0_n_91\,
O => \x_addr_out2_carry__6_i_1_n_0\
);
\x_addr_out2_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_92\,
I1 => \x_addr_out3__0_n_92\,
O => \x_addr_out2_carry__6_i_2_n_0\
);
\x_addr_out2_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_93\,
I1 => \x_addr_out3__0_n_93\,
O => \x_addr_out2_carry__6_i_3_n_0\
);
\x_addr_out2_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_94\,
I1 => \x_addr_out3__0_n_94\,
O => \x_addr_out2_carry__6_i_4_n_0\
);
\x_addr_out2_carry__7\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__6_n_0\,
CO(3) => \x_addr_out2_carry__7_n_0\,
CO(2) => \x_addr_out2_carry__7_n_1\,
CO(1) => \x_addr_out2_carry__7_n_2\,
CO(0) => \x_addr_out2_carry__7_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_87\,
DI(2) => \x_addr_out3__2_n_88\,
DI(1) => \x_addr_out3__2_n_89\,
DI(0) => \x_addr_out3__2_n_90\,
O(3 downto 0) => p_1_in(21 downto 18),
S(3) => \x_addr_out2_carry__7_i_1_n_0\,
S(2) => \x_addr_out2_carry__7_i_2_n_0\,
S(1) => \x_addr_out2_carry__7_i_3_n_0\,
S(0) => \x_addr_out2_carry__7_i_4_n_0\
);
\x_addr_out2_carry__7_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_87\,
I1 => \x_addr_out3__0_n_87\,
O => \x_addr_out2_carry__7_i_1_n_0\
);
\x_addr_out2_carry__7_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_88\,
I1 => \x_addr_out3__0_n_88\,
O => \x_addr_out2_carry__7_i_2_n_0\
);
\x_addr_out2_carry__7_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_89\,
I1 => \x_addr_out3__0_n_89\,
O => \x_addr_out2_carry__7_i_3_n_0\
);
\x_addr_out2_carry__7_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_90\,
I1 => \x_addr_out3__0_n_90\,
O => \x_addr_out2_carry__7_i_4_n_0\
);
\x_addr_out2_carry__8\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__7_n_0\,
CO(3 downto 1) => \NLW_x_addr_out2_carry__8_CO_UNCONNECTED\(3 downto 1),
CO(0) => \x_addr_out2_carry__8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_addr_out3__2_n_86\,
O(3 downto 2) => \NLW_x_addr_out2_carry__8_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_1_in(23 downto 22),
S(3 downto 2) => B"00",
S(1) => \x_addr_out2_carry__8_i_1_n_0\,
S(0) => \x_addr_out2_carry__8_i_2_n_0\
);
\x_addr_out2_carry__8_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_85\,
I1 => \x_addr_out3__0_n_85\,
O => \x_addr_out2_carry__8_i_1_n_0\
);
\x_addr_out2_carry__8_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_86\,
I1 => \x_addr_out3__0_n_86\,
O => \x_addr_out2_carry__8_i_2_n_0\
);
x_addr_out2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_102\,
I1 => x_addr_out3_n_102,
O => x_addr_out2_carry_i_1_n_0
);
x_addr_out2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_103\,
I1 => x_addr_out3_n_103,
O => x_addr_out2_carry_i_2_n_0
);
x_addr_out2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_104\,
I1 => x_addr_out3_n_104,
O => x_addr_out2_carry_i_3_n_0
);
x_addr_out2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_105\,
I1 => x_addr_out3_n_105,
O => x_addr_out2_carry_i_4_n_0
);
x_addr_out3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => y_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_x_addr_out3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m01(15),
B(16) => rot_m01(15),
B(15 downto 0) => rot_m01(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_x_addr_out3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_x_addr_out3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_x_addr_out3_OVERFLOW_UNCONNECTED,
P(47) => x_addr_out3_n_58,
P(46) => x_addr_out3_n_59,
P(45) => x_addr_out3_n_60,
P(44) => x_addr_out3_n_61,
P(43) => x_addr_out3_n_62,
P(42) => x_addr_out3_n_63,
P(41) => x_addr_out3_n_64,
P(40) => x_addr_out3_n_65,
P(39) => x_addr_out3_n_66,
P(38) => x_addr_out3_n_67,
P(37) => x_addr_out3_n_68,
P(36) => x_addr_out3_n_69,
P(35) => x_addr_out3_n_70,
P(34) => x_addr_out3_n_71,
P(33) => x_addr_out3_n_72,
P(32) => x_addr_out3_n_73,
P(31) => x_addr_out3_n_74,
P(30) => x_addr_out3_n_75,
P(29) => x_addr_out3_n_76,
P(28) => x_addr_out3_n_77,
P(27) => x_addr_out3_n_78,
P(26) => x_addr_out3_n_79,
P(25) => x_addr_out3_n_80,
P(24) => x_addr_out3_n_81,
P(23) => x_addr_out3_n_82,
P(22) => x_addr_out3_n_83,
P(21) => x_addr_out3_n_84,
P(20) => x_addr_out3_n_85,
P(19) => x_addr_out3_n_86,
P(18) => x_addr_out3_n_87,
P(17) => x_addr_out3_n_88,
P(16) => x_addr_out3_n_89,
P(15) => x_addr_out3_n_90,
P(14) => x_addr_out3_n_91,
P(13) => x_addr_out3_n_92,
P(12) => x_addr_out3_n_93,
P(11) => x_addr_out3_n_94,
P(10) => x_addr_out3_n_95,
P(9) => x_addr_out3_n_96,
P(8) => x_addr_out3_n_97,
P(7) => x_addr_out3_n_98,
P(6) => x_addr_out3_n_99,
P(5) => x_addr_out3_n_100,
P(4) => x_addr_out3_n_101,
P(3) => x_addr_out3_n_102,
P(2) => x_addr_out3_n_103,
P(1) => x_addr_out3_n_104,
P(0) => x_addr_out3_n_105,
PATTERNBDETECT => NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => x_addr_out3_n_106,
PCOUT(46) => x_addr_out3_n_107,
PCOUT(45) => x_addr_out3_n_108,
PCOUT(44) => x_addr_out3_n_109,
PCOUT(43) => x_addr_out3_n_110,
PCOUT(42) => x_addr_out3_n_111,
PCOUT(41) => x_addr_out3_n_112,
PCOUT(40) => x_addr_out3_n_113,
PCOUT(39) => x_addr_out3_n_114,
PCOUT(38) => x_addr_out3_n_115,
PCOUT(37) => x_addr_out3_n_116,
PCOUT(36) => x_addr_out3_n_117,
PCOUT(35) => x_addr_out3_n_118,
PCOUT(34) => x_addr_out3_n_119,
PCOUT(33) => x_addr_out3_n_120,
PCOUT(32) => x_addr_out3_n_121,
PCOUT(31) => x_addr_out3_n_122,
PCOUT(30) => x_addr_out3_n_123,
PCOUT(29) => x_addr_out3_n_124,
PCOUT(28) => x_addr_out3_n_125,
PCOUT(27) => x_addr_out3_n_126,
PCOUT(26) => x_addr_out3_n_127,
PCOUT(25) => x_addr_out3_n_128,
PCOUT(24) => x_addr_out3_n_129,
PCOUT(23) => x_addr_out3_n_130,
PCOUT(22) => x_addr_out3_n_131,
PCOUT(21) => x_addr_out3_n_132,
PCOUT(20) => x_addr_out3_n_133,
PCOUT(19) => x_addr_out3_n_134,
PCOUT(18) => x_addr_out3_n_135,
PCOUT(17) => x_addr_out3_n_136,
PCOUT(16) => x_addr_out3_n_137,
PCOUT(15) => x_addr_out3_n_138,
PCOUT(14) => x_addr_out3_n_139,
PCOUT(13) => x_addr_out3_n_140,
PCOUT(12) => x_addr_out3_n_141,
PCOUT(11) => x_addr_out3_n_142,
PCOUT(10) => x_addr_out3_n_143,
PCOUT(9) => x_addr_out3_n_144,
PCOUT(8) => x_addr_out3_n_145,
PCOUT(7) => x_addr_out3_n_146,
PCOUT(6) => x_addr_out3_n_147,
PCOUT(5) => x_addr_out3_n_148,
PCOUT(4) => x_addr_out3_n_149,
PCOUT(3) => x_addr_out3_n_150,
PCOUT(2) => x_addr_out3_n_151,
PCOUT(1) => x_addr_out3_n_152,
PCOUT(0) => x_addr_out3_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_x_addr_out3_UNDERFLOW_UNCONNECTED
);
\x_addr_out3__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m01(15),
A(28) => rot_m01(15),
A(27) => rot_m01(15),
A(26) => rot_m01(15),
A(25) => rot_m01(15),
A(24) => rot_m01(15),
A(23) => rot_m01(15),
A(22) => rot_m01(15),
A(21) => rot_m01(15),
A(20) => rot_m01(15),
A(19) => rot_m01(15),
A(18) => rot_m01(15),
A(17) => rot_m01(15),
A(16) => rot_m01(15),
A(15 downto 0) => rot_m01(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => y_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__0_n_58\,
P(46) => \x_addr_out3__0_n_59\,
P(45) => \x_addr_out3__0_n_60\,
P(44) => \x_addr_out3__0_n_61\,
P(43) => \x_addr_out3__0_n_62\,
P(42) => \x_addr_out3__0_n_63\,
P(41) => \x_addr_out3__0_n_64\,
P(40) => \x_addr_out3__0_n_65\,
P(39) => \x_addr_out3__0_n_66\,
P(38) => \x_addr_out3__0_n_67\,
P(37) => \x_addr_out3__0_n_68\,
P(36) => \x_addr_out3__0_n_69\,
P(35) => \x_addr_out3__0_n_70\,
P(34) => \x_addr_out3__0_n_71\,
P(33) => \x_addr_out3__0_n_72\,
P(32) => \x_addr_out3__0_n_73\,
P(31) => \x_addr_out3__0_n_74\,
P(30) => \x_addr_out3__0_n_75\,
P(29) => \x_addr_out3__0_n_76\,
P(28) => \x_addr_out3__0_n_77\,
P(27) => \x_addr_out3__0_n_78\,
P(26) => \x_addr_out3__0_n_79\,
P(25) => \x_addr_out3__0_n_80\,
P(24) => \x_addr_out3__0_n_81\,
P(23) => \x_addr_out3__0_n_82\,
P(22) => \x_addr_out3__0_n_83\,
P(21) => \x_addr_out3__0_n_84\,
P(20) => \x_addr_out3__0_n_85\,
P(19) => \x_addr_out3__0_n_86\,
P(18) => \x_addr_out3__0_n_87\,
P(17) => \x_addr_out3__0_n_88\,
P(16) => \x_addr_out3__0_n_89\,
P(15) => \x_addr_out3__0_n_90\,
P(14) => \x_addr_out3__0_n_91\,
P(13) => \x_addr_out3__0_n_92\,
P(12) => \x_addr_out3__0_n_93\,
P(11) => \x_addr_out3__0_n_94\,
P(10) => \x_addr_out3__0_n_95\,
P(9) => \x_addr_out3__0_n_96\,
P(8) => \x_addr_out3__0_n_97\,
P(7) => \x_addr_out3__0_n_98\,
P(6) => \x_addr_out3__0_n_99\,
P(5) => \x_addr_out3__0_n_100\,
P(4) => \x_addr_out3__0_n_101\,
P(3) => \x_addr_out3__0_n_102\,
P(2) => \x_addr_out3__0_n_103\,
P(1) => \x_addr_out3__0_n_104\,
P(0) => \x_addr_out3__0_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => x_addr_out3_n_106,
PCIN(46) => x_addr_out3_n_107,
PCIN(45) => x_addr_out3_n_108,
PCIN(44) => x_addr_out3_n_109,
PCIN(43) => x_addr_out3_n_110,
PCIN(42) => x_addr_out3_n_111,
PCIN(41) => x_addr_out3_n_112,
PCIN(40) => x_addr_out3_n_113,
PCIN(39) => x_addr_out3_n_114,
PCIN(38) => x_addr_out3_n_115,
PCIN(37) => x_addr_out3_n_116,
PCIN(36) => x_addr_out3_n_117,
PCIN(35) => x_addr_out3_n_118,
PCIN(34) => x_addr_out3_n_119,
PCIN(33) => x_addr_out3_n_120,
PCIN(32) => x_addr_out3_n_121,
PCIN(31) => x_addr_out3_n_122,
PCIN(30) => x_addr_out3_n_123,
PCIN(29) => x_addr_out3_n_124,
PCIN(28) => x_addr_out3_n_125,
PCIN(27) => x_addr_out3_n_126,
PCIN(26) => x_addr_out3_n_127,
PCIN(25) => x_addr_out3_n_128,
PCIN(24) => x_addr_out3_n_129,
PCIN(23) => x_addr_out3_n_130,
PCIN(22) => x_addr_out3_n_131,
PCIN(21) => x_addr_out3_n_132,
PCIN(20) => x_addr_out3_n_133,
PCIN(19) => x_addr_out3_n_134,
PCIN(18) => x_addr_out3_n_135,
PCIN(17) => x_addr_out3_n_136,
PCIN(16) => x_addr_out3_n_137,
PCIN(15) => x_addr_out3_n_138,
PCIN(14) => x_addr_out3_n_139,
PCIN(13) => x_addr_out3_n_140,
PCIN(12) => x_addr_out3_n_141,
PCIN(11) => x_addr_out3_n_142,
PCIN(10) => x_addr_out3_n_143,
PCIN(9) => x_addr_out3_n_144,
PCIN(8) => x_addr_out3_n_145,
PCIN(7) => x_addr_out3_n_146,
PCIN(6) => x_addr_out3_n_147,
PCIN(5) => x_addr_out3_n_148,
PCIN(4) => x_addr_out3_n_149,
PCIN(3) => x_addr_out3_n_150,
PCIN(2) => x_addr_out3_n_151,
PCIN(1) => x_addr_out3_n_152,
PCIN(0) => x_addr_out3_n_153,
PCOUT(47 downto 0) => \NLW_x_addr_out3__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED\
);
\x_addr_out3__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => x_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m00(15),
B(16) => rot_m00(15),
B(15 downto 0) => rot_m00(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => \NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__1_n_58\,
P(46) => \x_addr_out3__1_n_59\,
P(45) => \x_addr_out3__1_n_60\,
P(44) => \x_addr_out3__1_n_61\,
P(43) => \x_addr_out3__1_n_62\,
P(42) => \x_addr_out3__1_n_63\,
P(41) => \x_addr_out3__1_n_64\,
P(40) => \x_addr_out3__1_n_65\,
P(39) => \x_addr_out3__1_n_66\,
P(38) => \x_addr_out3__1_n_67\,
P(37) => \x_addr_out3__1_n_68\,
P(36) => \x_addr_out3__1_n_69\,
P(35) => \x_addr_out3__1_n_70\,
P(34) => \x_addr_out3__1_n_71\,
P(33) => \x_addr_out3__1_n_72\,
P(32) => \x_addr_out3__1_n_73\,
P(31) => \x_addr_out3__1_n_74\,
P(30) => \x_addr_out3__1_n_75\,
P(29) => \x_addr_out3__1_n_76\,
P(28) => \x_addr_out3__1_n_77\,
P(27) => \x_addr_out3__1_n_78\,
P(26) => \x_addr_out3__1_n_79\,
P(25) => \x_addr_out3__1_n_80\,
P(24) => \x_addr_out3__1_n_81\,
P(23) => \x_addr_out3__1_n_82\,
P(22) => \x_addr_out3__1_n_83\,
P(21) => \x_addr_out3__1_n_84\,
P(20) => \x_addr_out3__1_n_85\,
P(19) => \x_addr_out3__1_n_86\,
P(18) => \x_addr_out3__1_n_87\,
P(17) => \x_addr_out3__1_n_88\,
P(16) => \x_addr_out3__1_n_89\,
P(15) => \x_addr_out3__1_n_90\,
P(14) => \x_addr_out3__1_n_91\,
P(13) => \x_addr_out3__1_n_92\,
P(12) => \x_addr_out3__1_n_93\,
P(11) => \x_addr_out3__1_n_94\,
P(10) => \x_addr_out3__1_n_95\,
P(9) => \x_addr_out3__1_n_96\,
P(8) => \x_addr_out3__1_n_97\,
P(7) => \x_addr_out3__1_n_98\,
P(6) => \x_addr_out3__1_n_99\,
P(5) => \x_addr_out3__1_n_100\,
P(4) => \x_addr_out3__1_n_101\,
P(3) => \x_addr_out3__1_n_102\,
P(2) => \x_addr_out3__1_n_103\,
P(1) => \x_addr_out3__1_n_104\,
P(0) => \x_addr_out3__1_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => \x_addr_out3__1_n_106\,
PCOUT(46) => \x_addr_out3__1_n_107\,
PCOUT(45) => \x_addr_out3__1_n_108\,
PCOUT(44) => \x_addr_out3__1_n_109\,
PCOUT(43) => \x_addr_out3__1_n_110\,
PCOUT(42) => \x_addr_out3__1_n_111\,
PCOUT(41) => \x_addr_out3__1_n_112\,
PCOUT(40) => \x_addr_out3__1_n_113\,
PCOUT(39) => \x_addr_out3__1_n_114\,
PCOUT(38) => \x_addr_out3__1_n_115\,
PCOUT(37) => \x_addr_out3__1_n_116\,
PCOUT(36) => \x_addr_out3__1_n_117\,
PCOUT(35) => \x_addr_out3__1_n_118\,
PCOUT(34) => \x_addr_out3__1_n_119\,
PCOUT(33) => \x_addr_out3__1_n_120\,
PCOUT(32) => \x_addr_out3__1_n_121\,
PCOUT(31) => \x_addr_out3__1_n_122\,
PCOUT(30) => \x_addr_out3__1_n_123\,
PCOUT(29) => \x_addr_out3__1_n_124\,
PCOUT(28) => \x_addr_out3__1_n_125\,
PCOUT(27) => \x_addr_out3__1_n_126\,
PCOUT(26) => \x_addr_out3__1_n_127\,
PCOUT(25) => \x_addr_out3__1_n_128\,
PCOUT(24) => \x_addr_out3__1_n_129\,
PCOUT(23) => \x_addr_out3__1_n_130\,
PCOUT(22) => \x_addr_out3__1_n_131\,
PCOUT(21) => \x_addr_out3__1_n_132\,
PCOUT(20) => \x_addr_out3__1_n_133\,
PCOUT(19) => \x_addr_out3__1_n_134\,
PCOUT(18) => \x_addr_out3__1_n_135\,
PCOUT(17) => \x_addr_out3__1_n_136\,
PCOUT(16) => \x_addr_out3__1_n_137\,
PCOUT(15) => \x_addr_out3__1_n_138\,
PCOUT(14) => \x_addr_out3__1_n_139\,
PCOUT(13) => \x_addr_out3__1_n_140\,
PCOUT(12) => \x_addr_out3__1_n_141\,
PCOUT(11) => \x_addr_out3__1_n_142\,
PCOUT(10) => \x_addr_out3__1_n_143\,
PCOUT(9) => \x_addr_out3__1_n_144\,
PCOUT(8) => \x_addr_out3__1_n_145\,
PCOUT(7) => \x_addr_out3__1_n_146\,
PCOUT(6) => \x_addr_out3__1_n_147\,
PCOUT(5) => \x_addr_out3__1_n_148\,
PCOUT(4) => \x_addr_out3__1_n_149\,
PCOUT(3) => \x_addr_out3__1_n_150\,
PCOUT(2) => \x_addr_out3__1_n_151\,
PCOUT(1) => \x_addr_out3__1_n_152\,
PCOUT(0) => \x_addr_out3__1_n_153\,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED\
);
\x_addr_out3__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m00(15),
A(28) => rot_m00(15),
A(27) => rot_m00(15),
A(26) => rot_m00(15),
A(25) => rot_m00(15),
A(24) => rot_m00(15),
A(23) => rot_m00(15),
A(22) => rot_m00(15),
A(21) => rot_m00(15),
A(20) => rot_m00(15),
A(19) => rot_m00(15),
A(18) => rot_m00(15),
A(17) => rot_m00(15),
A(16) => rot_m00(15),
A(15 downto 0) => rot_m00(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => x_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__2_n_58\,
P(46) => \x_addr_out3__2_n_59\,
P(45) => \x_addr_out3__2_n_60\,
P(44) => \x_addr_out3__2_n_61\,
P(43) => \x_addr_out3__2_n_62\,
P(42) => \x_addr_out3__2_n_63\,
P(41) => \x_addr_out3__2_n_64\,
P(40) => \x_addr_out3__2_n_65\,
P(39) => \x_addr_out3__2_n_66\,
P(38) => \x_addr_out3__2_n_67\,
P(37) => \x_addr_out3__2_n_68\,
P(36) => \x_addr_out3__2_n_69\,
P(35) => \x_addr_out3__2_n_70\,
P(34) => \x_addr_out3__2_n_71\,
P(33) => \x_addr_out3__2_n_72\,
P(32) => \x_addr_out3__2_n_73\,
P(31) => \x_addr_out3__2_n_74\,
P(30) => \x_addr_out3__2_n_75\,
P(29) => \x_addr_out3__2_n_76\,
P(28) => \x_addr_out3__2_n_77\,
P(27) => \x_addr_out3__2_n_78\,
P(26) => \x_addr_out3__2_n_79\,
P(25) => \x_addr_out3__2_n_80\,
P(24) => \x_addr_out3__2_n_81\,
P(23) => \x_addr_out3__2_n_82\,
P(22) => \x_addr_out3__2_n_83\,
P(21) => \x_addr_out3__2_n_84\,
P(20) => \x_addr_out3__2_n_85\,
P(19) => \x_addr_out3__2_n_86\,
P(18) => \x_addr_out3__2_n_87\,
P(17) => \x_addr_out3__2_n_88\,
P(16) => \x_addr_out3__2_n_89\,
P(15) => \x_addr_out3__2_n_90\,
P(14) => \x_addr_out3__2_n_91\,
P(13) => \x_addr_out3__2_n_92\,
P(12) => \x_addr_out3__2_n_93\,
P(11) => \x_addr_out3__2_n_94\,
P(10) => \x_addr_out3__2_n_95\,
P(9) => \x_addr_out3__2_n_96\,
P(8) => \x_addr_out3__2_n_97\,
P(7) => \x_addr_out3__2_n_98\,
P(6) => \x_addr_out3__2_n_99\,
P(5) => \x_addr_out3__2_n_100\,
P(4) => \x_addr_out3__2_n_101\,
P(3) => \x_addr_out3__2_n_102\,
P(2) => \x_addr_out3__2_n_103\,
P(1) => \x_addr_out3__2_n_104\,
P(0) => \x_addr_out3__2_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => \x_addr_out3__1_n_106\,
PCIN(46) => \x_addr_out3__1_n_107\,
PCIN(45) => \x_addr_out3__1_n_108\,
PCIN(44) => \x_addr_out3__1_n_109\,
PCIN(43) => \x_addr_out3__1_n_110\,
PCIN(42) => \x_addr_out3__1_n_111\,
PCIN(41) => \x_addr_out3__1_n_112\,
PCIN(40) => \x_addr_out3__1_n_113\,
PCIN(39) => \x_addr_out3__1_n_114\,
PCIN(38) => \x_addr_out3__1_n_115\,
PCIN(37) => \x_addr_out3__1_n_116\,
PCIN(36) => \x_addr_out3__1_n_117\,
PCIN(35) => \x_addr_out3__1_n_118\,
PCIN(34) => \x_addr_out3__1_n_119\,
PCIN(33) => \x_addr_out3__1_n_120\,
PCIN(32) => \x_addr_out3__1_n_121\,
PCIN(31) => \x_addr_out3__1_n_122\,
PCIN(30) => \x_addr_out3__1_n_123\,
PCIN(29) => \x_addr_out3__1_n_124\,
PCIN(28) => \x_addr_out3__1_n_125\,
PCIN(27) => \x_addr_out3__1_n_126\,
PCIN(26) => \x_addr_out3__1_n_127\,
PCIN(25) => \x_addr_out3__1_n_128\,
PCIN(24) => \x_addr_out3__1_n_129\,
PCIN(23) => \x_addr_out3__1_n_130\,
PCIN(22) => \x_addr_out3__1_n_131\,
PCIN(21) => \x_addr_out3__1_n_132\,
PCIN(20) => \x_addr_out3__1_n_133\,
PCIN(19) => \x_addr_out3__1_n_134\,
PCIN(18) => \x_addr_out3__1_n_135\,
PCIN(17) => \x_addr_out3__1_n_136\,
PCIN(16) => \x_addr_out3__1_n_137\,
PCIN(15) => \x_addr_out3__1_n_138\,
PCIN(14) => \x_addr_out3__1_n_139\,
PCIN(13) => \x_addr_out3__1_n_140\,
PCIN(12) => \x_addr_out3__1_n_141\,
PCIN(11) => \x_addr_out3__1_n_142\,
PCIN(10) => \x_addr_out3__1_n_143\,
PCIN(9) => \x_addr_out3__1_n_144\,
PCIN(8) => \x_addr_out3__1_n_145\,
PCIN(7) => \x_addr_out3__1_n_146\,
PCIN(6) => \x_addr_out3__1_n_147\,
PCIN(5) => \x_addr_out3__1_n_148\,
PCIN(4) => \x_addr_out3__1_n_149\,
PCIN(3) => \x_addr_out3__1_n_150\,
PCIN(2) => \x_addr_out3__1_n_151\,
PCIN(1) => \x_addr_out3__1_n_152\,
PCIN(0) => \x_addr_out3__1_n_153\,
PCOUT(47 downto 0) => \NLW_x_addr_out3__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"66F0"
)
port map (
I0 => p_1_in(14),
I1 => t_x(0),
I2 => x_addr_in(0),
I3 => enable,
O => \x_addr_out[0]_i_1_n_0\
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(15),
I1 => x_addr_in(1),
I2 => enable,
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(16),
I1 => x_addr_in(2),
I2 => enable,
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(17),
I1 => x_addr_in(3),
I2 => enable,
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(18),
I1 => x_addr_in(4),
I2 => enable,
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(19),
I1 => x_addr_in(5),
I2 => enable,
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(20),
I1 => x_addr_in(6),
I2 => enable,
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(21),
I1 => x_addr_in(7),
I2 => enable,
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(22),
I1 => x_addr_in(8),
I2 => enable,
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(23),
I1 => x_addr_in(9),
I2 => enable,
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[0]_i_1_n_0\,
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
y_addr_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y_addr_out0_carry_n_0,
CO(2) => y_addr_out0_carry_n_1,
CO(1) => y_addr_out0_carry_n_2,
CO(0) => y_addr_out0_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => y_addr_out2(31 downto 28),
O(3 downto 1) => p_0_in(3 downto 1),
O(0) => NLW_y_addr_out0_carry_O_UNCONNECTED(0),
S(3) => y_addr_out0_carry_i_1_n_0,
S(2) => y_addr_out0_carry_i_2_n_0,
S(1) => y_addr_out0_carry_i_3_n_0,
S(0) => y_addr_out0_carry_i_4_n_0
);
\y_addr_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y_addr_out0_carry_n_0,
CO(3) => \y_addr_out0_carry__0_n_0\,
CO(2) => \y_addr_out0_carry__0_n_1\,
CO(1) => \y_addr_out0_carry__0_n_2\,
CO(0) => \y_addr_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => y_addr_out2(35 downto 32),
O(3 downto 0) => p_0_in(7 downto 4),
S(3) => \y_addr_out0_carry__0_i_1_n_0\,
S(2) => \y_addr_out0_carry__0_i_2_n_0\,
S(1) => \y_addr_out0_carry__0_i_3_n_0\,
S(0) => \y_addr_out0_carry__0_i_4_n_0\
);
\y_addr_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(35),
I1 => t_y(7),
O => \y_addr_out0_carry__0_i_1_n_0\
);
\y_addr_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(34),
I1 => t_y(6),
O => \y_addr_out0_carry__0_i_2_n_0\
);
\y_addr_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(33),
I1 => t_y(5),
O => \y_addr_out0_carry__0_i_3_n_0\
);
\y_addr_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(32),
I1 => t_y(4),
O => \y_addr_out0_carry__0_i_4_n_0\
);
\y_addr_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out0_carry__0_n_0\,
CO(3 downto 1) => \NLW_y_addr_out0_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_addr_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => y_addr_out2(36),
O(3 downto 2) => \NLW_y_addr_out0_carry__1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_0_in(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \y_addr_out0_carry__1_i_1_n_0\,
S(0) => \y_addr_out0_carry__1_i_2_n_0\
);
\y_addr_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(37),
I1 => t_y(9),
O => \y_addr_out0_carry__1_i_1_n_0\
);
\y_addr_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(36),
I1 => t_y(8),
O => \y_addr_out0_carry__1_i_2_n_0\
);
y_addr_out0_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(31),
I1 => t_y(3),
O => y_addr_out0_carry_i_1_n_0
);
y_addr_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(30),
I1 => t_y(2),
O => y_addr_out0_carry_i_2_n_0
);
y_addr_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(29),
I1 => t_y(1),
O => y_addr_out0_carry_i_3_n_0
);
y_addr_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(28),
I1 => t_y(0),
O => y_addr_out0_carry_i_4_n_0
);
y_addr_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y_addr_out2_carry_n_0,
CO(2) => y_addr_out2_carry_n_1,
CO(1) => y_addr_out2_carry_n_2,
CO(0) => y_addr_out2_carry_n_3,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_102\,
DI(2) => \y_addr_out3__1_n_103\,
DI(1) => \y_addr_out3__1_n_104\,
DI(0) => \y_addr_out3__1_n_105\,
O(3 downto 0) => NLW_y_addr_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => y_addr_out2_carry_i_1_n_0,
S(2) => y_addr_out2_carry_i_2_n_0,
S(1) => y_addr_out2_carry_i_3_n_0,
S(0) => y_addr_out2_carry_i_4_n_0
);
\y_addr_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y_addr_out2_carry_n_0,
CO(3) => \y_addr_out2_carry__0_n_0\,
CO(2) => \y_addr_out2_carry__0_n_1\,
CO(1) => \y_addr_out2_carry__0_n_2\,
CO(0) => \y_addr_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_98\,
DI(2) => \y_addr_out3__1_n_99\,
DI(1) => \y_addr_out3__1_n_100\,
DI(0) => \y_addr_out3__1_n_101\,
O(3 downto 0) => \NLW_y_addr_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__0_i_1_n_0\,
S(2) => \y_addr_out2_carry__0_i_2_n_0\,
S(1) => \y_addr_out2_carry__0_i_3_n_0\,
S(0) => \y_addr_out2_carry__0_i_4_n_0\
);
\y_addr_out2_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_98\,
I1 => y_addr_out3_n_98,
O => \y_addr_out2_carry__0_i_1_n_0\
);
\y_addr_out2_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_99\,
I1 => y_addr_out3_n_99,
O => \y_addr_out2_carry__0_i_2_n_0\
);
\y_addr_out2_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_100\,
I1 => y_addr_out3_n_100,
O => \y_addr_out2_carry__0_i_3_n_0\
);
\y_addr_out2_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_101\,
I1 => y_addr_out3_n_101,
O => \y_addr_out2_carry__0_i_4_n_0\
);
\y_addr_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__0_n_0\,
CO(3) => \y_addr_out2_carry__1_n_0\,
CO(2) => \y_addr_out2_carry__1_n_1\,
CO(1) => \y_addr_out2_carry__1_n_2\,
CO(0) => \y_addr_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_94\,
DI(2) => \y_addr_out3__1_n_95\,
DI(1) => \y_addr_out3__1_n_96\,
DI(0) => \y_addr_out3__1_n_97\,
O(3 downto 0) => \NLW_y_addr_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__1_i_1_n_0\,
S(2) => \y_addr_out2_carry__1_i_2_n_0\,
S(1) => \y_addr_out2_carry__1_i_3_n_0\,
S(0) => \y_addr_out2_carry__1_i_4_n_0\
);
\y_addr_out2_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_94\,
I1 => y_addr_out3_n_94,
O => \y_addr_out2_carry__1_i_1_n_0\
);
\y_addr_out2_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_95\,
I1 => y_addr_out3_n_95,
O => \y_addr_out2_carry__1_i_2_n_0\
);
\y_addr_out2_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_96\,
I1 => y_addr_out3_n_96,
O => \y_addr_out2_carry__1_i_3_n_0\
);
\y_addr_out2_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_97\,
I1 => y_addr_out3_n_97,
O => \y_addr_out2_carry__1_i_4_n_0\
);
\y_addr_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__1_n_0\,
CO(3) => \y_addr_out2_carry__2_n_0\,
CO(2) => \y_addr_out2_carry__2_n_1\,
CO(1) => \y_addr_out2_carry__2_n_2\,
CO(0) => \y_addr_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_90\,
DI(2) => \y_addr_out3__1_n_91\,
DI(1) => \y_addr_out3__1_n_92\,
DI(0) => \y_addr_out3__1_n_93\,
O(3 downto 0) => \NLW_y_addr_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__2_i_1_n_0\,
S(2) => \y_addr_out2_carry__2_i_2_n_0\,
S(1) => \y_addr_out2_carry__2_i_3_n_0\,
S(0) => \y_addr_out2_carry__2_i_4_n_0\
);
\y_addr_out2_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_90\,
I1 => y_addr_out3_n_90,
O => \y_addr_out2_carry__2_i_1_n_0\
);
\y_addr_out2_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_91\,
I1 => y_addr_out3_n_91,
O => \y_addr_out2_carry__2_i_2_n_0\
);
\y_addr_out2_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_92\,
I1 => y_addr_out3_n_92,
O => \y_addr_out2_carry__2_i_3_n_0\
);
\y_addr_out2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_93\,
I1 => y_addr_out3_n_93,
O => \y_addr_out2_carry__2_i_4_n_0\
);
\y_addr_out2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__2_n_0\,
CO(3) => \y_addr_out2_carry__3_n_0\,
CO(2) => \y_addr_out2_carry__3_n_1\,
CO(1) => \y_addr_out2_carry__3_n_2\,
CO(0) => \y_addr_out2_carry__3_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_103\,
DI(2) => \y_addr_out3__2_n_104\,
DI(1) => \y_addr_out3__2_n_105\,
DI(0) => \y_addr_out3__1_n_89\,
O(3 downto 0) => \NLW_y_addr_out2_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__3_i_1_n_0\,
S(2) => \y_addr_out2_carry__3_i_2_n_0\,
S(1) => \y_addr_out2_carry__3_i_3_n_0\,
S(0) => \y_addr_out2_carry__3_i_4_n_0\
);
\y_addr_out2_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_103\,
I1 => \y_addr_out3__0_n_103\,
O => \y_addr_out2_carry__3_i_1_n_0\
);
\y_addr_out2_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_104\,
I1 => \y_addr_out3__0_n_104\,
O => \y_addr_out2_carry__3_i_2_n_0\
);
\y_addr_out2_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_105\,
I1 => \y_addr_out3__0_n_105\,
O => \y_addr_out2_carry__3_i_3_n_0\
);
\y_addr_out2_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_89\,
I1 => y_addr_out3_n_89,
O => \y_addr_out2_carry__3_i_4_n_0\
);
\y_addr_out2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__3_n_0\,
CO(3) => \y_addr_out2_carry__4_n_0\,
CO(2) => \y_addr_out2_carry__4_n_1\,
CO(1) => \y_addr_out2_carry__4_n_2\,
CO(0) => \y_addr_out2_carry__4_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_99\,
DI(2) => \y_addr_out3__2_n_100\,
DI(1) => \y_addr_out3__2_n_101\,
DI(0) => \y_addr_out3__2_n_102\,
O(3 downto 0) => \NLW_y_addr_out2_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__4_i_1_n_0\,
S(2) => \y_addr_out2_carry__4_i_2_n_0\,
S(1) => \y_addr_out2_carry__4_i_3_n_0\,
S(0) => \y_addr_out2_carry__4_i_4_n_0\
);
\y_addr_out2_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_99\,
I1 => \y_addr_out3__0_n_99\,
O => \y_addr_out2_carry__4_i_1_n_0\
);
\y_addr_out2_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_100\,
I1 => \y_addr_out3__0_n_100\,
O => \y_addr_out2_carry__4_i_2_n_0\
);
\y_addr_out2_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_101\,
I1 => \y_addr_out3__0_n_101\,
O => \y_addr_out2_carry__4_i_3_n_0\
);
\y_addr_out2_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_102\,
I1 => \y_addr_out3__0_n_102\,
O => \y_addr_out2_carry__4_i_4_n_0\
);
\y_addr_out2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__4_n_0\,
CO(3) => \y_addr_out2_carry__5_n_0\,
CO(2) => \y_addr_out2_carry__5_n_1\,
CO(1) => \y_addr_out2_carry__5_n_2\,
CO(0) => \y_addr_out2_carry__5_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_95\,
DI(2) => \y_addr_out3__2_n_96\,
DI(1) => \y_addr_out3__2_n_97\,
DI(0) => \y_addr_out3__2_n_98\,
O(3 downto 0) => \NLW_y_addr_out2_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__5_i_1_n_0\,
S(2) => \y_addr_out2_carry__5_i_2_n_0\,
S(1) => \y_addr_out2_carry__5_i_3_n_0\,
S(0) => \y_addr_out2_carry__5_i_4_n_0\
);
\y_addr_out2_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_95\,
I1 => \y_addr_out3__0_n_95\,
O => \y_addr_out2_carry__5_i_1_n_0\
);
\y_addr_out2_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_96\,
I1 => \y_addr_out3__0_n_96\,
O => \y_addr_out2_carry__5_i_2_n_0\
);
\y_addr_out2_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_97\,
I1 => \y_addr_out3__0_n_97\,
O => \y_addr_out2_carry__5_i_3_n_0\
);
\y_addr_out2_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_98\,
I1 => \y_addr_out3__0_n_98\,
O => \y_addr_out2_carry__5_i_4_n_0\
);
\y_addr_out2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__5_n_0\,
CO(3) => \y_addr_out2_carry__6_n_0\,
CO(2) => \y_addr_out2_carry__6_n_1\,
CO(1) => \y_addr_out2_carry__6_n_2\,
CO(0) => \y_addr_out2_carry__6_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_91\,
DI(2) => \y_addr_out3__2_n_92\,
DI(1) => \y_addr_out3__2_n_93\,
DI(0) => \y_addr_out3__2_n_94\,
O(3 downto 0) => y_addr_out2(31 downto 28),
S(3) => \y_addr_out2_carry__6_i_1_n_0\,
S(2) => \y_addr_out2_carry__6_i_2_n_0\,
S(1) => \y_addr_out2_carry__6_i_3_n_0\,
S(0) => \y_addr_out2_carry__6_i_4_n_0\
);
\y_addr_out2_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_91\,
I1 => \y_addr_out3__0_n_91\,
O => \y_addr_out2_carry__6_i_1_n_0\
);
\y_addr_out2_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_92\,
I1 => \y_addr_out3__0_n_92\,
O => \y_addr_out2_carry__6_i_2_n_0\
);
\y_addr_out2_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_93\,
I1 => \y_addr_out3__0_n_93\,
O => \y_addr_out2_carry__6_i_3_n_0\
);
\y_addr_out2_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_94\,
I1 => \y_addr_out3__0_n_94\,
O => \y_addr_out2_carry__6_i_4_n_0\
);
\y_addr_out2_carry__7\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__6_n_0\,
CO(3) => \y_addr_out2_carry__7_n_0\,
CO(2) => \y_addr_out2_carry__7_n_1\,
CO(1) => \y_addr_out2_carry__7_n_2\,
CO(0) => \y_addr_out2_carry__7_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_87\,
DI(2) => \y_addr_out3__2_n_88\,
DI(1) => \y_addr_out3__2_n_89\,
DI(0) => \y_addr_out3__2_n_90\,
O(3 downto 0) => y_addr_out2(35 downto 32),
S(3) => \y_addr_out2_carry__7_i_1_n_0\,
S(2) => \y_addr_out2_carry__7_i_2_n_0\,
S(1) => \y_addr_out2_carry__7_i_3_n_0\,
S(0) => \y_addr_out2_carry__7_i_4_n_0\
);
\y_addr_out2_carry__7_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_87\,
I1 => \y_addr_out3__0_n_87\,
O => \y_addr_out2_carry__7_i_1_n_0\
);
\y_addr_out2_carry__7_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_88\,
I1 => \y_addr_out3__0_n_88\,
O => \y_addr_out2_carry__7_i_2_n_0\
);
\y_addr_out2_carry__7_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_89\,
I1 => \y_addr_out3__0_n_89\,
O => \y_addr_out2_carry__7_i_3_n_0\
);
\y_addr_out2_carry__7_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_90\,
I1 => \y_addr_out3__0_n_90\,
O => \y_addr_out2_carry__7_i_4_n_0\
);
\y_addr_out2_carry__8\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__7_n_0\,
CO(3 downto 1) => \NLW_y_addr_out2_carry__8_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_addr_out2_carry__8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_addr_out3__2_n_86\,
O(3 downto 2) => \NLW_y_addr_out2_carry__8_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_addr_out2(37 downto 36),
S(3 downto 2) => B"00",
S(1) => \y_addr_out2_carry__8_i_1_n_0\,
S(0) => \y_addr_out2_carry__8_i_2_n_0\
);
\y_addr_out2_carry__8_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_85\,
I1 => \y_addr_out3__0_n_85\,
O => \y_addr_out2_carry__8_i_1_n_0\
);
\y_addr_out2_carry__8_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_86\,
I1 => \y_addr_out3__0_n_86\,
O => \y_addr_out2_carry__8_i_2_n_0\
);
y_addr_out2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_102\,
I1 => y_addr_out3_n_102,
O => y_addr_out2_carry_i_1_n_0
);
y_addr_out2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_103\,
I1 => y_addr_out3_n_103,
O => y_addr_out2_carry_i_2_n_0
);
y_addr_out2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_104\,
I1 => y_addr_out3_n_104,
O => y_addr_out2_carry_i_3_n_0
);
y_addr_out2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_105\,
I1 => y_addr_out3_n_105,
O => y_addr_out2_carry_i_4_n_0
);
y_addr_out3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => y_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_y_addr_out3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m11(15),
B(16) => rot_m11(15),
B(15 downto 0) => rot_m11(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_y_addr_out3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_y_addr_out3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_y_addr_out3_OVERFLOW_UNCONNECTED,
P(47) => y_addr_out3_n_58,
P(46) => y_addr_out3_n_59,
P(45) => y_addr_out3_n_60,
P(44) => y_addr_out3_n_61,
P(43) => y_addr_out3_n_62,
P(42) => y_addr_out3_n_63,
P(41) => y_addr_out3_n_64,
P(40) => y_addr_out3_n_65,
P(39) => y_addr_out3_n_66,
P(38) => y_addr_out3_n_67,
P(37) => y_addr_out3_n_68,
P(36) => y_addr_out3_n_69,
P(35) => y_addr_out3_n_70,
P(34) => y_addr_out3_n_71,
P(33) => y_addr_out3_n_72,
P(32) => y_addr_out3_n_73,
P(31) => y_addr_out3_n_74,
P(30) => y_addr_out3_n_75,
P(29) => y_addr_out3_n_76,
P(28) => y_addr_out3_n_77,
P(27) => y_addr_out3_n_78,
P(26) => y_addr_out3_n_79,
P(25) => y_addr_out3_n_80,
P(24) => y_addr_out3_n_81,
P(23) => y_addr_out3_n_82,
P(22) => y_addr_out3_n_83,
P(21) => y_addr_out3_n_84,
P(20) => y_addr_out3_n_85,
P(19) => y_addr_out3_n_86,
P(18) => y_addr_out3_n_87,
P(17) => y_addr_out3_n_88,
P(16) => y_addr_out3_n_89,
P(15) => y_addr_out3_n_90,
P(14) => y_addr_out3_n_91,
P(13) => y_addr_out3_n_92,
P(12) => y_addr_out3_n_93,
P(11) => y_addr_out3_n_94,
P(10) => y_addr_out3_n_95,
P(9) => y_addr_out3_n_96,
P(8) => y_addr_out3_n_97,
P(7) => y_addr_out3_n_98,
P(6) => y_addr_out3_n_99,
P(5) => y_addr_out3_n_100,
P(4) => y_addr_out3_n_101,
P(3) => y_addr_out3_n_102,
P(2) => y_addr_out3_n_103,
P(1) => y_addr_out3_n_104,
P(0) => y_addr_out3_n_105,
PATTERNBDETECT => NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => y_addr_out3_n_106,
PCOUT(46) => y_addr_out3_n_107,
PCOUT(45) => y_addr_out3_n_108,
PCOUT(44) => y_addr_out3_n_109,
PCOUT(43) => y_addr_out3_n_110,
PCOUT(42) => y_addr_out3_n_111,
PCOUT(41) => y_addr_out3_n_112,
PCOUT(40) => y_addr_out3_n_113,
PCOUT(39) => y_addr_out3_n_114,
PCOUT(38) => y_addr_out3_n_115,
PCOUT(37) => y_addr_out3_n_116,
PCOUT(36) => y_addr_out3_n_117,
PCOUT(35) => y_addr_out3_n_118,
PCOUT(34) => y_addr_out3_n_119,
PCOUT(33) => y_addr_out3_n_120,
PCOUT(32) => y_addr_out3_n_121,
PCOUT(31) => y_addr_out3_n_122,
PCOUT(30) => y_addr_out3_n_123,
PCOUT(29) => y_addr_out3_n_124,
PCOUT(28) => y_addr_out3_n_125,
PCOUT(27) => y_addr_out3_n_126,
PCOUT(26) => y_addr_out3_n_127,
PCOUT(25) => y_addr_out3_n_128,
PCOUT(24) => y_addr_out3_n_129,
PCOUT(23) => y_addr_out3_n_130,
PCOUT(22) => y_addr_out3_n_131,
PCOUT(21) => y_addr_out3_n_132,
PCOUT(20) => y_addr_out3_n_133,
PCOUT(19) => y_addr_out3_n_134,
PCOUT(18) => y_addr_out3_n_135,
PCOUT(17) => y_addr_out3_n_136,
PCOUT(16) => y_addr_out3_n_137,
PCOUT(15) => y_addr_out3_n_138,
PCOUT(14) => y_addr_out3_n_139,
PCOUT(13) => y_addr_out3_n_140,
PCOUT(12) => y_addr_out3_n_141,
PCOUT(11) => y_addr_out3_n_142,
PCOUT(10) => y_addr_out3_n_143,
PCOUT(9) => y_addr_out3_n_144,
PCOUT(8) => y_addr_out3_n_145,
PCOUT(7) => y_addr_out3_n_146,
PCOUT(6) => y_addr_out3_n_147,
PCOUT(5) => y_addr_out3_n_148,
PCOUT(4) => y_addr_out3_n_149,
PCOUT(3) => y_addr_out3_n_150,
PCOUT(2) => y_addr_out3_n_151,
PCOUT(1) => y_addr_out3_n_152,
PCOUT(0) => y_addr_out3_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_y_addr_out3_UNDERFLOW_UNCONNECTED
);
\y_addr_out3__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m11(15),
A(28) => rot_m11(15),
A(27) => rot_m11(15),
A(26) => rot_m11(15),
A(25) => rot_m11(15),
A(24) => rot_m11(15),
A(23) => rot_m11(15),
A(22) => rot_m11(15),
A(21) => rot_m11(15),
A(20) => rot_m11(15),
A(19) => rot_m11(15),
A(18) => rot_m11(15),
A(17) => rot_m11(15),
A(16) => rot_m11(15),
A(15 downto 0) => rot_m11(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => y_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__0_n_58\,
P(46) => \y_addr_out3__0_n_59\,
P(45) => \y_addr_out3__0_n_60\,
P(44) => \y_addr_out3__0_n_61\,
P(43) => \y_addr_out3__0_n_62\,
P(42) => \y_addr_out3__0_n_63\,
P(41) => \y_addr_out3__0_n_64\,
P(40) => \y_addr_out3__0_n_65\,
P(39) => \y_addr_out3__0_n_66\,
P(38) => \y_addr_out3__0_n_67\,
P(37) => \y_addr_out3__0_n_68\,
P(36) => \y_addr_out3__0_n_69\,
P(35) => \y_addr_out3__0_n_70\,
P(34) => \y_addr_out3__0_n_71\,
P(33) => \y_addr_out3__0_n_72\,
P(32) => \y_addr_out3__0_n_73\,
P(31) => \y_addr_out3__0_n_74\,
P(30) => \y_addr_out3__0_n_75\,
P(29) => \y_addr_out3__0_n_76\,
P(28) => \y_addr_out3__0_n_77\,
P(27) => \y_addr_out3__0_n_78\,
P(26) => \y_addr_out3__0_n_79\,
P(25) => \y_addr_out3__0_n_80\,
P(24) => \y_addr_out3__0_n_81\,
P(23) => \y_addr_out3__0_n_82\,
P(22) => \y_addr_out3__0_n_83\,
P(21) => \y_addr_out3__0_n_84\,
P(20) => \y_addr_out3__0_n_85\,
P(19) => \y_addr_out3__0_n_86\,
P(18) => \y_addr_out3__0_n_87\,
P(17) => \y_addr_out3__0_n_88\,
P(16) => \y_addr_out3__0_n_89\,
P(15) => \y_addr_out3__0_n_90\,
P(14) => \y_addr_out3__0_n_91\,
P(13) => \y_addr_out3__0_n_92\,
P(12) => \y_addr_out3__0_n_93\,
P(11) => \y_addr_out3__0_n_94\,
P(10) => \y_addr_out3__0_n_95\,
P(9) => \y_addr_out3__0_n_96\,
P(8) => \y_addr_out3__0_n_97\,
P(7) => \y_addr_out3__0_n_98\,
P(6) => \y_addr_out3__0_n_99\,
P(5) => \y_addr_out3__0_n_100\,
P(4) => \y_addr_out3__0_n_101\,
P(3) => \y_addr_out3__0_n_102\,
P(2) => \y_addr_out3__0_n_103\,
P(1) => \y_addr_out3__0_n_104\,
P(0) => \y_addr_out3__0_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => y_addr_out3_n_106,
PCIN(46) => y_addr_out3_n_107,
PCIN(45) => y_addr_out3_n_108,
PCIN(44) => y_addr_out3_n_109,
PCIN(43) => y_addr_out3_n_110,
PCIN(42) => y_addr_out3_n_111,
PCIN(41) => y_addr_out3_n_112,
PCIN(40) => y_addr_out3_n_113,
PCIN(39) => y_addr_out3_n_114,
PCIN(38) => y_addr_out3_n_115,
PCIN(37) => y_addr_out3_n_116,
PCIN(36) => y_addr_out3_n_117,
PCIN(35) => y_addr_out3_n_118,
PCIN(34) => y_addr_out3_n_119,
PCIN(33) => y_addr_out3_n_120,
PCIN(32) => y_addr_out3_n_121,
PCIN(31) => y_addr_out3_n_122,
PCIN(30) => y_addr_out3_n_123,
PCIN(29) => y_addr_out3_n_124,
PCIN(28) => y_addr_out3_n_125,
PCIN(27) => y_addr_out3_n_126,
PCIN(26) => y_addr_out3_n_127,
PCIN(25) => y_addr_out3_n_128,
PCIN(24) => y_addr_out3_n_129,
PCIN(23) => y_addr_out3_n_130,
PCIN(22) => y_addr_out3_n_131,
PCIN(21) => y_addr_out3_n_132,
PCIN(20) => y_addr_out3_n_133,
PCIN(19) => y_addr_out3_n_134,
PCIN(18) => y_addr_out3_n_135,
PCIN(17) => y_addr_out3_n_136,
PCIN(16) => y_addr_out3_n_137,
PCIN(15) => y_addr_out3_n_138,
PCIN(14) => y_addr_out3_n_139,
PCIN(13) => y_addr_out3_n_140,
PCIN(12) => y_addr_out3_n_141,
PCIN(11) => y_addr_out3_n_142,
PCIN(10) => y_addr_out3_n_143,
PCIN(9) => y_addr_out3_n_144,
PCIN(8) => y_addr_out3_n_145,
PCIN(7) => y_addr_out3_n_146,
PCIN(6) => y_addr_out3_n_147,
PCIN(5) => y_addr_out3_n_148,
PCIN(4) => y_addr_out3_n_149,
PCIN(3) => y_addr_out3_n_150,
PCIN(2) => y_addr_out3_n_151,
PCIN(1) => y_addr_out3_n_152,
PCIN(0) => y_addr_out3_n_153,
PCOUT(47 downto 0) => \NLW_y_addr_out3__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED\
);
\y_addr_out3__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => x_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m10(15),
B(16) => rot_m10(15),
B(15 downto 0) => rot_m10(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => \NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__1_n_58\,
P(46) => \y_addr_out3__1_n_59\,
P(45) => \y_addr_out3__1_n_60\,
P(44) => \y_addr_out3__1_n_61\,
P(43) => \y_addr_out3__1_n_62\,
P(42) => \y_addr_out3__1_n_63\,
P(41) => \y_addr_out3__1_n_64\,
P(40) => \y_addr_out3__1_n_65\,
P(39) => \y_addr_out3__1_n_66\,
P(38) => \y_addr_out3__1_n_67\,
P(37) => \y_addr_out3__1_n_68\,
P(36) => \y_addr_out3__1_n_69\,
P(35) => \y_addr_out3__1_n_70\,
P(34) => \y_addr_out3__1_n_71\,
P(33) => \y_addr_out3__1_n_72\,
P(32) => \y_addr_out3__1_n_73\,
P(31) => \y_addr_out3__1_n_74\,
P(30) => \y_addr_out3__1_n_75\,
P(29) => \y_addr_out3__1_n_76\,
P(28) => \y_addr_out3__1_n_77\,
P(27) => \y_addr_out3__1_n_78\,
P(26) => \y_addr_out3__1_n_79\,
P(25) => \y_addr_out3__1_n_80\,
P(24) => \y_addr_out3__1_n_81\,
P(23) => \y_addr_out3__1_n_82\,
P(22) => \y_addr_out3__1_n_83\,
P(21) => \y_addr_out3__1_n_84\,
P(20) => \y_addr_out3__1_n_85\,
P(19) => \y_addr_out3__1_n_86\,
P(18) => \y_addr_out3__1_n_87\,
P(17) => \y_addr_out3__1_n_88\,
P(16) => \y_addr_out3__1_n_89\,
P(15) => \y_addr_out3__1_n_90\,
P(14) => \y_addr_out3__1_n_91\,
P(13) => \y_addr_out3__1_n_92\,
P(12) => \y_addr_out3__1_n_93\,
P(11) => \y_addr_out3__1_n_94\,
P(10) => \y_addr_out3__1_n_95\,
P(9) => \y_addr_out3__1_n_96\,
P(8) => \y_addr_out3__1_n_97\,
P(7) => \y_addr_out3__1_n_98\,
P(6) => \y_addr_out3__1_n_99\,
P(5) => \y_addr_out3__1_n_100\,
P(4) => \y_addr_out3__1_n_101\,
P(3) => \y_addr_out3__1_n_102\,
P(2) => \y_addr_out3__1_n_103\,
P(1) => \y_addr_out3__1_n_104\,
P(0) => \y_addr_out3__1_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => \y_addr_out3__1_n_106\,
PCOUT(46) => \y_addr_out3__1_n_107\,
PCOUT(45) => \y_addr_out3__1_n_108\,
PCOUT(44) => \y_addr_out3__1_n_109\,
PCOUT(43) => \y_addr_out3__1_n_110\,
PCOUT(42) => \y_addr_out3__1_n_111\,
PCOUT(41) => \y_addr_out3__1_n_112\,
PCOUT(40) => \y_addr_out3__1_n_113\,
PCOUT(39) => \y_addr_out3__1_n_114\,
PCOUT(38) => \y_addr_out3__1_n_115\,
PCOUT(37) => \y_addr_out3__1_n_116\,
PCOUT(36) => \y_addr_out3__1_n_117\,
PCOUT(35) => \y_addr_out3__1_n_118\,
PCOUT(34) => \y_addr_out3__1_n_119\,
PCOUT(33) => \y_addr_out3__1_n_120\,
PCOUT(32) => \y_addr_out3__1_n_121\,
PCOUT(31) => \y_addr_out3__1_n_122\,
PCOUT(30) => \y_addr_out3__1_n_123\,
PCOUT(29) => \y_addr_out3__1_n_124\,
PCOUT(28) => \y_addr_out3__1_n_125\,
PCOUT(27) => \y_addr_out3__1_n_126\,
PCOUT(26) => \y_addr_out3__1_n_127\,
PCOUT(25) => \y_addr_out3__1_n_128\,
PCOUT(24) => \y_addr_out3__1_n_129\,
PCOUT(23) => \y_addr_out3__1_n_130\,
PCOUT(22) => \y_addr_out3__1_n_131\,
PCOUT(21) => \y_addr_out3__1_n_132\,
PCOUT(20) => \y_addr_out3__1_n_133\,
PCOUT(19) => \y_addr_out3__1_n_134\,
PCOUT(18) => \y_addr_out3__1_n_135\,
PCOUT(17) => \y_addr_out3__1_n_136\,
PCOUT(16) => \y_addr_out3__1_n_137\,
PCOUT(15) => \y_addr_out3__1_n_138\,
PCOUT(14) => \y_addr_out3__1_n_139\,
PCOUT(13) => \y_addr_out3__1_n_140\,
PCOUT(12) => \y_addr_out3__1_n_141\,
PCOUT(11) => \y_addr_out3__1_n_142\,
PCOUT(10) => \y_addr_out3__1_n_143\,
PCOUT(9) => \y_addr_out3__1_n_144\,
PCOUT(8) => \y_addr_out3__1_n_145\,
PCOUT(7) => \y_addr_out3__1_n_146\,
PCOUT(6) => \y_addr_out3__1_n_147\,
PCOUT(5) => \y_addr_out3__1_n_148\,
PCOUT(4) => \y_addr_out3__1_n_149\,
PCOUT(3) => \y_addr_out3__1_n_150\,
PCOUT(2) => \y_addr_out3__1_n_151\,
PCOUT(1) => \y_addr_out3__1_n_152\,
PCOUT(0) => \y_addr_out3__1_n_153\,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED\
);
\y_addr_out3__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m10(15),
A(28) => rot_m10(15),
A(27) => rot_m10(15),
A(26) => rot_m10(15),
A(25) => rot_m10(15),
A(24) => rot_m10(15),
A(23) => rot_m10(15),
A(22) => rot_m10(15),
A(21) => rot_m10(15),
A(20) => rot_m10(15),
A(19) => rot_m10(15),
A(18) => rot_m10(15),
A(17) => rot_m10(15),
A(16) => rot_m10(15),
A(15 downto 0) => rot_m10(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => x_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__2_n_58\,
P(46) => \y_addr_out3__2_n_59\,
P(45) => \y_addr_out3__2_n_60\,
P(44) => \y_addr_out3__2_n_61\,
P(43) => \y_addr_out3__2_n_62\,
P(42) => \y_addr_out3__2_n_63\,
P(41) => \y_addr_out3__2_n_64\,
P(40) => \y_addr_out3__2_n_65\,
P(39) => \y_addr_out3__2_n_66\,
P(38) => \y_addr_out3__2_n_67\,
P(37) => \y_addr_out3__2_n_68\,
P(36) => \y_addr_out3__2_n_69\,
P(35) => \y_addr_out3__2_n_70\,
P(34) => \y_addr_out3__2_n_71\,
P(33) => \y_addr_out3__2_n_72\,
P(32) => \y_addr_out3__2_n_73\,
P(31) => \y_addr_out3__2_n_74\,
P(30) => \y_addr_out3__2_n_75\,
P(29) => \y_addr_out3__2_n_76\,
P(28) => \y_addr_out3__2_n_77\,
P(27) => \y_addr_out3__2_n_78\,
P(26) => \y_addr_out3__2_n_79\,
P(25) => \y_addr_out3__2_n_80\,
P(24) => \y_addr_out3__2_n_81\,
P(23) => \y_addr_out3__2_n_82\,
P(22) => \y_addr_out3__2_n_83\,
P(21) => \y_addr_out3__2_n_84\,
P(20) => \y_addr_out3__2_n_85\,
P(19) => \y_addr_out3__2_n_86\,
P(18) => \y_addr_out3__2_n_87\,
P(17) => \y_addr_out3__2_n_88\,
P(16) => \y_addr_out3__2_n_89\,
P(15) => \y_addr_out3__2_n_90\,
P(14) => \y_addr_out3__2_n_91\,
P(13) => \y_addr_out3__2_n_92\,
P(12) => \y_addr_out3__2_n_93\,
P(11) => \y_addr_out3__2_n_94\,
P(10) => \y_addr_out3__2_n_95\,
P(9) => \y_addr_out3__2_n_96\,
P(8) => \y_addr_out3__2_n_97\,
P(7) => \y_addr_out3__2_n_98\,
P(6) => \y_addr_out3__2_n_99\,
P(5) => \y_addr_out3__2_n_100\,
P(4) => \y_addr_out3__2_n_101\,
P(3) => \y_addr_out3__2_n_102\,
P(2) => \y_addr_out3__2_n_103\,
P(1) => \y_addr_out3__2_n_104\,
P(0) => \y_addr_out3__2_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => \y_addr_out3__1_n_106\,
PCIN(46) => \y_addr_out3__1_n_107\,
PCIN(45) => \y_addr_out3__1_n_108\,
PCIN(44) => \y_addr_out3__1_n_109\,
PCIN(43) => \y_addr_out3__1_n_110\,
PCIN(42) => \y_addr_out3__1_n_111\,
PCIN(41) => \y_addr_out3__1_n_112\,
PCIN(40) => \y_addr_out3__1_n_113\,
PCIN(39) => \y_addr_out3__1_n_114\,
PCIN(38) => \y_addr_out3__1_n_115\,
PCIN(37) => \y_addr_out3__1_n_116\,
PCIN(36) => \y_addr_out3__1_n_117\,
PCIN(35) => \y_addr_out3__1_n_118\,
PCIN(34) => \y_addr_out3__1_n_119\,
PCIN(33) => \y_addr_out3__1_n_120\,
PCIN(32) => \y_addr_out3__1_n_121\,
PCIN(31) => \y_addr_out3__1_n_122\,
PCIN(30) => \y_addr_out3__1_n_123\,
PCIN(29) => \y_addr_out3__1_n_124\,
PCIN(28) => \y_addr_out3__1_n_125\,
PCIN(27) => \y_addr_out3__1_n_126\,
PCIN(26) => \y_addr_out3__1_n_127\,
PCIN(25) => \y_addr_out3__1_n_128\,
PCIN(24) => \y_addr_out3__1_n_129\,
PCIN(23) => \y_addr_out3__1_n_130\,
PCIN(22) => \y_addr_out3__1_n_131\,
PCIN(21) => \y_addr_out3__1_n_132\,
PCIN(20) => \y_addr_out3__1_n_133\,
PCIN(19) => \y_addr_out3__1_n_134\,
PCIN(18) => \y_addr_out3__1_n_135\,
PCIN(17) => \y_addr_out3__1_n_136\,
PCIN(16) => \y_addr_out3__1_n_137\,
PCIN(15) => \y_addr_out3__1_n_138\,
PCIN(14) => \y_addr_out3__1_n_139\,
PCIN(13) => \y_addr_out3__1_n_140\,
PCIN(12) => \y_addr_out3__1_n_141\,
PCIN(11) => \y_addr_out3__1_n_142\,
PCIN(10) => \y_addr_out3__1_n_143\,
PCIN(9) => \y_addr_out3__1_n_144\,
PCIN(8) => \y_addr_out3__1_n_145\,
PCIN(7) => \y_addr_out3__1_n_146\,
PCIN(6) => \y_addr_out3__1_n_147\,
PCIN(5) => \y_addr_out3__1_n_148\,
PCIN(4) => \y_addr_out3__1_n_149\,
PCIN(3) => \y_addr_out3__1_n_150\,
PCIN(2) => \y_addr_out3__1_n_151\,
PCIN(1) => \y_addr_out3__1_n_152\,
PCIN(0) => \y_addr_out3__1_n_153\,
PCOUT(47 downto 0) => \NLW_y_addr_out3__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED\
);
\y_addr_out[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(28),
I1 => t_y(0),
O => p_0_in(0)
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(0),
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(1),
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(2),
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(3),
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(4),
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(5),
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(6),
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(7),
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(8),
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(9),
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_transform_0_1 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_transform_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_transform_0_1 : entity is "system_vga_transform_0_1,vga_transform,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_transform_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_transform_0_1 : entity is "vga_transform,Vivado 2016.4";
end system_vga_transform_0_1;
architecture STRUCTURE of system_vga_transform_0_1 is
begin
U0: entity work.system_vga_transform_0_1_vga_transform
port map (
clk => clk,
enable => enable,
rot_m00(15 downto 0) => rot_m00(15 downto 0),
rot_m01(15 downto 0) => rot_m01(15 downto 0),
rot_m10(15 downto 0) => rot_m10(15 downto 0),
rot_m11(15 downto 0) => rot_m11(15 downto 0),
t_x(9 downto 0) => t_x(9 downto 0),
t_y(9 downto 0) => t_y(9 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
| mit | 5ae3f9c853df0930baa81046df34ab9b | 0.537321 | 2.340549 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/filter_v1_00_a/hdl/vhdl/filter.vhd | 3 | 17,735 | ------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 17:57:17 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library filter_v1_00_a;
use filter_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity filter is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
CLK_48 : in std_logic;
--RST : in std_logic;
HP_BTN : in std_logic;
BP_BTN : in std_logic;
LP_BTN : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity filter;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of filter is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 30;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity filter_v1_00_a.user_logic --work.user_logic --
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
CLK_48 => CLK_48,
RST => '0', -- disable resest so that the filter is always in the working mode.
HP_BTN => HP_BTN,
BP_BTN => BP_BTN,
LP_BTN => LP_BTN,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
FILTER_DONE => FILTER_DONE,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 57694b0948ab55f43b8bdc13b261e541 | 0.453566 | 4.056496 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/synth/system_zybo_hdmi_0_0.vhd | 3 | 4,422 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "zybo_hdmi,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zybo_hdmi_0_0_arch : ARCHITECTURE IS "system_zybo_hdmi_0_0,zybo_hdmi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "system_zybo_hdmi_0_0,zybo_hdmi,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zybo_hdmi,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
| mit | eaa0a6b496f7e756d6866b8d1b7fb257 | 0.708955 | 3.691152 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dsputil_pac.vhd | 2 | 4,295 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
package dsputil_pac is
function bit_extent(val : std_logic; size :natural) return std_logic_vector;
function dsp_abs(val : signed) return signed;
function dsp_abs(val : std_logic_vector) return std_logic_vector;
function ones(size : natural) return unsigned;
function ones(size : natural) return std_logic_vector;
-- function zeros(size : natural) return unsigned;
-- function zeros(size : natural) return std_logic_vector;
function sig_one(size : natural) return unsigned;
function sig_one(size : natural) return signed;
function sig_one(size : natural) return std_logic_vector;
end dsputil_pac;
package body dsputil_pac is
function bit_extent(val : std_logic; size :natural) return std_logic_vector
is
variable vect_out : std_logic_vector((size - 1) downto 0);
begin
vect_out := (others => val);
return vect_out;
end bit_extent;
function dsp_abs(val : signed) return signed
is
constant numlength : natural := val'length;
alias val_in : signed((numlength - 1) downto 0) is val;
variable val_out : signed((numlength - 1) downto 0);
begin
if val_in(numlength - 1) = '0' then
val_out := val_in;
else
val_out := -val_in;
end if;
return val_out;
end dsp_abs;
function dsp_abs(val : std_logic_vector) return std_logic_vector
is
constant numlength : natural := val'length;
variable val_out : std_logic_vector((numlength - 1) downto 0);
begin
val_out := std_logic_vector(dsp_abs(signed(val)));
return val_out;
end dsp_abs;
function ones(size : natural) return unsigned
is
variable vect_ones : unsigned((size - 1) downto 0);
begin
vect_ones := (others => '1');
return vect_ones;
end ones;
function ones(size : natural) return std_logic_vector
is
variable vect_ones : std_logic_vector((size - 1) downto 0);
begin
vect_ones := (others => '1');
return vect_ones;
end ones;
-- function zeros(size : natural) return unsigned
-- is
-- variable vect_zeros : unsigned((size - 1) downto 0);
-- begin
-- vect_zeros := (others => '0');
-- return vect_zeros;
-- end zeros;
-- function zeros(size : natural) return std_logic_vector
-- is
-- variable vect_zeros : std_logic_vector((size - 1) downto 0);
-- begin
-- vect_zeros := (others => '0');
-- return vect_zeros;
-- end zeros;
function sig_one(size : natural) return unsigned
is
variable vect_one : unsigned((size - 1) downto 0);
begin
vect_one((size - 1) downto 0) := (others => '1');
return vect_one;
end sig_one;
function sig_one(size : natural) return signed
is
variable vect_one : signed((size - 1) downto 0);
begin
vect_one(size - 1) := '0';
vect_one((size - 2) downto 0) := (others => '1');
return vect_one;
end sig_one;
function sig_one(size : natural) return std_logic_vector
is
variable vect_one : std_logic_vector((size - 1) downto 0);
begin
vect_one(size - 1) := '0';
vect_one((size - 2) downto 0) := (others => '1');
return vect_one;
end sig_one;
end dsputil_pac;
| gpl-3.0 | b5f4cb97cbed6608ef78d4a0217357ea | 0.620023 | 3.636749 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/sim/system_vga_sync_0_0.vhd | 2 | 4,026 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit | fa54c1bc8822cf71d265ce19dfd73854 | 0.691257 | 3.867435 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_1_0/system_vga_nmsuppression_1_0_sim_netlist.vhdl | 1 | 215,472 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:29:19 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_nmsuppression_1_0 -prefix
-- system_vga_nmsuppression_1_0_ system_vga_nmsuppression_1_0_sim_netlist.vhdl
-- Design : system_vga_nmsuppression_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_1_0_vga_nmsuppression is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
active : in STD_LOGIC;
clk : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
enable : in STD_LOGIC
);
end system_vga_nmsuppression_1_0_vga_nmsuppression;
architecture STRUCTURE of system_vga_nmsuppression_1_0_vga_nmsuppression is
signal \hessian_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_3\ : STD_LOGIC;
signal hessian_out2_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_1 : STD_LOGIC;
signal hessian_out2_carry_n_2 : STD_LOGIC;
signal hessian_out2_carry_n_3 : STD_LOGIC;
signal \hessian_out3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_3\ : STD_LOGIC;
signal hessian_out3_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_1 : STD_LOGIC;
signal hessian_out3_carry_n_2 : STD_LOGIC;
signal hessian_out3_carry_n_3 : STD_LOGIC;
signal \hessian_out4_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_3\ : STD_LOGIC;
signal hessian_out4_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_1 : STD_LOGIC;
signal hessian_out4_carry_n_2 : STD_LOGIC;
signal hessian_out4_carry_n_3 : STD_LOGIC;
signal \hessian_out5_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_3\ : STD_LOGIC;
signal hessian_out5_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_1 : STD_LOGIC;
signal hessian_out5_carry_n_2 : STD_LOGIC;
signal hessian_out5_carry_n_3 : STD_LOGIC;
signal \hessian_out6_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_3\ : STD_LOGIC;
signal hessian_out6_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_1 : STD_LOGIC;
signal hessian_out6_carry_n_2 : STD_LOGIC;
signal hessian_out6_carry_n_3 : STD_LOGIC;
signal \hessian_out7_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_3\ : STD_LOGIC;
signal hessian_out7_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_1 : STD_LOGIC;
signal hessian_out7_carry_n_2 : STD_LOGIC;
signal hessian_out7_carry_n_3 : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_3\ : STD_LOGIC;
signal hessian_out8_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_1 : STD_LOGIC;
signal hessian_out8_carry_n_2 : STD_LOGIC;
signal hessian_out8_carry_n_3 : STD_LOGIC;
signal \hessian_out[31]_i_1_n_0\ : STD_LOGIC;
signal \hessian_out[31]_i_2_n_0\ : STD_LOGIC;
signal \hessian_reg[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[10]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[11]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[1]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[4][0]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][10]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][11]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][12]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][13]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][14]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][15]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][16]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][17]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][18]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][19]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][1]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][20]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][21]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][22]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][23]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][24]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][25]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][26]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][27]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][28]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][29]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][2]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][30]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][31]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][3]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][4]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][5]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][6]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][7]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][8]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][9]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[5]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[6]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[7]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[8]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[9]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 0 to 0 );
signal \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal NLW_hessian_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out4_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out5_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out6_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out7_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out8_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute srl_bus_name : string;
attribute srl_bus_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name : string;
attribute srl_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4][0]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4][10]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4][11]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4][12]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4][13]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4][14]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4][15]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4][16]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4][17]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4][18]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4][19]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4][1]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4][20]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4][21]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4][22]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4][23]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4][24]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4][25]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4][26]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4][27]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4][28]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4][29]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4][2]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4][30]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4][31]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4][3]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4][4]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4][5]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4][6]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4][7]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4][8]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4][9]_srl3 ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[9]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y_addr_out[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y_addr_out[9]_i_1\ : label is "soft_lutpair3";
begin
hessian_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out2_carry_n_0,
CO(2) => hessian_out2_carry_n_1,
CO(1) => hessian_out2_carry_n_2,
CO(0) => hessian_out2_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out2_carry_i_1_n_0,
DI(2) => hessian_out2_carry_i_2_n_0,
DI(1) => hessian_out2_carry_i_3_n_0,
DI(0) => hessian_out2_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out2_carry_i_5_n_0,
S(2) => hessian_out2_carry_i_6_n_0,
S(1) => hessian_out2_carry_i_7_n_0,
S(0) => hessian_out2_carry_i_8_n_0
);
\hessian_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out2_carry_n_0,
CO(3) => \hessian_out2_carry__0_n_0\,
CO(2) => \hessian_out2_carry__0_n_1\,
CO(1) => \hessian_out2_carry__0_n_2\,
CO(0) => \hessian_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__0_i_1_n_0\,
DI(2) => \hessian_out2_carry__0_i_2_n_0\,
DI(1) => \hessian_out2_carry__0_i_3_n_0\,
DI(0) => \hessian_out2_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__0_i_5_n_0\,
S(2) => \hessian_out2_carry__0_i_6_n_0\,
S(1) => \hessian_out2_carry__0_i_7_n_0\,
S(0) => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_1_n_0\
);
\hessian_out2_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_2_n_0\
);
\hessian_out2_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_3_n_0\
);
\hessian_out2_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_4_n_0\
);
\hessian_out2_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_5_n_0\
);
\hessian_out2_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_6_n_0\
);
\hessian_out2_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_7_n_0\
);
\hessian_out2_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__0_n_0\,
CO(3) => \hessian_out2_carry__1_n_0\,
CO(2) => \hessian_out2_carry__1_n_1\,
CO(1) => \hessian_out2_carry__1_n_2\,
CO(0) => \hessian_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__1_i_1_n_0\,
DI(2) => \hessian_out2_carry__1_i_2_n_0\,
DI(1) => \hessian_out2_carry__1_i_3_n_0\,
DI(0) => \hessian_out2_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__1_i_5_n_0\,
S(2) => \hessian_out2_carry__1_i_6_n_0\,
S(1) => \hessian_out2_carry__1_i_7_n_0\,
S(0) => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_1_n_0\
);
\hessian_out2_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_2_n_0\
);
\hessian_out2_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_3_n_0\
);
\hessian_out2_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_4_n_0\
);
\hessian_out2_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_5_n_0\
);
\hessian_out2_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_6_n_0\
);
\hessian_out2_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_7_n_0\
);
\hessian_out2_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__1_n_0\,
CO(3) => \hessian_out2_carry__2_n_0\,
CO(2) => \hessian_out2_carry__2_n_1\,
CO(1) => \hessian_out2_carry__2_n_2\,
CO(0) => \hessian_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__2_i_1_n_0\,
DI(2) => \hessian_out2_carry__2_i_2_n_0\,
DI(1) => \hessian_out2_carry__2_i_3_n_0\,
DI(0) => \hessian_out2_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__2_i_5_n_0\,
S(2) => \hessian_out2_carry__2_i_6_n_0\,
S(1) => \hessian_out2_carry__2_i_7_n_0\,
S(0) => \hessian_out2_carry__2_i_8_n_0\
);
\hessian_out2_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_1_n_0\
);
\hessian_out2_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_2_n_0\
);
\hessian_out2_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_3_n_0\
);
\hessian_out2_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_4_n_0\
);
\hessian_out2_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_5_n_0\
);
\hessian_out2_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_6_n_0\
);
\hessian_out2_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_7_n_0\
);
\hessian_out2_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_8_n_0\
);
hessian_out2_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_1_n_0
);
hessian_out2_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_2_n_0
);
hessian_out2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_3_n_0
);
hessian_out2_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_4_n_0
);
hessian_out2_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_5_n_0
);
hessian_out2_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_6_n_0
);
hessian_out2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_7_n_0
);
hessian_out2_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_8_n_0
);
hessian_out3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out3_carry_n_0,
CO(2) => hessian_out3_carry_n_1,
CO(1) => hessian_out3_carry_n_2,
CO(0) => hessian_out3_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out3_carry_i_1_n_0,
DI(2) => hessian_out3_carry_i_2_n_0,
DI(1) => hessian_out3_carry_i_3_n_0,
DI(0) => hessian_out3_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out3_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out3_carry_i_5_n_0,
S(2) => hessian_out3_carry_i_6_n_0,
S(1) => hessian_out3_carry_i_7_n_0,
S(0) => hessian_out3_carry_i_8_n_0
);
\hessian_out3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out3_carry_n_0,
CO(3) => \hessian_out3_carry__0_n_0\,
CO(2) => \hessian_out3_carry__0_n_1\,
CO(1) => \hessian_out3_carry__0_n_2\,
CO(0) => \hessian_out3_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__0_i_1_n_0\,
DI(2) => \hessian_out3_carry__0_i_2_n_0\,
DI(1) => \hessian_out3_carry__0_i_3_n_0\,
DI(0) => \hessian_out3_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__0_i_5_n_0\,
S(2) => \hessian_out3_carry__0_i_6_n_0\,
S(1) => \hessian_out3_carry__0_i_7_n_0\,
S(0) => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_1_n_0\
);
\hessian_out3_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_2_n_0\
);
\hessian_out3_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_3_n_0\
);
\hessian_out3_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_4_n_0\
);
\hessian_out3_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_5_n_0\
);
\hessian_out3_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_6_n_0\
);
\hessian_out3_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_7_n_0\
);
\hessian_out3_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__0_n_0\,
CO(3) => \hessian_out3_carry__1_n_0\,
CO(2) => \hessian_out3_carry__1_n_1\,
CO(1) => \hessian_out3_carry__1_n_2\,
CO(0) => \hessian_out3_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__1_i_1_n_0\,
DI(2) => \hessian_out3_carry__1_i_2_n_0\,
DI(1) => \hessian_out3_carry__1_i_3_n_0\,
DI(0) => \hessian_out3_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__1_i_5_n_0\,
S(2) => \hessian_out3_carry__1_i_6_n_0\,
S(1) => \hessian_out3_carry__1_i_7_n_0\,
S(0) => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_1_n_0\
);
\hessian_out3_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_2_n_0\
);
\hessian_out3_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_3_n_0\
);
\hessian_out3_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_4_n_0\
);
\hessian_out3_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_5_n_0\
);
\hessian_out3_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_6_n_0\
);
\hessian_out3_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_7_n_0\
);
\hessian_out3_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__1_n_0\,
CO(3) => \hessian_out3_carry__2_n_0\,
CO(2) => \hessian_out3_carry__2_n_1\,
CO(1) => \hessian_out3_carry__2_n_2\,
CO(0) => \hessian_out3_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__2_i_1_n_0\,
DI(2) => \hessian_out3_carry__2_i_2_n_0\,
DI(1) => \hessian_out3_carry__2_i_3_n_0\,
DI(0) => \hessian_out3_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__2_i_5_n_0\,
S(2) => \hessian_out3_carry__2_i_6_n_0\,
S(1) => \hessian_out3_carry__2_i_7_n_0\,
S(0) => \hessian_out3_carry__2_i_8_n_0\
);
\hessian_out3_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_1_n_0\
);
\hessian_out3_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_2_n_0\
);
\hessian_out3_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_3_n_0\
);
\hessian_out3_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_4_n_0\
);
\hessian_out3_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_5_n_0\
);
\hessian_out3_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_6_n_0\
);
\hessian_out3_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_7_n_0\
);
\hessian_out3_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_8_n_0\
);
hessian_out3_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_1_n_0
);
hessian_out3_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_2_n_0
);
hessian_out3_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_3_n_0
);
hessian_out3_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_4_n_0
);
hessian_out3_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_5_n_0
);
hessian_out3_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_6_n_0
);
hessian_out3_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_7_n_0
);
hessian_out3_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_8_n_0
);
hessian_out4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out4_carry_n_0,
CO(2) => hessian_out4_carry_n_1,
CO(1) => hessian_out4_carry_n_2,
CO(0) => hessian_out4_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out4_carry_i_1_n_0,
DI(2) => hessian_out4_carry_i_2_n_0,
DI(1) => hessian_out4_carry_i_3_n_0,
DI(0) => hessian_out4_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out4_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out4_carry_i_5_n_0,
S(2) => hessian_out4_carry_i_6_n_0,
S(1) => hessian_out4_carry_i_7_n_0,
S(0) => hessian_out4_carry_i_8_n_0
);
\hessian_out4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out4_carry_n_0,
CO(3) => \hessian_out4_carry__0_n_0\,
CO(2) => \hessian_out4_carry__0_n_1\,
CO(1) => \hessian_out4_carry__0_n_2\,
CO(0) => \hessian_out4_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__0_i_1_n_0\,
DI(2) => \hessian_out4_carry__0_i_2_n_0\,
DI(1) => \hessian_out4_carry__0_i_3_n_0\,
DI(0) => \hessian_out4_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__0_i_5_n_0\,
S(2) => \hessian_out4_carry__0_i_6_n_0\,
S(1) => \hessian_out4_carry__0_i_7_n_0\,
S(0) => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_1_n_0\
);
\hessian_out4_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_2_n_0\
);
\hessian_out4_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_3_n_0\
);
\hessian_out4_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_4_n_0\
);
\hessian_out4_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_5_n_0\
);
\hessian_out4_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_6_n_0\
);
\hessian_out4_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_7_n_0\
);
\hessian_out4_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__0_n_0\,
CO(3) => \hessian_out4_carry__1_n_0\,
CO(2) => \hessian_out4_carry__1_n_1\,
CO(1) => \hessian_out4_carry__1_n_2\,
CO(0) => \hessian_out4_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__1_i_1_n_0\,
DI(2) => \hessian_out4_carry__1_i_2_n_0\,
DI(1) => \hessian_out4_carry__1_i_3_n_0\,
DI(0) => \hessian_out4_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__1_i_5_n_0\,
S(2) => \hessian_out4_carry__1_i_6_n_0\,
S(1) => \hessian_out4_carry__1_i_7_n_0\,
S(0) => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_1_n_0\
);
\hessian_out4_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_2_n_0\
);
\hessian_out4_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_3_n_0\
);
\hessian_out4_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_4_n_0\
);
\hessian_out4_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_5_n_0\
);
\hessian_out4_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_6_n_0\
);
\hessian_out4_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_7_n_0\
);
\hessian_out4_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__1_n_0\,
CO(3) => \hessian_out4_carry__2_n_0\,
CO(2) => \hessian_out4_carry__2_n_1\,
CO(1) => \hessian_out4_carry__2_n_2\,
CO(0) => \hessian_out4_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__2_i_1_n_0\,
DI(2) => \hessian_out4_carry__2_i_2_n_0\,
DI(1) => \hessian_out4_carry__2_i_3_n_0\,
DI(0) => \hessian_out4_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__2_i_5_n_0\,
S(2) => \hessian_out4_carry__2_i_6_n_0\,
S(1) => \hessian_out4_carry__2_i_7_n_0\,
S(0) => \hessian_out4_carry__2_i_8_n_0\
);
\hessian_out4_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_1_n_0\
);
\hessian_out4_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_2_n_0\
);
\hessian_out4_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_3_n_0\
);
\hessian_out4_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_4_n_0\
);
\hessian_out4_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_5_n_0\
);
\hessian_out4_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_6_n_0\
);
\hessian_out4_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_7_n_0\
);
\hessian_out4_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_8_n_0\
);
hessian_out4_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_1_n_0
);
hessian_out4_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_2_n_0
);
hessian_out4_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_3_n_0
);
hessian_out4_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_4_n_0
);
hessian_out4_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_5_n_0
);
hessian_out4_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_6_n_0
);
hessian_out4_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_7_n_0
);
hessian_out4_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_8_n_0
);
hessian_out5_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out5_carry_n_0,
CO(2) => hessian_out5_carry_n_1,
CO(1) => hessian_out5_carry_n_2,
CO(0) => hessian_out5_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out5_carry_i_1_n_0,
DI(2) => hessian_out5_carry_i_2_n_0,
DI(1) => hessian_out5_carry_i_3_n_0,
DI(0) => hessian_out5_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out5_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out5_carry_i_5_n_0,
S(2) => hessian_out5_carry_i_6_n_0,
S(1) => hessian_out5_carry_i_7_n_0,
S(0) => hessian_out5_carry_i_8_n_0
);
\hessian_out5_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out5_carry_n_0,
CO(3) => \hessian_out5_carry__0_n_0\,
CO(2) => \hessian_out5_carry__0_n_1\,
CO(1) => \hessian_out5_carry__0_n_2\,
CO(0) => \hessian_out5_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__0_i_1_n_0\,
DI(2) => \hessian_out5_carry__0_i_2_n_0\,
DI(1) => \hessian_out5_carry__0_i_3_n_0\,
DI(0) => \hessian_out5_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__0_i_5_n_0\,
S(2) => \hessian_out5_carry__0_i_6_n_0\,
S(1) => \hessian_out5_carry__0_i_7_n_0\,
S(0) => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_1_n_0\
);
\hessian_out5_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_2_n_0\
);
\hessian_out5_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_3_n_0\
);
\hessian_out5_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_4_n_0\
);
\hessian_out5_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_5_n_0\
);
\hessian_out5_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_6_n_0\
);
\hessian_out5_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_7_n_0\
);
\hessian_out5_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__0_n_0\,
CO(3) => \hessian_out5_carry__1_n_0\,
CO(2) => \hessian_out5_carry__1_n_1\,
CO(1) => \hessian_out5_carry__1_n_2\,
CO(0) => \hessian_out5_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__1_i_1_n_0\,
DI(2) => \hessian_out5_carry__1_i_2_n_0\,
DI(1) => \hessian_out5_carry__1_i_3_n_0\,
DI(0) => \hessian_out5_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__1_i_5_n_0\,
S(2) => \hessian_out5_carry__1_i_6_n_0\,
S(1) => \hessian_out5_carry__1_i_7_n_0\,
S(0) => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_1_n_0\
);
\hessian_out5_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_2_n_0\
);
\hessian_out5_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_3_n_0\
);
\hessian_out5_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_4_n_0\
);
\hessian_out5_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_5_n_0\
);
\hessian_out5_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_6_n_0\
);
\hessian_out5_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_7_n_0\
);
\hessian_out5_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__1_n_0\,
CO(3) => \hessian_out5_carry__2_n_0\,
CO(2) => \hessian_out5_carry__2_n_1\,
CO(1) => \hessian_out5_carry__2_n_2\,
CO(0) => \hessian_out5_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__2_i_1_n_0\,
DI(2) => \hessian_out5_carry__2_i_2_n_0\,
DI(1) => \hessian_out5_carry__2_i_3_n_0\,
DI(0) => \hessian_out5_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__2_i_5_n_0\,
S(2) => \hessian_out5_carry__2_i_6_n_0\,
S(1) => \hessian_out5_carry__2_i_7_n_0\,
S(0) => \hessian_out5_carry__2_i_8_n_0\
);
\hessian_out5_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_1_n_0\
);
\hessian_out5_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_2_n_0\
);
\hessian_out5_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_3_n_0\
);
\hessian_out5_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_4_n_0\
);
\hessian_out5_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_5_n_0\
);
\hessian_out5_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_6_n_0\
);
\hessian_out5_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_7_n_0\
);
\hessian_out5_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_8_n_0\
);
hessian_out5_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_1_n_0
);
hessian_out5_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_2_n_0
);
hessian_out5_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_3_n_0
);
hessian_out5_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_4_n_0
);
hessian_out5_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_5_n_0
);
hessian_out5_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_6_n_0
);
hessian_out5_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_7_n_0
);
hessian_out5_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_8_n_0
);
hessian_out6_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out6_carry_n_0,
CO(2) => hessian_out6_carry_n_1,
CO(1) => hessian_out6_carry_n_2,
CO(0) => hessian_out6_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out6_carry_i_1_n_0,
DI(2) => hessian_out6_carry_i_2_n_0,
DI(1) => hessian_out6_carry_i_3_n_0,
DI(0) => hessian_out6_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out6_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out6_carry_i_5_n_0,
S(2) => hessian_out6_carry_i_6_n_0,
S(1) => hessian_out6_carry_i_7_n_0,
S(0) => hessian_out6_carry_i_8_n_0
);
\hessian_out6_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out6_carry_n_0,
CO(3) => \hessian_out6_carry__0_n_0\,
CO(2) => \hessian_out6_carry__0_n_1\,
CO(1) => \hessian_out6_carry__0_n_2\,
CO(0) => \hessian_out6_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__0_i_1_n_0\,
DI(2) => \hessian_out6_carry__0_i_2_n_0\,
DI(1) => \hessian_out6_carry__0_i_3_n_0\,
DI(0) => \hessian_out6_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__0_i_5_n_0\,
S(2) => \hessian_out6_carry__0_i_6_n_0\,
S(1) => \hessian_out6_carry__0_i_7_n_0\,
S(0) => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_1_n_0\
);
\hessian_out6_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_2_n_0\
);
\hessian_out6_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_3_n_0\
);
\hessian_out6_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_4_n_0\
);
\hessian_out6_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_5_n_0\
);
\hessian_out6_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_6_n_0\
);
\hessian_out6_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_7_n_0\
);
\hessian_out6_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__0_n_0\,
CO(3) => \hessian_out6_carry__1_n_0\,
CO(2) => \hessian_out6_carry__1_n_1\,
CO(1) => \hessian_out6_carry__1_n_2\,
CO(0) => \hessian_out6_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__1_i_1_n_0\,
DI(2) => \hessian_out6_carry__1_i_2_n_0\,
DI(1) => \hessian_out6_carry__1_i_3_n_0\,
DI(0) => \hessian_out6_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__1_i_5_n_0\,
S(2) => \hessian_out6_carry__1_i_6_n_0\,
S(1) => \hessian_out6_carry__1_i_7_n_0\,
S(0) => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_1_n_0\
);
\hessian_out6_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_2_n_0\
);
\hessian_out6_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_3_n_0\
);
\hessian_out6_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_4_n_0\
);
\hessian_out6_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_5_n_0\
);
\hessian_out6_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_6_n_0\
);
\hessian_out6_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_7_n_0\
);
\hessian_out6_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__1_n_0\,
CO(3) => \hessian_out6_carry__2_n_0\,
CO(2) => \hessian_out6_carry__2_n_1\,
CO(1) => \hessian_out6_carry__2_n_2\,
CO(0) => \hessian_out6_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__2_i_1_n_0\,
DI(2) => \hessian_out6_carry__2_i_2_n_0\,
DI(1) => \hessian_out6_carry__2_i_3_n_0\,
DI(0) => \hessian_out6_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__2_i_5_n_0\,
S(2) => \hessian_out6_carry__2_i_6_n_0\,
S(1) => \hessian_out6_carry__2_i_7_n_0\,
S(0) => \hessian_out6_carry__2_i_8_n_0\
);
\hessian_out6_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_1_n_0\
);
\hessian_out6_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_2_n_0\
);
\hessian_out6_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_3_n_0\
);
\hessian_out6_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_4_n_0\
);
\hessian_out6_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_5_n_0\
);
\hessian_out6_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_6_n_0\
);
\hessian_out6_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_7_n_0\
);
\hessian_out6_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_8_n_0\
);
hessian_out6_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_1_n_0
);
hessian_out6_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_2_n_0
);
hessian_out6_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_3_n_0
);
hessian_out6_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_4_n_0
);
hessian_out6_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_5_n_0
);
hessian_out6_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_6_n_0
);
hessian_out6_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_7_n_0
);
hessian_out6_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_8_n_0
);
hessian_out7_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out7_carry_n_0,
CO(2) => hessian_out7_carry_n_1,
CO(1) => hessian_out7_carry_n_2,
CO(0) => hessian_out7_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out7_carry_i_1_n_0,
DI(2) => hessian_out7_carry_i_2_n_0,
DI(1) => hessian_out7_carry_i_3_n_0,
DI(0) => hessian_out7_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out7_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out7_carry_i_5_n_0,
S(2) => hessian_out7_carry_i_6_n_0,
S(1) => hessian_out7_carry_i_7_n_0,
S(0) => hessian_out7_carry_i_8_n_0
);
\hessian_out7_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out7_carry_n_0,
CO(3) => \hessian_out7_carry__0_n_0\,
CO(2) => \hessian_out7_carry__0_n_1\,
CO(1) => \hessian_out7_carry__0_n_2\,
CO(0) => \hessian_out7_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__0_i_1_n_0\,
DI(2) => \hessian_out7_carry__0_i_2_n_0\,
DI(1) => \hessian_out7_carry__0_i_3_n_0\,
DI(0) => \hessian_out7_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__0_i_5_n_0\,
S(2) => \hessian_out7_carry__0_i_6_n_0\,
S(1) => \hessian_out7_carry__0_i_7_n_0\,
S(0) => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_1_n_0\
);
\hessian_out7_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_2_n_0\
);
\hessian_out7_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_3_n_0\
);
\hessian_out7_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_4_n_0\
);
\hessian_out7_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_5_n_0\
);
\hessian_out7_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_6_n_0\
);
\hessian_out7_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_7_n_0\
);
\hessian_out7_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__0_n_0\,
CO(3) => \hessian_out7_carry__1_n_0\,
CO(2) => \hessian_out7_carry__1_n_1\,
CO(1) => \hessian_out7_carry__1_n_2\,
CO(0) => \hessian_out7_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__1_i_1_n_0\,
DI(2) => \hessian_out7_carry__1_i_2_n_0\,
DI(1) => \hessian_out7_carry__1_i_3_n_0\,
DI(0) => \hessian_out7_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__1_i_5_n_0\,
S(2) => \hessian_out7_carry__1_i_6_n_0\,
S(1) => \hessian_out7_carry__1_i_7_n_0\,
S(0) => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_1_n_0\
);
\hessian_out7_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_2_n_0\
);
\hessian_out7_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_3_n_0\
);
\hessian_out7_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_4_n_0\
);
\hessian_out7_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_5_n_0\
);
\hessian_out7_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_6_n_0\
);
\hessian_out7_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_7_n_0\
);
\hessian_out7_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__1_n_0\,
CO(3) => \hessian_out7_carry__2_n_0\,
CO(2) => \hessian_out7_carry__2_n_1\,
CO(1) => \hessian_out7_carry__2_n_2\,
CO(0) => \hessian_out7_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__2_i_1_n_0\,
DI(2) => \hessian_out7_carry__2_i_2_n_0\,
DI(1) => \hessian_out7_carry__2_i_3_n_0\,
DI(0) => \hessian_out7_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__2_i_5_n_0\,
S(2) => \hessian_out7_carry__2_i_6_n_0\,
S(1) => \hessian_out7_carry__2_i_7_n_0\,
S(0) => \hessian_out7_carry__2_i_8_n_0\
);
\hessian_out7_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[1]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_1_n_0\
);
\hessian_out7_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_2_n_0\
);
\hessian_out7_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_3_n_0\
);
\hessian_out7_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_4_n_0\
);
\hessian_out7_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[1]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_5_n_0\
);
\hessian_out7_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_6_n_0\
);
\hessian_out7_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_7_n_0\
);
\hessian_out7_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_8_n_0\
);
hessian_out7_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_1_n_0
);
hessian_out7_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_2_n_0
);
hessian_out7_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_3_n_0
);
hessian_out7_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_4_n_0
);
hessian_out7_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_5_n_0
);
hessian_out7_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_6_n_0
);
hessian_out7_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_7_n_0
);
hessian_out7_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_8_n_0
);
\hessian_out8__15_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hessian_out8__15_carry_n_0\,
CO(2) => \hessian_out8__15_carry_n_1\,
CO(1) => \hessian_out8__15_carry_n_2\,
CO(0) => \hessian_out8__15_carry_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry_i_1_n_0\,
DI(2) => \hessian_out8__15_carry_i_2_n_0\,
DI(1) => \hessian_out8__15_carry_i_3_n_0\,
DI(0) => \hessian_out8__15_carry_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry_i_5_n_0\,
S(2) => \hessian_out8__15_carry_i_6_n_0\,
S(1) => \hessian_out8__15_carry_i_7_n_0\,
S(0) => \hessian_out8__15_carry_i_8_n_0\
);
\hessian_out8__15_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry_n_0\,
CO(3) => \hessian_out8__15_carry__0_n_0\,
CO(2) => \hessian_out8__15_carry__0_n_1\,
CO(1) => \hessian_out8__15_carry__0_n_2\,
CO(0) => \hessian_out8__15_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__0_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__0_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__0_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__0_i_5_n_0\,
S(2) => \hessian_out8__15_carry__0_i_6_n_0\,
S(1) => \hessian_out8__15_carry__0_i_7_n_0\,
S(0) => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_1_n_0\
);
\hessian_out8__15_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_2_n_0\
);
\hessian_out8__15_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_3_n_0\
);
\hessian_out8__15_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_4_n_0\
);
\hessian_out8__15_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_5_n_0\
);
\hessian_out8__15_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_6_n_0\
);
\hessian_out8__15_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_7_n_0\
);
\hessian_out8__15_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__0_n_0\,
CO(3) => \hessian_out8__15_carry__1_n_0\,
CO(2) => \hessian_out8__15_carry__1_n_1\,
CO(1) => \hessian_out8__15_carry__1_n_2\,
CO(0) => \hessian_out8__15_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__1_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__1_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__1_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__1_i_5_n_0\,
S(2) => \hessian_out8__15_carry__1_i_6_n_0\,
S(1) => \hessian_out8__15_carry__1_i_7_n_0\,
S(0) => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_1_n_0\
);
\hessian_out8__15_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_2_n_0\
);
\hessian_out8__15_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_3_n_0\
);
\hessian_out8__15_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_4_n_0\
);
\hessian_out8__15_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_5_n_0\
);
\hessian_out8__15_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_6_n_0\
);
\hessian_out8__15_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_7_n_0\
);
\hessian_out8__15_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__1_n_0\,
CO(3) => \hessian_out8__15_carry__2_n_0\,
CO(2) => \hessian_out8__15_carry__2_n_1\,
CO(1) => \hessian_out8__15_carry__2_n_2\,
CO(0) => \hessian_out8__15_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__2_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__2_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__2_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__2_i_5_n_0\,
S(2) => \hessian_out8__15_carry__2_i_6_n_0\,
S(1) => \hessian_out8__15_carry__2_i_7_n_0\,
S(0) => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_1_n_0\
);
\hessian_out8__15_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_2_n_0\
);
\hessian_out8__15_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_3_n_0\
);
\hessian_out8__15_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_4_n_0\
);
\hessian_out8__15_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_5_n_0\
);
\hessian_out8__15_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_6_n_0\
);
\hessian_out8__15_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_7_n_0\
);
\hessian_out8__15_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_1_n_0\
);
\hessian_out8__15_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_2_n_0\
);
\hessian_out8__15_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_3_n_0\
);
\hessian_out8__15_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_4_n_0\
);
\hessian_out8__15_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_5_n_0\
);
\hessian_out8__15_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_6_n_0\
);
\hessian_out8__15_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_7_n_0\
);
\hessian_out8__15_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_8_n_0\
);
hessian_out8_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out8_carry_n_0,
CO(2) => hessian_out8_carry_n_1,
CO(1) => hessian_out8_carry_n_2,
CO(0) => hessian_out8_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out8_carry_i_1_n_0,
DI(2) => hessian_out8_carry_i_2_n_0,
DI(1) => hessian_out8_carry_i_3_n_0,
DI(0) => hessian_out8_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out8_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out8_carry_i_5_n_0,
S(2) => hessian_out8_carry_i_6_n_0,
S(1) => hessian_out8_carry_i_7_n_0,
S(0) => hessian_out8_carry_i_8_n_0
);
\hessian_out8_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out8_carry_n_0,
CO(3) => \hessian_out8_carry__0_n_0\,
CO(2) => \hessian_out8_carry__0_n_1\,
CO(1) => \hessian_out8_carry__0_n_2\,
CO(0) => \hessian_out8_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__0_i_1_n_0\,
DI(2) => \hessian_out8_carry__0_i_2_n_0\,
DI(1) => \hessian_out8_carry__0_i_3_n_0\,
DI(0) => \hessian_out8_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__0_i_5_n_0\,
S(2) => \hessian_out8_carry__0_i_6_n_0\,
S(1) => \hessian_out8_carry__0_i_7_n_0\,
S(0) => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[0]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_1_n_0\
);
\hessian_out8_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[0]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_2_n_0\
);
\hessian_out8_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[0]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_3_n_0\
);
\hessian_out8_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[0]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_4_n_0\
);
\hessian_out8_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[0]\(14),
I2 => \hessian_reg[6]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_5_n_0\
);
\hessian_out8_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[0]\(12),
I2 => \hessian_reg[6]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_6_n_0\
);
\hessian_out8_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[0]\(10),
I2 => \hessian_reg[6]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_7_n_0\
);
\hessian_out8_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[0]\(8),
I2 => \hessian_reg[6]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__0_n_0\,
CO(3) => \hessian_out8_carry__1_n_0\,
CO(2) => \hessian_out8_carry__1_n_1\,
CO(1) => \hessian_out8_carry__1_n_2\,
CO(0) => \hessian_out8_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__1_i_1_n_0\,
DI(2) => \hessian_out8_carry__1_i_2_n_0\,
DI(1) => \hessian_out8_carry__1_i_3_n_0\,
DI(0) => \hessian_out8_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__1_i_5_n_0\,
S(2) => \hessian_out8_carry__1_i_6_n_0\,
S(1) => \hessian_out8_carry__1_i_7_n_0\,
S(0) => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[0]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_1_n_0\
);
\hessian_out8_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[0]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_2_n_0\
);
\hessian_out8_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[0]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_3_n_0\
);
\hessian_out8_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[0]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_4_n_0\
);
\hessian_out8_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[0]\(22),
I2 => \hessian_reg[6]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_5_n_0\
);
\hessian_out8_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[0]\(20),
I2 => \hessian_reg[6]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_6_n_0\
);
\hessian_out8_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[0]\(18),
I2 => \hessian_reg[6]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_7_n_0\
);
\hessian_out8_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[0]\(16),
I2 => \hessian_reg[6]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__1_n_0\,
CO(3) => \hessian_out8_carry__2_n_0\,
CO(2) => \hessian_out8_carry__2_n_1\,
CO(1) => \hessian_out8_carry__2_n_2\,
CO(0) => \hessian_out8_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__2_i_1_n_0\,
DI(2) => \hessian_out8_carry__2_i_2_n_0\,
DI(1) => \hessian_out8_carry__2_i_3_n_0\,
DI(0) => \hessian_out8_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__2_i_5_n_0\,
S(2) => \hessian_out8_carry__2_i_6_n_0\,
S(1) => \hessian_out8_carry__2_i_7_n_0\,
S(0) => \hessian_out8_carry__2_i_8_n_0\
);
\hessian_out8_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[0]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_1_n_0\
);
\hessian_out8_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[0]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_2_n_0\
);
\hessian_out8_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[0]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_3_n_0\
);
\hessian_out8_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[0]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_4_n_0\
);
\hessian_out8_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[0]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_5_n_0\
);
\hessian_out8_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[0]\(28),
I2 => \hessian_reg[6]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_6_n_0\
);
\hessian_out8_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[0]\(26),
I2 => \hessian_reg[6]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_7_n_0\
);
\hessian_out8_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[0]\(24),
I2 => \hessian_reg[6]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_8_n_0\
);
hessian_out8_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[0]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_1_n_0
);
hessian_out8_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[0]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_2_n_0
);
hessian_out8_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[0]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_3_n_0
);
hessian_out8_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[0]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_4_n_0
);
hessian_out8_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[0]\(6),
I2 => \hessian_reg[6]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_5_n_0
);
hessian_out8_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[0]\(4),
I2 => \hessian_reg[6]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_6_n_0
);
hessian_out8_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[0]\(2),
I2 => \hessian_reg[6]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_7_n_0
);
hessian_out8_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[0]\(0),
I2 => \hessian_reg[6]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_8_n_0
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80000"
)
port map (
I0 => active,
I1 => \hessian_out8__15_carry__2_n_0\,
I2 => \hessian_out[31]_i_2_n_0\,
I3 => \hessian_out2_carry__2_n_0\,
I4 => enable,
O => \hessian_out[31]_i_1_n_0\
);
\hessian_out[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \hessian_out3_carry__2_n_0\,
I1 => \hessian_out5_carry__2_n_0\,
I2 => \hessian_out8_carry__2_n_0\,
I3 => \hessian_out7_carry__2_n_0\,
I4 => \hessian_out6_carry__2_n_0\,
I5 => \hessian_out4_carry__2_n_0\,
O => \hessian_out[31]_i_2_n_0\
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => hessian_out(0),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => hessian_out(10),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => hessian_out(11),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => hessian_out(12),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => hessian_out(13),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => hessian_out(14),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => hessian_out(15),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => hessian_out(16),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => hessian_out(17),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => hessian_out(18),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => hessian_out(19),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => hessian_out(1),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => hessian_out(20),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => hessian_out(21),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => hessian_out(22),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => hessian_out(23),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => hessian_out(24),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => hessian_out(25),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => hessian_out(26),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => hessian_out(27),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => hessian_out(28),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => hessian_out(29),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => hessian_out(2),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => hessian_out(30),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => hessian_out(31),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => hessian_out(3),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => hessian_out(4),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => hessian_out(5),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => hessian_out(6),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => hessian_out(7),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => hessian_out(8),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => hessian_out(9),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(0),
Q => \hessian_reg[0]\(0),
R => '0'
);
\hessian_reg[0][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(10),
Q => \hessian_reg[0]\(10),
R => '0'
);
\hessian_reg[0][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(11),
Q => \hessian_reg[0]\(11),
R => '0'
);
\hessian_reg[0][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(12),
Q => \hessian_reg[0]\(12),
R => '0'
);
\hessian_reg[0][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(13),
Q => \hessian_reg[0]\(13),
R => '0'
);
\hessian_reg[0][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(14),
Q => \hessian_reg[0]\(14),
R => '0'
);
\hessian_reg[0][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(15),
Q => \hessian_reg[0]\(15),
R => '0'
);
\hessian_reg[0][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(16),
Q => \hessian_reg[0]\(16),
R => '0'
);
\hessian_reg[0][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(17),
Q => \hessian_reg[0]\(17),
R => '0'
);
\hessian_reg[0][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(18),
Q => \hessian_reg[0]\(18),
R => '0'
);
\hessian_reg[0][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(19),
Q => \hessian_reg[0]\(19),
R => '0'
);
\hessian_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(1),
Q => \hessian_reg[0]\(1),
R => '0'
);
\hessian_reg[0][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(20),
Q => \hessian_reg[0]\(20),
R => '0'
);
\hessian_reg[0][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(21),
Q => \hessian_reg[0]\(21),
R => '0'
);
\hessian_reg[0][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(22),
Q => \hessian_reg[0]\(22),
R => '0'
);
\hessian_reg[0][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(23),
Q => \hessian_reg[0]\(23),
R => '0'
);
\hessian_reg[0][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(24),
Q => \hessian_reg[0]\(24),
R => '0'
);
\hessian_reg[0][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(25),
Q => \hessian_reg[0]\(25),
R => '0'
);
\hessian_reg[0][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(26),
Q => \hessian_reg[0]\(26),
R => '0'
);
\hessian_reg[0][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(27),
Q => \hessian_reg[0]\(27),
R => '0'
);
\hessian_reg[0][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(28),
Q => \hessian_reg[0]\(28),
R => '0'
);
\hessian_reg[0][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(29),
Q => \hessian_reg[0]\(29),
R => '0'
);
\hessian_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(2),
Q => \hessian_reg[0]\(2),
R => '0'
);
\hessian_reg[0][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(30),
Q => \hessian_reg[0]\(30),
R => '0'
);
\hessian_reg[0][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(31),
Q => \hessian_reg[0]\(31),
R => '0'
);
\hessian_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(3),
Q => \hessian_reg[0]\(3),
R => '0'
);
\hessian_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(4),
Q => \hessian_reg[0]\(4),
R => '0'
);
\hessian_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(5),
Q => \hessian_reg[0]\(5),
R => '0'
);
\hessian_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(6),
Q => \hessian_reg[0]\(6),
R => '0'
);
\hessian_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(7),
Q => \hessian_reg[0]\(7),
R => '0'
);
\hessian_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(8),
Q => \hessian_reg[0]\(8),
R => '0'
);
\hessian_reg[0][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(9),
Q => \hessian_reg[0]\(9),
R => '0'
);
\hessian_reg[10][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(0),
Q => \hessian_reg[10]\(0),
R => '0'
);
\hessian_reg[10][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(10),
Q => \hessian_reg[10]\(10),
R => '0'
);
\hessian_reg[10][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(11),
Q => \hessian_reg[10]\(11),
R => '0'
);
\hessian_reg[10][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(12),
Q => \hessian_reg[10]\(12),
R => '0'
);
\hessian_reg[10][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(13),
Q => \hessian_reg[10]\(13),
R => '0'
);
\hessian_reg[10][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(14),
Q => \hessian_reg[10]\(14),
R => '0'
);
\hessian_reg[10][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(15),
Q => \hessian_reg[10]\(15),
R => '0'
);
\hessian_reg[10][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(16),
Q => \hessian_reg[10]\(16),
R => '0'
);
\hessian_reg[10][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(17),
Q => \hessian_reg[10]\(17),
R => '0'
);
\hessian_reg[10][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(18),
Q => \hessian_reg[10]\(18),
R => '0'
);
\hessian_reg[10][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(19),
Q => \hessian_reg[10]\(19),
R => '0'
);
\hessian_reg[10][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(1),
Q => \hessian_reg[10]\(1),
R => '0'
);
\hessian_reg[10][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(20),
Q => \hessian_reg[10]\(20),
R => '0'
);
\hessian_reg[10][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(21),
Q => \hessian_reg[10]\(21),
R => '0'
);
\hessian_reg[10][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(22),
Q => \hessian_reg[10]\(22),
R => '0'
);
\hessian_reg[10][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(23),
Q => \hessian_reg[10]\(23),
R => '0'
);
\hessian_reg[10][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(24),
Q => \hessian_reg[10]\(24),
R => '0'
);
\hessian_reg[10][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(25),
Q => \hessian_reg[10]\(25),
R => '0'
);
\hessian_reg[10][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(26),
Q => \hessian_reg[10]\(26),
R => '0'
);
\hessian_reg[10][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(27),
Q => \hessian_reg[10]\(27),
R => '0'
);
\hessian_reg[10][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(28),
Q => \hessian_reg[10]\(28),
R => '0'
);
\hessian_reg[10][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(29),
Q => \hessian_reg[10]\(29),
R => '0'
);
\hessian_reg[10][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(2),
Q => \hessian_reg[10]\(2),
R => '0'
);
\hessian_reg[10][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(30),
Q => \hessian_reg[10]\(30),
R => '0'
);
\hessian_reg[10][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(31),
Q => \hessian_reg[10]\(31),
R => '0'
);
\hessian_reg[10][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(3),
Q => \hessian_reg[10]\(3),
R => '0'
);
\hessian_reg[10][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(4),
Q => \hessian_reg[10]\(4),
R => '0'
);
\hessian_reg[10][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(5),
Q => \hessian_reg[10]\(5),
R => '0'
);
\hessian_reg[10][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(6),
Q => \hessian_reg[10]\(6),
R => '0'
);
\hessian_reg[10][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(7),
Q => \hessian_reg[10]\(7),
R => '0'
);
\hessian_reg[10][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(8),
Q => \hessian_reg[10]\(8),
R => '0'
);
\hessian_reg[10][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(9),
Q => \hessian_reg[10]\(9),
R => '0'
);
\hessian_reg[11][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(0),
Q => \hessian_reg[11]\(0),
R => '0'
);
\hessian_reg[11][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(10),
Q => \hessian_reg[11]\(10),
R => '0'
);
\hessian_reg[11][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(11),
Q => \hessian_reg[11]\(11),
R => '0'
);
\hessian_reg[11][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(12),
Q => \hessian_reg[11]\(12),
R => '0'
);
\hessian_reg[11][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(13),
Q => \hessian_reg[11]\(13),
R => '0'
);
\hessian_reg[11][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(14),
Q => \hessian_reg[11]\(14),
R => '0'
);
\hessian_reg[11][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(15),
Q => \hessian_reg[11]\(15),
R => '0'
);
\hessian_reg[11][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(16),
Q => \hessian_reg[11]\(16),
R => '0'
);
\hessian_reg[11][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(17),
Q => \hessian_reg[11]\(17),
R => '0'
);
\hessian_reg[11][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(18),
Q => \hessian_reg[11]\(18),
R => '0'
);
\hessian_reg[11][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(19),
Q => \hessian_reg[11]\(19),
R => '0'
);
\hessian_reg[11][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(1),
Q => \hessian_reg[11]\(1),
R => '0'
);
\hessian_reg[11][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(20),
Q => \hessian_reg[11]\(20),
R => '0'
);
\hessian_reg[11][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(21),
Q => \hessian_reg[11]\(21),
R => '0'
);
\hessian_reg[11][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(22),
Q => \hessian_reg[11]\(22),
R => '0'
);
\hessian_reg[11][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(23),
Q => \hessian_reg[11]\(23),
R => '0'
);
\hessian_reg[11][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(24),
Q => \hessian_reg[11]\(24),
R => '0'
);
\hessian_reg[11][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(25),
Q => \hessian_reg[11]\(25),
R => '0'
);
\hessian_reg[11][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(26),
Q => \hessian_reg[11]\(26),
R => '0'
);
\hessian_reg[11][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(27),
Q => \hessian_reg[11]\(27),
R => '0'
);
\hessian_reg[11][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(28),
Q => \hessian_reg[11]\(28),
R => '0'
);
\hessian_reg[11][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(29),
Q => \hessian_reg[11]\(29),
R => '0'
);
\hessian_reg[11][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(2),
Q => \hessian_reg[11]\(2),
R => '0'
);
\hessian_reg[11][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(30),
Q => \hessian_reg[11]\(30),
R => '0'
);
\hessian_reg[11][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(31),
Q => \hessian_reg[11]\(31),
R => '0'
);
\hessian_reg[11][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(3),
Q => \hessian_reg[11]\(3),
R => '0'
);
\hessian_reg[11][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(4),
Q => \hessian_reg[11]\(4),
R => '0'
);
\hessian_reg[11][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(5),
Q => \hessian_reg[11]\(5),
R => '0'
);
\hessian_reg[11][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(6),
Q => \hessian_reg[11]\(6),
R => '0'
);
\hessian_reg[11][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(7),
Q => \hessian_reg[11]\(7),
R => '0'
);
\hessian_reg[11][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(8),
Q => \hessian_reg[11]\(8),
R => '0'
);
\hessian_reg[11][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(9),
Q => \hessian_reg[11]\(9),
R => '0'
);
\hessian_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(0),
Q => \hessian_reg[1]\(0),
R => '0'
);
\hessian_reg[1][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(10),
Q => \hessian_reg[1]\(10),
R => '0'
);
\hessian_reg[1][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(11),
Q => \hessian_reg[1]\(11),
R => '0'
);
\hessian_reg[1][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(12),
Q => \hessian_reg[1]\(12),
R => '0'
);
\hessian_reg[1][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(13),
Q => \hessian_reg[1]\(13),
R => '0'
);
\hessian_reg[1][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(14),
Q => \hessian_reg[1]\(14),
R => '0'
);
\hessian_reg[1][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(15),
Q => \hessian_reg[1]\(15),
R => '0'
);
\hessian_reg[1][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(16),
Q => \hessian_reg[1]\(16),
R => '0'
);
\hessian_reg[1][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(17),
Q => \hessian_reg[1]\(17),
R => '0'
);
\hessian_reg[1][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(18),
Q => \hessian_reg[1]\(18),
R => '0'
);
\hessian_reg[1][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(19),
Q => \hessian_reg[1]\(19),
R => '0'
);
\hessian_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(1),
Q => \hessian_reg[1]\(1),
R => '0'
);
\hessian_reg[1][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(20),
Q => \hessian_reg[1]\(20),
R => '0'
);
\hessian_reg[1][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(21),
Q => \hessian_reg[1]\(21),
R => '0'
);
\hessian_reg[1][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(22),
Q => \hessian_reg[1]\(22),
R => '0'
);
\hessian_reg[1][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(23),
Q => \hessian_reg[1]\(23),
R => '0'
);
\hessian_reg[1][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(24),
Q => \hessian_reg[1]\(24),
R => '0'
);
\hessian_reg[1][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(25),
Q => \hessian_reg[1]\(25),
R => '0'
);
\hessian_reg[1][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(26),
Q => \hessian_reg[1]\(26),
R => '0'
);
\hessian_reg[1][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(27),
Q => \hessian_reg[1]\(27),
R => '0'
);
\hessian_reg[1][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(28),
Q => \hessian_reg[1]\(28),
R => '0'
);
\hessian_reg[1][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(29),
Q => \hessian_reg[1]\(29),
R => '0'
);
\hessian_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(2),
Q => \hessian_reg[1]\(2),
R => '0'
);
\hessian_reg[1][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(30),
Q => \hessian_reg[1]\(30),
R => '0'
);
\hessian_reg[1][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(31),
Q => \hessian_reg[1]\(31),
R => '0'
);
\hessian_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(3),
Q => \hessian_reg[1]\(3),
R => '0'
);
\hessian_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(4),
Q => \hessian_reg[1]\(4),
R => '0'
);
\hessian_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(5),
Q => \hessian_reg[1]\(5),
R => '0'
);
\hessian_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(6),
Q => \hessian_reg[1]\(6),
R => '0'
);
\hessian_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(7),
Q => \hessian_reg[1]\(7),
R => '0'
);
\hessian_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(8),
Q => \hessian_reg[1]\(8),
R => '0'
);
\hessian_reg[1][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(9),
Q => \hessian_reg[1]\(9),
R => '0'
);
\hessian_reg[4][0]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(0),
Q => \hessian_reg[4][0]_srl3_n_0\
);
\hessian_reg[4][10]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(10),
Q => \hessian_reg[4][10]_srl3_n_0\
);
\hessian_reg[4][11]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(11),
Q => \hessian_reg[4][11]_srl3_n_0\
);
\hessian_reg[4][12]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(12),
Q => \hessian_reg[4][12]_srl3_n_0\
);
\hessian_reg[4][13]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(13),
Q => \hessian_reg[4][13]_srl3_n_0\
);
\hessian_reg[4][14]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(14),
Q => \hessian_reg[4][14]_srl3_n_0\
);
\hessian_reg[4][15]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(15),
Q => \hessian_reg[4][15]_srl3_n_0\
);
\hessian_reg[4][16]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(16),
Q => \hessian_reg[4][16]_srl3_n_0\
);
\hessian_reg[4][17]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(17),
Q => \hessian_reg[4][17]_srl3_n_0\
);
\hessian_reg[4][18]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(18),
Q => \hessian_reg[4][18]_srl3_n_0\
);
\hessian_reg[4][19]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(19),
Q => \hessian_reg[4][19]_srl3_n_0\
);
\hessian_reg[4][1]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(1),
Q => \hessian_reg[4][1]_srl3_n_0\
);
\hessian_reg[4][20]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(20),
Q => \hessian_reg[4][20]_srl3_n_0\
);
\hessian_reg[4][21]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(21),
Q => \hessian_reg[4][21]_srl3_n_0\
);
\hessian_reg[4][22]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(22),
Q => \hessian_reg[4][22]_srl3_n_0\
);
\hessian_reg[4][23]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(23),
Q => \hessian_reg[4][23]_srl3_n_0\
);
\hessian_reg[4][24]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(24),
Q => \hessian_reg[4][24]_srl3_n_0\
);
\hessian_reg[4][25]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(25),
Q => \hessian_reg[4][25]_srl3_n_0\
);
\hessian_reg[4][26]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(26),
Q => \hessian_reg[4][26]_srl3_n_0\
);
\hessian_reg[4][27]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(27),
Q => \hessian_reg[4][27]_srl3_n_0\
);
\hessian_reg[4][28]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(28),
Q => \hessian_reg[4][28]_srl3_n_0\
);
\hessian_reg[4][29]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(29),
Q => \hessian_reg[4][29]_srl3_n_0\
);
\hessian_reg[4][2]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(2),
Q => \hessian_reg[4][2]_srl3_n_0\
);
\hessian_reg[4][30]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(30),
Q => \hessian_reg[4][30]_srl3_n_0\
);
\hessian_reg[4][31]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(31),
Q => \hessian_reg[4][31]_srl3_n_0\
);
\hessian_reg[4][3]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(3),
Q => \hessian_reg[4][3]_srl3_n_0\
);
\hessian_reg[4][4]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(4),
Q => \hessian_reg[4][4]_srl3_n_0\
);
\hessian_reg[4][5]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(5),
Q => \hessian_reg[4][5]_srl3_n_0\
);
\hessian_reg[4][6]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(6),
Q => \hessian_reg[4][6]_srl3_n_0\
);
\hessian_reg[4][7]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(7),
Q => \hessian_reg[4][7]_srl3_n_0\
);
\hessian_reg[4][8]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(8),
Q => \hessian_reg[4][8]_srl3_n_0\
);
\hessian_reg[4][9]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(9),
Q => \hessian_reg[4][9]_srl3_n_0\
);
\hessian_reg[5][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][0]_srl3_n_0\,
Q => \hessian_reg[5]\(0),
R => '0'
);
\hessian_reg[5][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][10]_srl3_n_0\,
Q => \hessian_reg[5]\(10),
R => '0'
);
\hessian_reg[5][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][11]_srl3_n_0\,
Q => \hessian_reg[5]\(11),
R => '0'
);
\hessian_reg[5][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][12]_srl3_n_0\,
Q => \hessian_reg[5]\(12),
R => '0'
);
\hessian_reg[5][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][13]_srl3_n_0\,
Q => \hessian_reg[5]\(13),
R => '0'
);
\hessian_reg[5][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][14]_srl3_n_0\,
Q => \hessian_reg[5]\(14),
R => '0'
);
\hessian_reg[5][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][15]_srl3_n_0\,
Q => \hessian_reg[5]\(15),
R => '0'
);
\hessian_reg[5][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][16]_srl3_n_0\,
Q => \hessian_reg[5]\(16),
R => '0'
);
\hessian_reg[5][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][17]_srl3_n_0\,
Q => \hessian_reg[5]\(17),
R => '0'
);
\hessian_reg[5][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][18]_srl3_n_0\,
Q => \hessian_reg[5]\(18),
R => '0'
);
\hessian_reg[5][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][19]_srl3_n_0\,
Q => \hessian_reg[5]\(19),
R => '0'
);
\hessian_reg[5][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][1]_srl3_n_0\,
Q => \hessian_reg[5]\(1),
R => '0'
);
\hessian_reg[5][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][20]_srl3_n_0\,
Q => \hessian_reg[5]\(20),
R => '0'
);
\hessian_reg[5][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][21]_srl3_n_0\,
Q => \hessian_reg[5]\(21),
R => '0'
);
\hessian_reg[5][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][22]_srl3_n_0\,
Q => \hessian_reg[5]\(22),
R => '0'
);
\hessian_reg[5][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][23]_srl3_n_0\,
Q => \hessian_reg[5]\(23),
R => '0'
);
\hessian_reg[5][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][24]_srl3_n_0\,
Q => \hessian_reg[5]\(24),
R => '0'
);
\hessian_reg[5][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][25]_srl3_n_0\,
Q => \hessian_reg[5]\(25),
R => '0'
);
\hessian_reg[5][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][26]_srl3_n_0\,
Q => \hessian_reg[5]\(26),
R => '0'
);
\hessian_reg[5][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][27]_srl3_n_0\,
Q => \hessian_reg[5]\(27),
R => '0'
);
\hessian_reg[5][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][28]_srl3_n_0\,
Q => \hessian_reg[5]\(28),
R => '0'
);
\hessian_reg[5][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][29]_srl3_n_0\,
Q => \hessian_reg[5]\(29),
R => '0'
);
\hessian_reg[5][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][2]_srl3_n_0\,
Q => \hessian_reg[5]\(2),
R => '0'
);
\hessian_reg[5][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][30]_srl3_n_0\,
Q => \hessian_reg[5]\(30),
R => '0'
);
\hessian_reg[5][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][31]_srl3_n_0\,
Q => \hessian_reg[5]\(31),
R => '0'
);
\hessian_reg[5][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][3]_srl3_n_0\,
Q => \hessian_reg[5]\(3),
R => '0'
);
\hessian_reg[5][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][4]_srl3_n_0\,
Q => \hessian_reg[5]\(4),
R => '0'
);
\hessian_reg[5][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][5]_srl3_n_0\,
Q => \hessian_reg[5]\(5),
R => '0'
);
\hessian_reg[5][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][6]_srl3_n_0\,
Q => \hessian_reg[5]\(6),
R => '0'
);
\hessian_reg[5][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][7]_srl3_n_0\,
Q => \hessian_reg[5]\(7),
R => '0'
);
\hessian_reg[5][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][8]_srl3_n_0\,
Q => \hessian_reg[5]\(8),
R => '0'
);
\hessian_reg[5][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][9]_srl3_n_0\,
Q => \hessian_reg[5]\(9),
R => '0'
);
\hessian_reg[6][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(0),
Q => \hessian_reg[6]\(0),
R => '0'
);
\hessian_reg[6][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(10),
Q => \hessian_reg[6]\(10),
R => '0'
);
\hessian_reg[6][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(11),
Q => \hessian_reg[6]\(11),
R => '0'
);
\hessian_reg[6][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(12),
Q => \hessian_reg[6]\(12),
R => '0'
);
\hessian_reg[6][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(13),
Q => \hessian_reg[6]\(13),
R => '0'
);
\hessian_reg[6][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(14),
Q => \hessian_reg[6]\(14),
R => '0'
);
\hessian_reg[6][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(15),
Q => \hessian_reg[6]\(15),
R => '0'
);
\hessian_reg[6][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(16),
Q => \hessian_reg[6]\(16),
R => '0'
);
\hessian_reg[6][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(17),
Q => \hessian_reg[6]\(17),
R => '0'
);
\hessian_reg[6][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(18),
Q => \hessian_reg[6]\(18),
R => '0'
);
\hessian_reg[6][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(19),
Q => \hessian_reg[6]\(19),
R => '0'
);
\hessian_reg[6][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(1),
Q => \hessian_reg[6]\(1),
R => '0'
);
\hessian_reg[6][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(20),
Q => \hessian_reg[6]\(20),
R => '0'
);
\hessian_reg[6][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(21),
Q => \hessian_reg[6]\(21),
R => '0'
);
\hessian_reg[6][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(22),
Q => \hessian_reg[6]\(22),
R => '0'
);
\hessian_reg[6][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(23),
Q => \hessian_reg[6]\(23),
R => '0'
);
\hessian_reg[6][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(24),
Q => \hessian_reg[6]\(24),
R => '0'
);
\hessian_reg[6][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(25),
Q => \hessian_reg[6]\(25),
R => '0'
);
\hessian_reg[6][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(26),
Q => \hessian_reg[6]\(26),
R => '0'
);
\hessian_reg[6][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(27),
Q => \hessian_reg[6]\(27),
R => '0'
);
\hessian_reg[6][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(28),
Q => \hessian_reg[6]\(28),
R => '0'
);
\hessian_reg[6][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(29),
Q => \hessian_reg[6]\(29),
R => '0'
);
\hessian_reg[6][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(2),
Q => \hessian_reg[6]\(2),
R => '0'
);
\hessian_reg[6][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(30),
Q => \hessian_reg[6]\(30),
R => '0'
);
\hessian_reg[6][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(31),
Q => \hessian_reg[6]\(31),
R => '0'
);
\hessian_reg[6][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(3),
Q => \hessian_reg[6]\(3),
R => '0'
);
\hessian_reg[6][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(4),
Q => \hessian_reg[6]\(4),
R => '0'
);
\hessian_reg[6][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(5),
Q => \hessian_reg[6]\(5),
R => '0'
);
\hessian_reg[6][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(6),
Q => \hessian_reg[6]\(6),
R => '0'
);
\hessian_reg[6][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(7),
Q => \hessian_reg[6]\(7),
R => '0'
);
\hessian_reg[6][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(8),
Q => \hessian_reg[6]\(8),
R => '0'
);
\hessian_reg[6][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(9),
Q => \hessian_reg[6]\(9),
R => '0'
);
\hessian_reg[7][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => \hessian_reg[7]\(0),
R => '0'
);
\hessian_reg[7][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => \hessian_reg[7]\(10),
R => '0'
);
\hessian_reg[7][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => \hessian_reg[7]\(11),
R => '0'
);
\hessian_reg[7][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => \hessian_reg[7]\(12),
R => '0'
);
\hessian_reg[7][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => \hessian_reg[7]\(13),
R => '0'
);
\hessian_reg[7][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => \hessian_reg[7]\(14),
R => '0'
);
\hessian_reg[7][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => \hessian_reg[7]\(15),
R => '0'
);
\hessian_reg[7][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => \hessian_reg[7]\(16),
R => '0'
);
\hessian_reg[7][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => \hessian_reg[7]\(17),
R => '0'
);
\hessian_reg[7][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => \hessian_reg[7]\(18),
R => '0'
);
\hessian_reg[7][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => \hessian_reg[7]\(19),
R => '0'
);
\hessian_reg[7][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => \hessian_reg[7]\(1),
R => '0'
);
\hessian_reg[7][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => \hessian_reg[7]\(20),
R => '0'
);
\hessian_reg[7][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => \hessian_reg[7]\(21),
R => '0'
);
\hessian_reg[7][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => \hessian_reg[7]\(22),
R => '0'
);
\hessian_reg[7][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => \hessian_reg[7]\(23),
R => '0'
);
\hessian_reg[7][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => \hessian_reg[7]\(24),
R => '0'
);
\hessian_reg[7][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => \hessian_reg[7]\(25),
R => '0'
);
\hessian_reg[7][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => \hessian_reg[7]\(26),
R => '0'
);
\hessian_reg[7][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => \hessian_reg[7]\(27),
R => '0'
);
\hessian_reg[7][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => \hessian_reg[7]\(28),
R => '0'
);
\hessian_reg[7][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => \hessian_reg[7]\(29),
R => '0'
);
\hessian_reg[7][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => \hessian_reg[7]\(2),
R => '0'
);
\hessian_reg[7][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => \hessian_reg[7]\(30),
R => '0'
);
\hessian_reg[7][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => \hessian_reg[7]\(31),
R => '0'
);
\hessian_reg[7][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => \hessian_reg[7]\(3),
R => '0'
);
\hessian_reg[7][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => \hessian_reg[7]\(4),
R => '0'
);
\hessian_reg[7][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => \hessian_reg[7]\(5),
R => '0'
);
\hessian_reg[7][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => \hessian_reg[7]\(6),
R => '0'
);
\hessian_reg[7][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => \hessian_reg[7]\(7),
R => '0'
);
\hessian_reg[7][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => \hessian_reg[7]\(8),
R => '0'
);
\hessian_reg[7][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => \hessian_reg[7]\(9),
R => '0'
);
\hessian_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(0),
Q => \hessian_reg[8]\(0),
R => '0'
);
\hessian_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(10),
Q => \hessian_reg[8]\(10),
R => '0'
);
\hessian_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(11),
Q => \hessian_reg[8]\(11),
R => '0'
);
\hessian_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(12),
Q => \hessian_reg[8]\(12),
R => '0'
);
\hessian_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(13),
Q => \hessian_reg[8]\(13),
R => '0'
);
\hessian_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(14),
Q => \hessian_reg[8]\(14),
R => '0'
);
\hessian_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(15),
Q => \hessian_reg[8]\(15),
R => '0'
);
\hessian_reg[8][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(16),
Q => \hessian_reg[8]\(16),
R => '0'
);
\hessian_reg[8][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(17),
Q => \hessian_reg[8]\(17),
R => '0'
);
\hessian_reg[8][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(18),
Q => \hessian_reg[8]\(18),
R => '0'
);
\hessian_reg[8][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(19),
Q => \hessian_reg[8]\(19),
R => '0'
);
\hessian_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(1),
Q => \hessian_reg[8]\(1),
R => '0'
);
\hessian_reg[8][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(20),
Q => \hessian_reg[8]\(20),
R => '0'
);
\hessian_reg[8][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(21),
Q => \hessian_reg[8]\(21),
R => '0'
);
\hessian_reg[8][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(22),
Q => \hessian_reg[8]\(22),
R => '0'
);
\hessian_reg[8][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(23),
Q => \hessian_reg[8]\(23),
R => '0'
);
\hessian_reg[8][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(24),
Q => \hessian_reg[8]\(24),
R => '0'
);
\hessian_reg[8][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(25),
Q => \hessian_reg[8]\(25),
R => '0'
);
\hessian_reg[8][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(26),
Q => \hessian_reg[8]\(26),
R => '0'
);
\hessian_reg[8][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(27),
Q => \hessian_reg[8]\(27),
R => '0'
);
\hessian_reg[8][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(28),
Q => \hessian_reg[8]\(28),
R => '0'
);
\hessian_reg[8][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(29),
Q => \hessian_reg[8]\(29),
R => '0'
);
\hessian_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(2),
Q => \hessian_reg[8]\(2),
R => '0'
);
\hessian_reg[8][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(30),
Q => \hessian_reg[8]\(30),
R => '0'
);
\hessian_reg[8][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(31),
Q => \hessian_reg[8]\(31),
R => '0'
);
\hessian_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(3),
Q => \hessian_reg[8]\(3),
R => '0'
);
\hessian_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(4),
Q => \hessian_reg[8]\(4),
R => '0'
);
\hessian_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(5),
Q => \hessian_reg[8]\(5),
R => '0'
);
\hessian_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(6),
Q => \hessian_reg[8]\(6),
R => '0'
);
\hessian_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(7),
Q => \hessian_reg[8]\(7),
R => '0'
);
\hessian_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(8),
Q => \hessian_reg[8]\(8),
R => '0'
);
\hessian_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(9),
Q => \hessian_reg[8]\(9),
R => '0'
);
\hessian_reg[9][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(0),
Q => \hessian_reg[9]\(0),
R => '0'
);
\hessian_reg[9][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(10),
Q => \hessian_reg[9]\(10),
R => '0'
);
\hessian_reg[9][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(11),
Q => \hessian_reg[9]\(11),
R => '0'
);
\hessian_reg[9][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(12),
Q => \hessian_reg[9]\(12),
R => '0'
);
\hessian_reg[9][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(13),
Q => \hessian_reg[9]\(13),
R => '0'
);
\hessian_reg[9][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(14),
Q => \hessian_reg[9]\(14),
R => '0'
);
\hessian_reg[9][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(15),
Q => \hessian_reg[9]\(15),
R => '0'
);
\hessian_reg[9][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(16),
Q => \hessian_reg[9]\(16),
R => '0'
);
\hessian_reg[9][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(17),
Q => \hessian_reg[9]\(17),
R => '0'
);
\hessian_reg[9][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(18),
Q => \hessian_reg[9]\(18),
R => '0'
);
\hessian_reg[9][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(19),
Q => \hessian_reg[9]\(19),
R => '0'
);
\hessian_reg[9][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(1),
Q => \hessian_reg[9]\(1),
R => '0'
);
\hessian_reg[9][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(20),
Q => \hessian_reg[9]\(20),
R => '0'
);
\hessian_reg[9][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(21),
Q => \hessian_reg[9]\(21),
R => '0'
);
\hessian_reg[9][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(22),
Q => \hessian_reg[9]\(22),
R => '0'
);
\hessian_reg[9][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(23),
Q => \hessian_reg[9]\(23),
R => '0'
);
\hessian_reg[9][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(24),
Q => \hessian_reg[9]\(24),
R => '0'
);
\hessian_reg[9][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(25),
Q => \hessian_reg[9]\(25),
R => '0'
);
\hessian_reg[9][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(26),
Q => \hessian_reg[9]\(26),
R => '0'
);
\hessian_reg[9][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(27),
Q => \hessian_reg[9]\(27),
R => '0'
);
\hessian_reg[9][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(28),
Q => \hessian_reg[9]\(28),
R => '0'
);
\hessian_reg[9][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(29),
Q => \hessian_reg[9]\(29),
R => '0'
);
\hessian_reg[9][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(2),
Q => \hessian_reg[9]\(2),
R => '0'
);
\hessian_reg[9][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(30),
Q => \hessian_reg[9]\(30),
R => '0'
);
\hessian_reg[9][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(31),
Q => \hessian_reg[9]\(31),
R => '0'
);
\hessian_reg[9][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(3),
Q => \hessian_reg[9]\(3),
R => '0'
);
\hessian_reg[9][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(4),
Q => \hessian_reg[9]\(4),
R => '0'
);
\hessian_reg[9][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(5),
Q => \hessian_reg[9]\(5),
R => '0'
);
\hessian_reg[9][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(6),
Q => \hessian_reg[9]\(6),
R => '0'
);
\hessian_reg[9][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(7),
Q => \hessian_reg[9]\(7),
R => '0'
);
\hessian_reg[9][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(8),
Q => \hessian_reg[9]\(8),
R => '0'
);
\hessian_reg[9][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(9),
Q => \hessian_reg[9]\(9),
R => '0'
);
\minusOp_inferred__0/y_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => y_addr_in(0),
O => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\
);
\minusOp_inferred__0/y_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x_addr_in(0),
O => minusOp(0)
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x_addr_in(0),
I1 => x_addr_in(1),
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(1),
I1 => x_addr_in(0),
I2 => x_addr_in(2),
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(2),
I1 => x_addr_in(0),
I2 => x_addr_in(1),
I3 => x_addr_in(3),
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(3),
I1 => x_addr_in(1),
I2 => x_addr_in(0),
I3 => x_addr_in(2),
I4 => x_addr_in(4),
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_addr_out[9]_i_2_n_0\,
I1 => x_addr_in(6),
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(6),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(7),
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(7),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(6),
I3 => x_addr_in(8),
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(8),
I1 => x_addr_in(6),
I2 => \x_addr_out[9]_i_2_n_0\,
I3 => x_addr_in(7),
I4 => x_addr_in(9),
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[9]_i_2_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => minusOp(0),
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
\y_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => y_addr_in(0),
I1 => y_addr_in(1),
O => \y_addr_out[1]_i_1_n_0\
);
\y_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(1),
I1 => y_addr_in(0),
I2 => y_addr_in(2),
O => \y_addr_out[2]_i_1_n_0\
);
\y_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(2),
I1 => y_addr_in(0),
I2 => y_addr_in(1),
I3 => y_addr_in(3),
O => \y_addr_out[3]_i_1_n_0\
);
\y_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(3),
I1 => y_addr_in(1),
I2 => y_addr_in(0),
I3 => y_addr_in(2),
I4 => y_addr_in(4),
O => \y_addr_out[4]_i_1_n_0\
);
\y_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \y_addr_out[5]_i_1_n_0\
);
\y_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I1 => y_addr_in(6),
O => \y_addr_out[6]_i_1_n_0\
);
\y_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(6),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(7),
O => \y_addr_out[7]_i_1_n_0\
);
\y_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(7),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(6),
I3 => y_addr_in(8),
O => \y_addr_out[8]_i_1_n_0\
);
\y_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(8),
I1 => y_addr_in(6),
I2 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I3 => y_addr_in(7),
I4 => y_addr_in(9),
O => \y_addr_out[9]_i_1_n_0\
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\,
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[1]_i_1_n_0\,
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[2]_i_1_n_0\,
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[3]_i_1_n_0\,
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[4]_i_1_n_0\,
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[5]_i_1_n_0\,
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[6]_i_1_n_0\,
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[7]_i_1_n_0\,
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[8]_i_1_n_0\,
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[9]_i_1_n_0\,
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_1_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_nmsuppression_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_nmsuppression_1_0 : entity is "system_vga_nmsuppression_1_0,vga_nmsuppression,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_nmsuppression_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_nmsuppression_1_0 : entity is "vga_nmsuppression,Vivado 2016.4";
end system_vga_nmsuppression_1_0;
architecture STRUCTURE of system_vga_nmsuppression_1_0 is
begin
U0: entity work.system_vga_nmsuppression_1_0_vga_nmsuppression
port map (
active => active,
clk => clk,
enable => enable,
hessian_in(31 downto 0) => hessian_in(31 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
| mit | ce9793d173a34f865e62234d07f4160a | 0.507156 | 2.525724 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_10bit_unpack.vhd | 1 | 3,705 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 10bit pixel unpacker
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives 32-bit words from the long video packet payload in; and unpacks them
--into 40 bits of output (which is only active - signified with the 'dout_valid' output -
--80% of the time). It is intended that the dout_valid signal drives the write enable for a linebuffer
--or FIFO.
--At the moment only MIPI 10bit RAW format is supported, other formats may be
--supported in the future (for 8bit you could simply bypass this entity)
entity csi_rx_10bit_unpack is
Port ( clock : in STD_LOGIC; --word clock in
reset : in STD_LOGIC; --synchronous active high reset
enable : in STD_LOGIC; --active high enable
data_in : in STD_LOGIC_VECTOR (31 downto 0); --packet payload in
din_valid : in STD_LOGIC; --payload in valid
data_out : out STD_LOGIC_VECTOR (39 downto 0); --unpacked data out
dout_valid : out STD_LOGIC); --data out valid (see above)
end csi_rx_10bit_unpack;
architecture Behavioral of csi_rx_10bit_unpack is
signal dout_int : std_logic_vector(39 downto 0);
signal bytes_int : std_logic_vector(31 downto 0);
signal byte_count_int : integer range 0 to 4;
signal dout_valid_int : std_logic;
signal dout_unpacked : std_logic_vector(39 downto 0);
signal dout_valid_up : std_logic;
--Unpack CSI packed 10-bit to 4 sequential 10-bit pixels
function mipi_unpack(packed : std_logic_vector)
return std_logic_vector is
variable result : std_logic_vector(39 downto 0);
begin
result(9 downto 0) := packed(7 downto 0) & packed(33 downto 32);
result(19 downto 10) := packed(15 downto 8) & packed(35 downto 34);
result(29 downto 20) := packed(23 downto 16) & packed(37 downto 36);
result(39 downto 30) := packed(31 downto 24) & packed(39 downto 38);
return result;
end mipi_unpack;
begin
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
dout_int <= x"0000000000";
byte_count_int <= 0;
dout_valid_int <= '0';
elsif enable = '1' then
if din_valid = '1' then
--Behaviour is based on the number of bytes in the buffer
case byte_count_int is
when 0 =>
dout_int <= x"0000000000";
dout_valid_int <= '0';
bytes_int <= data_in;
byte_count_int <= 4;
when 1 =>
dout_int <= data_in & bytes_int(7 downto 0);
dout_valid_int <= '1';
bytes_int <= x"00000000";
byte_count_int <= 0;
when 2 =>
dout_int <= data_in(23 downto 0) & bytes_int(15 downto 0);
dout_valid_int <= '1';
bytes_int <= x"000000" & data_in(31 downto 24);
byte_count_int <= 1;
when 3 =>
dout_int <= data_in(15 downto 0) & bytes_int(23 downto 0);
dout_valid_int <= '1';
bytes_int <= x"0000" & data_in(31 downto 16);
byte_count_int <= 2;
when 4 =>
dout_int <= data_in(7 downto 0) & bytes_int(31 downto 0);
dout_valid_int <= '1';
bytes_int <= x"00" & data_in(31 downto 8);
byte_count_int <= 3;
end case;
else
byte_count_int <= 0;
dout_valid_int <= '0';
end if;
dout_unpacked <= mipi_unpack(dout_int);
dout_valid_up <= dout_valid_int;
data_out <= dout_unpacked;
dout_valid <= dout_valid_up;
end if;
end if;
end process;
end Behavioral;
| mit | eb49b34ce35075bb943a99cfeccce8a6 | 0.586775 | 3.614634 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70,465 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:32 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | e5d95cd2c4f7b2c03e8da87c0be920d0 | 0.533229 | 2.8123 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/inst/pass/cpu_l1mem_inst_pass-rtl.vhdl | 1 | 12,308 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
use sys.sys_config_pkg.all;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_inst_types_pkg.all;
use work.cpu_mmu_inst_types_pkg.all;
architecture rtl of cpu_l1mem_inst_pass is
type state_index_type is (
state_index_idle,
state_index_mmu_access,
state_index_bus_access
);
type state_type is array (state_index_type range state_index_type'high downto state_index_type'low) of std_ulogic;
constant state_idle : state_type := "001";
constant state_mmu_access : state_type := "010";
constant state_bus_access : state_type := "100";
type paddr_sel_index_type is (
paddr_sel_index_reg,
paddr_sel_index_pipe,
paddr_sel_index_mmu
);
type paddr_sel_type is array (paddr_sel_index_type range paddr_sel_index_type'high downto paddr_sel_index_type'low) of std_ulogic;
constant paddr_sel_reg : paddr_sel_type := "001";
constant paddr_sel_incoming : paddr_sel_type := "010";
constant paddr_sel_mmu : paddr_sel_type := "100";
type comb_type is record
state_next : state_type;
mmu_request : std_ulogic;
bus_request : std_ulogic;
bus_requested_next : std_ulogic;
incoming_request : std_ulogic;
use_incoming_request : std_ulogic;
be : std_ulogic;
mmuen : std_ulogic;
cacheen : std_ulogic;
priv : std_ulogic;
incoming_paddr : cpu_ipaddr_type;
mmu_paddr : cpu_ipaddr_type;
bus_paddr_sel : paddr_sel_type;
bus_paddr : cpu_ipaddr_type;
paddr_next : cpu_ipaddr_type;
end record;
type reg_type is record
state : state_type;
bus_requested : std_ulogic;
mmuen : std_ulogic;
cacheen : std_ulogic;
priv : std_ulogic;
paddr : cpu_ipaddr_type;
end record;
constant reg_x : reg_type := (
state => (others => 'X'),
bus_requested => 'X',
mmuen => 'X',
cacheen => 'X',
priv => 'X',
paddr => (others => 'X')
);
constant reg_init : reg_type := (
state => state_idle,
bus_requested => 'X',
mmuen => 'X',
cacheen => 'X',
priv => 'X',
paddr => (others => 'X')
);
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.incoming_request <= cpu_l1mem_inst_pass_ctrl_in.request(cpu_l1mem_inst_request_code_index_fetch);
with r.state select
c.state_next <= (state_index_idle => not c.incoming_request,
state_index_mmu_access => (c.incoming_request and
cpu_l1mem_inst_pass_ctrl_in.mmuen
),
state_index_bus_access => (c.incoming_request and
not cpu_l1mem_inst_pass_ctrl_in.mmuen
)
) when state_idle,
(state_index_idle => (cpu_mmu_inst_ctrl_out.ready and
not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_valid) and
not c.incoming_request
),
state_index_mmu_access => (not cpu_mmu_inst_ctrl_out.ready or
(not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_valid) and
c.incoming_request)
),
state_index_bus_access => cpu_mmu_inst_ctrl_out.ready
) when state_mmu_access,
(state_index_idle => (r.bus_requested and
sys_slave_ctrl_out.ready and
not c.incoming_request
),
state_index_mmu_access => (r.bus_requested and
sys_slave_ctrl_out.ready and
c.incoming_request and
cpu_l1mem_inst_pass_ctrl_in.mmuen
),
state_index_bus_access => ((sys_slave_ctrl_out.ready and
c.incoming_request and
not cpu_l1mem_inst_pass_ctrl_in.mmuen
) or
not r.bus_requested or
not sys_slave_ctrl_out.ready
)
) when state_bus_access,
(others => 'X') when others;
c.mmu_request <= r.state(state_index_idle) and c.incoming_request;
with r.state select
c.bus_request <= (c.incoming_request and
not cpu_l1mem_inst_pass_ctrl_in.mmuen) when state_idle,
cpu_mmu_inst_ctrl_out.ready when state_mmu_access,
(not r.bus_requested or
(c.incoming_request and
not cpu_l1mem_inst_pass_ctrl_in.mmuen)) when state_bus_access,
'X' when others;
c.use_incoming_request <= (r.state(state_index_idle) or
(r.state(state_index_bus_access) and sys_slave_ctrl_out.ready));
with r.state select
c.bus_requested_next <= not cpu_l1mem_inst_pass_ctrl_in.mmuen and sys_slave_ctrl_out.ready when state_idle,
cpu_mmu_inst_ctrl_out.ready and sys_slave_ctrl_out.ready when state_mmu_access,
r.bus_requested or sys_slave_ctrl_out.ready when state_bus_access,
'X' when others;
be_0 : if cpu_inst_endianness = little_endian generate
c.be <= '0';
end generate;
be_1 : if cpu_inst_endianness = big_endian generate
c.be <= '1';
end generate;
with c.use_incoming_request select
c.mmuen <= cpu_l1mem_inst_pass_ctrl_in.mmuen when '1',
r.mmuen when '0',
'X' when others;
with c.use_incoming_request select
c.cacheen <= cpu_l1mem_inst_pass_ctrl_in.cacheen when '1',
r.cacheen when '0',
'X' when others;
with c.use_incoming_request select
c.priv <= cpu_l1mem_inst_pass_ctrl_in.priv when '1',
r.priv when '0',
'X' when others;
incoming_paddr_vaddr_bigger : if cpu_ivaddr_bits >= cpu_ipaddr_bits generate
c.incoming_paddr <= cpu_l1mem_inst_pass_dp_in.vaddr(cpu_ipaddr_bits-1 downto 0);
end generate;
incoming_paddr_vaddr_smaller : if cpu_ivaddr_bits < cpu_ipaddr_bits generate
c.incoming_paddr(cpu_ipaddr_bits-1 downto cpu_ivaddr_bits) <= (others => '0');
c.incoming_paddr(cpu_ivaddr_bits-1 downto 0) <= cpu_l1mem_inst_pass_dp_in.vaddr;
end generate;
mmu_paddr_gen_0 : if cpu_ppn_bits = 0 generate
c.mmu_paddr <= r.paddr;
end generate;
mmu_paddr_gen_n : if cpu_ppn_bits > 0 generate
c.mmu_paddr <= cpu_mmu_inst_dp_out.ppn & r.paddr(cpu_ipoffset_bits-1 downto 0);
end generate;
with r.state select
c.bus_paddr_sel <= paddr_sel_incoming when state_idle,
paddr_sel_mmu when state_mmu_access,
(paddr_sel_index_reg => not r.bus_requested or not sys_slave_ctrl_out.ready,
paddr_sel_index_pipe => r.bus_requested and sys_slave_ctrl_out.ready,
paddr_sel_index_mmu => '0'
) when state_bus_access,
(others => 'X') when others;
with c.bus_paddr_sel select
c.bus_paddr <= r.paddr when paddr_sel_reg,
c.incoming_paddr when paddr_sel_incoming,
c.mmu_paddr when paddr_sel_mmu,
(others => 'X') when others;
c.paddr_next <= c.bus_paddr;
cpu_l1mem_inst_pass_ctrl_out <= (
ready => (sys_slave_ctrl_out.ready and
not r.state(state_index_mmu_access)),
result => (
cpu_l1mem_inst_result_code_index_valid => (
not ((r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_inst_ctrl_out.ready and
not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_valid)) or
(r.state(state_index_bus_access) and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error)
)
),
cpu_l1mem_inst_result_code_index_error => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_inst_ctrl_out.ready and
not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_error)) or
(r.state(state_index_bus_access) and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error)
),
cpu_l1mem_inst_result_code_index_tlbmiss => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_inst_ctrl_out.ready and
not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_tlbmiss))
),
cpu_l1mem_inst_result_code_index_pf => (
(r.state(state_index_mmu_access) and
r.mmuen and
cpu_mmu_inst_ctrl_out.ready and
not cpu_mmu_inst_ctrl_out.result(cpu_mmu_inst_result_code_index_pf))
)
)
);
cpu_l1mem_inst_pass_dp_out <= (
paddr => r.paddr,
data => sys_slave_dp_out.data(cpu_inst_bits-1 downto 0)
);
cpu_mmu_inst_ctrl_in <= (
request => c.mmu_request,
mmuen => c.mmuen
);
sys_master_ctrl_out <= (
request => c.bus_request,
be => c.be,
write => '0',
cacheable => c.cacheen,
priv => c.priv, -- TODO
inst => '1',
burst => '0',
bwrap => 'X',
bcycles => (others => 'X')
);
sys_master_dp_out <= (
size => std_ulogic_vector(to_unsigned(cpu_log2_inst_bytes, sys_transfer_size_bits)),
paddr => (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.bus_paddr & (cpu_log2_inst_bytes-1 downto 0 => '0'),
data => (others => 'X')
);
r_next <= (
state => c.state_next,
bus_requested => c.bus_requested_next,
mmuen => c.mmuen,
cacheen => c.cacheen,
priv => c.priv,
paddr => c.paddr_next
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
end;
| apache-2.0 | 07356a78191ba576dea97626dad70bf7 | 0.502519 | 3.798765 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/synth/system_vga_hessian_1_0.vhd | 2 | 4,403 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_1_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_1_0;
ARCHITECTURE system_vga_hessian_1_0_arch OF system_vga_hessian_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_1_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_1_0_arch : ARCHITECTURE IS "system_vga_hessian_1_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_1_0_arch: ARCHITECTURE IS "system_vga_hessian_1_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=41,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_1_0_arch;
| mit | d81109e601b34d5898d936e40d3d7e05 | 0.719509 | 3.678363 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ipshared/c07e/vga_sync.vhd | 2 | 2,792 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture Structural of vga_sync is
-- sync counters
signal v_count_reg: std_logic_vector(9 downto 0);
signal h_count_reg: std_logic_vector(9 downto 0);
begin
-- registers
process (clk,rst)
begin
if rst='0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
hsync <= '1';
hsync <= '1';
active <= '0';
elsif (rising_edge(clk)) then
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
| mit | aca9e53f179a460136070ab3b78b5a60 | 0.459169 | 3.867036 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/test_benches/DES_Decrypt_TestBench.vhd | 2 | 5,602 | --******************************************************************************
-- Copyright (c) 2016 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
--------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 20:45:11 02/14/2017
-- Design Name:
-- Module Name: DES_DECRYPT Testbench.vhd
-- Project Name: DES_Fully_Pipelined
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies: DES_Fully_Pipelined Design and txt_util.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
--------------------------------------------------------------------------------
LIBRARY ieee;
Use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use work.txt_util.all;
ENTITY DES_Decrypt_testBench IS
END DES_Decrypt_testBench;
ARCHITECTURE behavior OF DES_Decrypt_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DES_CRYPTO_CORE --desCryptoCore
PORT(
reset : IN std_logic;
EN : IN std_logic;
clk : IN std_logic;
DES_IN : IN std_logic_vector(63 downto 0);
USER_KEY : IN std_logic_vector(63 downto 0);
DES_OUT : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
COMPONENT DES IS
PORT(
PT : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
KIN: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
CT: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RST: IN STD_LOGIC;
CLK: IN STD_LOGIC;
TEST_MODE: IN STD_LOGIC;
SCAN_OUT : OUT STD_LOGIC);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal EN : std_logic := '0';
signal clk : std_logic := '0';
signal DES_IN : std_logic_vector(63 downto 0) := (others => '0');
signal USER_KEY : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal DES_OUT : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal ERROR,ERRORD: integer :=0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DES_CRYPTO_CORE PORT MAP (
reset => reset,
EN => EN,
clk => clk,
DES_IN => DES_IN,
USER_KEY => USER_KEY,
DES_OUT => DES_OUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
readcmd: process
file CryptoCore_TestVectors: TEXT;
variable file_line: Line;
variable test_vector_key_in: std_logic_vector (63 downto 0);
variable test_vector_din: std_logic_vector (63 downto 0);
variable test_vector_expected_dout : std_logic_vector (63 downto 0);
Begin
reset <= '1';
USER_KEY <= (others => '0');
DES_IN <= (others => '0');
En <= '0';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
reset <= '0';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
print ("DES Test#1 has begun.");
FILE_OPEN (CryptoCore_TestVectors, "../src/test_vectors/DES_TV_Triplets_NBS.txt", READ_MODE); --In case of problems, use absolute path
loop
If endfile (CryptoCore_TestVectors) then
exit;
End If;
readline (CryptoCore_TestVectors, file_line);
hread (file_line, test_vector_key_in);
hread (file_line, test_vector_expected_dout);
hread (file_line, test_vector_din);
USER_KEY <= test_vector_key_in;
-- din_vld_T <= '1'; --# When Designs have din and key valid use this
-- Key_vld <= '1';
DES_IN <= test_vector_din;
wait until rising_edge (clk);
-- din_vld_T <= '0';
-- wait until dout_rdy_T = '1'; --# When Designs have dout use this to get the result
wait for 20*clk_period;
wait until rising_edge (clk);
If DES_OUT /= test_vector_expected_dout then
print ("***ERROR: test vector failed to compare"); ERROR<=ERROR+1;
print ((" Expected PT: ") & hstr (test_vector_expected_dout (63 downto 0)) & (" Received PT: ") & hstr (DES_OUT (63 downto 0)));
End If;
End loop;
print ("Test#1 completed");
print ("");
print ("");
if ERROR=0 then
print ("All tests complete- PASS");
else
print (("All tests complete 4 Decrypt - FAIL --> Total ERRORS=") & integer'image(ERROR));
end if;
wait;
end process;
END;
| mit | 6dee63f3b3086377172af3a1c50170f9 | 0.603177 | 3.565882 | false | true | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_sim_netlist.vhdl | 1 | 5,896 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:27:54 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_1_0_rgb565_to_rgb888 is
port (
rgb_888 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rgb565_to_rgb888_1_0_rgb565_to_rgb888 : entity is "rgb565_to_rgb888";
end system_rgb565_to_rgb888_1_0_rgb565_to_rgb888;
architecture STRUCTURE of system_rgb565_to_rgb888_1_0_rgb565_to_rgb888 is
begin
\rgb_888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(5),
Q => rgb_888(5),
R => '0'
);
\rgb_888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(6),
Q => rgb_888(6),
R => '0'
);
\rgb_888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(7),
Q => rgb_888(7),
R => '0'
);
\rgb_888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(8),
Q => rgb_888(8),
R => '0'
);
\rgb_888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(9),
Q => rgb_888(9),
R => '0'
);
\rgb_888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(10),
Q => rgb_888(10),
R => '0'
);
\rgb_888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(11),
Q => rgb_888(11),
R => '0'
);
\rgb_888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(12),
Q => rgb_888(12),
R => '0'
);
\rgb_888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(13),
Q => rgb_888(13),
R => '0'
);
\rgb_888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(14),
Q => rgb_888(14),
R => '0'
);
\rgb_888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(15),
Q => rgb_888(15),
R => '0'
);
\rgb_888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(0),
Q => rgb_888(0),
R => '0'
);
\rgb_888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(1),
Q => rgb_888(1),
R => '0'
);
\rgb_888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(2),
Q => rgb_888(2),
R => '0'
);
\rgb_888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(3),
Q => rgb_888(3),
R => '0'
);
\rgb_888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(4),
Q => rgb_888(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_1_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_1_0 : entity is "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_1_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_1_0;
architecture STRUCTURE of system_rgb565_to_rgb888_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 20 downto 3 );
begin
rgb_888(23 downto 21) <= \^rgb_888\(18 downto 16);
rgb_888(20 downto 16) <= \^rgb_888\(20 downto 16);
rgb_888(15 downto 14) <= \^rgb_888\(9 downto 8);
rgb_888(13 downto 3) <= \^rgb_888\(13 downto 3);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_rgb565_to_rgb888_1_0_rgb565_to_rgb888
port map (
clk => clk,
rgb_565(15 downto 0) => rgb_565(15 downto 0),
rgb_888(15 downto 13) => \^rgb_888\(18 downto 16),
rgb_888(12 downto 11) => \^rgb_888\(20 downto 19),
rgb_888(10 downto 9) => \^rgb_888\(9 downto 8),
rgb_888(8 downto 5) => \^rgb_888\(13 downto 10),
rgb_888(4 downto 0) => \^rgb_888\(7 downto 3)
);
end STRUCTURE;
| mit | 2112e56c74326fcc507b3e4542158421 | 0.539518 | 3.043882 | false | false | false | false |
loa-org/loa-hdl | modules/pwm/hdl/pwm_module.vhd | 2 | 2,239 | -------------------------------------------------------------------------------
-- PWM Module
--
-- Connects the pwm entity to the internal bus system.
--
-- @author Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pwm_pkg.all;
use work.utils_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity pwm_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
WIDTH : positive := 12; -- Number of bits for the PWM generation (e.g. 12 => 0..4095)
PRESCALER : positive := 2
);
port (
pwm_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic
);
end pwm_module;
-------------------------------------------------------------------------------
architecture behavioral of pwm_module is
type pwm_module_type is record
pwm : std_logic_vector (WIDTH - 1 downto 0);
end record;
signal r, rin : pwm_module_type;
signal clk_en : std_logic;
begin
seq_proc : process(reset, clk)
begin
if rising_edge(clk) then
if reset = '1' then
r.pwm <= (others => '0');
else
r <= rin;
end if;
end if;
end process seq_proc;
comb_proc : process(r, bus_i)
variable v : pwm_module_type;
begin
v := r;
if bus_i.we = '1' and
bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
v.pwm := bus_i.data(WIDTH - 1 downto 0);
end if;
rin <= v;
end process comb_proc;
bus_o.data <= (others => '0');
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
-- Generate a PWM
pwm_1 : pwm
generic map (
WIDTH => WIDTH)
port map (
clk_en_p => clk_en,
value_p => r.pwm,
output_p => pwm_p,
reset => reset,
clk => clk);
end behavioral;
| bsd-3-clause | 6b72c32b59d050e04b36c553bf8a1021 | 0.466726 | 3.921191 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_pipeline_tb.vhd | 2 | 2,232 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipeline"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipeline_tb is
end entity goertzel_pipeline_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_pipeline_tb is
-- component generics
constant Q : natural := 13;
-- component ports
signal coef_p : goertzel_coef_type := (others => '0');
signal input_p : goertzel_input_type := (others => '0');
signal delay_p : goertzel_result_type := (others => (others => '0'));
signal result_p : goertzel_result_type := (others => (others => '0'));
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_pipeline
generic map (
Q => Q)
port map (
coef_p => coef_p,
input_p => input_p,
delay_p => delay_p,
result_p => result_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
wait until clk = '0';
-- resize is not exactly what's intende because it takes care of the sign
-- bit (MSB) when truncating. But for simple test purposes this does not
-- matter as the actual data is unimportant.
coef_p <= resize(x"323fe", coef_p'length);
delay_p <= resize(x"1ffff", 18) & resize(x"14238", 18);
input_p <= resize(x"193af", input_p'length);
end process WaveGen_Proc;
end architecture tb;
| bsd-3-clause | 07ca3a953e7b110abcf4ba814ac781bb | 0.452509 | 4.5 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl | 1 | 3,213 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0_clock_splitter is
port (
clk_out : out STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clock_splitter_0_0_clock_splitter : entity is "clock_splitter";
end system_clock_splitter_0_0_clock_splitter;
architecture STRUCTURE of system_clock_splitter_0_0_clock_splitter is
signal clk_i_1_n_0 : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal last_edge : STD_LOGIC;
begin
clk_out <= \^clk_out\;
clk_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => latch_edge,
I1 => last_edge,
I2 => \^clk_out\,
O => clk_i_1_n_0
);
clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => clk_i_1_n_0,
Q => \^clk_out\,
R => '0'
);
last_edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => latch_edge,
Q => last_edge,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clock_splitter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_clock_splitter_0_0 : entity is "system_clock_splitter_0_0,clock_splitter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_clock_splitter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_clock_splitter_0_0 : entity is "clock_splitter,Vivado 2016.4";
end system_clock_splitter_0_0;
architecture STRUCTURE of system_clock_splitter_0_0 is
begin
U0: entity work.system_clock_splitter_0_0_clock_splitter
port map (
clk_in => clk_in,
clk_out => clk_out,
latch_edge => latch_edge
);
end STRUCTURE;
| mit | aa2a795d44b616ce00e9d129893c209b | 0.623405 | 3.48104 | false | false | false | false |
pgavin/carpe | hdl/sim/uart/uart_pkg.vhdl | 1 | 4,157 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.numeric_pkg.all;
use util.types_pkg.all;
package uart_pkg is
constant uart_rsel_bits : integer := 4;
subtype uart_rsel_type is std_ulogic_vector(uart_rsel_bits-1 downto 0);
constant uart_rsel_rx : uart_rsel_type := "0000"; -- 0x0: In: Receive buffer (DLAB=0)
constant uart_rsel_tx : uart_rsel_type := "0000"; -- 0x0: Out: Transmit buffer (DLAB=0)
constant uart_rsel_dll : uart_rsel_type := "0000"; -- 0x0: Out: Divisor Latch Low (DLAB=1)
constant uart_rsel_dlm : uart_rsel_type := "0001"; -- 0x1: Out: Divisor Latch High (DLAB=1)
constant uart_rsel_ier : uart_rsel_type := "0001"; -- 0x1: Out: Interrupt Enable Register
constant uart_rsel_iir : uart_rsel_type := "0010"; -- 0x2: In: Interrupt ID Register
constant uart_rsel_fcr : uart_rsel_type := "0010"; -- 0x2: Out: FIFO Control Register
constant uart_rsel_efr : uart_rsel_type := "0010"; -- 0x2: I/O: Extended Features Register
constant uart_rsel_lcr : uart_rsel_type := "0011"; -- 0x3: Out: Line Control Register
constant uart_rsel_mcr : uart_rsel_type := "0100"; -- 0x4: Out: Modem Control Register
constant uart_rsel_lsr : uart_rsel_type := "0101"; -- 0x5: In: Line Status Register
constant uart_rsel_msr : uart_rsel_type := "0110"; -- 0x6: In: Modem Status Register
constant uart_rsel_scr : uart_rsel_type := "0111"; -- 0x7: I/O: Scratch Register
-- Line Status Register
constant uart_lsr_temt : byte_type := "01000000"; -- 0x40: transmitter empty
constant uart_lsr_thre : byte_type := "00100000"; -- 0x20: transmit-hold-register empty
constant uart_lsr_bi : byte_type := "00010000"; -- 0x10: break interrupt indicator
constant uart_lsr_fe : byte_type := "00001000"; -- 0x08: frame error indicator
constant uart_lsr_pe : byte_type := "00000100"; -- 0x04: parity error indicator
constant uart_lsr_oe : byte_type := "00000010"; -- 0x02: overrun error indicator
constant uart_lsr_dr : byte_type := "00000001"; -- 0x01: receiver data ready
-- Line Control Register
constant uart_lcr_dlab : byte_type := "10000000"; -- 0x80: divisor latch access bit */
constant uart_lcr_sbc : byte_type := "01000000"; -- 0x40: set break control */
constant uart_lcr_spar : byte_type := "00100000"; -- 0x20: stick parity (?) */
constant uart_lcr_epar : byte_type := "00010000"; -- 0x10: even parity select */
constant uart_lcr_parity : byte_type := "00001000"; -- 0x08: parity enable */
constant uart_lcr_stop : byte_type := "00000100"; -- 0x04: stop bits: 0=1 stop bit, 1= 2 stop bits */
constant uart_lcr_wlen5 : byte_type := "00000000"; -- 0x00: wordlength: 5 bits */
constant uart_lcr_wlen6 : byte_type := "00000001"; -- 0x01: wordlength: 6 bits */
constant uart_lcr_wlen7 : byte_type := "00000010"; -- 0x02: wordlength: 7 bits */
constant uart_lcr_wlen8 : byte_type := "00000011"; -- 0x03: wordlength: 8 bits */
end package;
| apache-2.0 | 8fb60f8316d080a693f4e41b891d3f0b | 0.609815 | 3.701692 | false | false | false | false |
loa-org/loa-hdl | modules/uss_tx/tb/serialiser_tb.vhd | 2 | 2,230 | -------------------------------------------------------------------------------
-- Title : Testbench for serialiser
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser_tb is
end serialiser_tb;
-------------------------------------------------------------------------------
architecture tb of serialiser_tb is
use work.utils_pkg.all;
-- Component generics
constant BITPATTERN_WIDTH : integer := 16;
-- Signals for component ports
signal pattern : std_logic_vector(BITPATTERN_WIDTH - 1 downto 0) := (others => '0');
signal bitstream : std_logic;
signal clk_bit : std_logic := '0';
signal clk : std_logic := '0';
begin -- tb
---------------------------------------------------------------------------
-- component instatiation
---------------------------------------------------------------------------
serialiser_1 : entity work.serialiser
generic map (
BITPATTERN_WIDTH => BITPATTERN_WIDTH)
port map (
pattern_in_p => pattern,
bitstream_out_p => bitstream,
clk_bit => clk_bit,
clk => clk);
-------------------------------------------------------------------------------
-- Stimuli
-------------------------------------------------------------------------------
-- clock generation, 50 MHz
clk <= not clk after 10 ns;
-- Bit clock
-- 50 MHz / 25000 = 2 kHz
-- For testbench 200 kHz
fractional_clock_divider_1 : entity work.fractional_clock_divider
generic map (
DIV => 250,
MUL => 1)
port map (
clk_out_p => clk_bit,
clk => clk);
pattern <= x"8000";
end tb;
| bsd-3-clause | 297896b1e9beaab8c1537e85694357cb | 0.355157 | 5.946667 | false | false | false | false |
loa-org/loa-hdl | modules/ws2812/hdl/ws2812_cfg_pkg.vhd | 1 | 1,185 | -------------------------------------------------------------------------------
-- Title : WS2812 Controller Configuration Package
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-14
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ws2812_cfg_pkg is
-- literal values are for 50MHz system clock
constant reset_cycles : integer := 2750; -- 55 us
constant one_th_cycles : integer := 35; -- 700ns
constant one_tl_cycles : integer := 30; -- 600ns
constant zero_th_cycles : integer := 18; -- 350ns (360ns)
constant zero_tl_cycles : integer := 40; -- 800ns
end ws2812_cfg_pkg;
| bsd-3-clause | 1badbe8fe949d8a2a71252b1d739858b | 0.457384 | 5.021186 | false | false | false | false |
sbourdeauducq/dspunit | sim/gen_memory.vhd | 2 | 5,348 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2006-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity gen_memory is
generic (
addr_width : natural := 11;
data_width : natural := 8
);
port (
--@inputs
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
--@outputs;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end gen_memory;
--=----------------------------------------------------------------------------
architecture archi_gen_memory of gen_memory is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type memType is array((2**addr_width - 1) downto 0) of std_logic_vector((data_width - 1) downto 0);
-- Fonction d'initialisation du programme
function initialize_ram
return memType is
variable result : memType;
begin
--result(3) := std_logic_vector(to_signed(50000, data_width));
-- result(16) := x"4000";
-- result(0) := x"7FFF";
-- result(11) := x"0000";
-- result(12) := x"4000";
-- for i in 0 to 15 loop
-- result(i) := (others => '0');
-- end loop;
-- for i in 17 to 29 loop
-- result(i) := (others => '0');
-- end loop;
for i in 0 to (2**addr_width - 1) loop
result(i) := (others => '0');
end loop;
return result;
end initialize_ram;
signal s_ram_block : memType := initialize_ram;
signal s_address_a : std_logic_vector((addr_width - 1) downto 0);
signal s_address_b : std_logic_vector((addr_width - 1) downto 0);
signal s_w_clk : std_logic;
begin -- archs_gen_memory
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
ramProc_a : process (clock_a)
begin -- process ramProc
if rising_edge(clock_a) then -- rising clock edge
s_address_a <= address_a;
q_a <= s_ram_block(to_integer(unsigned(s_address_a)));
end if;
end process ramProc_a;
ramProc_b : process (clock_b)
begin -- process ramProc
if rising_edge(clock_b) then -- rising clock edge
s_address_b <= address_b;
q_b <= s_ram_block(to_integer(unsigned(s_address_b)));
end if;
end process ramProc_b;
ramWrite : process (clock_a, clock_b)
begin -- process ramWrite
-- if rising_edge(s_w_clk) then -- rising clock edge
if wren_a = '1' then
if falling_edge(clock_a) then -- rising clock edge
s_ram_block(to_integer(unsigned(address_a))) <= data_a;
end if;
elsif wren_b = '1' then
if falling_edge(clock_b) then -- rising clock edge
s_ram_block(to_integer(unsigned(address_b))) <= data_b;
end if;
end if;
end process ramWrite;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_w_clk <= (clock_a and wren_a) or (clock_b and wren_b);
end archi_gen_memory;
-------------------------------------------------------------------------------
| gpl-3.0 | 63b4c376a2060b50b4755fac0b9c9036 | 0.454001 | 4.351505 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_feature_transform/vga_feature_transform.srcs/sources_1/new/vga_feature_transform.vhd | 3 | 11,732 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_feature_transform is
generic (
NUM_FEATURES : integer := 64
);
port (
clk : in std_logic;
clk_x2 : in std_logic;
rst : in std_logic;
active : in std_logic;
vsync : in std_logic;
x_addr_0 : in std_logic_vector(9 downto 0);
y_addr_0 : in std_logic_vector(9 downto 0);
hessian_0 : in std_logic_vector(31 downto 0);
x_addr_1 : in std_logic_vector(9 downto 0);
y_addr_1 : in std_logic_vector(9 downto 0);
hessian_1 : in std_logic_vector(31 downto 0);
rot_m00 : out std_logic_vector(15 downto 0);
rot_m01 : out std_logic_vector(15 downto 0);
rot_m10 : out std_logic_vector(15 downto 0);
rot_m11 : out std_logic_vector(15 downto 0);
t_x : out std_logic_vector(9 downto 0);
t_y : out std_logic_vector(9 downto 0);
state : out std_logic_vector(1 downto 0)
);
end vga_feature_transform;
architecture Behavioral of vga_feature_transform is
component feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end component;
type HESSIAN_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(31 downto 0);
type POINT_ARRAY is array (NUM_FEATURES downto 0) of std_logic_vector(9 downto 0);
signal hessian_buffer_left_0 : HESSIAN_ARRAY;
signal hessian_buffer_right_0 : HESSIAN_ARRAY;
signal point_buffer_x_left_0 : POINT_ARRAY;
signal point_buffer_y_left_0 : POINT_ARRAY;
signal point_buffer_x_right_0 : POINT_ARRAY;
signal point_buffer_y_right_0 : POINT_ARRAY;
signal hessian_buffer_left_1 : HESSIAN_ARRAY;
signal hessian_buffer_right_1 : HESSIAN_ARRAY;
signal point_buffer_x_left_1 : POINT_ARRAY;
signal point_buffer_y_left_1 : POINT_ARRAY;
signal point_buffer_x_right_1 : POINT_ARRAY;
signal point_buffer_y_right_1 : POINT_ARRAY;
signal sort_enable : std_logic := '0';
signal clear : std_logic := '0';
signal sum_index : integer := 0;
signal state_s : std_logic_vector(1 downto 0) := "00";
signal sum_x_0, sum_x_1, sum_y_0, sum_y_1, center_x_0, center_x_1, center_y_0, center_y_1, t_xs, t_ys, last_t_xs, last_t_ys : unsigned(31 downto 0) := x"00000000";
signal ready : std_logic := '0';
begin
rot_m00 <= x"4000";
rot_m01 <= x"0000";
rot_m10 <= x"0000";
rot_m11 <= x"4000";
state <= state_s;
process(clk)
begin
if rising_edge(clk) then
if rst = '0' then
state_s <= "00";
clear <= '1';
ready <= '0';
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
t_xs <= x"00000000";
t_ys <= x"00000000";
last_t_xs <= x"00000000";
last_t_ys <= x"00000000";
else
if state_s = "00" then
clear <= '0';
ready <= '0';
if vsync = '1' then
sort_enable <= '1';
if active = '1' and unsigned(x_addr_0) > 50 and unsigned(x_addr_0) < 590 and unsigned(y_addr_0) > 50 and unsigned(y_addr_0) < 430 then
hessian_buffer_left_0(0) <= hessian_0;
point_buffer_x_left_0(0) <= x_addr_0;
point_buffer_y_left_0(0) <= y_addr_0;
else
hessian_buffer_left_0(0) <= x"00000000";
point_buffer_x_left_0(0) <= "0000000000";
point_buffer_y_left_0(0) <= "0000000000";
end if;
if active = '1' and unsigned(x_addr_1) > 50 and unsigned(x_addr_1) < 590 and unsigned(y_addr_1) > 50 and unsigned(y_addr_1) < 430 then
hessian_buffer_left_1(0) <= hessian_1;
point_buffer_x_left_1(0) <= x_addr_1;
point_buffer_y_left_1(0) <= y_addr_1;
else
hessian_buffer_left_1(0) <= x"00000000";
point_buffer_x_left_1(0) <= "0000000000";
point_buffer_y_left_1(0) <= "0000000000";
end if;
else
state_s <= "01";
sort_enable <= '0';
sum_x_0 <= x"00000000";
sum_y_0 <= x"00000000";
sum_x_1 <= x"00000000";
sum_y_1 <= x"00000000";
sum_index <= 1;
end if;
elsif state_s = "01" then
if sum_index <= NUM_FEATURES then
sum_x_0 <= sum_x_0 + unsigned(point_buffer_x_left_0(sum_index));
sum_y_0 <= sum_y_0 + unsigned(point_buffer_y_left_0(sum_index));
sum_x_1 <= sum_x_1 + unsigned(point_buffer_x_left_1(sum_index));
sum_y_1 <= sum_y_1 + unsigned(point_buffer_y_left_1(sum_index));
sum_index <= sum_index + 1;
else
center_x_0 <= sum_x_0 srl 6;
center_y_0 <= sum_y_0 srl 6;
center_x_1 <= sum_x_1 srl 6;
center_y_1 <= sum_y_1 srl 6;
state_s <= "10";
end if;
elsif state_s = "10" then
t_xs <= (center_x_1 - center_x_0) + last_t_xs;
t_ys <= (center_y_1 - center_y_0) + last_t_ys;
state_s <= "11";
elsif state_s = "11" then
if vsync = '1' and ready = '1' then
last_t_xs <= t_xs;
last_t_ys <= t_ys;
t_x <= std_logic_vector(t_xs(9 downto 0));
t_y <= std_logic_vector(t_ys(9 downto 0));
clear <= '1';
state_s <= "00";
else
if vsync = '0' then
ready <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
GEN_FEATURE_BUFFER_0 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_0(i),
y_in_left => point_buffer_y_left_0(i),
hessian_in_left => hessian_buffer_left_0(i),
x_in_right => point_buffer_x_right_0(i+1),
y_in_right => point_buffer_y_right_0(i+1),
hessian_in_right => hessian_buffer_right_0(i+1),
x_out_left => point_buffer_x_left_0(i+1),
y_out_left => point_buffer_y_left_0(i+1),
hessian_out_left => hessian_buffer_left_0(i+1),
x_out_right => point_buffer_x_right_0(i),
y_out_right => point_buffer_y_right_0(i),
hessian_out_right => hessian_buffer_right_0(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_0;
GEN_FEATURE_BUFFER_1 : for i in 0 to NUM_FEATURES - 1 generate
U_EVEN : if i mod 2 = 0 generate
U: feature_buffer_block generic map (
PARITY => '0'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_EVEN;
U_ODD : if i mod 2 = 1 generate
U: feature_buffer_block generic map (
PARITY => '1'
) port map (
clk_x2 => clk_x2,
enable => sort_enable,
clear => clear,
x_in_left => point_buffer_x_left_1(i),
y_in_left => point_buffer_y_left_1(i),
hessian_in_left => hessian_buffer_left_1(i),
x_in_right => point_buffer_x_right_1(i+1),
y_in_right => point_buffer_y_right_1(i+1),
hessian_in_right => hessian_buffer_right_1(i+1),
x_out_left => point_buffer_x_left_1(i+1),
y_out_left => point_buffer_y_left_1(i+1),
hessian_out_left => hessian_buffer_left_1(i+1),
x_out_right => point_buffer_x_right_1(i),
y_out_right => point_buffer_y_right_1(i),
hessian_out_right => hessian_buffer_right_1(i)
);
end generate U_ODD;
end generate GEN_FEATURE_BUFFER_1;
end Behavioral;
| mit | bfa6c24ae547838ebe7d815e7073aed2 | 0.46582 | 3.440469 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/synth/system_vga_sync_0_0.vhd | 2 | 4,819 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit | e76103db0fc5cadb70c387da74eef5ac | 0.70305 | 3.664639 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cache/replace/lru/cpu_l1mem_data_cache_replace_lru-rtl.vhdl | 1 | 2,071 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library mem;
use work.cpu_l1mem_data_cache_config_pkg.all;
architecture rtl of cpu_l1mem_data_cache_replace_lru is
begin
lru : entity mem.cache_replace_lru(rtl)
generic map (
log2_assoc => cpu_l1mem_data_cache_log2_assoc,
index_bits => cpu_l1mem_data_cache_index_bits
)
port map (
clk => clk,
rstn => rstn,
re => cpu_l1mem_data_cache_replace_lru_ctrl_in.re,
rindex => cpu_l1mem_data_cache_replace_lru_dp_in.rindex,
rway => cpu_l1mem_data_cache_replace_lru_ctrl_out.rway,
rstate => cpu_l1mem_data_cache_replace_lru_dp_out.rstate,
we => cpu_l1mem_data_cache_replace_lru_ctrl_in.we,
windex => cpu_l1mem_data_cache_replace_lru_dp_in.windex,
wway => cpu_l1mem_data_cache_replace_lru_ctrl_in.wway,
wstate => cpu_l1mem_data_cache_replace_lru_dp_in.wstate
);
end;
| apache-2.0 | 88728a24d3ec40e8dce41aba5527aa04 | 0.544182 | 3.982692 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/reg32.vhd | 2 | 441 | library ieee ;
use ieee.std_logic_1164.all;
entity reg32 is
port(
a : in std_logic_vector (1 to 32);
q : out std_logic_vector (1 to 32);
reset : in std_logic;
clk : in std_logic
);
end reg32;
architecture synth of reg32 is
signal memory : std_logic_vector (1 to 32) ;
begin
process(clk,reset)
begin
if(reset = '1') then
memory <= (others => '0');
elsif(clk = '1' and clk'event) then
memory <= a;
end if;
end process;
q <= memory;
end synth;
| mit | 02771ba351606db7a174fed351dca2b4 | 0.678005 | 2.73913 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/rgb565_to_g8/rgb565_to_g8.srcs/sources_1/new/rgb565_to_g8.vhd | 1 | 1,137 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: rgb565_to_g8 - Structural
-- Description: Converts rgb565 to 8-bit grayscale
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb565_to_g8 is
port(
rgb565: in std_logic_vector(15 downto 0);
g8: out std_logic_vector(7 downto 0)
);
end rgb565_to_g8;
architecture Structural of rgb565_to_g8 is
signal red : unsigned(4 downto 0);
signal green : unsigned(5 downto 0);
signal blue : unsigned(4 downto 0);
signal sum : unsigned(7 downto 0);
begin
red <= unsigned(rgb565(15 downto 10));
green <= unsigned(rgb565(9 downto 5));
blue <= unsigned(rgb565(4 downto 0));
sum <= (red + green + blue) / 3;
g8 <= std_logic_vector(sum);
end Structural;
| mit | ca846c25fc5ef5e4b309ffcad11cc05c | 0.57168 | 3.989474 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/mul_pipe_inferred-rtl.vhdl | 1 | 2,284 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of mul_pipe_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
end record;
type register_type is array(0 to stages-1) of std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
signal c : comb_type;
signal r, r_next : register_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src1(src2_bits-1) and not unsgnd) & src2;
c.result_tmp <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
r_next(0) <= c.result_tmp(src1_bits+src2_bits-1 downto 0);
stages_gt_1 : if stages > 1 generate
pipeline_loop : for n in 1 to stages-1 generate
r_next(n) <= r(n-1);
end generate;
end generate;
result <= r(stages-1);
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | 898a7b0070395c9964757328a18b3b8c | 0.551226 | 3.924399 | false | false | false | false |
loa-org/loa-hdl | modules/ram/hdl/xilinx_block_ram.vhd | 2 | 9,197 | -------------------------------------------------------------------------------
-- Title : Xilinx Dual Port RAM with asymmetric port widths.
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: VHDL template for Xilinx Block RAM
--
-- True generic VHDL memory interface without instantiation of device specific
-- primitives. Asymmetrical port width are possible and can be both simulated
-- with GHDL and sythesized with Xilinx XST, which recognises the primitives.
--
-- Synchronous, Dual Port RAM, no parity,
-- "read-first" behaviour, which is the recommended behaviour.
--
-- Possible configurations per port are (see xapp463.pdf):
--
-- +-----------+------+------+
-- | | Addr | Data |
-- | Addresses | Bits | Bits |
-- +-----------+------+------+
-- | 16K | 14 | 1 |
-- | 8K | 13 | 2 |
-- | 4K | 12 | 4 |
-- | 2K | 11 | 8 |
-- | 2K | 11 | 9 |
-- | 1K | 10 | 16 |
-- | 1K | 10 | 18 |
-- | 512 | 9 | 32 |
-- | 512 | 9 | 36 |
-- | 256 | 8 | 72 |
-- +-----------+------+------+
--
-- To synthesize this HDL template with Xilinx XST it is necessary to choose the "new parser".
-- 1) Right-click on "Synthesize - XST"
-- 2) Process Properties
-- 3) Change Property Display Level to Advanced
-- 4) Add "-use_new_parser yes" to Other XST Command Line Options
--
-- You will see that XST recognises the Dual Port Block RAM with
-- asymmetrical port successfully.
--
-- =========================================================================
-- * Advanced HDL Synthesis *
-- =========================================================================
--
--
-- Synthesizing (advanced) Unit <xilinx_block_ram_dual_port>.
-- INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <read_a> <read_b>
-- -----------------------------------------------------------------------
-- | ram_type | Block | |
-- -----------------------------------------------------------------------
-- | Port A |
-- | aspect ratio | 2048-word x 8-bit | |
-- | mode | read-first | |
-- | clkA | connected to signal <clk_a> | rise |
-- | weA | connected to signal <we_a> | high |
-- | addrA | connected to signal <addr_a> | |
-- | diA | connected to signal <din_a> | |
-- | doA | connected to signal <read_a> | |
-- -----------------------------------------------------------------------
-- | optimization | speed | |
-- -----------------------------------------------------------------------
-- | Port B |
-- | aspect ratio | 1024-word x 16-bit | |
-- | mode | read-first | |
-- | clkB | connected to signal <clk_b> | rise |
-- | weB<3> | connected to signal <we_b> | high |
-- | weB<2> | connected to signal <we_b> | high |
-- | weB<1> | connected to signal <we_b> | high |
-- | weB<0> | connected to signal <we_b> | high |
-- | addrB | connected to signal <addr_b> | |
-- | diB | connected to signal <din_b> | |
-- | doB | connected to signal <read_b> | |
-- -----------------------------------------------------------------------
-- | optimization | speed | |
-- -----------------------------------------------------------------------
-- Unit <xilinx_block_ram_dual_port> synthesized (advanced).
--
--
--
-------------------------------------------------------------------------------
-- Relationship between port A and B
-------------------------------------------------------------------------------
--
-- 35 18 17 0
-- addr 0x00 at port B: |----data-w----| |----data-v----|
-- addr 0x01 at port B: |----data-y----| |----data-x----|
--
-- 17 0
-- addr 0x00 at port A: |----data-v----|
-- addr 0x01 at port A: |----data-w----|
-- addr 0x02 at port A: |----data-x----|
-- addr 0x03 at port A: |----data-y----|
--
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.xilinx_block_ram_pkg.all;
entity xilinx_block_ram_dual_port is
generic (
ADDR_A_WIDTH : positive := 11;
ADDR_B_WIDTH : positive := 11;
DATA_A_WIDTH : positive := 8;
DATA_B_WIDTH : positive := 8);
port (
addr_a : in std_logic_vector(ADDR_A_WIDTH-1 downto 0);
addr_b : in std_logic_vector(ADDR_B_WIDTH-1 downto 0);
din_a : in std_logic_vector(DATA_A_WIDTH-1 downto 0);
din_b : in std_logic_vector(DATA_B_WIDTH-1 downto 0);
dout_a : out std_logic_vector(DATA_A_WIDTH-1 downto 0);
dout_b : out std_logic_vector(DATA_B_WIDTH-1 downto 0);
we_a : in std_logic; -- write enable
we_b : in std_logic; -- write enable
en_a : in std_logic; -- enable the port
en_b : in std_logic; -- enable the port
ssr_a : in std_logic; -- synchronous reset of output latches
ssr_b : in std_logic; -- synchronous reset of output latches
clk_a : in std_logic;
clk_b : in std_logic);
end xilinx_block_ram_dual_port;
architecture behavourial of xilinx_block_ram_dual_port is
constant MIN_WIDTH : positive := minn(DATA_A_WIDTH, DATA_B_WIDTH);
constant MAX_WIDTH : positive := max(DATA_A_WIDTH, DATA_B_WIDTH);
constant MAX_SIZE : positive := max(2**ADDR_A_WIDTH, 2**ADDR_B_WIDTH);
constant RATIO : positive := MAX_WIDTH / MIN_WIDTH;
type ram_type is array (0 to MAX_SIZE-1) of std_logic_vector(MIN_WIDTH-1 downto 0);
shared variable ram : ram_type := (others => (others => '0'));
signal reg_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal reg_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
begin -- behavourial
ram_proc : process (clk_a)
variable read_a : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
begin -- process ram_proc
if rising_edge(clk_a) then
if en_a = '1' then
if ssr_a = '1' then
read_a := (others => '0');
else
read_a := ram(conv_integer(addr_a));
end if;
if (we_a = '1') then
ram(conv_integer(addr_a)) := din_a;
end if;
end if; -- en_a
reg_a <= read_a;
end if;
end process ram_proc;
ram_b_proc : process(clk_b)
variable read_b : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
begin -- process ram_b_proc
if rising_edge(clk_b) then
if en_b = '1' then
if RATIO = 1 then
-- symmetrical port widths
if ssr_b = '1' then
read_b := (others => '0');
else
read_b := ram(conv_integer(addr_b));
end if;
if we_b = '1' then
ram(conv_integer(addr_b)) := din_b;
end if;
else
-- RATIO != 1, asymmetrical port widths
if ssr_b = '1' then
read_b := (others => '0');
else
for i in 0 to RATIO-1 loop
read_b((i+1)*MIN_WIDTH-1 downto i*MIN_WIDTH) := ram(conv_integer(addr_b & conv_std_logic_vector(i, log2(RATIO))));
end loop;
end if;
if we_b = '1' then
for i in 0 to RATIO-1 loop
ram(conv_integer(addr_b & conv_std_logic_vector(i, log2(RATIO)))) := din_b((i+1)*MIN_WIDTH-1 downto i*MIN_WIDTH);
end loop; -- i
end if;
end if; -- ratio = 1
end if; -- en_b = '1'
reg_b <= read_b;
end if;
end process ram_b_proc;
dout_a <= reg_a;
dout_b <= reg_b;
end behavourial;
| bsd-3-clause | 2b943ea5f4aa56a9184e2c5e759be075 | 0.398934 | 4.014404 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/bldc_driver_stage_converter_tb.vhd | 2 | 3,036 | -------------------------------------------------------------------------------
-- Title : Testbench for design "bldc_driver_stage_converter"
-- Project :
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity bldc_driver_stage_converter_tb is
end entity bldc_driver_stage_converter_tb;
-------------------------------------------------------------------------------
architecture tb of bldc_driver_stage_converter_tb is
-- component ports
signal bldc_driver_stage : bldc_driver_stage_type := (a => (high => '0', low => '0'),
b => (high => '0', low => '0'),
c => (high => '0', low => '0')
);
signal bldc_driver_stage_st : bldc_driver_stage_st_type;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.bldc_driver_stage_converter
port map (
bldc_driver_stage => bldc_driver_stage,
bldc_driver_stage_st => bldc_driver_stage_st);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- All off
-- default
wait until clk = '1';
-- P1 H
bldc_driver_stage.a.high <= '1';
wait until clk = '1';
-- P1 L
bldc_driver_stage.a.high <= '0';
bldc_driver_stage.a.low <= '1';
wait until clk = '1';
-- P1 H L shoot through
bldc_driver_stage.a.high <= '1';
bldc_driver_stage.a.low <= '1';
wait until clk = '1';
-- P2 H
bldc_driver_stage.a.low <= '0';
bldc_driver_stage.a.high <= '0';
bldc_driver_stage.b.high <= '1';
wait until clk = '1';
-- P2 L
bldc_driver_stage.b.high <= '0';
bldc_driver_stage.b.low <= '1';
wait until clk = '1';
-- P3H
bldc_driver_stage.c.high <= '1';
wait until clk = '1';
-- P3L
bldc_driver_stage.c.high <= '0';
bldc_driver_stage.c.low <= '1';
wait;
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration bldc_driver_stage_converter_tb_tb_cfg of bldc_driver_stage_converter_tb is
for tb
end for;
end bldc_driver_stage_converter_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | e52987d4b4ce953c7cd36c508c94ab27 | 0.410079 | 4.380952 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl | 1 | 267,051 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:16:39 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl
-- Design : system_auto_us_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_word : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC;
use_wrap_buffer : out STD_LOGIC;
first_mi_word_q : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\current_word_1_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_READY_I : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
\USE_RTL_ADDR.addr_q_reg[4]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\out\ : in STD_LOGIC;
\m_payload_i_reg[66]\ : in STD_LOGIC;
use_wrap_buffer_reg_0 : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 10 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ : in STD_LOGIC;
\m_payload_i_reg[65]\ : in STD_LOGIC_VECTOR ( 65 downto 0 );
\current_word_1_reg[2]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
signal M_AXI_RDATA_I : STD_LOGIC_VECTOR ( 63 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^current_word_1_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_3_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_7_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_8_n_0 : STD_LOGIC;
signal s_ready_i_i_9_n_0 : STD_LOGIC;
signal \^use_wrap_buffer\ : STD_LOGIC;
signal use_wrap_buffer_i_1_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_3_n_0 : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
signal wrap_buffer_available_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[0]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[5]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_3\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_4\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_4 : label is "soft_lutpair38";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_6 : label is "soft_lutpair33";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_7 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_8 : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair37";
attribute SOFT_HLUTNM of s_ready_i_i_9 : label is "soft_lutpair33";
begin
SR(0) <= \^sr\(0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ <= \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\;
\current_word_1_reg[2]_0\(2 downto 0) <= \^current_word_1_reg[2]_0\(2 downto 0);
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer <= \^use_wrap_buffer\;
\M_AXI_RDATA_I[63]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => \^first_mi_word_q\,
I2 => Q(9),
I3 => mr_rvalid,
I4 => rd_cmd_valid,
O => p_7_in
);
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(0),
Q => M_AXI_RDATA_I(0),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(10),
Q => M_AXI_RDATA_I(10),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(11),
Q => M_AXI_RDATA_I(11),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(12),
Q => M_AXI_RDATA_I(12),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(13),
Q => M_AXI_RDATA_I(13),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(14),
Q => M_AXI_RDATA_I(14),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(15),
Q => M_AXI_RDATA_I(15),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(16),
Q => M_AXI_RDATA_I(16),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(17),
Q => M_AXI_RDATA_I(17),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(18),
Q => M_AXI_RDATA_I(18),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(19),
Q => M_AXI_RDATA_I(19),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(1),
Q => M_AXI_RDATA_I(1),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(20),
Q => M_AXI_RDATA_I(20),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(21),
Q => M_AXI_RDATA_I(21),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(22),
Q => M_AXI_RDATA_I(22),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(23),
Q => M_AXI_RDATA_I(23),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(24),
Q => M_AXI_RDATA_I(24),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(25),
Q => M_AXI_RDATA_I(25),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(26),
Q => M_AXI_RDATA_I(26),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(27),
Q => M_AXI_RDATA_I(27),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(28),
Q => M_AXI_RDATA_I(28),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(29),
Q => M_AXI_RDATA_I(29),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(2),
Q => M_AXI_RDATA_I(2),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(30),
Q => M_AXI_RDATA_I(30),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(31),
Q => M_AXI_RDATA_I(31),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(32),
Q => M_AXI_RDATA_I(32),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(33),
Q => M_AXI_RDATA_I(33),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(34),
Q => M_AXI_RDATA_I(34),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(35),
Q => M_AXI_RDATA_I(35),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(36),
Q => M_AXI_RDATA_I(36),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(37),
Q => M_AXI_RDATA_I(37),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(38),
Q => M_AXI_RDATA_I(38),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(39),
Q => M_AXI_RDATA_I(39),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(3),
Q => M_AXI_RDATA_I(3),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(40),
Q => M_AXI_RDATA_I(40),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(41),
Q => M_AXI_RDATA_I(41),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(42),
Q => M_AXI_RDATA_I(42),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(43),
Q => M_AXI_RDATA_I(43),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(44),
Q => M_AXI_RDATA_I(44),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(45),
Q => M_AXI_RDATA_I(45),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(46),
Q => M_AXI_RDATA_I(46),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(47),
Q => M_AXI_RDATA_I(47),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(48),
Q => M_AXI_RDATA_I(48),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(49),
Q => M_AXI_RDATA_I(49),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(4),
Q => M_AXI_RDATA_I(4),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(50),
Q => M_AXI_RDATA_I(50),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(51),
Q => M_AXI_RDATA_I(51),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(52),
Q => M_AXI_RDATA_I(52),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(53),
Q => M_AXI_RDATA_I(53),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(54),
Q => M_AXI_RDATA_I(54),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(55),
Q => M_AXI_RDATA_I(55),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(56),
Q => M_AXI_RDATA_I(56),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(57),
Q => M_AXI_RDATA_I(57),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(58),
Q => M_AXI_RDATA_I(58),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(59),
Q => M_AXI_RDATA_I(59),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(5),
Q => M_AXI_RDATA_I(5),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(60),
Q => M_AXI_RDATA_I(60),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(61),
Q => M_AXI_RDATA_I(61),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(62),
Q => M_AXI_RDATA_I(62),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(63),
Q => M_AXI_RDATA_I(63),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(6),
Q => M_AXI_RDATA_I(6),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(7),
Q => M_AXI_RDATA_I(7),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(8),
Q => M_AXI_RDATA_I(8),
R => \^sr\(0)
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(9),
Q => M_AXI_RDATA_I(9),
R => \^sr\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F010000FFFFFFFF"
)
port map (
I0 => s_axi_rlast_INST_0_i_1_n_0,
I1 => wrap_buffer_available,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I3 => \^use_wrap_buffer\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\,
I5 => rd_cmd_valid,
O => M_READY_I
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"A080"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => rd_cmd_valid,
I3 => mr_rvalid,
O => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => '1',
D => \m_payload_i_reg[66]\,
Q => \^first_mi_word_q\,
S => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2FFF7000"
)
port map (
I0 => \^first_mi_word_q\,
I1 => Q(0),
I2 => use_wrap_buffer_reg_0,
I3 => mr_rvalid,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F070F07078F878"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => \^first_mi_word_q\,
I4 => Q(1),
I5 => \USE_RTL_LENGTH.length_counter_q[1]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7078F878F8F070F0"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \^first_mi_word_q\,
I4 => Q(2),
I5 => s_axi_rlast_INST_0_i_3_n_0,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF80007F770888"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => Q(3),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I5 => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => \^first_mi_word_q\,
I2 => Q(2),
I3 => s_axi_rlast_INST_0_i_3_n_0,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F780F7087F08F708"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I4 => \^first_mi_word_q\,
I5 => Q(4),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF5DDDDFFF5"
)
port map (
I0 => s_axi_rlast_INST_0_i_3_n_0,
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F087F80F7807F80"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0151"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \^first_mi_word_q\,
I3 => Q(4),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F087F80F7807F80"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I4 => \^first_mi_word_q\,
I5 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => Q(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F087F80F7807F80"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => mr_rvalid,
I2 => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I4 => \^first_mi_word_q\,
I5 => Q(7),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000011101"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => Q(4),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^sr\(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^sr\(0)
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(0),
R => \^sr\(0)
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(1),
R => \^sr\(0)
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(2),
R => \^sr\(0)
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => p_15_in,
D => \^s_axi_rlast\,
Q => \^first_word\,
S => \^sr\(0)
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A888"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => rd_cmd_valid,
I3 => mr_rvalid,
O => p_15_in
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(0),
Q => \^current_word_1_reg[2]_0\(0),
R => \^sr\(0)
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(1),
Q => \^current_word_1_reg[2]_0\(1),
R => \^sr\(0)
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(2),
Q => \^current_word_1_reg[2]_0\(2),
R => \^sr\(0)
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(64),
Q => rresp_wrap_buffer(0),
R => \^sr\(0)
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[65]\(65),
Q => rresp_wrap_buffer(1),
R => \^sr\(0)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(0),
I1 => M_AXI_RDATA_I(0),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(32),
I5 => M_AXI_RDATA_I(32),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(10),
I1 => M_AXI_RDATA_I(10),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(42),
I5 => M_AXI_RDATA_I(42),
O => s_axi_rdata(10)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(11),
I1 => M_AXI_RDATA_I(11),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(43),
I5 => M_AXI_RDATA_I(43),
O => s_axi_rdata(11)
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(12),
I1 => M_AXI_RDATA_I(12),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(44),
I5 => M_AXI_RDATA_I(44),
O => s_axi_rdata(12)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(13),
I1 => M_AXI_RDATA_I(13),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(45),
I5 => M_AXI_RDATA_I(45),
O => s_axi_rdata(13)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(14),
I1 => M_AXI_RDATA_I(14),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(46),
I5 => M_AXI_RDATA_I(46),
O => s_axi_rdata(14)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(15),
I1 => M_AXI_RDATA_I(15),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(47),
I5 => M_AXI_RDATA_I(47),
O => s_axi_rdata(15)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(16),
I1 => M_AXI_RDATA_I(16),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(48),
I5 => M_AXI_RDATA_I(48),
O => s_axi_rdata(16)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(17),
I1 => M_AXI_RDATA_I(17),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(49),
I5 => M_AXI_RDATA_I(49),
O => s_axi_rdata(17)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(18),
I1 => M_AXI_RDATA_I(18),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(50),
I5 => M_AXI_RDATA_I(50),
O => s_axi_rdata(18)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(19),
I1 => M_AXI_RDATA_I(19),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(51),
I5 => M_AXI_RDATA_I(51),
O => s_axi_rdata(19)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(1),
I1 => M_AXI_RDATA_I(1),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(33),
I5 => M_AXI_RDATA_I(33),
O => s_axi_rdata(1)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(20),
I1 => M_AXI_RDATA_I(20),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(52),
I5 => M_AXI_RDATA_I(52),
O => s_axi_rdata(20)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(21),
I1 => M_AXI_RDATA_I(21),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(53),
I5 => M_AXI_RDATA_I(53),
O => s_axi_rdata(21)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(22),
I1 => M_AXI_RDATA_I(22),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(54),
I5 => M_AXI_RDATA_I(54),
O => s_axi_rdata(22)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(23),
I1 => M_AXI_RDATA_I(23),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(55),
I5 => M_AXI_RDATA_I(55),
O => s_axi_rdata(23)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(24),
I1 => M_AXI_RDATA_I(24),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(56),
I5 => M_AXI_RDATA_I(56),
O => s_axi_rdata(24)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(25),
I1 => M_AXI_RDATA_I(25),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(57),
I5 => M_AXI_RDATA_I(57),
O => s_axi_rdata(25)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(26),
I1 => M_AXI_RDATA_I(26),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(58),
I5 => M_AXI_RDATA_I(58),
O => s_axi_rdata(26)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(27),
I1 => M_AXI_RDATA_I(27),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(59),
I5 => M_AXI_RDATA_I(59),
O => s_axi_rdata(27)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(28),
I1 => M_AXI_RDATA_I(28),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(60),
I5 => M_AXI_RDATA_I(60),
O => s_axi_rdata(28)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(29),
I1 => M_AXI_RDATA_I(29),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(61),
I5 => M_AXI_RDATA_I(61),
O => s_axi_rdata(29)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(2),
I1 => M_AXI_RDATA_I(2),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(34),
I5 => M_AXI_RDATA_I(34),
O => s_axi_rdata(2)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(30),
I1 => M_AXI_RDATA_I(30),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(62),
I5 => M_AXI_RDATA_I(62),
O => s_axi_rdata(30)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(31),
I1 => M_AXI_RDATA_I(31),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(63),
I5 => M_AXI_RDATA_I(63),
O => s_axi_rdata(31)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(3),
I1 => M_AXI_RDATA_I(3),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(35),
I5 => M_AXI_RDATA_I(35),
O => s_axi_rdata(3)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(4),
I1 => M_AXI_RDATA_I(4),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(36),
I5 => M_AXI_RDATA_I(36),
O => s_axi_rdata(4)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(5),
I1 => M_AXI_RDATA_I(5),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(37),
I5 => M_AXI_RDATA_I(37),
O => s_axi_rdata(5)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(6),
I1 => M_AXI_RDATA_I(6),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(38),
I5 => M_AXI_RDATA_I(38),
O => s_axi_rdata(6)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(7),
I1 => M_AXI_RDATA_I(7),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(39),
I5 => M_AXI_RDATA_I(39),
O => s_axi_rdata(7)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(8),
I1 => M_AXI_RDATA_I(8),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(40),
I5 => M_AXI_RDATA_I(40),
O => s_axi_rdata(8)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAFFCAF0CA0FCA00"
)
port map (
I0 => \m_payload_i_reg[65]\(9),
I1 => M_AXI_RDATA_I(9),
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[2]_1\,
I4 => \m_payload_i_reg[65]\(41),
I5 => M_AXI_RDATA_I(41),
O => s_axi_rdata(9)
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0F01"
)
port map (
I0 => s_axi_rlast_INST_0_i_1_n_0,
I1 => wrap_buffer_available,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I3 => \^use_wrap_buffer\,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => s_axi_rlast_INST_0_i_3_n_0,
I1 => s_axi_rlast_INST_0_i_4_n_0,
I2 => s_axi_rlast_INST_0_i_5_n_0,
I3 => s_axi_rlast_INST_0_i_6_n_0,
I4 => s_axi_rlast_INST_0_i_7_n_0,
I5 => s_axi_rlast_INST_0_i_8_n_0,
O => s_axi_rlast_INST_0_i_1_n_0
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => Q(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => Q(0),
O => s_axi_rlast_INST_0_i_3_n_0
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => s_axi_rlast_INST_0_i_6_n_0
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => s_axi_rlast_INST_0_i_7_n_0
);
s_axi_rlast_INST_0_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => Q(6),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I3 => \^first_mi_word_q\,
I4 => Q(5),
O => s_axi_rlast_INST_0_i_8_n_0
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => \m_payload_i_reg[65]\(64),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => \m_payload_i_reg[65]\(65),
O => s_axi_rresp(1)
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => rd_cmd_valid,
I2 => mr_rvalid,
O => s_axi_rvalid
);
s_ready_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => s_axi_rlast_INST_0_i_8_n_0,
I1 => s_ready_i_i_9_n_0,
I2 => s_axi_rlast_INST_0_i_5_n_0,
I3 => s_axi_rlast_INST_0_i_4_n_0,
I4 => s_axi_rlast_INST_0_i_3_n_0,
I5 => wrap_buffer_available,
O => \USE_RTL_ADDR.addr_q_reg[4]\
);
s_ready_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^current_word_1_reg[2]_0\(1),
I1 => Q(10),
I2 => \^first_word\,
I3 => Q(8),
O => \m_payload_i_reg[0]\
);
s_ready_i_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => Q(7),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => Q(4),
O => s_ready_i_i_9_n_0
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10001000"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_rlast_INST_0_i_1_n_0,
I2 => use_wrap_buffer_reg_0,
I3 => wrap_buffer_available,
I4 => use_wrap_buffer_i_3_n_0,
I5 => \^use_wrap_buffer\,
O => use_wrap_buffer_i_1_n_0
);
use_wrap_buffer_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004000400044"
)
port map (
I0 => m_valid_i_reg,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
I2 => \^use_wrap_buffer\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\,
I4 => wrap_buffer_available,
I5 => s_axi_rlast_INST_0_i_1_n_0,
O => use_wrap_buffer_i_3_n_0
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => use_wrap_buffer_i_1_n_0,
Q => \^use_wrap_buffer\,
R => \^sr\(0)
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB8888"
)
port map (
I0 => p_7_in,
I1 => use_wrap_buffer_reg_0,
I2 => s_axi_rlast_INST_0_i_1_n_0,
I3 => m_valid_i_reg,
I4 => wrap_buffer_available,
O => wrap_buffer_available_i_1_n_0
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => wrap_buffer_available_i_1_n_0,
Q => wrap_buffer_available,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
port (
\aresetn_d_reg[1]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 44 downto 0 );
signal \USE_READ.read_addr_inst/access_need_extra_word__3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst/cmd_next_word_ii__10\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_READ.read_addr_inst/mi_word_intra_len__8\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \^aresetn_d_reg[1]_0\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 27 downto 0 );
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arburst[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
signal upsized_length : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_5\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_axi_araddr[2]_INST_0_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_3\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_4\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_2\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_6\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_6\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0_i_2\ : label is "soft_lutpair58";
begin
Q(44 downto 0) <= \^q\(44 downto 0);
\aresetn_d_reg[1]_0\ <= \^aresetn_d_reg[1]_0\;
\in\(27 downto 0) <= \^in\(27 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
O => \^in\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAAAE"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFCECFEAAFCA8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFEEFFFEEEEE"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => sr_arsize(0),
I3 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(0),
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000022202AA"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\,
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414144414141044"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8848488848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFC0000EEFC"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8448"
)
port map (
I0 => sr_araddr(2),
I1 => \^in\(13),
I2 => \USE_READ.read_addr_inst/mi_word_intra_len__8\(2),
I3 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\,
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF04440"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
O => \USE_READ.read_addr_inst/mi_word_intra_len__8\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAEAEAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I5 => sr_araddr(1),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040400040004000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5_n_0\,
I2 => sr_araddr(0),
I3 => sr_arburst(0),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000100010000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888882288888828"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_araddr(1),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => sr_araddr(0),
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^in\(13),
I1 => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2),
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF5FF07000A00F8"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_araddr(2),
O => \USE_READ.read_addr_inst/cmd_next_word_ii__10\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100010001000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_araddr(1),
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^in\(13),
I1 => sr_araddr(2),
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554555455540000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0\,
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"13100000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0\,
I2 => s_axi_arlen_ii(2),
I3 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I4 => \^q\(33),
O => \^in\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFE0000000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \^q\(33),
O => \^in\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^in\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^in\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^in\(9)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => '1',
Q => \^aresetn_d_reg[1]_0\,
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \^aresetn_d_reg[1]_0\,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEFCCCCCCCC"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000040400"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFA0A0A0B0"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I5 => \m_axi_araddr[1]_INST_0_i_3_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(4),
O => \m_axi_araddr[1]_INST_0_i_2_n_0\
);
\m_axi_araddr[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400044444"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I1 => sr_araddr(1),
I2 => \m_axi_araddr[1]_INST_0_i_4_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I5 => s_axi_arlen_ii(0),
O => \m_axi_araddr[1]_INST_0_i_3_n_0\
);
\m_axi_araddr[1]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_araddr[1]_INST_0_i_4_n_0\
);
\m_axi_araddr[1]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[1]_INST_0_i_5_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABABAB00000000"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
I2 => \m_axi_araddr[2]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
I5 => sr_araddr(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_araddr[2]_INST_0_i_2_n_0\,
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => s_axi_arlen_ii(7),
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_2_n_0\
);
\m_axi_araddr[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \m_axi_araddr[2]_INST_0_i_3_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00004000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => \^q\(33),
I2 => s_axi_arlen_ii(2),
I3 => sr_arburst(1),
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_arburst[0]_INST_0_i_1_n_0\,
O => m_axi_arburst(0)
);
\m_axi_arburst[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(1),
I4 => \m_axi_arburst[0]_INST_0_i_2_n_0\,
I5 => sr_arburst(0),
O => \m_axi_arburst[0]_INST_0_i_1_n_0\
);
\m_axi_arburst[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03030700"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
O => \m_axi_arburst[0]_INST_0_i_2_n_0\
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFF00FF00"
)
port map (
I0 => \^q\(33),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arburst[1]_INST_0_i_1_n_0\,
I3 => \m_axi_arburst[1]_INST_0_i_2_n_0\,
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => m_axi_arburst(1)
);
\m_axi_arburst[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(0),
I2 => sr_arsize(2),
O => \m_axi_arburst[1]_INST_0_i_1_n_0\
);
\m_axi_arburst[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00A000BB00B100"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arburst(1),
I4 => sr_arsize(1),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arburst[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00151515FFEAEAEA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(0),
I5 => \USE_READ.read_addr_inst/access_need_extra_word__3\,
O => \^in\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_1_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F800000000"
)
port map (
I0 => sr_araddr(2),
I1 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I5 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
O => \USE_READ.read_addr_inst/access_need_extra_word__3\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030202"
)
port map (
I0 => sr_araddr(2),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"151515EA15EA15EA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(1),
O => \^in\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFAAEAAA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I2 => sr_araddr(0),
I3 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I4 => sr_araddr(2),
I5 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_araddr(0),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_10_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(2),
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E888"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(1),
I4 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F4000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_9_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_10_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000A800"
)
port map (
I0 => \^q\(33),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A800A800A800"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(0),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[1]_INST_0_i_9_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(2),
O => \^in\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEAAAEAAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00003777FFFFC888"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I5 => upsized_length(3),
O => \^in\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5540400000000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_5_n_0\,
I1 => sr_araddr(1),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040400040000000"
)
port map (
I0 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => sr_araddr(2),
I4 => s_axi_arlen_ii(2),
I5 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_7_n_0\,
O => upsized_length(3)
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => \^q\(33),
I4 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA80"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_7_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555566656665666"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => s_axi_arlen_ii(4),
O => \^in\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F0800000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000A0C"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"07070F0F07F8F0F0"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[5]_INST_0_i_2_n_0\,
O => \^in\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A0C00"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[5]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"556A6A6A"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I4 => s_axi_arlen_ii(6),
O => \^in\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0000000A0000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(4),
I4 => s_axi_arlen_ii(5),
I5 => s_axi_arlen_ii(7),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000100010000000"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => \^q\(33),
I4 => sr_arburst(0),
I5 => sr_arburst(1),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(6),
I2 => s_axi_arlen_ii(4),
I3 => s_axi_arlen_ii(5),
I4 => s_axi_arlen_ii(7),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => \^in\(7)
);
\m_axi_arlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \m_axi_arlen[7]_INST_0_i_3_n_0\,
I1 => s_axi_arlen_ii(2),
I2 => \^q\(33),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => s_axi_arlen_ii(3),
O => \m_axi_arlen[7]_INST_0_i_1_n_0\
);
\m_axi_arlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(33),
O => \m_axi_arlen[7]_INST_0_i_2_n_0\
);
\m_axi_arlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => sr_araddr(2),
I1 => s_axi_arlen_ii(0),
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => sr_arsize(1),
O => \m_axi_arlen[7]_INST_0_i_3_n_0\
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(0),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAFFFFFFFE"
)
port map (
I0 => sr_arsize(1),
I1 => s_axi_arlen_ii(2),
I2 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
O => m_axi_arsize(1)
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000100000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_arlen[7]_INST_0_i_2_n_0\,
I5 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^q\(6),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"D100"
)
port map (
I0 => cmd_push_block_reg,
I1 => \^s_axi_arready\,
I2 => s_axi_arvalid,
I3 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"D5DF0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => cmd_push_block_reg,
I2 => \^sr_arvalid\,
I3 => s_axi_arvalid,
I4 => \^aresetn_d_reg[1]_0\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
m_axi_rready : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
use_wrap_buffer_reg : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 65 downto 0 );
\out\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
use_wrap_buffer_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^use_rtl_length.first_mi_word_q_reg\ : STD_LOGIC;
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 66 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair28";
begin
\USE_RTL_LENGTH.first_mi_word_q_reg\ <= \^use_rtl_length.first_mi_word_q_reg\;
m_axi_rready <= \^m_axi_rready\;
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^m_axi_rlast\,
I1 => use_wrap_buffer_reg_0,
I2 => \^use_rtl_length.first_mi_word_q_reg\,
I3 => first_mi_word_q,
O => \USE_RTL_LENGTH.first_mi_word_q_reg_0\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(0),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(10),
Q => Q(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(11),
Q => Q(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(12),
Q => Q(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(13),
Q => Q(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(14),
Q => Q(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(15),
Q => Q(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(16),
Q => Q(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(17),
Q => Q(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(18),
Q => Q(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(19),
Q => Q(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(1),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(20),
Q => Q(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(21),
Q => Q(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(22),
Q => Q(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(23),
Q => Q(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(24),
Q => Q(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(25),
Q => Q(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(26),
Q => Q(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(27),
Q => Q(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(28),
Q => Q(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(29),
Q => Q(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(2),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(30),
Q => Q(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(31),
Q => Q(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(32),
Q => Q(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(33),
Q => Q(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(34),
Q => Q(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(35),
Q => Q(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(36),
Q => Q(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(37),
Q => Q(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(38),
Q => Q(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(39),
Q => Q(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(3),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(40),
Q => Q(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(41),
Q => Q(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(42),
Q => Q(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(43),
Q => Q(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(44),
Q => Q(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(45),
Q => Q(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(46),
Q => Q(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(47),
Q => Q(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(48),
Q => Q(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(49),
Q => Q(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(4),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(50),
Q => Q(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(51),
Q => Q(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(52),
Q => Q(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(53),
Q => Q(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(54),
Q => Q(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(55),
Q => Q(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(56),
Q => Q(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(57),
Q => Q(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(58),
Q => Q(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(59),
Q => Q(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(5),
Q => Q(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(60),
Q => Q(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(61),
Q => Q(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(62),
Q => Q(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(63),
Q => Q(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(64),
Q => Q(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(65),
Q => Q(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(66),
Q => \^m_axi_rlast\,
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(6),
Q => Q(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(7),
Q => Q(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(8),
Q => Q(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(9),
Q => Q(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF0000"
)
port map (
I0 => use_wrap_buffer_reg_0,
I1 => \^use_rtl_length.first_mi_word_q_reg\,
I2 => m_axi_rvalid,
I3 => \^m_axi_rready\,
I4 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^use_rtl_length.first_mi_word_q_reg\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF0000"
)
port map (
I0 => m_axi_rvalid,
I1 => \^m_axi_rready\,
I2 => use_wrap_buffer_reg_0,
I3 => \^use_rtl_length.first_mi_word_q_reg\,
I4 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"07"
)
port map (
I0 => \^use_rtl_length.first_mi_word_q_reg\,
I1 => rd_cmd_valid,
I2 => use_wrap_buffer,
O => use_wrap_buffer_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
port (
rd_cmd_valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
M_READY_I : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_word : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
signal \^q\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^current_word_1_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[2]_i_3_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^rd_cmd_valid\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_10_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_11_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_9_n_0 : STD_LOGIC;
signal s_ready_i_i_4_n_0 : STD_LOGIC;
signal s_ready_i_i_5_n_0 : STD_LOGIC;
signal s_ready_i_i_8_n_0 : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair43";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \current_word_1[0]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \current_word_1[2]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair45";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_10 : label is "soft_lutpair41";
attribute SOFT_HLUTNM of s_ready_i_i_8 : label is "soft_lutpair42";
begin
Q(10 downto 0) <= \^q\(10 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\;
\current_word_1_reg[2]\(2 downto 0) <= \^current_word_1_reg[2]\(2 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
rd_cmd_valid <= \^rd_cmd_valid\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => cmd_last_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => cmd_last_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => \^q\(8),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => rd_cmd_next_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => rd_cmd_first_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(9),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_modified,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(10),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => data_Exists_I,
Q => \^rd_cmd_valid\,
R => SR(0)
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999999999999699"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => cmd_push_block,
I3 => sr_arvalid,
I4 => buffer_Full_q,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFBA2045"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => M_READY_I,
I2 => valid_Write,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800EFEE1011"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I2 => M_READY_I,
I3 => valid_Write,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808080508080"
)
port map (
I0 => M_READY_I,
I1 => data_Exists_I_i_2_n_0,
I2 => data_Exists_I,
I3 => cmd_push_block,
I4 => sr_arvalid,
I5 => buffer_Full_q,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFE80000001"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888080888880888"
)
port map (
I0 => valid_Write,
I1 => \^rd_cmd_valid\,
I2 => use_wrap_buffer_reg,
I3 => use_wrap_buffer,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\,
I5 => wrap_buffer_available_reg,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => SR(0)
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00200000"
)
port map (
I0 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => M_READY_I,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => SR(0)
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => m_axi_arready,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80008"
)
port map (
I0 => rd_cmd_mask(0),
I1 => \pre_next_word_1_reg[2]\(0),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_next_word(0),
O => \^current_word_1_reg[2]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(1),
I1 => \^q\(8),
I2 => first_word,
I3 => \^q\(10),
I4 => \pre_next_word_1_reg[2]\(1),
O => \^current_word_1_reg[2]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80008"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \pre_next_word_1_reg[2]\(2),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_next_word(2),
O => \^current_word_1_reg[2]\(2)
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF000404FF00FF04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
I3 => data_Exists_I,
I4 => data_Exists_I_i_2_n_0,
I5 => M_READY_I,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => SR(0)
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_arvalid
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => mr_rvalid,
O => E(0)
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"54570000ABA80000"
)
port map (
I0 => rd_cmd_next_word(0),
I1 => \^q\(10),
I2 => first_word,
I3 => \pre_next_word_1_reg[2]\(0),
I4 => rd_cmd_mask(0),
I5 => cmd_step(0),
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8488844448444888"
)
port map (
I0 => \pre_next_word_1[1]_i_2_n_0\,
I1 => rd_cmd_mask(1),
I2 => \pre_next_word_1_reg[2]\(1),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \^q\(8),
I5 => cmd_step(1),
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80008"
)
port map (
I0 => cmd_step(0),
I1 => \pre_next_word_1_reg[2]\(0),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_next_word(0),
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8884448444488848"
)
port map (
I0 => \pre_next_word_1[2]_i_3_n_0\,
I1 => rd_cmd_mask(2),
I2 => rd_cmd_next_word(2),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \pre_next_word_1_reg[2]\(2),
I5 => cmd_step(2),
O => D(2)
);
\pre_next_word_1[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEFEEEA888A8880"
)
port map (
I0 => cmd_step(1),
I1 => \^q\(8),
I2 => first_word,
I3 => \^q\(10),
I4 => \pre_next_word_1_reg[2]\(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => \pre_next_word_1[2]_i_3_n_0\
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000001FD"
)
port map (
I0 => \current_word_1_reg[2]_0\(2),
I1 => first_word,
I2 => \^q\(10),
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
O => \s_axi_rdata[31]\
);
s_axi_rlast_INST_0_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(10),
I1 => first_word,
O => s_axi_rlast_INST_0_i_10_n_0
);
s_axi_rlast_INST_0_i_11: unisim.vcomponents.LUT5
generic map(
INIT => X"5556AAA6"
)
port map (
I0 => cmd_last_word(2),
I1 => \current_word_1_reg[2]_0\(2),
I2 => first_word,
I3 => \^q\(10),
I4 => rd_cmd_first_word(2),
O => s_axi_rlast_INST_0_i_11_n_0
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBBBEEEBE"
)
port map (
I0 => s_axi_rlast_INST_0_i_9_n_0,
I1 => cmd_last_word(1),
I2 => rd_cmd_first_word(1),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \current_word_1_reg[2]_0\(1),
I5 => s_axi_rlast_INST_0_i_11_n_0,
O => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\
);
s_axi_rlast_INST_0_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(0),
I1 => rd_cmd_first_word(0),
I2 => first_word,
I3 => \^q\(10),
I4 => \current_word_1_reg[2]_0\(0),
O => s_axi_rlast_INST_0_i_9_n_0
);
s_ready_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8A8AAA8A8"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => s_ready_i_i_4_n_0,
I2 => s_ready_i_i_5_n_0,
I3 => use_wrap_buffer,
I4 => wrap_buffer_available_reg,
I5 => \^use_ff_out.use_rtl_output_pipeline.m_valid_q_reg_0\,
O => \^m_payload_i_reg[0]\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8088"
)
port map (
I0 => m_axi_arready,
I1 => s_axi_aresetn,
I2 => cmd_push_block,
I3 => buffer_Full_q,
O => s_ready_i_reg
);
s_ready_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_rready,
I1 => \^rd_cmd_valid\,
O => \^m_payload_i_reg[0]_0\
);
s_ready_i_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(10),
I1 => rd_cmd_modified,
O => s_ready_i_i_4_n_0
);
s_ready_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0111011100000111"
)
port map (
I0 => rd_cmd_complete_wrap,
I1 => \^current_word_1_reg[2]\(2),
I2 => rd_cmd_mask(1),
I3 => \pre_next_word_1_reg[1]\,
I4 => rd_cmd_mask(0),
I5 => s_ready_i_i_8_n_0,
O => s_ready_i_i_5_n_0
);
s_ready_i_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"5457"
)
port map (
I0 => rd_cmd_next_word(0),
I1 => \^q\(10),
I2 => first_word,
I3 => \pre_next_word_1_reg[2]\(0),
O => s_ready_i_i_8_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
rd_cmd_valid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 10 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\current_word_1_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
M_READY_I : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\pre_next_word_1_reg[1]\ : in STD_LOGIC;
first_word : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
M_READY_I => M_READY_I,
Q(10 downto 0) => Q(10 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[2]\(2 downto 0) => \current_word_1_reg[2]\(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => \current_word_1_reg[2]_0\(2 downto 0),
first_word => first_word,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \m_payload_i_reg[0]_0\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[1]\ => \pre_next_word_1_reg[1]\,
\pre_next_word_1_reg[2]\(2 downto 0) => \pre_next_word_1_reg[2]\(2 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
s_axi_rready => s_axi_rready,
s_ready_i_reg => s_ready_i_reg,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
wrap_buffer_available_reg => wrap_buffer_available_reg
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
use_wrap_buffer_reg : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 65 downto 0 );
\out\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
use_wrap_buffer_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(65 downto 0) => Q(65 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => mr_rvalid,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
first_mi_word_q => first_mi_word_q,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
rd_cmd_valid => rd_cmd_valid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
use_wrap_buffer_reg_0 => use_wrap_buffer_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
\aresetn_d_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
s_axi_arready : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
begin
ar_pipe: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice
port map (
D(60 downto 0) => D(60 downto 0),
Q(44 downto 0) => Q(44 downto 0),
SR(0) => SR(0),
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]\,
cmd_push_block_reg => cmd_push_block_reg,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\out\ => \out\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => s_ready_i_reg,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
Q : out STD_LOGIC_VECTOR ( 44 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rready : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 2 downto 0 );
\out\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \GEN_CMD_QUEUE.cmd_queue/M_READY_I\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_5\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_10\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_11\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_12\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_13\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_14\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_15\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_2\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_22\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_23\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_4\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_8\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_9\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_modified_i : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 22 downto 16 );
signal pre_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 1 to 1 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal rd_cmd_valid : STD_LOGIC;
signal si_register_slice_inst_n_0 : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_63 : STD_LOGIC;
signal si_register_slice_inst_n_64 : STD_LOGIC;
signal si_register_slice_inst_n_65 : STD_LOGIC;
signal si_register_slice_inst_n_66 : STD_LOGIC;
signal si_register_slice_inst_n_67 : STD_LOGIC;
signal si_register_slice_inst_n_68 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \r_pipe/p_1_in\,
Q(65 downto 64) => mr_rresp(1 downto 0),
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\,
\aresetn_d_reg[0]\ => si_register_slice_inst_n_0,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
first_mi_word_q => first_mi_word_q,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
rd_cmd_valid => rd_cmd_valid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_2\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
M_READY_I => \GEN_CMD_QUEUE.cmd_queue/M_READY_I\,
Q(10) => rd_cmd_fix,
Q(9) => rd_cmd_packed_wrap,
Q(8) => rd_cmd_next_word(1),
Q(7) => \USE_READ.read_addr_inst_n_8\,
Q(6) => \USE_READ.read_addr_inst_n_9\,
Q(5) => \USE_READ.read_addr_inst_n_10\,
Q(4) => \USE_READ.read_addr_inst_n_11\,
Q(3) => \USE_READ.read_addr_inst_n_12\,
Q(2) => \USE_READ.read_addr_inst_n_13\,
Q(1) => \USE_READ.read_addr_inst_n_14\,
Q(0) => \USE_READ.read_addr_inst_n_15\,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\ => \USE_READ.read_addr_inst_n_4\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_10\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\(2 downto 0) => current_word_1(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ => \USE_READ.read_addr_inst_n_3\,
\USE_RTL_ADDR.addr_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
\current_word_1_reg[2]_0\(2 downto 0) => pre_next_word_1(2 downto 0),
\current_word_1_reg[2]_1\ => \USE_READ.read_addr_inst_n_22\,
first_mi_word_q => first_mi_word_q,
first_word => first_word,
\m_payload_i_reg[0]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_5\,
\m_payload_i_reg[65]\(65 downto 64) => mr_rresp(1 downto 0),
\m_payload_i_reg[65]\(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
\m_payload_i_reg[65]\(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
\m_payload_i_reg[65]\(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
\m_payload_i_reg[65]\(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
\m_payload_i_reg[65]\(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
\m_payload_i_reg[65]\(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
\m_payload_i_reg[65]\(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
\m_payload_i_reg[65]\(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
\m_payload_i_reg[65]\(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
\m_payload_i_reg[65]\(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
\m_payload_i_reg[65]\(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
\m_payload_i_reg[65]\(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
\m_payload_i_reg[65]\(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
\m_payload_i_reg[65]\(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
\m_payload_i_reg[65]\(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
\m_payload_i_reg[65]\(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
\m_payload_i_reg[65]\(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
\m_payload_i_reg[65]\(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
\m_payload_i_reg[65]\(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
\m_payload_i_reg[65]\(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
\m_payload_i_reg[65]\(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
\m_payload_i_reg[65]\(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
\m_payload_i_reg[65]\(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
\m_payload_i_reg[65]\(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
\m_payload_i_reg[65]\(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
\m_payload_i_reg[65]\(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
\m_payload_i_reg[65]\(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
\m_payload_i_reg[65]\(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
\m_payload_i_reg[65]\(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
\m_payload_i_reg[65]\(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
\m_payload_i_reg[65]\(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
\m_payload_i_reg[65]\(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
\m_payload_i_reg[65]\(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
\m_payload_i_reg[65]\(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
\m_payload_i_reg[65]\(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
\m_payload_i_reg[65]\(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
\m_payload_i_reg[65]\(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
\m_payload_i_reg[65]\(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
\m_payload_i_reg[65]\(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
\m_payload_i_reg[65]\(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
\m_payload_i_reg[65]\(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
\m_payload_i_reg[65]\(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
\m_payload_i_reg[65]\(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
\m_payload_i_reg[65]\(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
\m_payload_i_reg[65]\(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
\m_payload_i_reg[65]\(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
\m_payload_i_reg[65]\(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
\m_payload_i_reg[65]\(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
\m_payload_i_reg[65]\(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
\m_payload_i_reg[65]\(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
\m_payload_i_reg[65]\(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
\m_payload_i_reg[65]\(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
\m_payload_i_reg[65]\(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
\m_payload_i_reg[65]\(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
\m_payload_i_reg[65]\(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
\m_payload_i_reg[65]\(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
\m_payload_i_reg[65]\(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
\m_payload_i_reg[65]\(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
\m_payload_i_reg[65]\(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
\m_payload_i_reg[65]\(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
\m_payload_i_reg[65]\(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
\m_payload_i_reg[65]\(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
\m_payload_i_reg[65]\(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
\m_payload_i_reg[65]\(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
\m_payload_i_reg[66]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\,
m_valid_i_reg => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_2\
);
\USE_READ.read_addr_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => \r_pipe/p_1_in\,
M_READY_I => \GEN_CMD_QUEUE.cmd_queue/M_READY_I\,
Q(10) => rd_cmd_fix,
Q(9) => rd_cmd_packed_wrap,
Q(8) => rd_cmd_next_word(1),
Q(7) => \USE_READ.read_addr_inst_n_8\,
Q(6) => \USE_READ.read_addr_inst_n_9\,
Q(5) => \USE_READ.read_addr_inst_n_10\,
Q(4) => \USE_READ.read_addr_inst_n_11\,
Q(3) => \USE_READ.read_addr_inst_n_12\,
Q(2) => \USE_READ.read_addr_inst_n_13\,
Q(1) => \USE_READ.read_addr_inst_n_14\,
Q(0) => \USE_READ.read_addr_inst_n_15\,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_READ.read_addr_inst_n_4\,
\current_word_1_reg[2]\(2 downto 0) => next_word(2 downto 0),
\current_word_1_reg[2]_0\(2 downto 0) => current_word_1(2 downto 0),
first_word => first_word,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_63,
\in\(12) => si_register_slice_inst_n_64,
\in\(11) => si_register_slice_inst_n_65,
\in\(10) => si_register_slice_inst_n_66,
\in\(9) => si_register_slice_inst_n_67,
\in\(8) => si_register_slice_inst_n_68,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \USE_READ.read_addr_inst_n_2\,
\m_payload_i_reg[0]_0\ => \USE_READ.read_addr_inst_n_3\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_5\,
\pre_next_word_1_reg[2]\(2 downto 0) => pre_next_word_1(2 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \USE_READ.read_addr_inst_n_22\,
s_axi_rready => s_axi_rready,
s_ready_i_reg => \USE_READ.read_addr_inst_n_23\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_10\,
wrap_buffer_available_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\
);
si_register_slice_inst: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
D(60 downto 0) => D(60 downto 0),
Q(44 downto 0) => Q(44 downto 0),
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_0,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_23\,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_63,
\in\(12) => si_register_slice_inst_n_64,
\in\(11) => si_register_slice_inst_n_65,
\in\(10) => si_register_slice_inst_n_66,
\in\(9) => si_register_slice_inst_n_67,
\in\(8) => si_register_slice_inst_n_68,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\out\ => \out\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => si_register_slice_inst_n_1,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_1_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
begin
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_wready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_arregion(3 downto 0),
D(56 downto 53) => s_axi_arqos(3 downto 0),
D(52) => s_axi_arlock(0),
D(51 downto 44) => s_axi_arlen(7 downto 0),
D(43 downto 40) => s_axi_arcache(3 downto 0),
D(39 downto 38) => s_axi_arburst(1 downto 0),
D(37 downto 35) => s_axi_arsize(2 downto 0),
D(34 downto 32) => s_axi_arprot(2 downto 0),
D(31 downto 0) => s_axi_araddr(31 downto 0),
Q(44 downto 41) => m_axi_arregion(3 downto 0),
Q(40 downto 37) => m_axi_arqos(3 downto 0),
Q(36) => m_axi_arlock(0),
Q(35 downto 32) => m_axi_arcache(3 downto 0),
Q(31 downto 29) => m_axi_arprot(2 downto 0),
Q(28 downto 0) => m_axi_araddr(31 downto 3),
m_axi_araddr(2 downto 0) => m_axi_araddr(2 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_1 : entity is "system_auto_us_1,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_1 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_1;
architecture STRUCTURE of system_auto_us_1 is
signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(63 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"01",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '1',
s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid => '0'
);
end STRUCTURE;
| mit | 8982f5c1553fa3de101107d388cdce9a | 0.551168 | 2.580702 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_buffer_register_0_0/system_buffer_register_0_0_sim_netlist.vhdl | 1 | 7,575 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 17:33:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_0_0 -prefix
-- system_buffer_register_0_0_ system_buffer_register_0_0_sim_netlist.vhdl
-- Design : system_buffer_register_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0_buffer_register is
port (
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
clk : in STD_LOGIC
);
end system_buffer_register_0_0_buffer_register;
architecture STRUCTURE of system_buffer_register_0_0_buffer_register is
begin
\val_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(0),
Q => val_out(0),
R => '0'
);
\val_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(10),
Q => val_out(10),
R => '0'
);
\val_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(11),
Q => val_out(11),
R => '0'
);
\val_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(12),
Q => val_out(12),
R => '0'
);
\val_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(13),
Q => val_out(13),
R => '0'
);
\val_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(14),
Q => val_out(14),
R => '0'
);
\val_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(15),
Q => val_out(15),
R => '0'
);
\val_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(16),
Q => val_out(16),
R => '0'
);
\val_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(17),
Q => val_out(17),
R => '0'
);
\val_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(18),
Q => val_out(18),
R => '0'
);
\val_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(19),
Q => val_out(19),
R => '0'
);
\val_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(1),
Q => val_out(1),
R => '0'
);
\val_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(20),
Q => val_out(20),
R => '0'
);
\val_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(21),
Q => val_out(21),
R => '0'
);
\val_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(22),
Q => val_out(22),
R => '0'
);
\val_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(23),
Q => val_out(23),
R => '0'
);
\val_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(24),
Q => val_out(24),
R => '0'
);
\val_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(25),
Q => val_out(25),
R => '0'
);
\val_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(26),
Q => val_out(26),
R => '0'
);
\val_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(27),
Q => val_out(27),
R => '0'
);
\val_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(28),
Q => val_out(28),
R => '0'
);
\val_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(29),
Q => val_out(29),
R => '0'
);
\val_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(2),
Q => val_out(2),
R => '0'
);
\val_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(30),
Q => val_out(30),
R => '0'
);
\val_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(31),
Q => val_out(31),
R => '0'
);
\val_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(3),
Q => val_out(3),
R => '0'
);
\val_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(4),
Q => val_out(4),
R => '0'
);
\val_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(5),
Q => val_out(5),
R => '0'
);
\val_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(6),
Q => val_out(6),
R => '0'
);
\val_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(7),
Q => val_out(7),
R => '0'
);
\val_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(8),
Q => val_out(8),
R => '0'
);
\val_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(9),
Q => val_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_buffer_register_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_buffer_register_0_0 : entity is "system_buffer_register_0_0,buffer_register,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_buffer_register_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_buffer_register_0_0 : entity is "buffer_register,Vivado 2016.4";
end system_buffer_register_0_0;
architecture STRUCTURE of system_buffer_register_0_0 is
begin
U0: entity work.system_buffer_register_0_0_buffer_register
port map (
clk => clk,
val_in(31 downto 0) => val_in(31 downto 0),
val_out(31 downto 0) => val_out(31 downto 0)
);
end STRUCTURE;
| mit | 53c046fe7d3d06f9b68e0523bad2ff16 | 0.486865 | 3.101966 | false | false | false | false |
phil91stud/pwm_hdl | pwm/testbench/tb_pwm.vhd | 1 | 1,199 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_pwm is
end entity tb_pwm;
architecture testbench of tb_pwm is
component pwm is
generic(
pwm_bits : natural := 31
);
port(
clk : in std_logic;
resetn : in std_logic;
enable : in std_logic;
duty_cycle : in std_logic_vector(pwm_bits - 1 downto 0);
--phase : in std_logic_vector(pwm_bits - 1 downto 0);
highimp : in std_logic;
pwm_out : out std_logic;
pwm_out_n: out std_logic
);
end component pwm;
signal clock : std_logic := '1';
signal resetn : std_logic := '1';
signal enable : std_logic := '0';
signal duty : std_logic_vector(2 downto 0);
signal highimp : std_logic := '0';
signal pwm0 : std_logic;
signal pwm1 : std_logic;
constant PERIOD : time := 10 ns;
begin
-- instance
dut: pwm
generic map(3)
port map(
clk => clock,
resetn => resetn,
enable => enable,
duty_cycle => duty,
highimp => highimp,
pwm_out => pwm0,
pwm_out_n => pwm1
);
-- stimuli
clock <= not clock after PERIOD/2;
duty <= "100";
process
begin
wait for 4*PERIOD;
enable <= '1';
--wait for us;
--highimp <= '1';
--wait for 500 ns;
--enable <= '0';
--highimp <= '0';
wait;
end process;
end architecture testbench; | mit | a30e983577839036342e2aa36c72243f | 0.653878 | 2.589633 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl | 1 | 804,707 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:21 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_i2c_sender : entity is "i2c_sender";
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_zed_hdmi : entity is "zed_hdmi";
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
| mit | d3b1c4118aab79d6bcb32e7a0fcdcce6 | 0.480125 | 2.231807 | false | false | false | false |
loa-org/loa-hdl | modules/spw_node/hdl/spw_node.vhd | 1 | 7,871 | -------------------------------------------------------------------------------
-- Title : SpaceWire Node Module
-------------------------------------------------------------------------------
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: This module interfaces a SpW stram core with the Loa bus.
-- Timecode featrues aren't accessible.
-- RX and TX FIFOs are accessible via a single address. The data is combined
-- with fifo status flags, eleminating additional polling of the FIFO flags.
--
-- Note: This module supports only synchronous resets, due to the
-- encapsulated ip-core
--
-------------------------------------------------------------------------------
-- Copyright (c) 2015 Carl Treudler
-------------------------------------------------------------------------------
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
--
-- Register Map
-------------------------------------------------------------------------------
-- BASE FIFO Rx & Tx (RW)
--
-- ro d15 tx fifo half full
-- ro d14 tx fifo ready
-- ro d13 rx fifo halffull
-- ro d12 rx fifo valid (word ready to read)
-- (..) unused
-- rw d8 flag-bit of data
-- rw d7..d0 data
--
-------------------------------------------------------------------------------
-- BASE + 1 Status (RO)
--
-- ro d15 tx fifo half full
-- ro d14 tx fifo ready
-- ro d13 rx fifo halffull
-- ro d12 rx fifo valid (word ready to read)
-- (..) unused
-- ro d6 started
-- ro d5 connecting
-- ro d4 running
-- ro d3 errdisc
-- ro d2 errpar
-- ro d1 erresc
-- ro d0 errcred
--
-------------------------------------------------------------------------------
-- BASE + 2 Control Reg. (RW)
--
-- rw d15..d8 tx baudrate divider
-- (..) unused
-- rw d2 linkdis
-- rw d1 linkstart
-- rw d0 autostart
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reset_pkg.all;
use work.spwpkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spw_node is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
RESET_IMPL : reset_type := sync);
port (
do_p : out std_logic;
so_p : out std_logic;
di_p : in std_logic;
si_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic);
end entity spw_node;
architecture behavioural of spw_node is
signal txwrite : std_logic;
signal txflag : std_logic;
signal txdata : std_logic_vector(7 downto 0);
signal txrdy : std_logic;
signal txhalff : std_logic;
signal rxvalid : std_logic;
signal rxhalff : std_logic;
signal rxflag : std_logic;
signal rxdata : std_logic_vector(7 downto 0);
signal rxread : std_logic;
-- link control signal
signal autostart : std_logic;
signal linkstart : std_logic;
signal linkdis : std_logic;
signal txdivcnt : std_logic_vector(7 downto 0);
-- link status signals
signal started : std_logic;
signal connecting : std_logic;
signal running : std_logic;
signal errdisc : std_logic;
signal errpar : std_logic;
signal erresc : std_logic;
signal errcred : std_logic;
-- Status and Control Register
signal statusword : std_logic_vector(3 downto 0);
signal ext_statusword : std_logic_vector(6 downto 0);
signal ctrlword : std_logic_vector(15 downto 0) := (others => '0');
signal bus_o_data : std_logic_vector(15 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------------
-- signal mapping and bit definition of registers
-----------------------------------------------------------------------------
-- short status word, also delivered for each read of the fifo
statusword <= txhalff & txrdy & rxhalff & rxvalid;
-- extended status word, delivered together with short statusword via a
-- read from the status register
ext_statusword <= started & connecting & running & errdisc & errpar & erresc & errcred;
-- control register
autostart <= ctrlword(0);
linkstart <= ctrlword(1);
linkdis <= ctrlword(2);
txdivcnt <= ctrlword(15 downto 8);
-- generate fifo read and write strobes
rxread <= '1' when (bus_i.re = '1' and bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS + 0, 15))) else '0';
txwrite <= '1' when (bus_i.we = '1' and bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS + 0, 15))) else '0';
-- mapping of bus to tx fifo
txdata <= bus_i.data(7 downto 0);
txflag <= bus_i.data(8);
bus_o.data <= bus_o_data;
-----------------------------------------------------------------------------
-- Adhoc implementation of bus output
-----------------------------------------------------------------------------
control_reg : process (clk) is
begin -- process
if rising_edge(clk) then
-- this module doesn't support async reset, as the spw codec doesn't anyway
if reset = '0' then
if bus_i.we = '1' and bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS + 2, 15)) then
ctrlword <= bus_i.data;
end if;
if (bus_i.re = '1' and bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS + 0, 15))) then
bus_o_data <= statusword & "000" & rxflag & rxdata;
elsif (bus_i.re = '1' and bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS + 1, 15))) then
bus_o_data <= statusword & "00000" & ext_statusword;
elsif (bus_i.re = '1' and bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS + 2, 15))) then
bus_o_data <= ctrlword;
else
bus_o_data <= (others => '0');
end if;
else --reset
ctrlword <= (others => '0');
bus_o_data <= (others => '0');
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Spw Stream Core instantiation
----------------------------------------------------------------------------
spwstream_1 : entity work.spwstream
generic map (
sysfreq => 50000000.0,
txclkfreq => 50000000.0,
rximpl => impl_generic,
rxchunk => 1,
tximpl => impl_generic,
rxfifosize_bits => 11,
txfifosize_bits => 11)
port map (
-- clk and rst
clk => clk,
rxclk => clk,
txclk => clk,
rst => reset,
-- link controls
autostart => autostart,
linkstart => linkstart,
linkdis => linkdis,
txdivcnt => txdivcnt,
-- Timecodes are currently not supported
tick_in => '0',
ctrl_in => (others => '0'),
time_in => (others => '0'),
tick_out => open,
ctrl_out => open,
time_out => open,
-- tx fifo interface
txwrite => txwrite,
txflag => txflag,
txdata => txdata,
txrdy => txrdy,
txhalff => txhalff,
-- rx fifo interface
rxvalid => rxvalid,
rxhalff => rxhalff,
rxflag => rxflag,
rxdata => rxdata,
rxread => rxread,
-- link status
started => started,
connecting => connecting,
running => running,
errdisc => errdisc,
errpar => errpar,
erresc => erresc,
errcred => errcred,
-- actual SpW Link
spw_di => di_p,
spw_si => si_p,
spw_do => do_p,
spw_so => so_p
);
end behavioural;
| bsd-3-clause | 59c75ae2a51f18034f8725ca2793a69d | 0.492441 | 3.997461 | false | false | false | false |
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`protect end_protected
| mit | 8462cc185aa09ddea0ad8e79b3459489 | 0.955153 | 1.809723 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_banked_1r1w.vhdl | 1 | 2,677 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Cache Core (SRAMs), banked, 1 read port, 1 write port
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity cache_core_banked_1r1w is
generic (
log2_assoc : natural := 1;
word_bits : natural := 1;
index_bits : natural := 1;
offset_bits : natural := 0;
log2_banks : natural := 1;
tag_bits : natural := 1;
write_first : boolean := true
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
we : in std_ulogic;
wway : in std_ulogic_vector(2**log2_assoc-1 downto 0);
wtagen : in std_ulogic;
wdataen : in std_ulogic;
wbanken : in std_ulogic_vector(2**log2_banks-1 downto 0);
windex : in std_ulogic_vector(index_bits-1 downto 0);
woffset : in std_ulogic_vector(offset_bits-1 downto 0);
wtag : in std_ulogic_vector(tag_bits-1 downto 0);
wdata : in std_ulogic_vector2(2**log2_banks-1 downto 0, word_bits-1 downto 0);
re : in std_ulogic;
rway : in std_ulogic_vector(2**log2_assoc-1 downto 0);
rtagen : in std_ulogic;
rdataen : in std_ulogic;
rbanken : in std_ulogic_vector(2**log2_banks-1 downto 0);
rindex : in std_ulogic_vector(index_bits-1 downto 0);
roffset : in std_ulogic_vector(offset_bits-1 downto 0);
rtag : out std_ulogic_vector2(2**log2_assoc-1 downto 0, tag_bits-1 downto 0);
rdata : out std_ulogic_vector3(2**log2_assoc-1 downto 0, 2**log2_banks-1 downto 0, word_bits-1 downto 0)
);
end;
| apache-2.0 | 8093797439061bec41650ecc8c6c1e1d | 0.562196 | 3.807966 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/axi_vga_framebuffer_1.0/hdl/axi_vga_framebuffer_v1_0_S_AXI.vhd | 1 | 205,963 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_vga_framebuffer_v1_0_S_AXI;
architecture arch_imp of axi_vga_framebuffer_v1_0_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 8;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 266
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg40 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg41 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg42 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg43 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg44 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg45 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg46 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg47 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg48 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg49 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg50 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg51 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg52 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg53 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg54 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg55 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg56 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg57 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg58 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg59 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg60 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg61 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg62 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg63 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg64 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg65 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg66 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg67 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg68 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg69 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg70 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg71 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg72 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg73 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg74 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg75 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg76 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg77 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg78 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg79 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg80 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg81 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg82 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg83 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg84 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg85 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg86 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg87 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg88 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg89 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg90 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg91 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg92 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg93 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg94 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg95 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg96 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg97 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg98 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg99 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg100 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg101 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg102 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg103 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg104 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg105 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg106 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg107 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg108 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg109 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg110 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg111 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg112 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg113 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg114 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg115 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg116 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg117 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg118 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg119 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg120 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg121 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg122 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg123 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg124 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg125 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg126 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg127 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg128 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg129 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg130 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg131 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg132 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg133 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg134 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg135 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg136 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg137 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg138 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg139 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg140 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg141 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg142 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg143 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg144 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg145 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg146 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg147 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg148 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg149 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg150 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg151 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg152 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg153 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg154 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg155 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg156 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg157 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg158 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg159 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg160 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg161 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg162 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg163 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg164 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg165 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg166 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg167 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg168 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg169 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg170 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg171 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg172 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg173 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg174 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg175 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg176 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg177 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg178 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg179 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg180 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg181 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg182 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg183 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg184 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg185 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg186 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg187 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg188 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg189 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg190 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg191 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg192 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg193 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg194 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg195 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg196 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg197 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg198 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg199 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg200 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg201 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg202 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg203 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg204 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg205 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg206 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg207 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg208 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg209 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg210 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg211 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg212 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg213 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg214 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg215 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg216 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg217 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg218 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg219 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg220 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg221 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg222 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg223 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg224 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg225 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg226 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg227 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg228 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg229 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg230 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg231 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg232 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg233 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg234 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg235 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg236 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg237 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg238 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg239 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg240 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg241 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg242 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg243 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg244 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg245 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg246 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg247 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg248 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg249 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg250 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg251 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg252 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg253 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg254 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg255 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg256 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg257 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg258 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg259 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg260 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg261 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg262 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg263 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg264 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg265 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
type CHUNK is array(15 downto 0) of std_logic_vector(23 downto 0);
type CHUNKS is array(15 downto 0) of CHUNK;
signal memory : CHUNKS;
signal chunk_offset_x, chunk_offset_y : unsigned(9 downto 0);
signal req_chunk : std_logic := '0';
signal req_chunk_x : unsigned(9 downto 0);
signal req_chunk_y : unsigned(9 downto 0);
signal req_write : std_logic_vector(3 downto 0) := "0000";
signal req_write_addr_0, req_write_addr_1, req_write_addr_2, req_write_addr_3, req_write_data_0, req_write_data_1, req_write_data_2, req_write_data_3 : std_logic_vector(31 downto 0);
signal busy : std_logic := '0';
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
--slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
--slv_reg2 <= (others => '0');
--slv_reg3 <= (others => '0');
--slv_reg4 <= (others => '0');
--slv_reg5 <= (others => '0');
--slv_reg6 <= (others => '0');
--slv_reg7 <= (others => '0');
--slv_reg8 <= (others => '0');
--slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
slv_reg40 <= (others => '0');
slv_reg41 <= (others => '0');
slv_reg42 <= (others => '0');
slv_reg43 <= (others => '0');
slv_reg44 <= (others => '0');
slv_reg45 <= (others => '0');
slv_reg46 <= (others => '0');
slv_reg47 <= (others => '0');
slv_reg48 <= (others => '0');
slv_reg49 <= (others => '0');
slv_reg50 <= (others => '0');
slv_reg51 <= (others => '0');
slv_reg52 <= (others => '0');
slv_reg53 <= (others => '0');
slv_reg54 <= (others => '0');
slv_reg55 <= (others => '0');
slv_reg56 <= (others => '0');
slv_reg57 <= (others => '0');
slv_reg58 <= (others => '0');
slv_reg59 <= (others => '0');
slv_reg60 <= (others => '0');
slv_reg61 <= (others => '0');
slv_reg62 <= (others => '0');
slv_reg63 <= (others => '0');
slv_reg64 <= (others => '0');
slv_reg65 <= (others => '0');
slv_reg66 <= (others => '0');
slv_reg67 <= (others => '0');
slv_reg68 <= (others => '0');
slv_reg69 <= (others => '0');
slv_reg70 <= (others => '0');
slv_reg71 <= (others => '0');
slv_reg72 <= (others => '0');
slv_reg73 <= (others => '0');
slv_reg74 <= (others => '0');
slv_reg75 <= (others => '0');
slv_reg76 <= (others => '0');
slv_reg77 <= (others => '0');
slv_reg78 <= (others => '0');
slv_reg79 <= (others => '0');
slv_reg80 <= (others => '0');
slv_reg81 <= (others => '0');
slv_reg82 <= (others => '0');
slv_reg83 <= (others => '0');
slv_reg84 <= (others => '0');
slv_reg85 <= (others => '0');
slv_reg86 <= (others => '0');
slv_reg87 <= (others => '0');
slv_reg88 <= (others => '0');
slv_reg89 <= (others => '0');
slv_reg90 <= (others => '0');
slv_reg91 <= (others => '0');
slv_reg92 <= (others => '0');
slv_reg93 <= (others => '0');
slv_reg94 <= (others => '0');
slv_reg95 <= (others => '0');
slv_reg96 <= (others => '0');
slv_reg97 <= (others => '0');
slv_reg98 <= (others => '0');
slv_reg99 <= (others => '0');
slv_reg100 <= (others => '0');
slv_reg101 <= (others => '0');
slv_reg102 <= (others => '0');
slv_reg103 <= (others => '0');
slv_reg104 <= (others => '0');
slv_reg105 <= (others => '0');
slv_reg106 <= (others => '0');
slv_reg107 <= (others => '0');
slv_reg108 <= (others => '0');
slv_reg109 <= (others => '0');
slv_reg110 <= (others => '0');
slv_reg111 <= (others => '0');
slv_reg112 <= (others => '0');
slv_reg113 <= (others => '0');
slv_reg114 <= (others => '0');
slv_reg115 <= (others => '0');
slv_reg116 <= (others => '0');
slv_reg117 <= (others => '0');
slv_reg118 <= (others => '0');
slv_reg119 <= (others => '0');
slv_reg120 <= (others => '0');
slv_reg121 <= (others => '0');
slv_reg122 <= (others => '0');
slv_reg123 <= (others => '0');
slv_reg124 <= (others => '0');
slv_reg125 <= (others => '0');
slv_reg126 <= (others => '0');
slv_reg127 <= (others => '0');
slv_reg128 <= (others => '0');
slv_reg129 <= (others => '0');
slv_reg130 <= (others => '0');
slv_reg131 <= (others => '0');
slv_reg132 <= (others => '0');
slv_reg133 <= (others => '0');
slv_reg134 <= (others => '0');
slv_reg135 <= (others => '0');
slv_reg136 <= (others => '0');
slv_reg137 <= (others => '0');
slv_reg138 <= (others => '0');
slv_reg139 <= (others => '0');
slv_reg140 <= (others => '0');
slv_reg141 <= (others => '0');
slv_reg142 <= (others => '0');
slv_reg143 <= (others => '0');
slv_reg144 <= (others => '0');
slv_reg145 <= (others => '0');
slv_reg146 <= (others => '0');
slv_reg147 <= (others => '0');
slv_reg148 <= (others => '0');
slv_reg149 <= (others => '0');
slv_reg150 <= (others => '0');
slv_reg151 <= (others => '0');
slv_reg152 <= (others => '0');
slv_reg153 <= (others => '0');
slv_reg154 <= (others => '0');
slv_reg155 <= (others => '0');
slv_reg156 <= (others => '0');
slv_reg157 <= (others => '0');
slv_reg158 <= (others => '0');
slv_reg159 <= (others => '0');
slv_reg160 <= (others => '0');
slv_reg161 <= (others => '0');
slv_reg162 <= (others => '0');
slv_reg163 <= (others => '0');
slv_reg164 <= (others => '0');
slv_reg165 <= (others => '0');
slv_reg166 <= (others => '0');
slv_reg167 <= (others => '0');
slv_reg168 <= (others => '0');
slv_reg169 <= (others => '0');
slv_reg170 <= (others => '0');
slv_reg171 <= (others => '0');
slv_reg172 <= (others => '0');
slv_reg173 <= (others => '0');
slv_reg174 <= (others => '0');
slv_reg175 <= (others => '0');
slv_reg176 <= (others => '0');
slv_reg177 <= (others => '0');
slv_reg178 <= (others => '0');
slv_reg179 <= (others => '0');
slv_reg180 <= (others => '0');
slv_reg181 <= (others => '0');
slv_reg182 <= (others => '0');
slv_reg183 <= (others => '0');
slv_reg184 <= (others => '0');
slv_reg185 <= (others => '0');
slv_reg186 <= (others => '0');
slv_reg187 <= (others => '0');
slv_reg188 <= (others => '0');
slv_reg189 <= (others => '0');
slv_reg190 <= (others => '0');
slv_reg191 <= (others => '0');
slv_reg192 <= (others => '0');
slv_reg193 <= (others => '0');
slv_reg194 <= (others => '0');
slv_reg195 <= (others => '0');
slv_reg196 <= (others => '0');
slv_reg197 <= (others => '0');
slv_reg198 <= (others => '0');
slv_reg199 <= (others => '0');
slv_reg200 <= (others => '0');
slv_reg201 <= (others => '0');
slv_reg202 <= (others => '0');
slv_reg203 <= (others => '0');
slv_reg204 <= (others => '0');
slv_reg205 <= (others => '0');
slv_reg206 <= (others => '0');
slv_reg207 <= (others => '0');
slv_reg208 <= (others => '0');
slv_reg209 <= (others => '0');
slv_reg210 <= (others => '0');
slv_reg211 <= (others => '0');
slv_reg212 <= (others => '0');
slv_reg213 <= (others => '0');
slv_reg214 <= (others => '0');
slv_reg215 <= (others => '0');
slv_reg216 <= (others => '0');
slv_reg217 <= (others => '0');
slv_reg218 <= (others => '0');
slv_reg219 <= (others => '0');
slv_reg220 <= (others => '0');
slv_reg221 <= (others => '0');
slv_reg222 <= (others => '0');
slv_reg223 <= (others => '0');
slv_reg224 <= (others => '0');
slv_reg225 <= (others => '0');
slv_reg226 <= (others => '0');
slv_reg227 <= (others => '0');
slv_reg228 <= (others => '0');
slv_reg229 <= (others => '0');
slv_reg230 <= (others => '0');
slv_reg231 <= (others => '0');
slv_reg232 <= (others => '0');
slv_reg233 <= (others => '0');
slv_reg234 <= (others => '0');
slv_reg235 <= (others => '0');
slv_reg236 <= (others => '0');
slv_reg237 <= (others => '0');
slv_reg238 <= (others => '0');
slv_reg239 <= (others => '0');
slv_reg240 <= (others => '0');
slv_reg241 <= (others => '0');
slv_reg242 <= (others => '0');
slv_reg243 <= (others => '0');
slv_reg244 <= (others => '0');
slv_reg245 <= (others => '0');
slv_reg246 <= (others => '0');
slv_reg247 <= (others => '0');
slv_reg248 <= (others => '0');
slv_reg249 <= (others => '0');
slv_reg250 <= (others => '0');
slv_reg251 <= (others => '0');
slv_reg252 <= (others => '0');
slv_reg253 <= (others => '0');
slv_reg254 <= (others => '0');
slv_reg255 <= (others => '0');
slv_reg256 <= (others => '0');
slv_reg257 <= (others => '0');
slv_reg258 <= (others => '0');
slv_reg259 <= (others => '0');
slv_reg260 <= (others => '0');
slv_reg261 <= (others => '0');
slv_reg262 <= (others => '0');
slv_reg263 <= (others => '0');
slv_reg264 <= (others => '0');
slv_reg265 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
--slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
--slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
--slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
--slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
--slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
--slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
--slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
--slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
-- slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 32
slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 33
slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 34
slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 35
slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 36
slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 37
slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 38
slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 39
slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 40
slv_reg40(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 41
slv_reg41(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 42
slv_reg42(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 43
slv_reg43(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 44
slv_reg44(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 45
slv_reg45(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 46
slv_reg46(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 47
slv_reg47(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 48
slv_reg48(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 49
slv_reg49(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 50
slv_reg50(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 51
slv_reg51(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 52
slv_reg52(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 53
slv_reg53(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 54
slv_reg54(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 55
slv_reg55(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 56
slv_reg56(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 57
slv_reg57(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 58
slv_reg58(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 59
slv_reg59(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 60
slv_reg60(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 61
slv_reg61(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 62
slv_reg62(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 63
slv_reg63(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 64
slv_reg64(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 65
slv_reg65(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 66
slv_reg66(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 67
slv_reg67(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 68
slv_reg68(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 69
slv_reg69(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 70
slv_reg70(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 71
slv_reg71(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 72
slv_reg72(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 73
slv_reg73(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 74
slv_reg74(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 75
slv_reg75(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 76
slv_reg76(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 77
slv_reg77(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 78
slv_reg78(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 79
slv_reg79(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 80
slv_reg80(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 81
slv_reg81(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 82
slv_reg82(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 83
slv_reg83(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 84
slv_reg84(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 85
slv_reg85(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 86
slv_reg86(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 87
slv_reg87(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 88
slv_reg88(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 89
slv_reg89(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 90
slv_reg90(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 91
slv_reg91(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 92
slv_reg92(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 93
slv_reg93(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 94
slv_reg94(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 95
slv_reg95(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 96
slv_reg96(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 97
slv_reg97(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 98
slv_reg98(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 99
slv_reg99(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 100
slv_reg100(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 101
slv_reg101(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 102
slv_reg102(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 103
slv_reg103(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 104
slv_reg104(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 105
slv_reg105(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 106
slv_reg106(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 107
slv_reg107(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 108
slv_reg108(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 109
slv_reg109(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 110
slv_reg110(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 111
slv_reg111(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 112
slv_reg112(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 113
slv_reg113(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 114
slv_reg114(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 115
slv_reg115(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 116
slv_reg116(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 117
slv_reg117(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 118
slv_reg118(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 119
slv_reg119(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 120
slv_reg120(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 121
slv_reg121(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 122
slv_reg122(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 123
slv_reg123(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 124
slv_reg124(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 125
slv_reg125(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 126
slv_reg126(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 127
slv_reg127(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 128
slv_reg128(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 129
slv_reg129(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 130
slv_reg130(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 131
slv_reg131(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 132
slv_reg132(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 133
slv_reg133(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 134
slv_reg134(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 135
slv_reg135(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 136
slv_reg136(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 137
slv_reg137(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 138
slv_reg138(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 139
slv_reg139(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 140
slv_reg140(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 141
slv_reg141(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 142
slv_reg142(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 143
slv_reg143(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 144
slv_reg144(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 145
slv_reg145(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 146
slv_reg146(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 147
slv_reg147(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 148
slv_reg148(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 149
slv_reg149(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 150
slv_reg150(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 151
slv_reg151(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 152
slv_reg152(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 153
slv_reg153(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 154
slv_reg154(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 155
slv_reg155(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 156
slv_reg156(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 157
slv_reg157(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 158
slv_reg158(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 159
slv_reg159(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 160
slv_reg160(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 161
slv_reg161(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 162
slv_reg162(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 163
slv_reg163(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 164
slv_reg164(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 165
slv_reg165(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 166
slv_reg166(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 167
slv_reg167(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 168
slv_reg168(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 169
slv_reg169(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 170
slv_reg170(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 171
slv_reg171(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 172
slv_reg172(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 173
slv_reg173(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 174
slv_reg174(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 175
slv_reg175(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 176
slv_reg176(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 177
slv_reg177(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 178
slv_reg178(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 179
slv_reg179(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 180
slv_reg180(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 181
slv_reg181(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 182
slv_reg182(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 183
slv_reg183(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 184
slv_reg184(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 185
slv_reg185(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 186
slv_reg186(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 187
slv_reg187(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 188
slv_reg188(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 189
slv_reg189(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 190
slv_reg190(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 191
slv_reg191(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 192
slv_reg192(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 193
slv_reg193(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 194
slv_reg194(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 195
slv_reg195(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 196
slv_reg196(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 197
slv_reg197(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 198
slv_reg198(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 199
slv_reg199(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 200
slv_reg200(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 201
slv_reg201(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 202
slv_reg202(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 203
slv_reg203(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 204
slv_reg204(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 205
slv_reg205(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 206
slv_reg206(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011001111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 207
slv_reg207(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 208
slv_reg208(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 209
slv_reg209(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 210
slv_reg210(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 211
slv_reg211(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 212
slv_reg212(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 213
slv_reg213(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 214
slv_reg214(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011010111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 215
slv_reg215(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 216
slv_reg216(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 217
slv_reg217(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 218
slv_reg218(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 219
slv_reg219(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 220
slv_reg220(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 221
slv_reg221(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 222
slv_reg222(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011011111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 223
slv_reg223(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 224
slv_reg224(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 225
slv_reg225(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 226
slv_reg226(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 227
slv_reg227(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 228
slv_reg228(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 229
slv_reg229(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 230
slv_reg230(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011100111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 231
slv_reg231(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 232
slv_reg232(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 233
slv_reg233(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 234
slv_reg234(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 235
slv_reg235(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 236
slv_reg236(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 237
slv_reg237(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 238
slv_reg238(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011101111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 239
slv_reg239(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 240
slv_reg240(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 241
slv_reg241(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 242
slv_reg242(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 243
slv_reg243(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 244
slv_reg244(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 245
slv_reg245(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 246
slv_reg246(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011110111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 247
slv_reg247(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 248
slv_reg248(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 249
slv_reg249(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 250
slv_reg250(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 251
slv_reg251(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 252
slv_reg252(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 253
slv_reg253(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 254
slv_reg254(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011111111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 255
slv_reg255(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 256
slv_reg256(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 257
slv_reg257(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 258
slv_reg258(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 259
slv_reg259(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 260
slv_reg260(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 261
slv_reg261(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 262
slv_reg262(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100000111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 263
slv_reg263(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 264
slv_reg264(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100001001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 265
slv_reg265(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
-- slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
--slv_reg2 <= slv_reg2;
--slv_reg3 <= slv_reg3;
--slv_reg4 <= slv_reg4;
--slv_reg5 <= slv_reg5;
--slv_reg6 <= slv_reg6;
--slv_reg7 <= slv_reg7;
--slv_reg8 <= slv_reg8;
-- slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
slv_reg32 <= slv_reg32;
slv_reg33 <= slv_reg33;
slv_reg34 <= slv_reg34;
slv_reg35 <= slv_reg35;
slv_reg36 <= slv_reg36;
slv_reg37 <= slv_reg37;
slv_reg38 <= slv_reg38;
slv_reg39 <= slv_reg39;
slv_reg40 <= slv_reg40;
slv_reg41 <= slv_reg41;
slv_reg42 <= slv_reg42;
slv_reg43 <= slv_reg43;
slv_reg44 <= slv_reg44;
slv_reg45 <= slv_reg45;
slv_reg46 <= slv_reg46;
slv_reg47 <= slv_reg47;
slv_reg48 <= slv_reg48;
slv_reg49 <= slv_reg49;
slv_reg50 <= slv_reg50;
slv_reg51 <= slv_reg51;
slv_reg52 <= slv_reg52;
slv_reg53 <= slv_reg53;
slv_reg54 <= slv_reg54;
slv_reg55 <= slv_reg55;
slv_reg56 <= slv_reg56;
slv_reg57 <= slv_reg57;
slv_reg58 <= slv_reg58;
slv_reg59 <= slv_reg59;
slv_reg60 <= slv_reg60;
slv_reg61 <= slv_reg61;
slv_reg62 <= slv_reg62;
slv_reg63 <= slv_reg63;
slv_reg64 <= slv_reg64;
slv_reg65 <= slv_reg65;
slv_reg66 <= slv_reg66;
slv_reg67 <= slv_reg67;
slv_reg68 <= slv_reg68;
slv_reg69 <= slv_reg69;
slv_reg70 <= slv_reg70;
slv_reg71 <= slv_reg71;
slv_reg72 <= slv_reg72;
slv_reg73 <= slv_reg73;
slv_reg74 <= slv_reg74;
slv_reg75 <= slv_reg75;
slv_reg76 <= slv_reg76;
slv_reg77 <= slv_reg77;
slv_reg78 <= slv_reg78;
slv_reg79 <= slv_reg79;
slv_reg80 <= slv_reg80;
slv_reg81 <= slv_reg81;
slv_reg82 <= slv_reg82;
slv_reg83 <= slv_reg83;
slv_reg84 <= slv_reg84;
slv_reg85 <= slv_reg85;
slv_reg86 <= slv_reg86;
slv_reg87 <= slv_reg87;
slv_reg88 <= slv_reg88;
slv_reg89 <= slv_reg89;
slv_reg90 <= slv_reg90;
slv_reg91 <= slv_reg91;
slv_reg92 <= slv_reg92;
slv_reg93 <= slv_reg93;
slv_reg94 <= slv_reg94;
slv_reg95 <= slv_reg95;
slv_reg96 <= slv_reg96;
slv_reg97 <= slv_reg97;
slv_reg98 <= slv_reg98;
slv_reg99 <= slv_reg99;
slv_reg100 <= slv_reg100;
slv_reg101 <= slv_reg101;
slv_reg102 <= slv_reg102;
slv_reg103 <= slv_reg103;
slv_reg104 <= slv_reg104;
slv_reg105 <= slv_reg105;
slv_reg106 <= slv_reg106;
slv_reg107 <= slv_reg107;
slv_reg108 <= slv_reg108;
slv_reg109 <= slv_reg109;
slv_reg110 <= slv_reg110;
slv_reg111 <= slv_reg111;
slv_reg112 <= slv_reg112;
slv_reg113 <= slv_reg113;
slv_reg114 <= slv_reg114;
slv_reg115 <= slv_reg115;
slv_reg116 <= slv_reg116;
slv_reg117 <= slv_reg117;
slv_reg118 <= slv_reg118;
slv_reg119 <= slv_reg119;
slv_reg120 <= slv_reg120;
slv_reg121 <= slv_reg121;
slv_reg122 <= slv_reg122;
slv_reg123 <= slv_reg123;
slv_reg124 <= slv_reg124;
slv_reg125 <= slv_reg125;
slv_reg126 <= slv_reg126;
slv_reg127 <= slv_reg127;
slv_reg128 <= slv_reg128;
slv_reg129 <= slv_reg129;
slv_reg130 <= slv_reg130;
slv_reg131 <= slv_reg131;
slv_reg132 <= slv_reg132;
slv_reg133 <= slv_reg133;
slv_reg134 <= slv_reg134;
slv_reg135 <= slv_reg135;
slv_reg136 <= slv_reg136;
slv_reg137 <= slv_reg137;
slv_reg138 <= slv_reg138;
slv_reg139 <= slv_reg139;
slv_reg140 <= slv_reg140;
slv_reg141 <= slv_reg141;
slv_reg142 <= slv_reg142;
slv_reg143 <= slv_reg143;
slv_reg144 <= slv_reg144;
slv_reg145 <= slv_reg145;
slv_reg146 <= slv_reg146;
slv_reg147 <= slv_reg147;
slv_reg148 <= slv_reg148;
slv_reg149 <= slv_reg149;
slv_reg150 <= slv_reg150;
slv_reg151 <= slv_reg151;
slv_reg152 <= slv_reg152;
slv_reg153 <= slv_reg153;
slv_reg154 <= slv_reg154;
slv_reg155 <= slv_reg155;
slv_reg156 <= slv_reg156;
slv_reg157 <= slv_reg157;
slv_reg158 <= slv_reg158;
slv_reg159 <= slv_reg159;
slv_reg160 <= slv_reg160;
slv_reg161 <= slv_reg161;
slv_reg162 <= slv_reg162;
slv_reg163 <= slv_reg163;
slv_reg164 <= slv_reg164;
slv_reg165 <= slv_reg165;
slv_reg166 <= slv_reg166;
slv_reg167 <= slv_reg167;
slv_reg168 <= slv_reg168;
slv_reg169 <= slv_reg169;
slv_reg170 <= slv_reg170;
slv_reg171 <= slv_reg171;
slv_reg172 <= slv_reg172;
slv_reg173 <= slv_reg173;
slv_reg174 <= slv_reg174;
slv_reg175 <= slv_reg175;
slv_reg176 <= slv_reg176;
slv_reg177 <= slv_reg177;
slv_reg178 <= slv_reg178;
slv_reg179 <= slv_reg179;
slv_reg180 <= slv_reg180;
slv_reg181 <= slv_reg181;
slv_reg182 <= slv_reg182;
slv_reg183 <= slv_reg183;
slv_reg184 <= slv_reg184;
slv_reg185 <= slv_reg185;
slv_reg186 <= slv_reg186;
slv_reg187 <= slv_reg187;
slv_reg188 <= slv_reg188;
slv_reg189 <= slv_reg189;
slv_reg190 <= slv_reg190;
slv_reg191 <= slv_reg191;
slv_reg192 <= slv_reg192;
slv_reg193 <= slv_reg193;
slv_reg194 <= slv_reg194;
slv_reg195 <= slv_reg195;
slv_reg196 <= slv_reg196;
slv_reg197 <= slv_reg197;
slv_reg198 <= slv_reg198;
slv_reg199 <= slv_reg199;
slv_reg200 <= slv_reg200;
slv_reg201 <= slv_reg201;
slv_reg202 <= slv_reg202;
slv_reg203 <= slv_reg203;
slv_reg204 <= slv_reg204;
slv_reg205 <= slv_reg205;
slv_reg206 <= slv_reg206;
slv_reg207 <= slv_reg207;
slv_reg208 <= slv_reg208;
slv_reg209 <= slv_reg209;
slv_reg210 <= slv_reg210;
slv_reg211 <= slv_reg211;
slv_reg212 <= slv_reg212;
slv_reg213 <= slv_reg213;
slv_reg214 <= slv_reg214;
slv_reg215 <= slv_reg215;
slv_reg216 <= slv_reg216;
slv_reg217 <= slv_reg217;
slv_reg218 <= slv_reg218;
slv_reg219 <= slv_reg219;
slv_reg220 <= slv_reg220;
slv_reg221 <= slv_reg221;
slv_reg222 <= slv_reg222;
slv_reg223 <= slv_reg223;
slv_reg224 <= slv_reg224;
slv_reg225 <= slv_reg225;
slv_reg226 <= slv_reg226;
slv_reg227 <= slv_reg227;
slv_reg228 <= slv_reg228;
slv_reg229 <= slv_reg229;
slv_reg230 <= slv_reg230;
slv_reg231 <= slv_reg231;
slv_reg232 <= slv_reg232;
slv_reg233 <= slv_reg233;
slv_reg234 <= slv_reg234;
slv_reg235 <= slv_reg235;
slv_reg236 <= slv_reg236;
slv_reg237 <= slv_reg237;
slv_reg238 <= slv_reg238;
slv_reg239 <= slv_reg239;
slv_reg240 <= slv_reg240;
slv_reg241 <= slv_reg241;
slv_reg242 <= slv_reg242;
slv_reg243 <= slv_reg243;
slv_reg244 <= slv_reg244;
slv_reg245 <= slv_reg245;
slv_reg246 <= slv_reg246;
slv_reg247 <= slv_reg247;
slv_reg248 <= slv_reg248;
slv_reg249 <= slv_reg249;
slv_reg250 <= slv_reg250;
slv_reg251 <= slv_reg251;
slv_reg252 <= slv_reg252;
slv_reg253 <= slv_reg253;
slv_reg254 <= slv_reg254;
slv_reg255 <= slv_reg255;
slv_reg256 <= slv_reg256;
slv_reg257 <= slv_reg257;
slv_reg258 <= slv_reg258;
slv_reg259 <= slv_reg259;
slv_reg260 <= slv_reg260;
slv_reg261 <= slv_reg261;
slv_reg262 <= slv_reg262;
slv_reg263 <= slv_reg263;
slv_reg264 <= slv_reg264;
slv_reg265 <= slv_reg265;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, slv_reg40, slv_reg41, slv_reg42, slv_reg43, slv_reg44, slv_reg45, slv_reg46, slv_reg47, slv_reg48, slv_reg49, slv_reg50, slv_reg51, slv_reg52, slv_reg53, slv_reg54, slv_reg55, slv_reg56, slv_reg57, slv_reg58, slv_reg59, slv_reg60, slv_reg61, slv_reg62, slv_reg63, slv_reg64, slv_reg65, slv_reg66, slv_reg67, slv_reg68, slv_reg69, slv_reg70, slv_reg71, slv_reg72, slv_reg73, slv_reg74, slv_reg75, slv_reg76, slv_reg77, slv_reg78, slv_reg79, slv_reg80, slv_reg81, slv_reg82, slv_reg83, slv_reg84, slv_reg85, slv_reg86, slv_reg87, slv_reg88, slv_reg89, slv_reg90, slv_reg91, slv_reg92, slv_reg93, slv_reg94, slv_reg95, slv_reg96, slv_reg97, slv_reg98, slv_reg99, slv_reg100, slv_reg101, slv_reg102, slv_reg103, slv_reg104, slv_reg105, slv_reg106, slv_reg107, slv_reg108, slv_reg109, slv_reg110, slv_reg111, slv_reg112, slv_reg113, slv_reg114, slv_reg115, slv_reg116, slv_reg117, slv_reg118, slv_reg119, slv_reg120, slv_reg121, slv_reg122, slv_reg123, slv_reg124, slv_reg125, slv_reg126, slv_reg127, slv_reg128, slv_reg129, slv_reg130, slv_reg131, slv_reg132, slv_reg133, slv_reg134, slv_reg135, slv_reg136, slv_reg137, slv_reg138, slv_reg139, slv_reg140, slv_reg141, slv_reg142, slv_reg143, slv_reg144, slv_reg145, slv_reg146, slv_reg147, slv_reg148, slv_reg149, slv_reg150, slv_reg151, slv_reg152, slv_reg153, slv_reg154, slv_reg155, slv_reg156, slv_reg157, slv_reg158, slv_reg159, slv_reg160, slv_reg161, slv_reg162, slv_reg163, slv_reg164, slv_reg165, slv_reg166, slv_reg167, slv_reg168, slv_reg169, slv_reg170, slv_reg171, slv_reg172, slv_reg173, slv_reg174, slv_reg175, slv_reg176, slv_reg177, slv_reg178, slv_reg179, slv_reg180, slv_reg181, slv_reg182, slv_reg183, slv_reg184, slv_reg185, slv_reg186, slv_reg187, slv_reg188, slv_reg189, slv_reg190, slv_reg191, slv_reg192, slv_reg193, slv_reg194, slv_reg195, slv_reg196, slv_reg197, slv_reg198, slv_reg199, slv_reg200, slv_reg201, slv_reg202, slv_reg203, slv_reg204, slv_reg205, slv_reg206, slv_reg207, slv_reg208, slv_reg209, slv_reg210, slv_reg211, slv_reg212, slv_reg213, slv_reg214, slv_reg215, slv_reg216, slv_reg217, slv_reg218, slv_reg219, slv_reg220, slv_reg221, slv_reg222, slv_reg223, slv_reg224, slv_reg225, slv_reg226, slv_reg227, slv_reg228, slv_reg229, slv_reg230, slv_reg231, slv_reg232, slv_reg233, slv_reg234, slv_reg235, slv_reg236, slv_reg237, slv_reg238, slv_reg239, slv_reg240, slv_reg241, slv_reg242, slv_reg243, slv_reg244, slv_reg245, slv_reg246, slv_reg247, slv_reg248, slv_reg249, slv_reg250, slv_reg251, slv_reg252, slv_reg253, slv_reg254, slv_reg255, slv_reg256, slv_reg257, slv_reg258, slv_reg259, slv_reg260, slv_reg261, slv_reg262, slv_reg263, slv_reg264, slv_reg265, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when b"000000101" =>
reg_data_out <= slv_reg5;
when b"000000110" =>
reg_data_out <= slv_reg6;
when b"000000111" =>
reg_data_out <= slv_reg7;
when b"000001000" =>
reg_data_out <= slv_reg8;
when b"000001001" =>
reg_data_out <= slv_reg9;
when b"000001010" =>
reg_data_out <= slv_reg10;
when b"000001011" =>
reg_data_out <= slv_reg11;
when b"000001100" =>
reg_data_out <= slv_reg12;
when b"000001101" =>
reg_data_out <= slv_reg13;
when b"000001110" =>
reg_data_out <= slv_reg14;
when b"000001111" =>
reg_data_out <= slv_reg15;
when b"000010000" =>
reg_data_out <= slv_reg16;
when b"000010001" =>
reg_data_out <= slv_reg17;
when b"000010010" =>
reg_data_out <= slv_reg18;
when b"000010011" =>
reg_data_out <= slv_reg19;
when b"000010100" =>
reg_data_out <= slv_reg20;
when b"000010101" =>
reg_data_out <= slv_reg21;
when b"000010110" =>
reg_data_out <= slv_reg22;
when b"000010111" =>
reg_data_out <= slv_reg23;
when b"000011000" =>
reg_data_out <= slv_reg24;
when b"000011001" =>
reg_data_out <= slv_reg25;
when b"000011010" =>
reg_data_out <= slv_reg26;
when b"000011011" =>
reg_data_out <= slv_reg27;
when b"000011100" =>
reg_data_out <= slv_reg28;
when b"000011101" =>
reg_data_out <= slv_reg29;
when b"000011110" =>
reg_data_out <= slv_reg30;
when b"000011111" =>
reg_data_out <= slv_reg31;
when b"000100000" =>
reg_data_out <= slv_reg32;
when b"000100001" =>
reg_data_out <= slv_reg33;
when b"000100010" =>
reg_data_out <= slv_reg34;
when b"000100011" =>
reg_data_out <= slv_reg35;
when b"000100100" =>
reg_data_out <= slv_reg36;
when b"000100101" =>
reg_data_out <= slv_reg37;
when b"000100110" =>
reg_data_out <= slv_reg38;
when b"000100111" =>
reg_data_out <= slv_reg39;
when b"000101000" =>
reg_data_out <= slv_reg40;
when b"000101001" =>
reg_data_out <= slv_reg41;
when b"000101010" =>
reg_data_out <= slv_reg42;
when b"000101011" =>
reg_data_out <= slv_reg43;
when b"000101100" =>
reg_data_out <= slv_reg44;
when b"000101101" =>
reg_data_out <= slv_reg45;
when b"000101110" =>
reg_data_out <= slv_reg46;
when b"000101111" =>
reg_data_out <= slv_reg47;
when b"000110000" =>
reg_data_out <= slv_reg48;
when b"000110001" =>
reg_data_out <= slv_reg49;
when b"000110010" =>
reg_data_out <= slv_reg50;
when b"000110011" =>
reg_data_out <= slv_reg51;
when b"000110100" =>
reg_data_out <= slv_reg52;
when b"000110101" =>
reg_data_out <= slv_reg53;
when b"000110110" =>
reg_data_out <= slv_reg54;
when b"000110111" =>
reg_data_out <= slv_reg55;
when b"000111000" =>
reg_data_out <= slv_reg56;
when b"000111001" =>
reg_data_out <= slv_reg57;
when b"000111010" =>
reg_data_out <= slv_reg58;
when b"000111011" =>
reg_data_out <= slv_reg59;
when b"000111100" =>
reg_data_out <= slv_reg60;
when b"000111101" =>
reg_data_out <= slv_reg61;
when b"000111110" =>
reg_data_out <= slv_reg62;
when b"000111111" =>
reg_data_out <= slv_reg63;
when b"001000000" =>
reg_data_out <= slv_reg64;
when b"001000001" =>
reg_data_out <= slv_reg65;
when b"001000010" =>
reg_data_out <= slv_reg66;
when b"001000011" =>
reg_data_out <= slv_reg67;
when b"001000100" =>
reg_data_out <= slv_reg68;
when b"001000101" =>
reg_data_out <= slv_reg69;
when b"001000110" =>
reg_data_out <= slv_reg70;
when b"001000111" =>
reg_data_out <= slv_reg71;
when b"001001000" =>
reg_data_out <= slv_reg72;
when b"001001001" =>
reg_data_out <= slv_reg73;
when b"001001010" =>
reg_data_out <= slv_reg74;
when b"001001011" =>
reg_data_out <= slv_reg75;
when b"001001100" =>
reg_data_out <= slv_reg76;
when b"001001101" =>
reg_data_out <= slv_reg77;
when b"001001110" =>
reg_data_out <= slv_reg78;
when b"001001111" =>
reg_data_out <= slv_reg79;
when b"001010000" =>
reg_data_out <= slv_reg80;
when b"001010001" =>
reg_data_out <= slv_reg81;
when b"001010010" =>
reg_data_out <= slv_reg82;
when b"001010011" =>
reg_data_out <= slv_reg83;
when b"001010100" =>
reg_data_out <= slv_reg84;
when b"001010101" =>
reg_data_out <= slv_reg85;
when b"001010110" =>
reg_data_out <= slv_reg86;
when b"001010111" =>
reg_data_out <= slv_reg87;
when b"001011000" =>
reg_data_out <= slv_reg88;
when b"001011001" =>
reg_data_out <= slv_reg89;
when b"001011010" =>
reg_data_out <= slv_reg90;
when b"001011011" =>
reg_data_out <= slv_reg91;
when b"001011100" =>
reg_data_out <= slv_reg92;
when b"001011101" =>
reg_data_out <= slv_reg93;
when b"001011110" =>
reg_data_out <= slv_reg94;
when b"001011111" =>
reg_data_out <= slv_reg95;
when b"001100000" =>
reg_data_out <= slv_reg96;
when b"001100001" =>
reg_data_out <= slv_reg97;
when b"001100010" =>
reg_data_out <= slv_reg98;
when b"001100011" =>
reg_data_out <= slv_reg99;
when b"001100100" =>
reg_data_out <= slv_reg100;
when b"001100101" =>
reg_data_out <= slv_reg101;
when b"001100110" =>
reg_data_out <= slv_reg102;
when b"001100111" =>
reg_data_out <= slv_reg103;
when b"001101000" =>
reg_data_out <= slv_reg104;
when b"001101001" =>
reg_data_out <= slv_reg105;
when b"001101010" =>
reg_data_out <= slv_reg106;
when b"001101011" =>
reg_data_out <= slv_reg107;
when b"001101100" =>
reg_data_out <= slv_reg108;
when b"001101101" =>
reg_data_out <= slv_reg109;
when b"001101110" =>
reg_data_out <= slv_reg110;
when b"001101111" =>
reg_data_out <= slv_reg111;
when b"001110000" =>
reg_data_out <= slv_reg112;
when b"001110001" =>
reg_data_out <= slv_reg113;
when b"001110010" =>
reg_data_out <= slv_reg114;
when b"001110011" =>
reg_data_out <= slv_reg115;
when b"001110100" =>
reg_data_out <= slv_reg116;
when b"001110101" =>
reg_data_out <= slv_reg117;
when b"001110110" =>
reg_data_out <= slv_reg118;
when b"001110111" =>
reg_data_out <= slv_reg119;
when b"001111000" =>
reg_data_out <= slv_reg120;
when b"001111001" =>
reg_data_out <= slv_reg121;
when b"001111010" =>
reg_data_out <= slv_reg122;
when b"001111011" =>
reg_data_out <= slv_reg123;
when b"001111100" =>
reg_data_out <= slv_reg124;
when b"001111101" =>
reg_data_out <= slv_reg125;
when b"001111110" =>
reg_data_out <= slv_reg126;
when b"001111111" =>
reg_data_out <= slv_reg127;
when b"010000000" =>
reg_data_out <= slv_reg128;
when b"010000001" =>
reg_data_out <= slv_reg129;
when b"010000010" =>
reg_data_out <= slv_reg130;
when b"010000011" =>
reg_data_out <= slv_reg131;
when b"010000100" =>
reg_data_out <= slv_reg132;
when b"010000101" =>
reg_data_out <= slv_reg133;
when b"010000110" =>
reg_data_out <= slv_reg134;
when b"010000111" =>
reg_data_out <= slv_reg135;
when b"010001000" =>
reg_data_out <= slv_reg136;
when b"010001001" =>
reg_data_out <= slv_reg137;
when b"010001010" =>
reg_data_out <= slv_reg138;
when b"010001011" =>
reg_data_out <= slv_reg139;
when b"010001100" =>
reg_data_out <= slv_reg140;
when b"010001101" =>
reg_data_out <= slv_reg141;
when b"010001110" =>
reg_data_out <= slv_reg142;
when b"010001111" =>
reg_data_out <= slv_reg143;
when b"010010000" =>
reg_data_out <= slv_reg144;
when b"010010001" =>
reg_data_out <= slv_reg145;
when b"010010010" =>
reg_data_out <= slv_reg146;
when b"010010011" =>
reg_data_out <= slv_reg147;
when b"010010100" =>
reg_data_out <= slv_reg148;
when b"010010101" =>
reg_data_out <= slv_reg149;
when b"010010110" =>
reg_data_out <= slv_reg150;
when b"010010111" =>
reg_data_out <= slv_reg151;
when b"010011000" =>
reg_data_out <= slv_reg152;
when b"010011001" =>
reg_data_out <= slv_reg153;
when b"010011010" =>
reg_data_out <= slv_reg154;
when b"010011011" =>
reg_data_out <= slv_reg155;
when b"010011100" =>
reg_data_out <= slv_reg156;
when b"010011101" =>
reg_data_out <= slv_reg157;
when b"010011110" =>
reg_data_out <= slv_reg158;
when b"010011111" =>
reg_data_out <= slv_reg159;
when b"010100000" =>
reg_data_out <= slv_reg160;
when b"010100001" =>
reg_data_out <= slv_reg161;
when b"010100010" =>
reg_data_out <= slv_reg162;
when b"010100011" =>
reg_data_out <= slv_reg163;
when b"010100100" =>
reg_data_out <= slv_reg164;
when b"010100101" =>
reg_data_out <= slv_reg165;
when b"010100110" =>
reg_data_out <= slv_reg166;
when b"010100111" =>
reg_data_out <= slv_reg167;
when b"010101000" =>
reg_data_out <= slv_reg168;
when b"010101001" =>
reg_data_out <= slv_reg169;
when b"010101010" =>
reg_data_out <= slv_reg170;
when b"010101011" =>
reg_data_out <= slv_reg171;
when b"010101100" =>
reg_data_out <= slv_reg172;
when b"010101101" =>
reg_data_out <= slv_reg173;
when b"010101110" =>
reg_data_out <= slv_reg174;
when b"010101111" =>
reg_data_out <= slv_reg175;
when b"010110000" =>
reg_data_out <= slv_reg176;
when b"010110001" =>
reg_data_out <= slv_reg177;
when b"010110010" =>
reg_data_out <= slv_reg178;
when b"010110011" =>
reg_data_out <= slv_reg179;
when b"010110100" =>
reg_data_out <= slv_reg180;
when b"010110101" =>
reg_data_out <= slv_reg181;
when b"010110110" =>
reg_data_out <= slv_reg182;
when b"010110111" =>
reg_data_out <= slv_reg183;
when b"010111000" =>
reg_data_out <= slv_reg184;
when b"010111001" =>
reg_data_out <= slv_reg185;
when b"010111010" =>
reg_data_out <= slv_reg186;
when b"010111011" =>
reg_data_out <= slv_reg187;
when b"010111100" =>
reg_data_out <= slv_reg188;
when b"010111101" =>
reg_data_out <= slv_reg189;
when b"010111110" =>
reg_data_out <= slv_reg190;
when b"010111111" =>
reg_data_out <= slv_reg191;
when b"011000000" =>
reg_data_out <= slv_reg192;
when b"011000001" =>
reg_data_out <= slv_reg193;
when b"011000010" =>
reg_data_out <= slv_reg194;
when b"011000011" =>
reg_data_out <= slv_reg195;
when b"011000100" =>
reg_data_out <= slv_reg196;
when b"011000101" =>
reg_data_out <= slv_reg197;
when b"011000110" =>
reg_data_out <= slv_reg198;
when b"011000111" =>
reg_data_out <= slv_reg199;
when b"011001000" =>
reg_data_out <= slv_reg200;
when b"011001001" =>
reg_data_out <= slv_reg201;
when b"011001010" =>
reg_data_out <= slv_reg202;
when b"011001011" =>
reg_data_out <= slv_reg203;
when b"011001100" =>
reg_data_out <= slv_reg204;
when b"011001101" =>
reg_data_out <= slv_reg205;
when b"011001110" =>
reg_data_out <= slv_reg206;
when b"011001111" =>
reg_data_out <= slv_reg207;
when b"011010000" =>
reg_data_out <= slv_reg208;
when b"011010001" =>
reg_data_out <= slv_reg209;
when b"011010010" =>
reg_data_out <= slv_reg210;
when b"011010011" =>
reg_data_out <= slv_reg211;
when b"011010100" =>
reg_data_out <= slv_reg212;
when b"011010101" =>
reg_data_out <= slv_reg213;
when b"011010110" =>
reg_data_out <= slv_reg214;
when b"011010111" =>
reg_data_out <= slv_reg215;
when b"011011000" =>
reg_data_out <= slv_reg216;
when b"011011001" =>
reg_data_out <= slv_reg217;
when b"011011010" =>
reg_data_out <= slv_reg218;
when b"011011011" =>
reg_data_out <= slv_reg219;
when b"011011100" =>
reg_data_out <= slv_reg220;
when b"011011101" =>
reg_data_out <= slv_reg221;
when b"011011110" =>
reg_data_out <= slv_reg222;
when b"011011111" =>
reg_data_out <= slv_reg223;
when b"011100000" =>
reg_data_out <= slv_reg224;
when b"011100001" =>
reg_data_out <= slv_reg225;
when b"011100010" =>
reg_data_out <= slv_reg226;
when b"011100011" =>
reg_data_out <= slv_reg227;
when b"011100100" =>
reg_data_out <= slv_reg228;
when b"011100101" =>
reg_data_out <= slv_reg229;
when b"011100110" =>
reg_data_out <= slv_reg230;
when b"011100111" =>
reg_data_out <= slv_reg231;
when b"011101000" =>
reg_data_out <= slv_reg232;
when b"011101001" =>
reg_data_out <= slv_reg233;
when b"011101010" =>
reg_data_out <= slv_reg234;
when b"011101011" =>
reg_data_out <= slv_reg235;
when b"011101100" =>
reg_data_out <= slv_reg236;
when b"011101101" =>
reg_data_out <= slv_reg237;
when b"011101110" =>
reg_data_out <= slv_reg238;
when b"011101111" =>
reg_data_out <= slv_reg239;
when b"011110000" =>
reg_data_out <= slv_reg240;
when b"011110001" =>
reg_data_out <= slv_reg241;
when b"011110010" =>
reg_data_out <= slv_reg242;
when b"011110011" =>
reg_data_out <= slv_reg243;
when b"011110100" =>
reg_data_out <= slv_reg244;
when b"011110101" =>
reg_data_out <= slv_reg245;
when b"011110110" =>
reg_data_out <= slv_reg246;
when b"011110111" =>
reg_data_out <= slv_reg247;
when b"011111000" =>
reg_data_out <= slv_reg248;
when b"011111001" =>
reg_data_out <= slv_reg249;
when b"011111010" =>
reg_data_out <= slv_reg250;
when b"011111011" =>
reg_data_out <= slv_reg251;
when b"011111100" =>
reg_data_out <= slv_reg252;
when b"011111101" =>
reg_data_out <= slv_reg253;
when b"011111110" =>
reg_data_out <= slv_reg254;
when b"011111111" =>
reg_data_out <= slv_reg255;
when b"100000000" =>
reg_data_out <= slv_reg256;
when b"100000001" =>
reg_data_out <= slv_reg257;
when b"100000010" =>
reg_data_out <= slv_reg258;
when b"100000011" =>
reg_data_out <= slv_reg259;
when b"100000100" =>
reg_data_out <= slv_reg260;
when b"100000101" =>
reg_data_out <= slv_reg261;
when b"100000110" =>
reg_data_out <= slv_reg262;
when b"100000111" =>
reg_data_out <= slv_reg263;
when b"100001000" =>
reg_data_out <= slv_reg264;
when b"100001001" =>
reg_data_out <= slv_reg265;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
memory(0)(0) <= slv_reg10;
memory(0)(1) <= slv_reg11;
memory(0)(2) <= slv_reg12;
memory(0)(3) <= slv_reg13;
memory(0)(4) <= slv_reg14;
memory(0)(5) <= slv_reg15;
memory(0)(6) <= slv_reg16;
memory(0)(7) <= slv_reg17;
memory(0)(8) <= slv_reg18;
memory(0)(9) <= slv_reg19;
memory(0)(10) <= slv_reg20;
memory(0)(11) <= slv_reg21;
memory(0)(12) <= slv_reg22;
memory(0)(13) <= slv_reg23;
memory(0)(14) <= slv_reg24;
memory(0)(15) <= slv_reg25;
memory(1)(0) <= slv_reg26;
memory(1)(1) <= slv_reg27;
memory(1)(2) <= slv_reg28;
memory(1)(3) <= slv_reg29;
memory(1)(4) <= slv_reg30;
memory(1)(5) <= slv_reg31;
memory(1)(6) <= slv_reg32;
memory(1)(7) <= slv_reg33;
memory(1)(8) <= slv_reg34;
memory(1)(9) <= slv_reg35;
memory(1)(10) <= slv_reg36;
memory(1)(11) <= slv_reg37;
memory(1)(12) <= slv_reg38;
memory(1)(13) <= slv_reg39;
memory(1)(14) <= slv_reg40;
memory(1)(15) <= slv_reg41;
memory(2)(0) <= slv_reg42;
memory(2)(1) <= slv_reg43;
memory(2)(2) <= slv_reg44;
memory(2)(3) <= slv_reg45;
memory(2)(4) <= slv_reg46;
memory(2)(5) <= slv_reg47;
memory(2)(6) <= slv_reg48;
memory(2)(7) <= slv_reg49;
memory(2)(8) <= slv_reg50;
memory(2)(9) <= slv_reg51;
memory(2)(10) <= slv_reg52;
memory(2)(11) <= slv_reg53;
memory(2)(12) <= slv_reg54;
memory(2)(13) <= slv_reg55;
memory(2)(14) <= slv_reg56;
memory(2)(15) <= slv_reg57;
memory(3)(0) <= slv_reg58;
memory(3)(1) <= slv_reg59;
memory(3)(2) <= slv_reg60;
memory(3)(3) <= slv_reg61;
memory(3)(4) <= slv_reg62;
memory(3)(5) <= slv_reg63;
memory(3)(6) <= slv_reg64;
memory(3)(7) <= slv_reg65;
memory(3)(8) <= slv_reg66;
memory(3)(9) <= slv_reg67;
memory(3)(10) <= slv_reg68;
memory(3)(11) <= slv_reg69;
memory(3)(12) <= slv_reg70;
memory(3)(13) <= slv_reg71;
memory(3)(14) <= slv_reg72;
memory(3)(15) <= slv_reg73;
memory(4)(0) <= slv_reg74;
memory(4)(1) <= slv_reg75;
memory(4)(2) <= slv_reg76;
memory(4)(3) <= slv_reg77;
memory(4)(4) <= slv_reg78;
memory(4)(5) <= slv_reg79;
memory(4)(6) <= slv_reg80;
memory(4)(7) <= slv_reg81;
memory(4)(8) <= slv_reg82;
memory(4)(9) <= slv_reg83;
memory(4)(10) <= slv_reg84;
memory(4)(11) <= slv_reg85;
memory(4)(12) <= slv_reg86;
memory(4)(13) <= slv_reg87;
memory(4)(14) <= slv_reg88;
memory(4)(15) <= slv_reg89;
memory(5)(0) <= slv_reg90;
memory(5)(1) <= slv_reg91;
memory(5)(2) <= slv_reg92;
memory(5)(3) <= slv_reg93;
memory(5)(4) <= slv_reg94;
memory(5)(5) <= slv_reg95;
memory(5)(6) <= slv_reg96;
memory(5)(7) <= slv_reg97;
memory(5)(8) <= slv_reg98;
memory(5)(9) <= slv_reg99;
memory(5)(10) <= slv_reg100;
memory(5)(11) <= slv_reg101;
memory(5)(12) <= slv_reg102;
memory(5)(13) <= slv_reg103;
memory(5)(14) <= slv_reg104;
memory(5)(15) <= slv_reg105;
memory(6)(0) <= slv_reg106;
memory(6)(1) <= slv_reg107;
memory(6)(2) <= slv_reg108;
memory(6)(3) <= slv_reg109;
memory(6)(4) <= slv_reg110;
memory(6)(5) <= slv_reg111;
memory(6)(6) <= slv_reg112;
memory(6)(7) <= slv_reg113;
memory(6)(8) <= slv_reg114;
memory(6)(9) <= slv_reg115;
memory(6)(10) <= slv_reg116;
memory(6)(11) <= slv_reg117;
memory(6)(12) <= slv_reg118;
memory(6)(13) <= slv_reg119;
memory(6)(14) <= slv_reg120;
memory(6)(15) <= slv_reg121;
memory(7)(0) <= slv_reg122;
memory(7)(1) <= slv_reg123;
memory(7)(2) <= slv_reg124;
memory(7)(3) <= slv_reg125;
memory(7)(4) <= slv_reg126;
memory(7)(5) <= slv_reg127;
memory(7)(6) <= slv_reg128;
memory(7)(7) <= slv_reg129;
memory(7)(8) <= slv_reg130;
memory(7)(9) <= slv_reg131;
memory(7)(10) <= slv_reg132;
memory(7)(11) <= slv_reg133;
memory(7)(12) <= slv_reg134;
memory(7)(13) <= slv_reg135;
memory(7)(14) <= slv_reg136;
memory(7)(15) <= slv_reg137;
memory(8)(0) <= slv_reg138;
memory(8)(1) <= slv_reg139;
memory(8)(2) <= slv_reg140;
memory(8)(3) <= slv_reg141;
memory(8)(4) <= slv_reg142;
memory(8)(5) <= slv_reg143;
memory(8)(6) <= slv_reg144;
memory(8)(7) <= slv_reg145;
memory(8)(8) <= slv_reg146;
memory(8)(9) <= slv_reg147;
memory(8)(10) <= slv_reg148;
memory(8)(11) <= slv_reg149;
memory(8)(12) <= slv_reg150;
memory(8)(13) <= slv_reg151;
memory(8)(14) <= slv_reg152;
memory(8)(15) <= slv_reg153;
memory(9)(0) <= slv_reg154;
memory(9)(1) <= slv_reg155;
memory(9)(2) <= slv_reg156;
memory(9)(3) <= slv_reg157;
memory(9)(4) <= slv_reg158;
memory(9)(5) <= slv_reg159;
memory(9)(6) <= slv_reg160;
memory(9)(7) <= slv_reg161;
memory(9)(8) <= slv_reg162;
memory(9)(9) <= slv_reg163;
memory(9)(10) <= slv_reg164;
memory(9)(11) <= slv_reg165;
memory(9)(12) <= slv_reg166;
memory(9)(13) <= slv_reg167;
memory(9)(14) <= slv_reg168;
memory(9)(15) <= slv_reg169;
memory(10)(0) <= slv_reg170;
memory(10)(1) <= slv_reg171;
memory(10)(2) <= slv_reg172;
memory(10)(3) <= slv_reg173;
memory(10)(4) <= slv_reg174;
memory(10)(5) <= slv_reg175;
memory(10)(6) <= slv_reg176;
memory(10)(7) <= slv_reg177;
memory(10)(8) <= slv_reg178;
memory(10)(9) <= slv_reg179;
memory(10)(10) <= slv_reg180;
memory(10)(11) <= slv_reg181;
memory(10)(12) <= slv_reg182;
memory(10)(13) <= slv_reg183;
memory(10)(14) <= slv_reg184;
memory(10)(15) <= slv_reg185;
memory(11)(0) <= slv_reg186;
memory(11)(1) <= slv_reg187;
memory(11)(2) <= slv_reg188;
memory(11)(3) <= slv_reg189;
memory(11)(4) <= slv_reg190;
memory(11)(5) <= slv_reg191;
memory(11)(6) <= slv_reg192;
memory(11)(7) <= slv_reg193;
memory(11)(8) <= slv_reg194;
memory(11)(9) <= slv_reg195;
memory(11)(10) <= slv_reg196;
memory(11)(11) <= slv_reg197;
memory(11)(12) <= slv_reg198;
memory(11)(13) <= slv_reg199;
memory(11)(14) <= slv_reg200;
memory(11)(15) <= slv_reg201;
memory(12)(0) <= slv_reg202;
memory(12)(1) <= slv_reg203;
memory(12)(2) <= slv_reg204;
memory(12)(3) <= slv_reg205;
memory(12)(4) <= slv_reg206;
memory(12)(5) <= slv_reg207;
memory(12)(6) <= slv_reg208;
memory(12)(7) <= slv_reg209;
memory(12)(8) <= slv_reg210;
memory(12)(9) <= slv_reg211;
memory(12)(10) <= slv_reg212;
memory(12)(11) <= slv_reg213;
memory(12)(12) <= slv_reg214;
memory(12)(13) <= slv_reg215;
memory(12)(14) <= slv_reg216;
memory(12)(15) <= slv_reg217;
memory(13)(0) <= slv_reg218;
memory(13)(1) <= slv_reg219;
memory(13)(2) <= slv_reg220;
memory(13)(3) <= slv_reg221;
memory(13)(4) <= slv_reg222;
memory(13)(5) <= slv_reg223;
memory(13)(6) <= slv_reg224;
memory(13)(7) <= slv_reg225;
memory(13)(8) <= slv_reg226;
memory(13)(9) <= slv_reg227;
memory(13)(10) <= slv_reg228;
memory(13)(11) <= slv_reg229;
memory(13)(12) <= slv_reg230;
memory(13)(13) <= slv_reg231;
memory(13)(14) <= slv_reg232;
memory(13)(15) <= slv_reg233;
memory(14)(0) <= slv_reg234;
memory(14)(1) <= slv_reg235;
memory(14)(2) <= slv_reg236;
memory(14)(3) <= slv_reg237;
memory(14)(4) <= slv_reg238;
memory(14)(5) <= slv_reg239;
memory(14)(6) <= slv_reg240;
memory(14)(7) <= slv_reg241;
memory(14)(8) <= slv_reg242;
memory(14)(9) <= slv_reg243;
memory(14)(10) <= slv_reg244;
memory(14)(11) <= slv_reg245;
memory(14)(12) <= slv_reg246;
memory(14)(13) <= slv_reg247;
memory(14)(14) <= slv_reg248;
memory(14)(15) <= slv_reg249;
memory(15)(0) <= slv_reg250;
memory(15)(1) <= slv_reg251;
memory(15)(2) <= slv_reg252;
memory(15)(3) <= slv_reg253;
memory(15)(4) <= slv_reg254;
memory(15)(5) <= slv_reg255;
memory(15)(6) <= slv_reg256;
memory(15)(7) <= slv_reg257;
memory(15)(8) <= slv_reg258;
memory(15)(9) <= slv_reg259;
memory(15)(10) <= slv_reg260;
memory(15)(11) <= slv_reg261;
memory(15)(12) <= slv_reg262;
memory(15)(13) <= slv_reg263;
memory(15)(14) <= slv_reg264;
memory(15)(15) <= slv_reg265;
process(clk)
variable x, y : unsigned(9 downto 0);
variable chunk_x, chunk_y, chunk_mapped_x, chunk_mapped_y : unsigned(9 downto 0);
variable chunk_index, chunk_mem_index : unsigned(3 downto 0);
begin
if rising_edge(clk) then
if active = '1' then
x := unsigned(x_addr_r);
y := unsigned(y_addr_r);
chunk_x := x srl 2;
chunk_y := y srl 2;
chunk_mapped_x := chunk_x - chunk_offset_x;
chunk_mapped_y := chunk_y - chunk_offset_y;
chunk_index(1 downto 0) := chunk_mapped_x(1 downto 0);
chunk_index(3 downto 2) := chunk_mapped_y(1 downto 0);
chunk_mem_index(1 downto 0) := x(1 downto 0);
chunk_mem_index(3 downto 2) := y(1 downto 0);
data_r(23 downto 0) <= memory(to_integer(chunk_index))(to_integer(chunk_mem_index));
if req_chunk = '0' then
if chunk_mapped_x(1 downto 0) = "00" then
req_chunk_x <= chunk_x - 1;
elsif chunk_mapped_x(1 downto 0) = "11" then
req_chunk_x <= chunk_x + 1;
end if;
if chunk_mapped_y(1 downto 0) = "00" then
req_chunk_y <= chunk_y - 1;
elsif chunk_mapped_y(1 downto 0) = "11" then
req_chunk_y <= chunk_y + 1;
end if;
if chunk_mapped_y(1 downto 0) = "00" or chunk_mapped_y(1 downto 0) = "11" or
chunk_mapped_x(1 downto 0) = "00" or chunk_mapped_x(1 downto 0) = "11" then
req_chunk <= '1';
end if;
end if;
if req_write(0) = '0' then
req_write(0) <= '1';
req_write_addr_0(9 downto 0) <= x_addr_w;
req_write_addr_0(19 downto 10) <= y_addr_w;
req_write_data_0(23 downto 0) <= data_w;
elsif req_write(1) = '0' then
req_write(1) <= '1';
req_write_addr_1(9 downto 0) <= x_addr_w;
req_write_addr_1(19 downto 10) <= y_addr_w;
req_write_data_1(23 downto 0) <= data_w;
elsif req_write(2) = '0' then
req_write(2) <= '1';
req_write_addr_2(9 downto 0) <= x_addr_w;
req_write_addr_2(19 downto 10) <= y_addr_w;
req_write_data_2(23 downto 0) <= data_w;
elsif req_write(3) = '0' then
req_write(3) <= '1';
req_write_addr_3(9 downto 0) <= x_addr_w;
req_write_addr_3(19 downto 10) <= y_addr_w;
req_write_data_3(23 downto 0) <= data_w;
end if;
end if;
end if;
end process;
process(S_AXI_ACLK)
variable control : std_logic_vector(1 downto 0) := "00";
begin
if rising_edge(S_AXI_ACLK) then
if slv_reg1(0) = '0' and busy = '0' then
-- idle
control := "00";
if req_write(0) = '1' then
slv_reg2 <= req_write_addr_0;
slv_reg3 <= req_write_data_0;
req_write(0) <= '0';
control := "01";
elsif req_write(1) = '1' then
slv_reg4 <= req_write_addr_1;
slv_reg5 <= req_write_data_1;
req_write(1) <= '0';
control := "01";
elsif req_write(2) = '1' then
slv_reg6 <= req_write_addr_2;
slv_reg7 <= req_write_data_2;
req_write(2) <= '0';
control := "01";
elsif req_write(3) = '1' then
slv_reg8 <= req_write_addr_3;
slv_reg9 <= req_write_data_3;
req_write(3) <= '0';
control := "01";
end if;
if req_chunk = '1' then
req_chunk <= '0';
slv_reg0(6) <= '1';
slv_reg0(16 downto 7) <= std_logic_vector(req_chunk_x);
slv_reg0(26 downto 17) <= std_logic_vector(req_chunk_y);
control := "01";
else
slv_reg0(6) <= '0';
end if;
if control = "01" then
slv_reg0(1 downto 0) <= control;
slv_reg0(5 downto 2) <= req_write;
busy <= '1';
end if;
end if;
if busy = '1' then
if slv_reg1(0) = '1' then
-- done, acknowledge
slv_reg0(1 downto 0) <= "10";
busy <= '0';
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
| mit | 467812ffa5f06f6683160f22bf7aa1f0 | 0.523638 | 3.465465 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/hdl/encoder_module_extended.vhd | 2 | 4,999 | -------------------------------------------------------------------------------
-- Title : Extended Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a quadrature decoder with a 16-bit counter and
-- encoder step time measurement to the internal bus system.
--
-- The normale encoder module is only able to count the number of encoder ticks
-- in a given timeframe. The extended module is able to also measure the time
-- between two ticks in the same direction.
-- If the direction changes or no tick is detected the value is 0xffff. Only
-- the last measurement is available and returned by a read operation.
--
-- Register map:
--
-- Offset | Register
-- -------+---------------
-- 0 | Ticks (16-bit)
-- 1 | Time between the last two ticks (16-bit)
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.encoder_module_pkg.all;
use work.quadrature_decoder_pkg.all;
use work.up_down_counter_pkg.all;
use work.input_capture_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module_extended is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
encoder_p : in encoder_type;
index_p : in std_logic; -- index can be used to reset the
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_module_extended;
-------------------------------------------------------------------------------
architecture behavioral of encoder_module_extended is
-- Base address converted to a logic vector for easier access.
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error (A and B lines changes at the same time), current not used
signal clk_capture : std_logic; -- Clock for input capture timer
signal counter : std_logic_vector(15 downto 0);
signal timer : std_logic_vector(15 downto 0);
type encoder_module_extended_type is record
counter : std_logic_vector(15 downto 0);
timer : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_module_extended_type := (
counter => (others => '0'),
timer => (others => '1'),
data_out => (others => '0'));
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, timer, r)
variable v : encoder_module_extended_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
v.timer := timer;
end if;
-- Check Bus Address (upper 14 (of 15) bits)
if bus_i.addr(14 downto 1) = BASE_ADDRESS_VECTOR(14 downto 1) then
if bus_i.re = '1' then
-- Select by offset
if bus_i.addr(0) = '0' then
v.data_out := r.counter;
else
v.data_out := r.timer;
end if;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : quadrature_decoder
port map (
encoder_p => encoder_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
-- clk = 50 MHz, divider = 10
-- => clk_capture = 5 MHz
--
-- 16-bit counter
-- => period = 2**16 / clk_capture = 0.0131s = 13.1ms
clock_divider_capture : clock_divider
generic map (
DIV => 10)
port map (
clk_out_p => clk_capture,
clk => clk);
input_capture_1 : input_capture
port map (
value_p => timer,
step_p => step,
dir_p => up_down,
clk_en_p => clk_capture,
clk => clk);
end behavioral;
| bsd-3-clause | 8b89127dcf488548fad799f970294784 | 0.518104 | 3.923862 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_2/UART_RX_CTRL.vhd | 2 | 2,891 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Vinayaka Jyothi
--
-- Create Date: 12:22:17 11/13/2016
-- Design Name:
-- Module Name: UART_RX_CTRL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_RX_CTRL is
port ( UART_RX : in STD_LOGIC;
CLK : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA : out STD_LOGIC := '0';
RESET_READ: in STD_LOGIC);
end UART_RX_CTRL;
architecture behavioral of UART_RX_CTRL is
constant FREQ : integer := 100000000; -- 100MHz Nexys4 CLK
constant BAUD : integer := 9600;
signal count : integer := 0;
constant sample_0: integer := 3 * FREQ/(BAUD*2)-1;
constant sample_1: integer := 5 * FREQ/(BAUD*2)-1;
constant sample_2: integer := 7 * FREQ/(BAUD*2)-1;
constant sample_3: integer := 9 * FREQ/(BAUD*2)-1;
constant sample_4: integer := 11 * FREQ/(BAUD*2)-1;
constant sample_5: integer := 13 * FREQ/(BAUD*2)-1;
constant sample_6: integer := 15 * FREQ/(BAUD*2)-1;
constant sample_7: integer := 17 * FREQ/(BAUD*2)-1;
constant stop_bit: integer := 19 * FREQ/(BAUD*2)-1;
signal byte: std_logic_vector(7 downto 0) := (others => '0');
begin
rx_state_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (RESET_READ = '1') then
READ_DATA <= '0';
end if;
case count is
when sample_0 => byte <= UART_RX & byte(7 downto 1);
when sample_1 => byte <= UART_RX & byte(7 downto 1);
when sample_2 => byte <= UART_RX & byte(7 downto 1);
when sample_3 => byte <= UART_RX & byte(7 downto 1);
when sample_4 => byte <= UART_RX & byte(7 downto 1);
when sample_5 => byte <= UART_RX & byte(7 downto 1);
when sample_6 => byte <= UART_RX & byte(7 downto 1);
when sample_7 => byte <= UART_RX & byte(7 downto 1);
when stop_bit =>
if UART_RX = '1' then
DATA <= byte;
READ_DATA <= '1';
end if;
when others => null;
end case;
if count = stop_bit then
count <= 0;
elsif count = 0 then
if UART_RX = '0' then
count <= count + 1;
end if;
else
count <= count + 1;
end if;
end if;
end process;
end behavioral;
| mit | 1c475cefff1188bfa331954ccf52b5fd | 0.480111 | 3.808959 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/xp.vhd | 2 | 894 | library ieee;
use ieee.std_logic_1164.all;
entity xp is port
(
ri : in std_logic_vector(1 TO 32);
e : out std_logic_vector(1 TO 48));
end xp;
architecture behavior of xp is
begin
e(1)<=ri(32);e(2)<=ri(1); e(3)<=ri(2); e(4)<=ri(3); e(5)<=ri(4); e(6)<=ri(5);
e(7)<=ri(4); e(8)<=ri(5); e(9)<=ri(6); e(10)<=ri(7); e(11)<=ri(8);e(12)<=ri(9);
e(13)<=ri(8); e(14)<=ri(9);e(15)<=ri(10); e(16)<=ri(11); e(17)<=ri(12); e(18)<=ri(13);
e(19)<=ri(12); e(20)<=ri(13); e(21)<=ri(14); e(22)<=ri(15); e(23)<=ri(16); e(24)<=ri(17);
e(25)<=ri(16); e(26)<=ri(17); e(27)<=ri(18); e(28)<=ri(19); e(29)<=ri(20); e(30)<=ri(21);
e(31)<=ri(20); e(32)<=ri(21); e(33)<=ri(22); e(34)<=ri(23); e(35)<=ri(24); e(36)<=ri(25);
e(37)<=ri(24); e(38)<=ri(25); e(39)<=ri(26); e(40)<=ri(27); e(41)<=ri(28); e(42)<=ri(29);
e(43)<=ri(28); e(44)<=ri(29); e(45)<=ri(30); e(46)<=ri(31); e(47)<=ri(32); e(48)<=ri(1);
end behavior;
| mit | cc0b783c9e68b6b5b1d873bb26b0b2cd | 0.506711 | 1.918455 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ltc2351/tb/adc_ltc2351_model_tb.vhd | 2 | 1,661 | -------------------------------------------------------------------------------
-- Title : Testbench for simple ADC LTC2351 model
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Test the model of LTC2351, not self-checking.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-------------------------------------------------------------------------------
entity adc_ltc2351_model_tb is
end adc_ltc2351_model_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ltc2351_model_tb is
use work.adc_ltc2351_pkg.all;
-- Component generics
-- none
-- Component ports
signal sck_p : std_logic := '0';
signal sdo_p : std_logic := '0';
signal conv_p : std_logic := '0';
begin
-- component instantiation
MUT : adc_ltc2351_model
port map (
sck => sck_p,
conv => conv_p,
sdo => sdo_p
);
----------------------------------------------------------------------------
-- clock generation
sck_p <= not sck_p after 20 ns;
waveform : process
begin -- process waveform
-- single pulse of CONV to start conversion
wait for 160 ns;
conv_p <= '1';
wait for 80 ns;
conv_p <= '0';
wait for 10 ms;
end process waveform;
end tb;
| bsd-3-clause | 3877132e1eccdf5fe1b81bdc839e14cd | 0.38531 | 5.048632 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl | 3 | 3,203 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0_clock_splitter is
port (
clk_out : out STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clock_splitter_0_0_clock_splitter : entity is "clock_splitter";
end system_clock_splitter_0_0_clock_splitter;
architecture STRUCTURE of system_clock_splitter_0_0_clock_splitter is
signal clk_i_1_n_0 : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal last_edge : STD_LOGIC;
begin
clk_out <= \^clk_out\;
clk_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => latch_edge,
I1 => last_edge,
I2 => \^clk_out\,
O => clk_i_1_n_0
);
clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => clk_i_1_n_0,
Q => \^clk_out\,
R => '0'
);
last_edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => latch_edge,
Q => last_edge,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clock_splitter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_clock_splitter_0_0 : entity is "system_clock_splitter_0_0,clock_splitter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_clock_splitter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_clock_splitter_0_0 : entity is "clock_splitter,Vivado 2016.4";
end system_clock_splitter_0_0;
architecture STRUCTURE of system_clock_splitter_0_0 is
begin
U0: entity work.system_clock_splitter_0_0_clock_splitter
port map (
clk_in => clk_in,
clk_out => clk_out,
latch_edge => latch_edge
);
end STRUCTURE;
| mit | 0830a0d946d20f2002cac6784c185e98 | 0.622854 | 3.48531 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 19,093 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Sun Apr 09 10:19:58 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished_0 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
gclk : out STD_LOGIC;
href_0 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
resend_0 : in STD_LOGIC;
resend_1 : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_vs : out STD_LOGIC;
vsync_0 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_zed_vga_0_0 is
port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component system_zed_vga_0_0;
component system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_rgb888_to_rgb565_0_0;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal rgb888_to_rgb565_0_rgb_565 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zed_vga_0_vga_b : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zed_vga_0_vga_g : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zed_vga_0_vga_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_vga_sync_0_active_UNCONNECTED : STD_LOGIC;
begin
gclk <= processing_system7_0_FCLK_CLK0;
vga_b(3 downto 0) <= zed_vga_0_vga_b(3 downto 0);
vga_g(3 downto 0) <= zed_vga_0_vga_g(3 downto 0);
vga_hs <= vga_sync_0_hsync;
vga_r(3 downto 0) <= zed_vga_0_vga_r(3 downto 0);
vga_vs <= vga_sync_0_vsync;
config_finished_0 <= 'Z';
config_finished_1 <= 'Z';
sioc_0 <= 'Z';
sioc_1 <= 'Z';
xclk_0 <= 'Z';
xclk_1 <= 'Z';
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => processing_system7_0_FCLK_RESET0_N,
x_not => inverter_0_x_not
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
rgb888_to_rgb565_0: component system_rgb888_to_rgb565_0_0
port map (
rgb_565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
rgb_888(23 downto 0) => vga_color_test_0_rgb(23 downto 0)
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => clk_wiz_0_clk_out1,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => NLW_vga_sync_0_active_UNCONNECTED,
clk_25 => clk_wiz_0_clk_out1,
hsync => vga_sync_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zed_vga_0: component system_zed_vga_0_0
port map (
rgb565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
vga_b(3 downto 0) => zed_vga_0_vga_b(3 downto 0),
vga_g(3 downto 0) => zed_vga_0_vga_g(3 downto 0),
vga_r(3 downto 0) => zed_vga_0_vga_r(3 downto 0)
);
end STRUCTURE;
| mit | 62e715e46ddd9505c71c5580bd4125b2 | 0.661708 | 2.893756 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dotopnorm.vhd | 2 | 12,286 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity dotopnorm is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_params : in std_logic_vector((cmdreg_data_width -1) downto 0);
offset_result : in std_logic_vector((cmdreg_data_width -1) downto 0);
opflag_select : in std_logic_vector((opflag_width - 1) downto 0);
result1 : in std_logic_vector((sig_width - 1) downto 0);
result2 : in std_logic_vector((2*sig_width - 1) downto 0);
cmp_greater : in std_logic;
--@outputs;
dsp_bus : out t_dsp_bus
);
end dotopnorm;
--=----------------------------------------------------------------------------
architecture archi_dotopnorm of dotopnorm is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_state_pipe_depth : integer := c_dspmem_pipe_depth + 2;
constant c_dotopnorm_pipe_depth : integer := c_dspmem_pipe_depth + 6;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_dotopnorm_state is (st_init, st_load_param1, st_load_param2, st_startpipe, st_compute, st_getnorm, st_storenorm1, st_storenorm2);
signal s_state : t_dotopnorm_state;
type t_state_pipe is array(0 to c_state_pipe_depth - 1) of t_dotopnorm_state;
signal s_state_pipe : t_state_pipe;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_r : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_w : unsigned((cmdreg_width - 1) downto 0);
signal s_addr_w_offs : unsigned((cmdreg_width - 1) downto 0);
signal s_wr_en : std_logic;
signal s_data_a : std_logic_vector((sig_width - 1) downto 0);
signal s_data_b : std_logic_vector((sig_width - 1) downto 0);
signal s_param1 : std_logic_vector((sig_width - 1) downto 0);
signal s_param2 : std_logic_vector((sig_width - 1) downto 0);
signal s_muladd_mode : std_logic;
signal s_data_out : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_norm : std_logic_vector((2*sig_width - 1) downto 0);
signal s_wr_norm_en : std_logic;
begin -- archs_dotopnorm
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_dotopnorm : process (clk)
begin -- process p_dotopnorm
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
s_dsp_bus.op_done <= '0';
s_addr_r <= (others => '0');
s_addr_w <= (others => '0');
s_wr_en <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_addr_w <= (others => '0');
s_addr_r <= (others => '0');
s_wr_en <= '0';
s_wr_norm_en <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_load_param1;
s_addr_r <= unsigned(offset_params); -- addr to get first param
end if;
when st_load_param1 =>
s_addr_r <= unsigned(offset_params) + 1; -- addr to get second param
s_state <= st_load_param2;
when st_load_param2 =>
s_addr_r <= (others => '0'); -- init addr counter to start signal reading
s_state <= st_startpipe;
s_dsp_bus.acc_mode2 <= acc_reset;
when st_startpipe =>
if s_addr_r = c_dotopnorm_pipe_depth - 1 then
s_wr_en <= '1';
s_state <= st_compute;
end if;
if s_addr_r = c_dotopnorm_pipe_depth - 3 then
s_dsp_bus.acc_mode2 <= acc_abs;
end if;
s_addr_w <= (others => '0'); -- init addr counter to start signal write
-- index increment
s_addr_r <= s_addr_r + 1;
when st_compute =>
if(s_addr_w = s_length - 1) then
s_wr_en <= '0';
s_state <= st_getnorm;
else
s_addr_r <= s_addr_r + 1;
s_addr_w <= s_addr_w + 1; -- and s_length;
s_dsp_bus.acc_mode2 <= acc_abs;
s_wr_en <= '1';
end if;
when st_getnorm =>
s_norm <= result2;
s_state <= st_storenorm1;
s_addr_r <= unsigned(offset_params);
s_wr_norm_en <= opflag_select(opflagbit_l1norm);
when st_storenorm1 =>
s_state <= st_storenorm2;
s_addr_r <= unsigned(offset_params) + 1;
when st_storenorm2 =>
s_wr_en <= '0';
s_wr_norm_en <= '0';
s_state <= st_init;
s_dsp_bus.op_done <= '1';
when others => null;
end case;
end if;
end if;
end process p_dotopnorm;
p_data_select : process (clk)
begin -- process p_data_select
if rising_edge(clk) then -- rising clock edge
case opflag_select(opflagbit_srcm2 downto opflagbit_srcm0) is
when "011" =>
s_data_a <= data_in_m0;
s_data_b <= data_in_m1;
when "101" =>
s_data_a <= data_in_m0;
s_data_b <= data_in_m2;
when "110" =>
s_data_a <= data_in_m1;
s_data_b <= data_in_m2;
when others =>
s_data_a <= data_in_m0;
s_data_b <= data_in_m1;
end case;
end if;
end process p_data_select;
p_out_select : process (clk)
begin -- process p_out_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= '0';
s_dsp_bus.wr_en_m2 <= '0';
elsif opflag_select(opflagbit_m0) = '1' then
s_dsp_bus.wr_en_m0 <= s_wr_en;
s_dsp_bus.wr_en_m1 <= s_wr_norm_en and opflag_select(opflagbit_srcm1);
s_dsp_bus.wr_en_m2 <= s_wr_norm_en and opflag_select(opflagbit_srcm2);
elsif opflag_select(opflagbit_m1) = '1' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= s_wr_en;
s_dsp_bus.wr_en_m2 <= s_wr_norm_en;
elsif opflag_select(opflagbit_m2) = '1' then
s_dsp_bus.wr_en_m0 <= '0';
s_dsp_bus.wr_en_m1 <= s_wr_norm_en;
s_dsp_bus.wr_en_m2 <= s_wr_en;
end if;
end if;
end process p_out_select;
p_adr_select : process (clk)
begin -- process p_adr_select
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_dsp_bus.addr_r_m0 <= (others => '0');
s_dsp_bus.addr_w_m0 <= (others => '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.c_en_m0 <= '0';
s_dsp_bus.c_en_m1 <= '0';
s_dsp_bus.c_en_m2 <= '0';
else
s_dsp_bus.addr_w_m0 <= s_addr_w_offs;
s_dsp_bus.addr_r_m0 <= s_addr_r;
if opflag_select(opflagbit_srcm1) = '1' then
s_dsp_bus.addr_m1 <= s_addr_r;
else
s_dsp_bus.addr_m1 <= s_addr_w_offs;
end if;
if opflag_select(opflagbit_srcm2) = '1' then
s_dsp_bus.addr_m2 <= s_addr_r;
else
s_dsp_bus.addr_m2 <= s_addr_w_offs;
end if;
s_dsp_bus.c_en_m0 <= opflag_select(opflagbit_srcm0) or opflag_select(opflagbit_m0);
s_dsp_bus.c_en_m1 <= opflag_select(opflagbit_srcm1) or opflag_select(opflagbit_m1);
s_dsp_bus.c_en_m2 <= opflag_select(opflagbit_srcm2) or opflag_select(opflagbit_m2);
end if;
end if;
end process p_adr_select;
p_op_ctrl : process (clk)
begin -- process p_op_ctrl
if rising_edge(clk) then -- rising clock edge
if s_muladd_mode = '1' then
-- sum of the two mul outputs
s_dsp_bus.mul_in_a1 <= s_data_a;
s_dsp_bus.mul_in_a2 <= s_data_b;
s_dsp_bus.mul_in_b1 <= s_param1;
s_dsp_bus.mul_in_b2 <= s_param2;
s_dsp_bus.acc_mode1 <= acc_sumstore;
else
s_dsp_bus.mul_in_a1 <= s_data_a;
s_dsp_bus.mul_in_b1 <= s_data_b;
s_dsp_bus.mul_in_a2 <= (others => '0');
s_dsp_bus.mul_in_b2 <= (others => '0');
s_dsp_bus.acc_mode1 <= acc_store;
end if;
end if;
end process p_op_ctrl;
p_data_out : process (clk)
begin -- process p_data_out
if rising_edge(clk) then -- rising clock edge
s_dsp_bus.data_out_m0 <= s_data_out;
s_dsp_bus.data_out_m1 <= s_data_out;
s_dsp_bus.data_out_m2 <= s_data_out;
end if;
end process p_data_out;
p_pipe : process (clk)
begin -- process p_pipe
if rising_edge(clk) then -- rising clock edge
s_state_pipe(0) <= s_state;
for i in 0 to c_state_pipe_depth - 2 loop
s_state_pipe(i + 1) <= s_state_pipe(i);
end loop;
end if;
end process p_pipe;
p_load_params : process (clk)
begin -- process p_load_params
if rising_edge(clk) then -- rising clock edge
case s_state_pipe(c_state_pipe_depth - 1) is
when st_load_param1 => s_param1 <= s_data_b;
when st_load_param2 => s_param2 <= s_data_b;
when others => null;
end case;
end if;
end process p_load_params;
p_data_out_sel : process (s_state,result1)
begin -- process p_data_out_sel
case s_state is
when st_compute => s_data_out <= result1;
when st_storenorm1 => s_data_out <= s_norm((sig_width - 1) downto 0);
when st_storenorm2 => s_data_out <= s_norm((2*sig_width - 1) downto sig_width);
when others => s_data_out <= (others => '0');
end case;
end process p_data_out_sel;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
s_dsp_bus.alu_select <= alu_mul;
s_muladd_mode <= opflag_select(opflagbit_muladd);
s_addr_w_offs <= s_addr_w + unsigned(offset_result);
end archi_dotopnorm;
| gpl-3.0 | 7fe734a24b3f66096a1e1141cde48e54 | 0.493326 | 3.320541 | false | false | false | false |
loa-org/loa-hdl | modules/hdlc/hdl/hdlc_dec.vhd | 2 | 4,200 | -------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Decode 8-Bit HDLC Async framing int 8-Bit Data + Frame Delimiter
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x00 to 0x7C -> 0x000 to 0x007C
-- 0x7f to 0xff -> 0x07f to 0x0ff
-- 0x7e -> 0x1XX
-- 0x7D, 0x5E -> 0x07E
-- 0x7D, 0x5D -> 0x07D
--
-- Input port can't take in data while it outputs an escape sequence!
-- TODO add a busy signal for the input.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_dec is
port (
din_p : in hdlc_dec_in_type;
dout_p : out hdlc_dec_out_type;
clk : in std_logic);
end hdlc_dec;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_dec is
type hdlc_dec_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_dec_type is record
state : hdlc_dec_state_type;
strobe : std_logic;
dout : std_logic_vector(8 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_dec_type := (state => NOM, strobe => '0', dout => (others => '0'));
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_dec_type;
begin
v := r;
v.strobe := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data = x"7e" then
v.dout := "1" & x"00";
v.strobe := '1';
elsif din_p.data = x"7d" then
v.state := ESC;
else
v.dout := "0" & din_p.data;
v.strobe := '1';
end if;
end if;
when ESC =>
if din_p.enable = '1' then
v.dout := "0" & din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := NOM;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | 58786bcdba8dd0089b882f250fd32416 | 0.368333 | 4.805492 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/dc_motor_module_extended_tb.vhd | 2 | 3,325 | -------------------------------------------------------------------------------
-- Title : Testbench for design "dc_motor_module_extended"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity dc_motor_module_extended_tb is
end dc_motor_module_extended_tb;
-------------------------------------------------------------------------------
architecture tb of dc_motor_module_extended_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant WIDTH : positive := 8;
constant PRESCALER : positive := 2;
-- component ports
signal pwm1 : std_logic := '0';
signal pwm2 : std_logic := '0';
signal sd : std_logic := '1';
signal break : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : dc_motor_module_extended
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
pwm1_p => pwm1,
pwm2_p => pwm2,
sd_p => sd,
break_p => break,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
bus_waveform : process
begin
wait for 100 ns;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0101", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 150 us;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0101", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 200 us;
-- Disable PWM via break
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0101", bus_i.addr'length)));
bus_i.data <= x"80ff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait;
end process;
-- Test break signal
process
begin
wait for 220 us;
break <= '1';
wait for 30 us;
break <= '0';
end process;
end tb;
| bsd-3-clause | 4b0443421f3659586f113a8ab7cbd6ba | 0.457143 | 3.839492 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70,942 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:55 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 2431a8226d1621b9fc5b52021a43d018 | 0.532773 | 2.812592 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/synth/system_vga_color_test_0_0.vhd | 6 | 4,080 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_color_test:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_color_test_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_color_test_0_0;
ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_color_test IS
GENERIC (
H_SIZE : INTEGER;
V_SIZE : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_color_test;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "vga_color_test,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_color_test_0_0_arch : ARCHITECTURE IS "system_vga_color_test_0_0,vga_color_test,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "system_vga_color_test_0_0,vga_color_test,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_color_test,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,V_SIZE=480}";
BEGIN
U0 : vga_color_test
GENERIC MAP (
H_SIZE => 640,
V_SIZE => 480
)
PORT MAP (
clk_25 => clk_25,
xaddr => xaddr,
yaddr => yaddr,
rgb => rgb
);
END system_vga_color_test_0_0_arch;
| mit | 3ca314be9f6b7fee319ae039fc496fb4 | 0.726471 | 3.763838 | false | true | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl | 1 | 24,812 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:41:40 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_color_test_0_0 -prefix
-- system_vga_color_test_0_0_ system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
| mit | 299487f7a192b2210cf7b208b9cf1ee2 | 0.47606 | 2.484679 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/tb/imotor_sender_tb.vhd | 2 | 2,632 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_sender"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_sender_tb is
end entity imotor_sender_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_sender_tb is
-- component generics
-- Component ports
-- clock
signal clk : std_logic := '1';
signal clock_s : imotor_timer_type;
signal imotor_input_s : imotor_input_type(1 downto 0) := (x"0403", x"0201");
signal data_tx_s : std_logic_vector(7 downto 0);
signal start_tx_s : std_logic;
signal busy_tx_s : std_logic;
signal txd_out_s : std_logic;
begin -- architecture behavourial
-- component instantiation
imotor_sender_1 : entity work.imotor_sender
generic map (
DATA_WORDS => 2,
DATA_WIDTH => 8)
port map (
data_in_p => imotor_input_s,
data_out_p => data_tx_s,
start_out_p => start_tx_s,
busy_in_p => busy_tx_s,
start_in_p => clock_s.send,
clk => clk);
imotor_timer_1 : imotor_timer
generic map (
CLOCK => 50E6,
BAUD => 10E6,
SEND_FREQUENCY => 1E5)
port map (
clock_out_p => clock_s,
clk => clk);
imotor_uart_tx_1 : entity work.imotor_uart_tx
generic map (
START_BITS => 1,
DATA_BITS => 8,
STOP_BITS => 1,
PARITY => None)
port map (
data_in_p => data_tx_s,
start_in_p => start_tx_s,
busy_out_p => busy_tx_s,
txd_out_p => txd_out_s,
clock_tx_in_p => clock_s.tx,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
wait until false;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | 14edfb02843de96232e81c2b610bc91e | 0.43579 | 4.300654 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/sim/system_affine_transform_0_1.vhd | 1 | 3,774 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:affine_transform:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_affine_transform_0_1 IS
PORT (
a00 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_affine_transform_0_1;
ARCHITECTURE system_affine_transform_0_1_arch OF system_affine_transform_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_affine_transform_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT affine_block_wrapper IS
PORT (
a00 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT affine_block_wrapper;
BEGIN
U0 : affine_block_wrapper
PORT MAP (
a00 => a00,
a01 => a01,
a10 => a10,
a11 => a11,
x_in => x_in,
x_out => x_out,
y_in => y_in,
y_out => y_out
);
END system_affine_transform_0_1_arch;
| mit | 789e2488d6cbea3b4b5cb45338953771 | 0.713037 | 3.774 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/symmetric_pwm.vhd | 2 | 3,874 | -------------------------------------------------------------------------------
-- Title : Symmetric PWM generator
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a center aligned PWM with deadtime. The deadtime and register width
-- can be changed by generics.
--
-- PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--
-- Example:
-- clk = 50 MHz
-- clk_en = constant '1' (no prescaler)
-- width = 8 => value = 0..255
--
-- => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package symmetric_pwm_pkg is
component symmetric_pwm is
generic (
WIDTH : natural);
port (
pwm_p : out std_logic;
underflow_p : out std_logic;
overflow_p : out std_logic;
clk_en_p : in std_logic;
value_p : in std_logic_vector (WIDTH - 1 downto 0);
reset : in std_logic;
clk : in std_logic);
end component symmetric_pwm;
end package symmetric_pwm_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity symmetric_pwm is
generic (
WIDTH : natural := 12); -- Number of bits used for the PWM (12bit => 0..4095)
port (
pwm_p : out std_logic; -- PWM output
underflow_p : out std_logic; -- PWM is in the middle of the 'on'-periode
overflow_p : out std_logic; -- PWM is in the middle of the 'off'-periode
clk_en_p : in std_logic; -- clock enable
value_p : in std_logic_vector (WIDTH - 1 downto 0);
reset : in std_logic; -- High active, Restarts the PWM period
clk : in std_logic
);
end symmetric_pwm;
-- ----------------------------------------------------------------------------
architecture behavioral of symmetric_pwm is
signal count : integer range 0 to ((2 ** WIDTH) - 2) := 0;
signal value_buf : std_logic_vector(width - 1 downto 0) := (others => '0');
signal dir : std_logic := '0'; -- 0 = up
begin
-- Counter
process
begin
wait until rising_edge(clk);
if reset = '1' then
-- Load new value and reset counter => restart periode
count <= 0;
value_buf <= value_p;
underflow_p <= '0';
overflow_p <= '0';
elsif clk_en_p = '1' then
underflow_p <= '0';
overflow_p <= '0';
-- counter
if (dir = '0') then -- up
if count < ((2 ** WIDTH) - 2) then
count <= count + 1;
else
dir <= '1';
count <= count - 1;
overflow_p <= '1';
-- Load new value from the shadow register (not active before
-- the next clock cycle)
value_buf <= value_p;
end if;
else -- down
if (count > 0) then
count <= count - 1;
else
dir <= '0';
count <= count + 1;
underflow_p <= '1';
end if;
end if;
end if;
end process;
-- Generate Output
process
begin
wait until rising_edge(clk);
if reset = '1' then
pwm_p <= '0';
else
-- comparator for the output
if count >= to_integer(unsigned(value_buf)) then
pwm_p <= '0';
else
pwm_p <= '1';
end if;
end if;
end process;
end behavioral;
| bsd-3-clause | 1e95116c6ceeb7d4d468545209af4f52 | 0.45302 | 4.073607 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_sim_netlist.vhdl | 1 | 21,910 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat Jun 03 23:38:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_overlay_0_0 -prefix
-- system_vga_overlay_0_0_ system_vga_overlay_0_0_sim_netlist.vhdl
-- Design : system_vga_overlay_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0_vga_overlay is
port (
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 20 downto 0 );
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
end system_vga_overlay_0_0_vga_overlay;
architecture STRUCTURE of system_vga_overlay_0_0_vga_overlay is
signal b_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal b_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal rgb0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb00_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb01_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rgb[11]_i_2_n_0\ : STD_LOGIC;
signal \rgb[11]_i_3_n_0\ : STD_LOGIC;
signal \rgb[11]_i_4_n_0\ : STD_LOGIC;
signal \rgb[11]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_2_n_0\ : STD_LOGIC;
signal \rgb[19]_i_3_n_0\ : STD_LOGIC;
signal \rgb[19]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_2_n_0\ : STD_LOGIC;
signal \rgb[3]_i_3_n_0\ : STD_LOGIC;
signal \rgb[3]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\b_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(0),
Q => b_0(0),
R => '0'
);
\b_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(1),
Q => b_0(1),
R => '0'
);
\b_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(2),
Q => b_0(2),
R => '0'
);
\b_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(3),
Q => b_0(3),
R => '0'
);
\b_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(4),
Q => b_0(4),
R => '0'
);
\b_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(5),
Q => b_0(5),
R => '0'
);
\b_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(6),
Q => b_0(6),
R => '0'
);
\b_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(0),
Q => b_1(0),
R => '0'
);
\b_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(1),
Q => b_1(1),
R => '0'
);
\b_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(2),
Q => b_1(2),
R => '0'
);
\b_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(3),
Q => b_1(3),
R => '0'
);
\b_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(4),
Q => b_1(4),
R => '0'
);
\b_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(5),
Q => b_1(5),
R => '0'
);
\b_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(6),
Q => b_1(6),
R => '0'
);
\g_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(7),
Q => g_0(0),
R => '0'
);
\g_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(8),
Q => g_0(1),
R => '0'
);
\g_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(9),
Q => g_0(2),
R => '0'
);
\g_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(10),
Q => g_0(3),
R => '0'
);
\g_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(11),
Q => g_0(4),
R => '0'
);
\g_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(12),
Q => g_0(5),
R => '0'
);
\g_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(13),
Q => g_0(6),
R => '0'
);
\g_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(7),
Q => g_1(0),
R => '0'
);
\g_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(8),
Q => g_1(1),
R => '0'
);
\g_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(9),
Q => g_1(2),
R => '0'
);
\g_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(10),
Q => g_1(3),
R => '0'
);
\g_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(11),
Q => g_1(4),
R => '0'
);
\g_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(12),
Q => g_1(5),
R => '0'
);
\g_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(13),
Q => g_1(6),
R => '0'
);
\r_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(14),
Q => r_0(0),
R => '0'
);
\r_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(15),
Q => r_0(1),
R => '0'
);
\r_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(16),
Q => r_0(2),
R => '0'
);
\r_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(17),
Q => r_0(3),
R => '0'
);
\r_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(18),
Q => r_0(4),
R => '0'
);
\r_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(19),
Q => r_0(5),
R => '0'
);
\r_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(20),
Q => r_0(6),
R => '0'
);
\r_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(14),
Q => r_1(0),
R => '0'
);
\r_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(15),
Q => r_1(1),
R => '0'
);
\r_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(16),
Q => r_1(2),
R => '0'
);
\r_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(17),
Q => r_1(3),
R => '0'
);
\r_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(18),
Q => r_1(4),
R => '0'
);
\r_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(19),
Q => r_1(5),
R => '0'
);
\r_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(20),
Q => r_1(6),
R => '0'
);
\rgb[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(3),
I1 => g_1(3),
O => \rgb[11]_i_2_n_0\
);
\rgb[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(2),
I1 => g_1(2),
O => \rgb[11]_i_3_n_0\
);
\rgb[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(1),
I1 => g_1(1),
O => \rgb[11]_i_4_n_0\
);
\rgb[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(0),
I1 => g_1(0),
O => \rgb[11]_i_5_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(6),
I1 => g_1(6),
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(5),
I1 => g_1(5),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(4),
I1 => g_1(4),
O => \rgb[15]_i_4_n_0\
);
\rgb[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(3),
I1 => r_1(3),
O => \rgb[19]_i_2_n_0\
);
\rgb[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(2),
I1 => r_1(2),
O => \rgb[19]_i_3_n_0\
);
\rgb[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(1),
I1 => r_1(1),
O => \rgb[19]_i_4_n_0\
);
\rgb[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(0),
I1 => r_1(0),
O => \rgb[19]_i_5_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(6),
I1 => r_1(6),
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(5),
I1 => r_1(5),
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(4),
I1 => r_1(4),
O => \rgb[23]_i_4_n_0\
);
\rgb[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(3),
I1 => b_1(3),
O => \rgb[3]_i_2_n_0\
);
\rgb[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(2),
I1 => b_1(2),
O => \rgb[3]_i_3_n_0\
);
\rgb[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(1),
I1 => b_1(1),
O => \rgb[3]_i_4_n_0\
);
\rgb[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(0),
I1 => b_1(0),
O => \rgb[3]_i_5_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(6),
I1 => b_1(6),
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(5),
I1 => b_1(5),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(4),
I1 => b_1(4),
O => \rgb[7]_i_4_n_0\
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[11]_i_1_n_0\,
CO(2) => \rgb_reg[11]_i_1_n_1\,
CO(1) => \rgb_reg[11]_i_1_n_2\,
CO(0) => \rgb_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => g_0(3 downto 0),
O(3 downto 0) => rgb00_out(3 downto 0),
S(3) => \rgb[11]_i_2_n_0\,
S(2) => \rgb[11]_i_3_n_0\,
S(1) => \rgb[11]_i_4_n_0\,
S(0) => \rgb[11]_i_5_n_0\
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[11]_i_1_n_0\,
CO(3) => rgb00_out(7),
CO(2) => \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[15]_i_1_n_2\,
CO(0) => \rgb_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => g_0(6 downto 4),
O(3) => \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb00_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[15]_i_2_n_0\,
S(1) => \rgb[15]_i_3_n_0\,
S(0) => \rgb[15]_i_4_n_0\
);
\rgb_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(0),
Q => rgb(16),
R => '0'
);
\rgb_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(1),
Q => rgb(17),
R => '0'
);
\rgb_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(2),
Q => rgb(18),
R => '0'
);
\rgb_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(3),
Q => rgb(19),
R => '0'
);
\rgb_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[19]_i_1_n_0\,
CO(2) => \rgb_reg[19]_i_1_n_1\,
CO(1) => \rgb_reg[19]_i_1_n_2\,
CO(0) => \rgb_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => r_0(3 downto 0),
O(3 downto 0) => rgb01_out(3 downto 0),
S(3) => \rgb[19]_i_2_n_0\,
S(2) => \rgb[19]_i_3_n_0\,
S(1) => \rgb[19]_i_4_n_0\,
S(0) => \rgb[19]_i_5_n_0\
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(4),
Q => rgb(20),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(5),
Q => rgb(21),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(6),
Q => rgb(22),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(7),
Q => rgb(23),
R => '0'
);
\rgb_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[19]_i_1_n_0\,
CO(3) => rgb01_out(7),
CO(2) => \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[23]_i_1_n_2\,
CO(0) => \rgb_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => r_0(6 downto 4),
O(3) => \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb01_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[23]_i_2_n_0\,
S(1) => \rgb[23]_i_3_n_0\,
S(0) => \rgb[23]_i_4_n_0\
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[3]_i_1_n_0\,
CO(2) => \rgb_reg[3]_i_1_n_1\,
CO(1) => \rgb_reg[3]_i_1_n_2\,
CO(0) => \rgb_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => b_0(3 downto 0),
O(3 downto 0) => rgb0(3 downto 0),
S(3) => \rgb[3]_i_2_n_0\,
S(2) => \rgb[3]_i_3_n_0\,
S(1) => \rgb[3]_i_4_n_0\,
S(0) => \rgb[3]_i_5_n_0\
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[3]_i_1_n_0\,
CO(3) => rgb0(7),
CO(2) => \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[7]_i_1_n_2\,
CO(0) => \rgb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => b_0(6 downto 4),
O(3) => \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb0(6 downto 4),
S(3) => '1',
S(2) => \rgb[7]_i_2_n_0\,
S(1) => \rgb[7]_i_3_n_0\,
S(0) => \rgb[7]_i_4_n_0\
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_overlay_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_overlay_0_0 : entity is "system_vga_overlay_0_0,vga_overlay,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_overlay_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_overlay_0_0 : entity is "vga_overlay,Vivado 2016.4";
end system_vga_overlay_0_0;
architecture STRUCTURE of system_vga_overlay_0_0 is
begin
U0: entity work.system_vga_overlay_0_0_vga_overlay
port map (
clk => clk,
rgb(23 downto 0) => rgb(23 downto 0),
rgb_0(20 downto 14) => rgb_0(23 downto 17),
rgb_0(13 downto 7) => rgb_0(15 downto 9),
rgb_0(6 downto 0) => rgb_0(7 downto 1),
rgb_1(20 downto 14) => rgb_1(23 downto 17),
rgb_1(13 downto 7) => rgb_1(15 downto 9),
rgb_1(6 downto 0) => rgb_1(7 downto 1)
);
end STRUCTURE;
| mit | 7a12c214f138c3034c121fb5d285b62d | 0.441853 | 2.580379 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/dc_driver_stage_converter_tb.vhd | 2 | 2,479 | -------------------------------------------------------------------------------
-- Title : Testbench for design "dc_driver_stage_converter"
-- Project :
-------------------------------------------------------------------------------
-- File : dc_driver_stage_converter_tb.vhd<2>
-- Author : Sascha <[email protected]>
-- Company :
-- Created : 2013-03-27
-- Last update: 2013-03-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-27 1.0 sascha Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity dc_driver_stage_converter_tb is
end entity dc_driver_stage_converter_tb;
-------------------------------------------------------------------------------
architecture tb of dc_driver_stage_converter_tb is
-- component ports
signal pwm1_in_p : std_logic;
signal pwm2_in_p : std_logic;
signal sd_in_p : std_logic;
signal dc_driver_stage_st_out_p : dc_driver_stage_st_type;
-- clock
signal Clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT: entity work.dc_driver_stage_converter
port map (
pwm1_in_p => pwm1_in_p,
pwm2_in_p => pwm2_in_p,
sd_in_p => sd_in_p,
dc_driver_stage_st_out_p => dc_driver_stage_st_out_p);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
wait until Clk = '1';
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration dc_driver_stage_converter_tb_tb_cfg of dc_driver_stage_converter_tb is
for tb
end for;
end dc_driver_stage_converter_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | 31a834300b38d1932c62b85e61a6dc01 | 0.410246 | 4.582255 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_split_controller_0_0/synth/system_vga_split_controller_0_0.vhd | 1 | 4,349 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_split_controller:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_split_controller_0_0 IS
PORT (
rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clock : IN STD_LOGIC;
hsync : IN STD_LOGIC;
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_vga_split_controller_0_0;
ARCHITECTURE system_vga_split_controller_0_0_arch OF system_vga_split_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_split_controller IS
GENERIC (
HALF_ROW : INTEGER
);
PORT (
rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clock : IN STD_LOGIC;
hsync : IN STD_LOGIC;
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT vga_split_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "vga_split_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_split_controller_0_0_arch : ARCHITECTURE IS "system_vga_split_controller_0_0,vga_split_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "system_vga_split_controller_0_0,vga_split_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_split_controller,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HALF_ROW=320}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clock: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : vga_split_controller
GENERIC MAP (
HALF_ROW => 320
)
PORT MAP (
rgb_0 => rgb_0,
rgb_1 => rgb_1,
clock => clock,
hsync => hsync,
rgb => rgb
);
END system_vga_split_controller_0_0_arch;
| mit | a859bd39aea57f0d265dfc8e099c8add | 0.733272 | 3.862345 | false | false | false | false |
loa-org/loa-hdl | modules/ir_rx/tb/ir_rx_module_tb.vhd | 2 | 3,983 | -------------------------------------------------------------------------------
-- Title : Testbench for design "ir_rx_module"
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_module_tb.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity ir_rx_module_tb is
end ir_rx_module_tb;
-------------------------------------------------------------------------------
architecture tb of ir_rx_module_tb is
-- component generics
constant BASE_ADDRESS_RESULTS : integer := 16#0800#;
constant BASE_ADDRESS_COEFS : integer := 16#0010#;
constant BASE_ADDRESS_TIMESTAMP : integer := 16#0100#;
-- component ports
signal adc_out_p : ir_rx_module_spi_out_type;
signal adc_in_p : ir_rx_module_spi_in_type := (others => (others => '0'));
signal sync_p : std_logic := '0';
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal done_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal clk_sample_en : std_logic := '0';
signal adc_values_test : std_logic_vector(13 downto 0) := (others => '0');
signal adc_values_test_signed : signed(13 downto 0) := (others => '0');
signal offset : signed(13 downto 0) := "10000000000000";
signal timestamp_s : timestamp_type := (others => '0');
-- clock
signal clk : std_logic := '1';
begin -- tb
ir_rx_module_1 : entity work.ir_rx_module
generic map (
BASE_ADDRESS_COEFS => BASE_ADDRESS_COEFS,
BASE_ADDRESS_RESULTS => BASE_ADDRESS_RESULTS,
BASE_ADDRESS_TIMESTAMP => BASE_ADDRESS_TIMESTAMP)
port map (
adc_o_p => adc_out_p,
adc_i_p => adc_in_p,
adc_values_o_p => open,
sync_o_p => sync_p,
bus_o_p => bus_o,
bus_i_p => bus_i,
done_o_p => done_p,
ack_i_p => ack_p,
clk_sample_en_i_p => clk_sample_en,
timestamp_i_p => timestamp_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
clk_sample_en <= '1';
wait until clk = '1';
-- do not repeat
wait;
end process WaveGen_Proc;
adc_values_test_signed <= signed(adc_values_test) - offset;
adc_proc : process
begin -- process adc_proc
wait until clk = '1';
adc_values_test <= "00000000000000";
wait until clk = '1';
adc_values_test <= "11111111111111";
wait until clk = '1';
adc_values_test <= "01111111111111";
wait until clk = '1';
adc_values_test <= "10000000000000";
-- do not repeat
wait;
end process adc_proc;
ack_proc : process
begin -- process ack_proc
ack_p <= '0';
wait for 90 us;
ack_p <= '1';
wait for 5 us;
ack_p <= '0';
end process ack_proc;
end tb;
| bsd-3-clause | 0c649c0300729ba41f57dc601bb7ef3a | 0.457695 | 3.951389 | false | true | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_banked_1r1w-rtl.vhdl | 1 | 4,578 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
library tech;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of cache_core_banked_1r1w is
constant assoc : natural := 2**log2_assoc;
constant banks : natural := 2**log2_banks;
type comb_type is record
tag_we : std_ulogic;
tag_wbanken : std_ulogic_vector(assoc-1 downto 0);
tag_waddr : std_ulogic_vector(index_bits-1 downto 0);
tag_wdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits downto 0);
tag_re : std_ulogic;
tag_rbanken : std_ulogic_vector(assoc-1 downto 0);
tag_raddr : std_ulogic_vector(index_bits-1 downto 0);
tag_rdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits downto 0);
data_we : std_ulogic;
data_wbanken : std_ulogic_vector(assoc*banks-1 downto 0);
data_waddr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_wdata : std_ulogic_vector2(assoc*banks-1 downto 0, word_bits-1 downto 0);
data_re : std_ulogic;
data_rbanken : std_ulogic_vector(assoc*banks-1 downto 0);
data_raddr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_rdata : std_ulogic_vector2(assoc*banks-1 downto 0, word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.tag_we <= we and wtagen;
c.tag_wbanken <= wway;
c.tag_waddr <= windex;
c.tag_re <= re and rtagen;
c.tag_rbanken <= rway;
c.tag_raddr <= rindex;
c.data_we <= we and wdataen;
c.data_waddr <= windex & woffset;
c.data_re <= re and rdataen;
c.data_raddr <= rindex & roffset;
way_loop : for n in assoc-1 downto 0 generate
tag_bit_loop : for m in tag_bits-1 downto 0 generate
c.tag_wdata(n, m) <= wtag(m);
rtag(n, m) <= c.tag_rdata(n, m);
end generate;
bank_loop : for m in banks-1 downto 0 generate
c.data_wbanken(n*banks+m) <= wway(n) and wbanken(m);
c.data_rbanken(n*banks+m) <= rway(n) and rbanken(m);
data_bit_loop : for p in word_bits-1 downto 0 generate
c.data_wdata(n*banks+m, p) <= wdata(m, p);
rdata(n, m, p) <= c.data_rdata(n*banks+m, p);
end generate;
end generate;
end generate;
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '0' =>
r <= r_init;
when '1' =>
r <= r_next;
when others =>
r <= r_x;
end case;
end if;
end process;
tag_sram : entity tech.syncram_banked_1r1w(rtl)
generic map (
addr_bits => index_bits,
word_bits => tag_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
we => c.tag_we,
wbanken => c.tag_wbanken,
waddr => c.tag_waddr,
wdata => c.tag_wdata,
re => c.tag_re,
rbanken => c.tag_rbanken,
raddr => c.tag_raddr,
rdata => c.tag_rdata
);
data_sram : entity tech.syncram_banked_1r1w(rtl)
generic map (
addr_bits => index_bits + offset_bits,
word_bits => word_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
we => c.data_we,
wbanken => c.data_wbanken,
waddr => c.data_waddr,
wdata => c.data_wdata,
re => c.data_re,
rbanken => c.data_rbanken,
raddr => c.data_raddr,
rdata => c.data_rdata
);
end;
| apache-2.0 | 7534c563a67941fb10d94a5449eff918 | 0.554391 | 3.429213 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl | 1 | 2,412 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:46:53 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0 is
port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_0_0 : entity is "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_0_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_0_0;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_565\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
\^rgb_565\(15 downto 0) <= rgb_565(15 downto 0);
rgb_888(23 downto 19) <= \^rgb_565\(15 downto 11);
rgb_888(18 downto 16) <= \^rgb_565\(15 downto 13);
rgb_888(15 downto 10) <= \^rgb_565\(10 downto 5);
rgb_888(9 downto 8) <= \^rgb_565\(10 downto 9);
rgb_888(7 downto 3) <= \^rgb_565\(4 downto 0);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
| mit | 0fe2f421769108338f47001ccc3eccd2 | 0.640547 | 3.373427 | false | false | false | false |
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