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lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_sim_netlist.vhdl | 1 | 3,213 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_sim_netlist.vhdl
-- Design : system_clock_splitter_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_1_0_clock_splitter is
port (
clk_out : out STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clock_splitter_1_0_clock_splitter : entity is "clock_splitter";
end system_clock_splitter_1_0_clock_splitter;
architecture STRUCTURE of system_clock_splitter_1_0_clock_splitter is
signal clk_i_1_n_0 : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal last_edge : STD_LOGIC;
begin
clk_out <= \^clk_out\;
clk_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => latch_edge,
I1 => last_edge,
I2 => \^clk_out\,
O => clk_i_1_n_0
);
clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => clk_i_1_n_0,
Q => \^clk_out\,
R => '0'
);
last_edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => latch_edge,
Q => last_edge,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_1_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clock_splitter_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_clock_splitter_1_0 : entity is "system_clock_splitter_1_0,clock_splitter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_clock_splitter_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_clock_splitter_1_0 : entity is "clock_splitter,Vivado 2016.4";
end system_clock_splitter_1_0;
architecture STRUCTURE of system_clock_splitter_1_0 is
begin
U0: entity work.system_clock_splitter_1_0_clock_splitter
port map (
clk_in => clk_in,
clk_out => clk_out,
latch_edge => latch_edge
);
end STRUCTURE;
| mit | dab8e2989e84ccf96acde14dcef03836 | 0.623405 | 3.48104 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/synth/system_util_vector_logic_0_0.vhd | 3 | 4,126 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY system_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_vector_logic_0_0;
ARCHITECTURE system_util_vector_logic_0_0_arch OF system_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_vector_logic_0_0_arch : ARCHITECTURE IS "system_util_vector_logic_0_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "system_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=and,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "and",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END system_util_vector_logic_0_0_arch;
| mit | 44213b805048441236fff299737c0f0d | 0.734367 | 3.774931 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_sim_netlist.vhdl | 1 | 158,108 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 20:55:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_g8_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0_rgb888_to_g8 is
port (
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rgb888_to_g8_0_0_rgb888_to_g8 : entity is "rgb888_to_g8";
end system_rgb888_to_g8_0_0_rgb888_to_g8;
architecture STRUCTURE of system_rgb888_to_g8_0_0_rgb888_to_g8 is
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal g810_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \g81__120_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_1\ : STD_LOGIC;
signal \g81__120_carry__0_n_2\ : STD_LOGIC;
signal \g81__120_carry__0_n_3\ : STD_LOGIC;
signal \g81__120_carry__0_n_4\ : STD_LOGIC;
signal \g81__120_carry__0_n_5\ : STD_LOGIC;
signal \g81__120_carry__0_n_6\ : STD_LOGIC;
signal \g81__120_carry__0_n_7\ : STD_LOGIC;
signal \g81__120_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_1\ : STD_LOGIC;
signal \g81__120_carry__1_n_2\ : STD_LOGIC;
signal \g81__120_carry__1_n_3\ : STD_LOGIC;
signal \g81__120_carry__1_n_4\ : STD_LOGIC;
signal \g81__120_carry__1_n_5\ : STD_LOGIC;
signal \g81__120_carry__1_n_6\ : STD_LOGIC;
signal \g81__120_carry__1_n_7\ : STD_LOGIC;
signal \g81__120_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_n_1\ : STD_LOGIC;
signal \g81__120_carry__2_n_3\ : STD_LOGIC;
signal \g81__120_carry__2_n_6\ : STD_LOGIC;
signal \g81__120_carry__2_n_7\ : STD_LOGIC;
signal \g81__120_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_1\ : STD_LOGIC;
signal \g81__120_carry_n_2\ : STD_LOGIC;
signal \g81__120_carry_n_3\ : STD_LOGIC;
signal \g81__120_carry_n_4\ : STD_LOGIC;
signal \g81__120_carry_n_5\ : STD_LOGIC;
signal \g81__120_carry_n_6\ : STD_LOGIC;
signal \g81__149_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_1\ : STD_LOGIC;
signal \g81__149_carry__0_n_2\ : STD_LOGIC;
signal \g81__149_carry__0_n_3\ : STD_LOGIC;
signal \g81__149_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_1\ : STD_LOGIC;
signal \g81__149_carry__1_n_2\ : STD_LOGIC;
signal \g81__149_carry__1_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_1\ : STD_LOGIC;
signal \g81__149_carry__2_n_2\ : STD_LOGIC;
signal \g81__149_carry__2_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_n_4\ : STD_LOGIC;
signal \g81__149_carry__2_n_5\ : STD_LOGIC;
signal \g81__149_carry__2_n_6\ : STD_LOGIC;
signal \g81__149_carry__2_n_7\ : STD_LOGIC;
signal \g81__149_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_1\ : STD_LOGIC;
signal \g81__149_carry__3_n_2\ : STD_LOGIC;
signal \g81__149_carry__3_n_3\ : STD_LOGIC;
signal \g81__149_carry__3_n_4\ : STD_LOGIC;
signal \g81__149_carry__3_n_5\ : STD_LOGIC;
signal \g81__149_carry__3_n_6\ : STD_LOGIC;
signal \g81__149_carry__3_n_7\ : STD_LOGIC;
signal \g81__149_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_2\ : STD_LOGIC;
signal \g81__149_carry__4_n_3\ : STD_LOGIC;
signal \g81__149_carry__4_n_5\ : STD_LOGIC;
signal \g81__149_carry__4_n_6\ : STD_LOGIC;
signal \g81__149_carry__4_n_7\ : STD_LOGIC;
signal \g81__149_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_1\ : STD_LOGIC;
signal \g81__149_carry_n_2\ : STD_LOGIC;
signal \g81__149_carry_n_3\ : STD_LOGIC;
signal \g81__206_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_1\ : STD_LOGIC;
signal \g81__206_carry__0_n_2\ : STD_LOGIC;
signal \g81__206_carry__0_n_3\ : STD_LOGIC;
signal \g81__206_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_1\ : STD_LOGIC;
signal \g81__206_carry__1_n_2\ : STD_LOGIC;
signal \g81__206_carry__1_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_1\ : STD_LOGIC;
signal \g81__206_carry__2_n_2\ : STD_LOGIC;
signal \g81__206_carry__2_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_n_4\ : STD_LOGIC;
signal \g81__206_carry__2_n_5\ : STD_LOGIC;
signal \g81__206_carry__2_n_6\ : STD_LOGIC;
signal \g81__206_carry__2_n_7\ : STD_LOGIC;
signal \g81__206_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_1\ : STD_LOGIC;
signal \g81__206_carry__3_n_2\ : STD_LOGIC;
signal \g81__206_carry__3_n_3\ : STD_LOGIC;
signal \g81__206_carry__3_n_4\ : STD_LOGIC;
signal \g81__206_carry__3_n_5\ : STD_LOGIC;
signal \g81__206_carry__3_n_6\ : STD_LOGIC;
signal \g81__206_carry__3_n_7\ : STD_LOGIC;
signal \g81__206_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_2\ : STD_LOGIC;
signal \g81__206_carry__4_n_3\ : STD_LOGIC;
signal \g81__206_carry__4_n_5\ : STD_LOGIC;
signal \g81__206_carry__4_n_6\ : STD_LOGIC;
signal \g81__206_carry__4_n_7\ : STD_LOGIC;
signal \g81__206_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_1\ : STD_LOGIC;
signal \g81__206_carry_n_2\ : STD_LOGIC;
signal \g81__206_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_1\ : STD_LOGIC;
signal \g81__22_carry__0_n_2\ : STD_LOGIC;
signal \g81__22_carry__0_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_n_4\ : STD_LOGIC;
signal \g81__22_carry__0_n_5\ : STD_LOGIC;
signal \g81__22_carry__0_n_6\ : STD_LOGIC;
signal \g81__22_carry__0_n_7\ : STD_LOGIC;
signal \g81__22_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_1\ : STD_LOGIC;
signal \g81__22_carry__1_n_2\ : STD_LOGIC;
signal \g81__22_carry__1_n_3\ : STD_LOGIC;
signal \g81__22_carry__1_n_4\ : STD_LOGIC;
signal \g81__22_carry__1_n_5\ : STD_LOGIC;
signal \g81__22_carry__1_n_6\ : STD_LOGIC;
signal \g81__22_carry__1_n_7\ : STD_LOGIC;
signal \g81__22_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_n_1\ : STD_LOGIC;
signal \g81__22_carry__2_n_3\ : STD_LOGIC;
signal \g81__22_carry__2_n_6\ : STD_LOGIC;
signal \g81__22_carry__2_n_7\ : STD_LOGIC;
signal \g81__22_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_1\ : STD_LOGIC;
signal \g81__22_carry_n_2\ : STD_LOGIC;
signal \g81__22_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry_n_4\ : STD_LOGIC;
signal \g81__22_carry_n_5\ : STD_LOGIC;
signal \g81__22_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_1\ : STD_LOGIC;
signal \g81__261_carry__0_n_2\ : STD_LOGIC;
signal \g81__261_carry__0_n_3\ : STD_LOGIC;
signal \g81__261_carry__0_n_4\ : STD_LOGIC;
signal \g81__261_carry__0_n_5\ : STD_LOGIC;
signal \g81__261_carry__0_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_n_7\ : STD_LOGIC;
signal \g81__261_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_1\ : STD_LOGIC;
signal \g81__261_carry__1_n_2\ : STD_LOGIC;
signal \g81__261_carry__1_n_3\ : STD_LOGIC;
signal \g81__261_carry__1_n_4\ : STD_LOGIC;
signal \g81__261_carry__1_n_5\ : STD_LOGIC;
signal \g81__261_carry__1_n_6\ : STD_LOGIC;
signal \g81__261_carry__1_n_7\ : STD_LOGIC;
signal \g81__261_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_n_1\ : STD_LOGIC;
signal \g81__261_carry__2_n_3\ : STD_LOGIC;
signal \g81__261_carry__2_n_6\ : STD_LOGIC;
signal \g81__261_carry__2_n_7\ : STD_LOGIC;
signal \g81__261_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_1\ : STD_LOGIC;
signal \g81__261_carry_n_2\ : STD_LOGIC;
signal \g81__261_carry_n_3\ : STD_LOGIC;
signal \g81__261_carry_n_4\ : STD_LOGIC;
signal \g81__261_carry_n_5\ : STD_LOGIC;
signal \g81__261_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry_n_7\ : STD_LOGIC;
signal \g81__301_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_1\ : STD_LOGIC;
signal \g81__301_carry__0_n_2\ : STD_LOGIC;
signal \g81__301_carry__0_n_3\ : STD_LOGIC;
signal \g81__301_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_1\ : STD_LOGIC;
signal \g81__301_carry__1_n_2\ : STD_LOGIC;
signal \g81__301_carry__1_n_3\ : STD_LOGIC;
signal \g81__301_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_1\ : STD_LOGIC;
signal \g81__301_carry__2_n_2\ : STD_LOGIC;
signal \g81__301_carry__2_n_3\ : STD_LOGIC;
signal \g81__301_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_1\ : STD_LOGIC;
signal \g81__301_carry__3_n_2\ : STD_LOGIC;
signal \g81__301_carry__3_n_3\ : STD_LOGIC;
signal \g81__301_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_1\ : STD_LOGIC;
signal \g81__301_carry__4_n_2\ : STD_LOGIC;
signal \g81__301_carry__4_n_3\ : STD_LOGIC;
signal \g81__301_carry__5_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_1\ : STD_LOGIC;
signal \g81__301_carry__5_n_2\ : STD_LOGIC;
signal \g81__301_carry__5_n_3\ : STD_LOGIC;
signal \g81__301_carry__6_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_n_1\ : STD_LOGIC;
signal \g81__301_carry__6_n_2\ : STD_LOGIC;
signal \g81__301_carry__6_n_3\ : STD_LOGIC;
signal \g81__301_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_1\ : STD_LOGIC;
signal \g81__301_carry_n_2\ : STD_LOGIC;
signal \g81__301_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_n_1\ : STD_LOGIC;
signal \g81__347_carry__0_n_2\ : STD_LOGIC;
signal \g81__347_carry__0_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_n_4\ : STD_LOGIC;
signal \g81__347_carry__0_n_5\ : STD_LOGIC;
signal \g81__347_carry__0_n_6\ : STD_LOGIC;
signal \g81__347_carry__0_n_7\ : STD_LOGIC;
signal \g81__347_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_1\ : STD_LOGIC;
signal \g81__347_carry_n_2\ : STD_LOGIC;
signal \g81__347_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry_n_4\ : STD_LOGIC;
signal \g81__347_carry_n_5\ : STD_LOGIC;
signal \g81__347_carry_n_6\ : STD_LOGIC;
signal \g81__347_carry_n_7\ : STD_LOGIC;
signal \g81__53_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_1\ : STD_LOGIC;
signal \g81__53_carry__0_n_2\ : STD_LOGIC;
signal \g81__53_carry__0_n_3\ : STD_LOGIC;
signal \g81__53_carry__0_n_4\ : STD_LOGIC;
signal \g81__53_carry__0_n_5\ : STD_LOGIC;
signal \g81__53_carry__0_n_6\ : STD_LOGIC;
signal \g81__53_carry__0_n_7\ : STD_LOGIC;
signal \g81__53_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_1\ : STD_LOGIC;
signal \g81__53_carry__1_n_2\ : STD_LOGIC;
signal \g81__53_carry__1_n_3\ : STD_LOGIC;
signal \g81__53_carry__1_n_4\ : STD_LOGIC;
signal \g81__53_carry__1_n_5\ : STD_LOGIC;
signal \g81__53_carry__1_n_6\ : STD_LOGIC;
signal \g81__53_carry__1_n_7\ : STD_LOGIC;
signal \g81__53_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_n_1\ : STD_LOGIC;
signal \g81__53_carry__2_n_3\ : STD_LOGIC;
signal \g81__53_carry__2_n_6\ : STD_LOGIC;
signal \g81__53_carry__2_n_7\ : STD_LOGIC;
signal \g81__53_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_1\ : STD_LOGIC;
signal \g81__53_carry_n_2\ : STD_LOGIC;
signal \g81__53_carry_n_3\ : STD_LOGIC;
signal \g81__53_carry_n_4\ : STD_LOGIC;
signal \g81__53_carry_n_5\ : STD_LOGIC;
signal \g81__53_carry_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_1\ : STD_LOGIC;
signal \g81__92_carry__0_n_2\ : STD_LOGIC;
signal \g81__92_carry__0_n_3\ : STD_LOGIC;
signal \g81__92_carry__0_n_4\ : STD_LOGIC;
signal \g81__92_carry__0_n_5\ : STD_LOGIC;
signal \g81__92_carry__0_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_n_7\ : STD_LOGIC;
signal \g81__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_1\ : STD_LOGIC;
signal \g81__92_carry__1_n_2\ : STD_LOGIC;
signal \g81__92_carry__1_n_3\ : STD_LOGIC;
signal \g81__92_carry__1_n_4\ : STD_LOGIC;
signal \g81__92_carry__1_n_5\ : STD_LOGIC;
signal \g81__92_carry__1_n_6\ : STD_LOGIC;
signal \g81__92_carry__1_n_7\ : STD_LOGIC;
signal \g81__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_n_1\ : STD_LOGIC;
signal \g81__92_carry__2_n_3\ : STD_LOGIC;
signal \g81__92_carry__2_n_6\ : STD_LOGIC;
signal \g81__92_carry__2_n_7\ : STD_LOGIC;
signal \g81__92_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_1\ : STD_LOGIC;
signal \g81__92_carry_n_2\ : STD_LOGIC;
signal \g81__92_carry_n_3\ : STD_LOGIC;
signal \g81__92_carry_n_4\ : STD_LOGIC;
signal \g81__92_carry_n_5\ : STD_LOGIC;
signal \g81__92_carry_n_6\ : STD_LOGIC;
signal \g81_carry__0_i_10_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_11_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_12_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_13_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_14_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_15_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_1\ : STD_LOGIC;
signal \g81_carry__0_n_2\ : STD_LOGIC;
signal \g81_carry__0_n_3\ : STD_LOGIC;
signal \g81_carry__0_n_4\ : STD_LOGIC;
signal \g81_carry__0_n_5\ : STD_LOGIC;
signal \g81_carry__0_n_6\ : STD_LOGIC;
signal \g81_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_1\ : STD_LOGIC;
signal \g81_carry__1_n_2\ : STD_LOGIC;
signal \g81_carry__1_n_3\ : STD_LOGIC;
signal \g81_carry__1_n_4\ : STD_LOGIC;
signal \g81_carry__1_n_5\ : STD_LOGIC;
signal \g81_carry__1_n_6\ : STD_LOGIC;
signal \g81_carry__1_n_7\ : STD_LOGIC;
signal \g81_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__2_n_1\ : STD_LOGIC;
signal \g81_carry__2_n_3\ : STD_LOGIC;
signal \g81_carry__2_n_6\ : STD_LOGIC;
signal \g81_carry__2_n_7\ : STD_LOGIC;
signal g81_carry_i_1_n_0 : STD_LOGIC;
signal g81_carry_i_2_n_0 : STD_LOGIC;
signal g81_carry_i_3_n_0 : STD_LOGIC;
signal g81_carry_i_4_n_0 : STD_LOGIC;
signal g81_carry_i_5_n_0 : STD_LOGIC;
signal g81_carry_i_6_n_0 : STD_LOGIC;
signal g81_carry_i_7_n_0 : STD_LOGIC;
signal g81_carry_n_0 : STD_LOGIC;
signal g81_carry_n_1 : STD_LOGIC;
signal g81_carry_n_2 : STD_LOGIC;
signal g81_carry_n_3 : STD_LOGIC;
signal g81_carry_n_7 : STD_LOGIC;
signal g83 : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \g83__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_1\ : STD_LOGIC;
signal \g83__0_carry__0_n_2\ : STD_LOGIC;
signal \g83__0_carry__0_n_3\ : STD_LOGIC;
signal \g83__0_carry__0_n_4\ : STD_LOGIC;
signal \g83__0_carry__0_n_5\ : STD_LOGIC;
signal \g83__0_carry__0_n_6\ : STD_LOGIC;
signal \g83__0_carry__0_n_7\ : STD_LOGIC;
signal \g83__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__1_n_2\ : STD_LOGIC;
signal \g83__0_carry__1_n_7\ : STD_LOGIC;
signal \g83__0_carry_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_1\ : STD_LOGIC;
signal \g83__0_carry_n_2\ : STD_LOGIC;
signal \g83__0_carry_n_3\ : STD_LOGIC;
signal \g83__0_carry_n_4\ : STD_LOGIC;
signal \g83__0_carry_n_5\ : STD_LOGIC;
signal \g83__0_carry_n_6\ : STD_LOGIC;
signal \g83__0_carry_n_7\ : STD_LOGIC;
signal g84 : STD_LOGIC;
signal \g84_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g84_carry__0_i_2_n_0\ : STD_LOGIC;
signal g84_carry_i_1_n_0 : STD_LOGIC;
signal g84_carry_i_2_n_0 : STD_LOGIC;
signal g84_carry_i_3_n_0 : STD_LOGIC;
signal g84_carry_i_4_n_0 : STD_LOGIC;
signal g84_carry_i_5_n_0 : STD_LOGIC;
signal g84_carry_i_6_n_0 : STD_LOGIC;
signal g84_carry_i_7_n_0 : STD_LOGIC;
signal g84_carry_i_8_n_0 : STD_LOGIC;
signal g84_carry_n_0 : STD_LOGIC;
signal g84_carry_n_1 : STD_LOGIC;
signal g84_carry_n_2 : STD_LOGIC;
signal g84_carry_n_3 : STD_LOGIC;
signal \NLW__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__120_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__149_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__149_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__206_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__206_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__22_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__22_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__22_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__261_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__261_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__301_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__301_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__347_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__53_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__53_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__53_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__92_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__92_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_g81_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g83__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g83__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_g84_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g84_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g84_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute HLUTNM : string;
attribute HLUTNM of \g81__120_carry__1_i_1\ : label is "lutpair7";
attribute HLUTNM of \g81__149_carry__0_i_1\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_2\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__0_i_5\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__0_i_6\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_7\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__1_i_1\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_2\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_3\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__1_i_4\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__1_i_5\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__1_i_6\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_7\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_8\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__2_i_1\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_2\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_3\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__2_i_4\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__2_i_5\ : label is "lutpair17";
attribute HLUTNM of \g81__149_carry__2_i_6\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_7\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_8\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__3_i_1\ : label is "lutpair17";
attribute HLUTNM of \g81__206_carry__0_i_1\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_2\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__0_i_5\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__0_i_6\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_7\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__1_i_1\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_2\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_3\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__1_i_4\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__1_i_5\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__1_i_6\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_7\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_8\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__2_i_1\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__2_i_4\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__2_i_6\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__3_i_1\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_3\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__3_i_6\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_8\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__4_i_2\ : label is "lutpair26";
attribute HLUTNM of \g81__206_carry__4_i_6\ : label is "lutpair26";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \g81_carry__0_i_10\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_11\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_12\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \g81_carry__0_i_13\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_14\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_15\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__0_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__1_i_9\ : label is "soft_lutpair3";
attribute HLUTNM of \g81_carry__2_i_2\ : label is "lutpair7";
attribute HLUTNM of \g83__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \g83__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_7\ : label is "lutpair0";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(4 downto 1),
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => \_carry_i_5_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_4\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_6\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3 downto 2) => \NLW__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \_carry__1_n_2\,
CO(0) => \NLW__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => g83(9),
S(3 downto 1) => B"001",
S(0) => \_carry__1_i_1_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_2\,
O => \_carry__1_i_1_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
O => \_carry_i_1_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_4\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_6\,
O => \_carry_i_5_n_0\
);
\g81__120_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__120_carry_n_0\,
CO(2) => \g81__120_carry_n_1\,
CO(1) => \g81__120_carry_n_2\,
CO(0) => \g81__120_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__120_carry_i_1_n_0\,
DI(1) => \g81__120_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__120_carry_n_4\,
O(2) => \g81__120_carry_n_5\,
O(1) => \g81__120_carry_n_6\,
O(0) => \NLW_g81__120_carry_O_UNCONNECTED\(0),
S(3) => \g81__120_carry_i_3_n_0\,
S(2) => \g81__120_carry_i_4_n_0\,
S(1) => \g81__120_carry_i_5_n_0\,
S(0) => \g81__120_carry_i_6_n_0\
);
\g81__120_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry_n_0\,
CO(3) => \g81__120_carry__0_n_0\,
CO(2) => \g81__120_carry__0_n_1\,
CO(1) => \g81__120_carry__0_n_2\,
CO(0) => \g81__120_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__120_carry__0_n_4\,
O(2) => \g81__120_carry__0_n_5\,
O(1) => \g81__120_carry__0_n_6\,
O(0) => \g81__120_carry__0_n_7\,
S(3) => \g81__120_carry__0_i_1_n_0\,
S(2) => \g81__120_carry__0_i_2_n_0\,
S(1) => \g81__120_carry__0_i_3_n_0\,
S(0) => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__120_carry__0_i_1_n_0\
);
\g81__120_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__120_carry__0_i_2_n_0\
);
\g81__120_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__120_carry__0_i_3_n_0\
);
\g81__120_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__0_n_0\,
CO(3) => \g81__120_carry__1_n_0\,
CO(2) => \g81__120_carry__1_n_1\,
CO(1) => \g81__120_carry__1_n_2\,
CO(0) => \g81__120_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__120_carry__1_n_4\,
O(2) => \g81__120_carry__1_n_5\,
O(1) => \g81__120_carry__1_n_6\,
O(0) => \g81__120_carry__1_n_7\,
S(3) => \g81__120_carry__1_i_1_n_0\,
S(2) => \g81__120_carry__1_i_2_n_0\,
S(1) => \g81__120_carry__1_i_3_n_0\,
S(0) => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"369C"
)
port map (
I0 => g84,
I1 => \g81_carry__1_i_1_n_0\,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__120_carry__1_i_1_n_0\
);
\g81__120_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_2_n_0\
);
\g81__120_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_3_n_0\
);
\g81__120_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__1_n_0\,
CO(3) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__120_carry__2_n_1\,
CO(1) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__120_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__120_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__120_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__120_carry__2_n_6\,
O(0) => \g81__120_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__120_carry__2_i_1_n_0\
);
\g81__120_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__120_carry_i_1_n_0\
);
\g81__120_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__120_carry_i_2_n_0\
);
\g81__120_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__120_carry_i_3_n_0\
);
\g81__120_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__120_carry_i_4_n_0\
);
\g81__120_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__120_carry_i_5_n_0\
);
\g81__120_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__120_carry_i_6_n_0\
);
\g81__149_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__149_carry_n_0\,
CO(2) => \g81__149_carry_n_1\,
CO(1) => \g81__149_carry_n_2\,
CO(0) => \g81__149_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry_i_1_n_0\,
DI(2) => \g81__149_carry_i_2_n_0\,
DI(1) => \g81__149_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__149_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry_i_4_n_0\,
S(2) => \g81__149_carry_i_5_n_0\,
S(1) => \g81__149_carry_i_6_n_0\,
S(0) => \g81__149_carry_i_7_n_0\
);
\g81__149_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry_n_0\,
CO(3) => \g81__149_carry__0_n_0\,
CO(2) => \g81__149_carry__0_n_1\,
CO(1) => \g81__149_carry__0_n_2\,
CO(0) => \g81__149_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__0_i_1_n_0\,
DI(2) => \g81__149_carry__0_i_2_n_0\,
DI(1) => \g81__149_carry__0_i_3_n_0\,
DI(0) => \g81__149_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__0_i_5_n_0\,
S(2) => \g81__149_carry__0_i_6_n_0\,
S(1) => \g81__149_carry__0_i_7_n_0\,
S(0) => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
O => \g81__149_carry__0_i_1_n_0\
);
\g81__149_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
O => \g81__149_carry__0_i_2_n_0\
);
\g81__149_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_6\,
I1 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_3_n_0\
);
\g81__149_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
O => \g81__149_carry__0_i_4_n_0\
);
\g81__149_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
I3 => \g81__149_carry__0_i_1_n_0\,
O => \g81__149_carry__0_i_5_n_0\
);
\g81__149_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
I3 => \g81__149_carry__0_i_2_n_0\,
O => \g81__149_carry__0_i_6_n_0\
);
\g81__149_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
I2 => \g81_carry__1_n_6\,
I3 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_7_n_0\
);
\g81__149_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
I2 => \g81__22_carry_n_4\,
I3 => \g81_carry__1_n_6\,
O => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__0_n_0\,
CO(3) => \g81__149_carry__1_n_0\,
CO(2) => \g81__149_carry__1_n_1\,
CO(1) => \g81__149_carry__1_n_2\,
CO(0) => \g81__149_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__1_i_1_n_0\,
DI(2) => \g81__149_carry__1_i_2_n_0\,
DI(1) => \g81__149_carry__1_i_3_n_0\,
DI(0) => \g81__149_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__1_i_5_n_0\,
S(2) => \g81__149_carry__1_i_6_n_0\,
S(1) => \g81__149_carry__1_i_7_n_0\,
S(0) => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__1_i_1_n_0\
);
\g81__149_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
O => \g81__149_carry__1_i_2_n_0\
);
\g81__149_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
O => \g81__149_carry__1_i_3_n_0\
);
\g81__149_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
O => \g81__149_carry__1_i_4_n_0\
);
\g81__149_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_1_n_0\,
O => \g81__149_carry__1_i_5_n_0\
);
\g81__149_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_2_n_0\,
O => \g81__149_carry__1_i_6_n_0\
);
\g81__149_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
I3 => \g81__149_carry__1_i_3_n_0\,
O => \g81__149_carry__1_i_7_n_0\
);
\g81__149_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
I3 => \g81__149_carry__1_i_4_n_0\,
O => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__1_n_0\,
CO(3) => \g81__149_carry__2_n_0\,
CO(2) => \g81__149_carry__2_n_1\,
CO(1) => \g81__149_carry__2_n_2\,
CO(0) => \g81__149_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__2_i_1_n_0\,
DI(2) => \g81__149_carry__2_i_2_n_0\,
DI(1) => \g81__149_carry__2_i_3_n_0\,
DI(0) => \g81__149_carry__2_i_4_n_0\,
O(3) => \g81__149_carry__2_n_4\,
O(2) => \g81__149_carry__2_n_5\,
O(1) => \g81__149_carry__2_n_6\,
O(0) => \g81__149_carry__2_n_7\,
S(3) => \g81__149_carry__2_i_5_n_0\,
S(2) => \g81__149_carry__2_i_6_n_0\,
S(1) => \g81__149_carry__2_i_7_n_0\,
S(0) => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_1_n_0\
);
\g81__149_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_2_n_0\
);
\g81__149_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_3_n_0\
);
\g81__149_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_4_n_0\
);
\g81__149_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_1_n_0\,
O => \g81__149_carry__2_i_5_n_0\
);
\g81__149_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_2_n_0\,
O => \g81__149_carry__2_i_6_n_0\
);
\g81__149_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_3_n_0\,
O => \g81__149_carry__2_i_7_n_0\
);
\g81__149_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_4_n_0\,
O => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__2_n_0\,
CO(3) => \g81__149_carry__3_n_0\,
CO(2) => \g81__149_carry__3_n_1\,
CO(1) => \g81__149_carry__3_n_2\,
CO(0) => \g81__149_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__2_i_2_n_0\,
DI(2) => \g81_carry__2_i_2_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81__149_carry__3_i_1_n_0\,
O(3) => \g81__149_carry__3_n_4\,
O(2) => \g81__149_carry__3_n_5\,
O(1) => \g81__149_carry__3_n_6\,
O(0) => \g81__149_carry__3_n_7\,
S(3) => \g81__149_carry__3_i_2_n_0\,
S(2) => \g81__149_carry__3_i_3_n_0\,
S(1) => \g81__149_carry__3_i_4_n_0\,
S(0) => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__3_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__3_i_1_n_0\
);
\g81__149_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_7\,
O => \g81__149_carry__3_i_2_n_0\
);
\g81__149_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_4\,
O => \g81__149_carry__3_i_3_n_0\
);
\g81__149_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_5\,
O => \g81__149_carry__3_i_4_n_0\
);
\g81__149_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__149_carry__3_i_1_n_0\,
I1 => \g81__53_carry__1_n_6\,
O => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__3_n_0\,
CO(3) => \g81__149_carry__4_n_0\,
CO(2) => \NLW_g81__149_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__149_carry__4_n_2\,
CO(0) => \g81__149_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__149_carry__4_i_1_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3) => \NLW_g81__149_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__149_carry__4_n_5\,
O(1) => \g81__149_carry__4_n_6\,
O(0) => \g81__149_carry__4_n_7\,
S(3 downto 2) => B"10",
S(1) => \g81__149_carry__4_i_2_n_0\,
S(0) => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__149_carry__4_i_1_n_0\
);
\g81__149_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_1\,
O => \g81__149_carry__4_i_2_n_0\
);
\g81__149_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_6\,
O => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
O => \g81__149_carry_i_1_n_0\
);
\g81__149_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
O => \g81__149_carry_i_2_n_0\
);
\g81__149_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_3_n_0\
);
\g81__149_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
I2 => \g81__22_carry_n_5\,
I3 => \g81_carry__1_n_7\,
O => \g81__149_carry_i_4_n_0\
);
\g81__149_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__22_carry_n_6\,
I3 => \g81_carry__0_n_4\,
O => \g81__149_carry_i_5_n_0\
);
\g81__149_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g81_carry__0_n_5\,
O => \g81__149_carry_i_6_n_0\
);
\g81__149_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_7_n_0\
);
\g81__206_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__206_carry_n_0\,
CO(2) => \g81__206_carry_n_1\,
CO(1) => \g81__206_carry_n_2\,
CO(0) => \g81__206_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry_i_1_n_0\,
DI(2) => \g81__206_carry_i_2_n_0\,
DI(1) => \g81__206_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__206_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry_i_4_n_0\,
S(2) => \g81__206_carry_i_5_n_0\,
S(1) => \g81__206_carry_i_6_n_0\,
S(0) => \g81__206_carry_i_7_n_0\
);
\g81__206_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry_n_0\,
CO(3) => \g81__206_carry__0_n_0\,
CO(2) => \g81__206_carry__0_n_1\,
CO(1) => \g81__206_carry__0_n_2\,
CO(0) => \g81__206_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__0_i_1_n_0\,
DI(2) => \g81__206_carry__0_i_2_n_0\,
DI(1) => \g81__206_carry__0_i_3_n_0\,
DI(0) => \g81__206_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__0_i_5_n_0\,
S(2) => \g81__206_carry__0_i_6_n_0\,
S(1) => \g81__206_carry__0_i_7_n_0\,
S(0) => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
O => \g81__206_carry__0_i_1_n_0\
);
\g81__206_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
O => \g81__206_carry__0_i_2_n_0\
);
\g81__206_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_4\,
I1 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_3_n_0\
);
\g81__206_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
O => \g81__206_carry__0_i_4_n_0\
);
\g81__206_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
I3 => \g81__206_carry__0_i_1_n_0\,
O => \g81__206_carry__0_i_5_n_0\
);
\g81__206_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
I3 => \g81__206_carry__0_i_2_n_0\,
O => \g81__206_carry__0_i_6_n_0\
);
\g81__206_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
I2 => \g81__92_carry_n_4\,
I3 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_7_n_0\
);
\g81__206_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
I2 => \g81__149_carry__3_n_7\,
I3 => \g81__92_carry_n_4\,
O => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__0_n_0\,
CO(3) => \g81__206_carry__1_n_0\,
CO(2) => \g81__206_carry__1_n_1\,
CO(1) => \g81__206_carry__1_n_2\,
CO(0) => \g81__206_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__1_i_1_n_0\,
DI(2) => \g81__206_carry__1_i_2_n_0\,
DI(1) => \g81__206_carry__1_i_3_n_0\,
DI(0) => \g81__206_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__1_i_5_n_0\,
S(2) => \g81__206_carry__1_i_6_n_0\,
S(1) => \g81__206_carry__1_i_7_n_0\,
S(0) => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
O => \g81__206_carry__1_i_1_n_0\
);
\g81__206_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
O => \g81__206_carry__1_i_2_n_0\
);
\g81__206_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
O => \g81__206_carry__1_i_3_n_0\
);
\g81__206_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
O => \g81__206_carry__1_i_4_n_0\
);
\g81__206_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
I3 => \g81__206_carry__1_i_1_n_0\,
O => \g81__206_carry__1_i_5_n_0\
);
\g81__206_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
I3 => \g81__206_carry__1_i_2_n_0\,
O => \g81__206_carry__1_i_6_n_0\
);
\g81__206_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
I3 => \g81__206_carry__1_i_3_n_0\,
O => \g81__206_carry__1_i_7_n_0\
);
\g81__206_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
I3 => \g81__206_carry__1_i_4_n_0\,
O => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__1_n_0\,
CO(3) => \g81__206_carry__2_n_0\,
CO(2) => \g81__206_carry__2_n_1\,
CO(1) => \g81__206_carry__2_n_2\,
CO(0) => \g81__206_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_i_1_n_0\,
DI(2) => \g81__206_carry__2_i_2_n_0\,
DI(1) => \g81__206_carry__2_i_3_n_0\,
DI(0) => \g81__206_carry__2_i_4_n_0\,
O(3) => \g81__206_carry__2_n_4\,
O(2) => \g81__206_carry__2_n_5\,
O(1) => \g81__206_carry__2_n_6\,
O(0) => \g81__206_carry__2_n_7\,
S(3) => \g81__206_carry__2_i_5_n_0\,
S(2) => \g81__206_carry__2_i_6_n_0\,
S(1) => \g81__206_carry__2_i_7_n_0\,
S(0) => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
O => \g81__206_carry__2_i_1_n_0\
);
\g81__206_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry__2_n_7\,
I1 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_2_n_0\
);
\g81__206_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__0_n_6\,
I3 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_3_n_0\
);
\g81__206_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
O => \g81__206_carry__2_i_4_n_0\
);
\g81__206_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_1_n_0\,
I1 => \g81__120_carry__1_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__2_i_5_n_0\
);
\g81__206_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
I2 => \g81__92_carry__2_n_7\,
I3 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_6_n_0\
);
\g81__206_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"888E77717771888E"
)
port map (
I0 => \g81__92_carry__1_n_4\,
I1 => \g81__120_carry__0_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
I4 => \g81__120_carry__0_n_5\,
I5 => \g81__92_carry__2_n_7\,
O => \g81__206_carry__2_i_7_n_0\
);
\g81__206_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_4_n_0\,
I1 => \g81__120_carry__0_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__2_n_0\,
CO(3) => \g81__206_carry__3_n_0\,
CO(2) => \g81__206_carry__3_n_1\,
CO(1) => \g81__206_carry__3_n_2\,
CO(0) => \g81__206_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_i_1_n_0\,
DI(2) => \g81__206_carry__3_i_2_n_0\,
DI(1) => \g81__206_carry__3_i_3_n_0\,
DI(0) => \g81__206_carry__3_i_4_n_0\,
O(3) => \g81__206_carry__3_n_4\,
O(2) => \g81__206_carry__3_n_5\,
O(1) => \g81__206_carry__3_n_6\,
O(0) => \g81__206_carry__3_n_7\,
S(3) => \g81__206_carry__3_i_5_n_0\,
S(2) => \g81__206_carry__3_i_6_n_0\,
S(1) => \g81__206_carry__3_i_7_n_0\,
S(0) => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_1_n_0\
);
\g81__206_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__3_i_2_n_0\
);
\g81__206_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_3_n_0\
);
\g81__206_carry__3_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__1_n_7\,
I3 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__3_i_4_n_0\
);
\g81__206_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_1_n_0\,
I1 => \g81__120_carry__2_n_7\,
O => \g81__206_carry__3_i_5_n_0\
);
\g81__206_carry__3_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__1_n_4\,
O => \g81__206_carry__3_i_6_n_0\
);
\g81__206_carry__3_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_3_n_0\,
I1 => \g81__120_carry__1_n_5\,
O => \g81__206_carry__3_i_7_n_0\
);
\g81__206_carry__3_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"56AAAAA9"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
I3 => \g81__92_carry__2_n_1\,
I4 => \g81__120_carry__1_n_7\,
O => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__3_n_0\,
CO(3) => \g81__206_carry__4_n_0\,
CO(2) => \NLW_g81__206_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__206_carry__4_n_2\,
CO(0) => \g81__206_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__206_carry__4_i_1_n_0\,
DI(1) => \g81__206_carry__4_i_2_n_0\,
DI(0) => \g81__206_carry__4_i_3_n_0\,
O(3) => \NLW_g81__206_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__206_carry__4_n_5\,
O(1) => \g81__206_carry__4_n_6\,
O(0) => \g81__206_carry__4_n_7\,
S(3) => '1',
S(2) => \g81__206_carry__4_i_4_n_0\,
S(1) => \g81__206_carry__4_i_5_n_0\,
S(0) => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_1_n_0\
);
\g81__206_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__4_i_2_n_0\
);
\g81__206_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_3_n_0\
);
\g81__206_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_4_n_0\
);
\g81__206_carry__4_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__4_i_2_n_0\,
I1 => \g81__120_carry__2_n_1\,
O => \g81__206_carry__4_i_5_n_0\
);
\g81__206_carry__4_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__2_n_6\,
O => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
O => \g81__206_carry_i_1_n_0\
);
\g81__206_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
O => \g81__206_carry_i_2_n_0\
);
\g81__206_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_3_n_0\
);
\g81__206_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
I2 => \g81__149_carry__2_n_4\,
I3 => \g81__92_carry_n_5\,
O => \g81__206_carry_i_4_n_0\
);
\g81__206_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
I2 => \g81__149_carry__2_n_5\,
I3 => \g81__92_carry_n_6\,
O => \g81__206_carry_i_5_n_0\
);
\g81__206_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
I2 => \g81__149_carry__2_n_6\,
I3 => g81_carry_n_7,
O => \g81__206_carry_i_6_n_0\
);
\g81__206_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_7_n_0\
);
\g81__22_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__22_carry_n_0\,
CO(2) => \g81__22_carry_n_1\,
CO(1) => \g81__22_carry_n_2\,
CO(0) => \g81__22_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__22_carry_i_1_n_0\,
DI(1) => \g81__22_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__22_carry_n_4\,
O(2) => \g81__22_carry_n_5\,
O(1) => \g81__22_carry_n_6\,
O(0) => \NLW_g81__22_carry_O_UNCONNECTED\(0),
S(3) => \g81__22_carry_i_3_n_0\,
S(2) => \g81__22_carry_i_4_n_0\,
S(1) => \g81__22_carry_i_5_n_0\,
S(0) => \g81__22_carry_i_6_n_0\
);
\g81__22_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry_n_0\,
CO(3) => \g81__22_carry__0_n_0\,
CO(2) => \g81__22_carry__0_n_1\,
CO(1) => \g81__22_carry__0_n_2\,
CO(0) => \g81__22_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__22_carry__0_n_4\,
O(2) => \g81__22_carry__0_n_5\,
O(1) => \g81__22_carry__0_n_6\,
O(0) => \g81__22_carry__0_n_7\,
S(3) => \g81__22_carry__0_i_1_n_0\,
S(2) => \g81__22_carry__0_i_2_n_0\,
S(1) => \g81__22_carry__0_i_3_n_0\,
S(0) => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__22_carry__0_i_1_n_0\
);
\g81__22_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__22_carry__0_i_2_n_0\
);
\g81__22_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__22_carry__0_i_3_n_0\
);
\g81__22_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__0_n_0\,
CO(3) => \g81__22_carry__1_n_0\,
CO(2) => \g81__22_carry__1_n_1\,
CO(1) => \g81__22_carry__1_n_2\,
CO(0) => \g81__22_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__22_carry__1_n_4\,
O(2) => \g81__22_carry__1_n_5\,
O(1) => \g81__22_carry__1_n_6\,
O(0) => \g81__22_carry__1_n_7\,
S(3) => \g81__22_carry__1_i_1_n_0\,
S(2) => \g81__22_carry__1_i_2_n_0\,
S(1) => \g81__22_carry__1_i_3_n_0\,
S(0) => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__22_carry__1_i_1_n_0\
);
\g81__22_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_2_n_0\
);
\g81__22_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_3_n_0\
);
\g81__22_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__1_n_0\,
CO(3) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__22_carry__2_n_1\,
CO(1) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__22_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__22_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__22_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__22_carry__2_n_6\,
O(0) => \g81__22_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__22_carry__2_i_1_n_0\
);
\g81__22_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__22_carry_i_1_n_0\
);
\g81__22_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__22_carry_i_2_n_0\
);
\g81__22_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__22_carry_i_3_n_0\
);
\g81__22_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__22_carry_i_4_n_0\
);
\g81__22_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__22_carry_i_5_n_0\
);
\g81__22_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__22_carry_i_6_n_0\
);
\g81__261_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__261_carry_n_0\,
CO(2) => \g81__261_carry_n_1\,
CO(1) => \g81__261_carry_n_2\,
CO(0) => \g81__261_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_n_6\,
DI(2) => \g81__206_carry__2_n_7\,
DI(1 downto 0) => B"01",
O(3) => \g81__261_carry_n_4\,
O(2) => \g81__261_carry_n_5\,
O(1) => \g81__261_carry_n_6\,
O(0) => \g81__261_carry_n_7\,
S(3) => \g81__261_carry_i_1_n_0\,
S(2) => \g81__261_carry_i_2_n_0\,
S(1) => \g81__261_carry_i_3_n_0\,
S(0) => \g81__261_carry_i_4_n_0\
);
\g81__261_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry_n_0\,
CO(3) => \g81__261_carry__0_n_0\,
CO(2) => \g81__261_carry__0_n_1\,
CO(1) => \g81__261_carry__0_n_2\,
CO(0) => \g81__261_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_n_6\,
DI(2) => \g81__206_carry__3_n_7\,
DI(1) => \g81__206_carry__2_n_4\,
DI(0) => \g81__206_carry__2_n_5\,
O(3) => \g81__261_carry__0_n_4\,
O(2) => \g81__261_carry__0_n_5\,
O(1) => \g81__261_carry__0_n_6\,
O(0) => \g81__261_carry__0_n_7\,
S(3) => \g81__261_carry__0_i_1_n_0\,
S(2) => \g81__261_carry__0_i_2_n_0\,
S(1) => \g81__261_carry__0_i_3_n_0\,
S(0) => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__206_carry__3_n_4\,
O => \g81__261_carry__0_i_1_n_0\
);
\g81__261_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__206_carry__3_n_5\,
O => \g81__261_carry__0_i_2_n_0\
);
\g81__261_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__206_carry__3_n_6\,
O => \g81__261_carry__0_i_3_n_0\
);
\g81__261_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__206_carry__3_n_7\,
O => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__0_n_0\,
CO(3) => \g81__261_carry__1_n_0\,
CO(2) => \g81__261_carry__1_n_1\,
CO(1) => \g81__261_carry__1_n_2\,
CO(0) => \g81__261_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__4_n_6\,
DI(2) => \g81__206_carry__4_n_7\,
DI(1) => \g81__206_carry__3_n_4\,
DI(0) => \g81__206_carry__3_n_5\,
O(3) => \g81__261_carry__1_n_4\,
O(2) => \g81__261_carry__1_n_5\,
O(1) => \g81__261_carry__1_n_6\,
O(0) => \g81__261_carry__1_n_7\,
S(3) => \g81__261_carry__1_i_1_n_0\,
S(2) => \g81__261_carry__1_i_2_n_0\,
S(1) => \g81__261_carry__1_i_3_n_0\,
S(0) => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_6\,
I1 => \g81__206_carry__4_n_0\,
O => \g81__261_carry__1_i_1_n_0\
);
\g81__261_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_7\,
I1 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__1_i_2_n_0\
);
\g81__261_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__206_carry__4_n_6\,
O => \g81__261_carry__1_i_3_n_0\
);
\g81__261_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__206_carry__4_n_7\,
O => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__1_n_0\,
CO(3) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__261_carry__2_n_1\,
CO(1) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__261_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__206_carry__4_n_0\,
DI(0) => \g81__206_carry__4_n_5\,
O(3 downto 2) => \NLW_g81__261_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__261_carry__2_n_6\,
O(0) => \g81__261_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \g81__261_carry__2_i_1_n_0\,
S(0) => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \g81__206_carry__4_n_0\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__261_carry__2_i_1_n_0\
);
\g81__261_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__206_carry__2_n_4\,
O => \g81__261_carry_i_1_n_0\
);
\g81__261_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__206_carry__2_n_5\,
O => \g81__261_carry_i_2_n_0\
);
\g81__261_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__261_carry_i_3_n_0\
);
\g81__261_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__261_carry_i_4_n_0\
);
\g81__301_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__301_carry_n_0\,
CO(2) => \g81__301_carry_n_1\,
CO(1) => \g81__301_carry_n_2\,
CO(0) => \g81__301_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry_i_1_n_0\,
DI(2) => \g81__301_carry_i_2_n_0\,
DI(1) => \g81__301_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__301_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry_i_4_n_0\,
S(2) => \g81__301_carry_i_5_n_0\,
S(1) => \g81__301_carry_i_6_n_0\,
S(0) => \g81__301_carry_i_7_n_0\
);
\g81__301_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry_n_0\,
CO(3) => \g81__301_carry__0_n_0\,
CO(2) => \g81__301_carry__0_n_1\,
CO(1) => \g81__301_carry__0_n_2\,
CO(0) => \g81__301_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__0_i_1_n_0\,
DI(2) => \g81__301_carry__0_i_2_n_0\,
DI(1) => \g81__301_carry__0_i_3_n_0\,
DI(0) => \g81__301_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__0_i_5_n_0\,
S(2) => \g81__301_carry__0_i_6_n_0\,
S(1) => \g81__301_carry__0_i_7_n_0\,
S(0) => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_5\,
I1 => g84,
I2 => g83(6),
I3 => \g83__0_carry__0_n_5\,
O => \g81__301_carry__0_i_1_n_0\
);
\g81__301_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_6\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
O => \g81__301_carry__0_i_2_n_0\
);
\g81__301_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_7\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
O => \g81__301_carry__0_i_3_n_0\
);
\g81__301_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_4\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
O => \g81__301_carry__0_i_4_n_0\
);
\g81__301_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
I3 => \g81__261_carry__0_n_5\,
I4 => \g81__261_carry__0_n_4\,
I5 => \g81_carry__1_i_9_n_0\,
O => \g81__301_carry__0_i_5_n_0\
);
\g81__301_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
I3 => \g81__261_carry__0_n_6\,
I4 => \g81__261_carry__0_n_5\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__301_carry__0_i_6_n_0\
);
\g81__301_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
I3 => \g81__261_carry__0_n_7\,
I4 => \g81__261_carry__0_n_6\,
I5 => \g81_carry__0_i_14_n_0\,
O => \g81__301_carry__0_i_7_n_0\
);
\g81__301_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => \g81__261_carry_n_4\,
I2 => \g81__261_carry__0_n_7\,
I3 => \g83__0_carry__0_n_7\,
I4 => g83(4),
I5 => g84,
O => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__0_n_0\,
CO(3) => \g81__301_carry__1_n_0\,
CO(2) => \g81__301_carry__1_n_1\,
CO(1) => \g81__301_carry__1_n_2\,
CO(0) => \g81__301_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__1_i_1_n_0\,
DI(2) => \g81__301_carry__1_i_2_n_0\,
DI(1) => \g81__301_carry__1_i_3_n_0\,
DI(0) => \g81__301_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__1_i_5_n_0\,
S(2) => \g81__301_carry__1_i_6_n_0\,
S(1) => \g81__301_carry__1_i_7_n_0\,
S(0) => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__1_i_1_n_0\
);
\g81__301_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_6\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__301_carry__1_i_2_n_0\
);
\g81__301_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_7\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__301_carry__1_i_3_n_0\
);
\g81__301_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_4\,
I1 => g84,
I2 => g83(7),
I3 => \g83__0_carry__0_n_4\,
O => \g81__301_carry__1_i_4_n_0\
);
\g81__301_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \g81__261_carry__1_n_4\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_5_n_0\
);
\g81__301_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"50AF30CF50AFCF30"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => \g81__261_carry__1_n_6\,
I3 => \g81__261_carry__1_n_5\,
I4 => g84,
I5 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_6_n_0\
);
\g81__301_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => g83(8),
I2 => g84,
I3 => \g81__261_carry__1_n_7\,
I4 => \g81__261_carry__1_n_6\,
I5 => \g81__301_carry__1_i_9_n_0\,
O => \g81__301_carry__1_i_7_n_0\
);
\g81__301_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__1_i_9_n_0\,
I1 => \g81__261_carry__0_n_4\,
I2 => \g81__261_carry__1_n_7\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => g84,
O => \g81__301_carry__1_i_9_n_0\
);
\g81__301_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__1_n_0\,
CO(3) => \g81__301_carry__2_n_0\,
CO(2) => \g81__301_carry__2_n_1\,
CO(1) => \g81__301_carry__2_n_2\,
CO(0) => \g81__301_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__2_i_1_n_0\,
DI(2) => \g81__301_carry__2_i_2_n_0\,
DI(1) => \g81__301_carry__2_i_3_n_0\,
DI(0) => \g81__301_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__2_i_5_n_0\,
S(2) => \g81__301_carry__2_i_6_n_0\,
S(1) => \g81__301_carry__2_i_7_n_0\,
S(0) => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__2_i_1_n_0\
);
\g81__301_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_2_n_0\
);
\g81__301_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_3_n_0\
);
\g81__301_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_4_n_0\
);
\g81__301_carry__2_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_5_n_0\
);
\g81__301_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6663"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \g81__261_carry__2_n_1\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_6_n_0\
);
\g81__301_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \g81__261_carry__2_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_7_n_0\
);
\g81__301_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \g81__261_carry__2_n_7\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__2_n_0\,
CO(3) => \g81__301_carry__3_n_0\,
CO(2) => \g81__301_carry__3_n_1\,
CO(1) => \g81__301_carry__3_n_2\,
CO(0) => \g81__301_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__3_i_1_n_0\,
DI(2) => \g81__301_carry__3_i_2_n_0\,
DI(1) => \g81__301_carry__3_i_3_n_0\,
DI(0) => \g81__301_carry__3_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__3_i_5_n_0\,
S(2) => \g81__301_carry__3_i_6_n_0\,
S(1) => \g81__301_carry__3_i_7_n_0\,
S(0) => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_1_n_0\
);
\g81__301_carry__3_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_2_n_0\
);
\g81__301_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_3_n_0\
);
\g81__301_carry__3_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_4_n_0\
);
\g81__301_carry__3_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_5_n_0\
);
\g81__301_carry__3_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_6_n_0\
);
\g81__301_carry__3_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_7_n_0\
);
\g81__301_carry__3_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__3_n_0\,
CO(3) => \g81__301_carry__4_n_0\,
CO(2) => \g81__301_carry__4_n_1\,
CO(1) => \g81__301_carry__4_n_2\,
CO(0) => \g81__301_carry__4_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__4_i_1_n_0\,
DI(2) => \g81__301_carry__4_i_2_n_0\,
DI(1) => \g81__301_carry__4_i_3_n_0\,
DI(0) => \g81__301_carry__4_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__4_i_5_n_0\,
S(2) => \g81__301_carry__4_i_6_n_0\,
S(1) => \g81__301_carry__4_i_7_n_0\,
S(0) => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__4_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_1_n_0\
);
\g81__301_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_2_n_0\
);
\g81__301_carry__4_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_3_n_0\
);
\g81__301_carry__4_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_4_n_0\
);
\g81__301_carry__4_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_5_n_0\
);
\g81__301_carry__4_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_6_n_0\
);
\g81__301_carry__4_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_7_n_0\
);
\g81__301_carry__4_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__4_n_0\,
CO(3) => \g81__301_carry__5_n_0\,
CO(2) => \g81__301_carry__5_n_1\,
CO(1) => \g81__301_carry__5_n_2\,
CO(0) => \g81__301_carry__5_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__5_i_1_n_0\,
DI(2) => \g81__301_carry__5_i_2_n_0\,
DI(1) => \g81__301_carry__5_i_3_n_0\,
DI(0) => \g81__301_carry__5_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__5_i_5_n_0\,
S(2) => \g81__301_carry__5_i_6_n_0\,
S(1) => \g81__301_carry__5_i_7_n_0\,
S(0) => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__5_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_1_n_0\
);
\g81__301_carry__5_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_2_n_0\
);
\g81__301_carry__5_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_3_n_0\
);
\g81__301_carry__5_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_4_n_0\
);
\g81__301_carry__5_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_5_n_0\
);
\g81__301_carry__5_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_6_n_0\
);
\g81__301_carry__5_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_7_n_0\
);
\g81__301_carry__5_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__5_n_0\,
CO(3) => \NLW_g81__301_carry__6_CO_UNCONNECTED\(3),
CO(2) => \g81__301_carry__6_n_1\,
CO(1) => \g81__301_carry__6_n_2\,
CO(0) => \g81__301_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__301_carry__6_i_1_n_0\,
DI(1) => \g81__301_carry__6_i_2_n_0\,
DI(0) => \g81__301_carry__6_i_3_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__6_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \g81__301_carry__6_i_4_n_0\,
S(1) => \g81__301_carry__6_i_5_n_0\,
S(0) => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry__6_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_1_n_0\
);
\g81__301_carry__6_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_2_n_0\
);
\g81__301_carry__6_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_3_n_0\
);
\g81__301_carry__6_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_4_n_0\
);
\g81__301_carry__6_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_5_n_0\
);
\g81__301_carry__6_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_5\,
I1 => g84,
I2 => g83(2),
I3 => \g83__0_carry_n_5\,
O => \g81__301_carry_i_1_n_0\
);
\g81__301_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABEF"
)
port map (
I0 => \g81__261_carry_n_6\,
I1 => g84,
I2 => g83(1),
I3 => \g83__0_carry_n_6\,
O => \g81__301_carry_i_2_n_0\
);
\g81__301_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g81__261_carry_n_7\,
I1 => \g83__0_carry_n_7\,
O => \g81__301_carry_i_3_n_0\
);
\g81__301_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
I3 => \g81__261_carry_n_5\,
I4 => \g81__261_carry_n_4\,
I5 => \g81_carry__0_i_9_n_0\,
O => \g81__301_carry_i_4_n_0\
);
\g81__301_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DD22DD22D2DD2D2"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__261_carry_n_6\,
I2 => \g81__261_carry_n_5\,
I3 => \g83__0_carry_n_5\,
I4 => g83(2),
I5 => g84,
O => \g81__301_carry_i_5_n_0\
);
\g81__301_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22DD22DD2D22D2D"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
I2 => \g81__261_carry_n_6\,
I3 => \g83__0_carry_n_6\,
I4 => g83(1),
I5 => g84,
O => \g81__301_carry_i_6_n_0\
);
\g81__301_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
O => \g81__301_carry_i_7_n_0\
);
\g81__347_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__347_carry_n_0\,
CO(2) => \g81__347_carry_n_1\,
CO(1) => \g81__347_carry_n_2\,
CO(0) => \g81__347_carry_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \g81__347_carry_n_4\,
O(2) => \g81__347_carry_n_5\,
O(1) => \g81__347_carry_n_6\,
O(0) => \g81__347_carry_n_7\,
S(3) => \g81__347_carry_i_1_n_0\,
S(2) => \g81__347_carry_i_2_n_0\,
S(1) => \g81__347_carry_i_3_n_0\,
S(0) => \g81__347_carry_i_4_n_0\
);
\g81__347_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__347_carry_n_0\,
CO(3) => \NLW_g81__347_carry__0_CO_UNCONNECTED\(3),
CO(2) => \g81__347_carry__0_n_1\,
CO(1) => \g81__347_carry__0_n_2\,
CO(0) => \g81__347_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \g81__347_carry__0_n_4\,
O(2) => \g81__347_carry__0_n_5\,
O(1) => \g81__347_carry__0_n_6\,
O(0) => \g81__347_carry__0_n_7\,
S(3) => \g81__347_carry__0_i_1_n_0\,
S(2) => \g81__347_carry__0_i_2_n_0\,
S(1) => \g81__347_carry__0_i_3_n_0\,
S(0) => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_4\,
O => \g81__347_carry__0_i_1_n_0\
);
\g81__347_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_5\,
O => \g81__347_carry__0_i_2_n_0\
);
\g81__347_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_6\,
O => \g81__347_carry__0_i_3_n_0\
);
\g81__347_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_7\,
O => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_4\,
O => \g81__347_carry_i_1_n_0\
);
\g81__347_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_5\,
O => \g81__347_carry_i_2_n_0\
);
\g81__347_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__347_carry_i_3_n_0\
);
\g81__347_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__347_carry_i_4_n_0\
);
\g81__53_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__53_carry_n_0\,
CO(2) => \g81__53_carry_n_1\,
CO(1) => \g81__53_carry_n_2\,
CO(0) => \g81__53_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__53_carry_i_1_n_0\,
DI(1) => \g81__53_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__53_carry_n_4\,
O(2) => \g81__53_carry_n_5\,
O(1) => \g81__53_carry_n_6\,
O(0) => \NLW_g81__53_carry_O_UNCONNECTED\(0),
S(3) => \g81__53_carry_i_3_n_0\,
S(2) => \g81__53_carry_i_4_n_0\,
S(1) => \g81__53_carry_i_5_n_0\,
S(0) => \g81__53_carry_i_6_n_0\
);
\g81__53_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry_n_0\,
CO(3) => \g81__53_carry__0_n_0\,
CO(2) => \g81__53_carry__0_n_1\,
CO(1) => \g81__53_carry__0_n_2\,
CO(0) => \g81__53_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__53_carry__0_n_4\,
O(2) => \g81__53_carry__0_n_5\,
O(1) => \g81__53_carry__0_n_6\,
O(0) => \g81__53_carry__0_n_7\,
S(3) => \g81__53_carry__0_i_1_n_0\,
S(2) => \g81__53_carry__0_i_2_n_0\,
S(1) => \g81__53_carry__0_i_3_n_0\,
S(0) => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__53_carry__0_i_1_n_0\
);
\g81__53_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__53_carry__0_i_2_n_0\
);
\g81__53_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__53_carry__0_i_3_n_0\
);
\g81__53_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__0_n_0\,
CO(3) => \g81__53_carry__1_n_0\,
CO(2) => \g81__53_carry__1_n_1\,
CO(1) => \g81__53_carry__1_n_2\,
CO(0) => \g81__53_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__53_carry__1_n_4\,
O(2) => \g81__53_carry__1_n_5\,
O(1) => \g81__53_carry__1_n_6\,
O(0) => \g81__53_carry__1_n_7\,
S(3) => \g81__53_carry__1_i_1_n_0\,
S(2) => \g81__53_carry__1_i_2_n_0\,
S(1) => \g81__53_carry__1_i_3_n_0\,
S(0) => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__53_carry__1_i_1_n_0\
);
\g81__53_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_2_n_0\
);
\g81__53_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_3_n_0\
);
\g81__53_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__1_n_0\,
CO(3) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__53_carry__2_n_1\,
CO(1) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__53_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__53_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__53_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__53_carry__2_n_6\,
O(0) => \g81__53_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__53_carry__2_i_1_n_0\
);
\g81__53_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__53_carry_i_1_n_0\
);
\g81__53_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__53_carry_i_2_n_0\
);
\g81__53_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__53_carry_i_3_n_0\
);
\g81__53_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__53_carry_i_4_n_0\
);
\g81__53_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__53_carry_i_5_n_0\
);
\g81__53_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__53_carry_i_6_n_0\
);
\g81__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__92_carry_n_0\,
CO(2) => \g81__92_carry_n_1\,
CO(1) => \g81__92_carry_n_2\,
CO(0) => \g81__92_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__92_carry_i_1_n_0\,
DI(1) => \g81__92_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__92_carry_n_4\,
O(2) => \g81__92_carry_n_5\,
O(1) => \g81__92_carry_n_6\,
O(0) => \NLW_g81__92_carry_O_UNCONNECTED\(0),
S(3) => \g81__92_carry_i_3_n_0\,
S(2) => \g81__92_carry_i_4_n_0\,
S(1) => \g81__92_carry_i_5_n_0\,
S(0) => \g81__92_carry_i_6_n_0\
);
\g81__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry_n_0\,
CO(3) => \g81__92_carry__0_n_0\,
CO(2) => \g81__92_carry__0_n_1\,
CO(1) => \g81__92_carry__0_n_2\,
CO(0) => \g81__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__92_carry__0_n_4\,
O(2) => \g81__92_carry__0_n_5\,
O(1) => \g81__92_carry__0_n_6\,
O(0) => \g81__92_carry__0_n_7\,
S(3) => \g81__92_carry__0_i_1_n_0\,
S(2) => \g81__92_carry__0_i_2_n_0\,
S(1) => \g81__92_carry__0_i_3_n_0\,
S(0) => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__92_carry__0_i_1_n_0\
);
\g81__92_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__92_carry__0_i_2_n_0\
);
\g81__92_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__92_carry__0_i_3_n_0\
);
\g81__92_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__0_n_0\,
CO(3) => \g81__92_carry__1_n_0\,
CO(2) => \g81__92_carry__1_n_1\,
CO(1) => \g81__92_carry__1_n_2\,
CO(0) => \g81__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__92_carry__1_n_4\,
O(2) => \g81__92_carry__1_n_5\,
O(1) => \g81__92_carry__1_n_6\,
O(0) => \g81__92_carry__1_n_7\,
S(3) => \g81__92_carry__1_i_1_n_0\,
S(2) => \g81__92_carry__1_i_2_n_0\,
S(1) => \g81__92_carry__1_i_3_n_0\,
S(0) => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__92_carry__1_i_1_n_0\
);
\g81__92_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_2_n_0\
);
\g81__92_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_3_n_0\
);
\g81__92_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__1_n_0\,
CO(3) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__92_carry__2_n_1\,
CO(1) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__92_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__92_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__92_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__92_carry__2_n_6\,
O(0) => \g81__92_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__92_carry__2_i_1_n_0\
);
\g81__92_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__92_carry_i_1_n_0\
);
\g81__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__92_carry_i_2_n_0\
);
\g81__92_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__92_carry_i_3_n_0\
);
\g81__92_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__92_carry_i_4_n_0\
);
\g81__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__92_carry_i_5_n_0\
);
\g81__92_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__92_carry_i_6_n_0\
);
g81_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g81_carry_n_0,
CO(2) => g81_carry_n_1,
CO(1) => g81_carry_n_2,
CO(0) => g81_carry_n_3,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => g81_carry_i_2_n_0,
DI(1) => g81_carry_i_3_n_0,
DI(0) => '0',
O(3 downto 1) => NLW_g81_carry_O_UNCONNECTED(3 downto 1),
O(0) => g81_carry_n_7,
S(3) => g81_carry_i_4_n_0,
S(2) => g81_carry_i_5_n_0,
S(1) => g81_carry_i_6_n_0,
S(0) => g81_carry_i_7_n_0
);
\g81_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g81_carry_n_0,
CO(3) => \g81_carry__0_n_0\,
CO(2) => \g81_carry__0_n_1\,
CO(1) => \g81_carry__0_n_2\,
CO(0) => \g81_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81_carry__0_n_4\,
O(2) => \g81_carry__0_n_5\,
O(1) => \g81_carry__0_n_6\,
O(0) => \NLW_g81_carry__0_O_UNCONNECTED\(0),
S(3) => \g81_carry__0_i_5_n_0\,
S(2) => \g81_carry__0_i_6_n_0\,
S(1) => \g81_carry__0_i_7_n_0\,
S(0) => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
I4 => g83(7),
I5 => \g83__0_carry__0_n_4\,
O => \g81_carry__0_i_1_n_0\
);
\g81_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81_carry__0_i_10_n_0\
);
\g81_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81_carry__0_i_11_n_0\
);
\g81_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
O => \g81_carry__0_i_12_n_0\
);
\g81_carry__0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
O => \g81_carry__0_i_13_n_0\
);
\g81_carry__0_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
O => \g81_carry__0_i_14_n_0\
);
\g81_carry__0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81_carry__0_i_15_n_0\
);
\g81_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_10_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => g83(6),
I5 => \g83__0_carry__0_n_5\,
O => \g81_carry__0_i_2_n_0\
);
\g81_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
I4 => g83(5),
I5 => \g83__0_carry__0_n_6\,
O => \g81_carry__0_i_3_n_0\
);
\g81_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C33CC33CA5A55A5A"
)
port map (
I0 => g83(5),
I1 => \g83__0_carry__0_n_6\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g83__0_carry_n_4\,
I4 => g83(3),
I5 => g84,
O => \g81_carry__0_i_4_n_0\
);
\g81_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81_carry__0_i_5_n_0\
);
\g81_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81_carry__0_i_6_n_0\
);
\g81_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81_carry__0_i_7_n_0\
);
\g81_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81_carry__0_i_9_n_0\
);
\g81_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__0_n_0\,
CO(3) => \g81_carry__1_n_0\,
CO(2) => \g81_carry__1_n_1\,
CO(1) => \g81_carry__1_n_2\,
CO(0) => \g81_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81_carry__1_n_4\,
O(2) => \g81_carry__1_n_5\,
O(1) => \g81_carry__1_n_6\,
O(0) => \g81_carry__1_n_7\,
S(3) => \g81_carry__1_i_5_n_0\,
S(2) => \g81_carry__1_i_6_n_0\,
S(1) => \g81_carry__1_i_7_n_0\,
S(0) => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(7),
I1 => \g83__0_carry__0_n_4\,
I2 => g84,
I3 => g83(9),
I4 => \g83__0_carry__1_n_2\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_1_n_0\
);
\g81_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(6),
I1 => \g83__0_carry__0_n_5\,
I2 => g84,
I3 => g83(8),
I4 => \g83__0_carry__1_n_7\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_2_n_0\
);
\g81_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(5),
I2 => \g83__0_carry__0_n_6\,
I3 => \g81_carry__1_i_9_n_0\,
I4 => g83(9),
I5 => \g83__0_carry__1_n_2\,
O => \g81_carry__1_i_3_n_0\
);
\g81_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(4),
I2 => \g83__0_carry__0_n_7\,
I3 => \g81_carry__0_i_12_n_0\,
I4 => g83(8),
I5 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_4_n_0\
);
\g81_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_5_n_0\
);
\g81_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_6_n_0\
);
\g81_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_7_n_0\
);
\g81_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_4\,
I1 => g83(7),
I2 => g84,
O => \g81_carry__1_i_9_n_0\
);
\g81_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__1_n_0\,
CO(3) => \NLW_g81_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81_carry__2_n_1\,
CO(1) => \NLW_g81_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81_carry__2_n_6\,
O(0) => \g81_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81_carry__2_i_3_n_0\
);
\g81_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_1_n_0\
);
\g81_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_2_n_0\
);
\g81_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81_carry__2_i_3_n_0\
);
g81_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_1_n_0
);
g81_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => g81_carry_i_2_n_0
);
g81_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => g81_carry_i_3_n_0
);
g81_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => g81_carry_i_4_n_0
);
g81_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => g81_carry_i_5_n_0
);
g81_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_6_n_0
);
g81_carry_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => g81_carry_i_7_n_0
);
\g83__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g83__0_carry_n_0\,
CO(2) => \g83__0_carry_n_1\,
CO(1) => \g83__0_carry_n_2\,
CO(0) => \g83__0_carry_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry_i_1_n_0\,
DI(2) => \g83__0_carry_i_2_n_0\,
DI(1) => \g83__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \g83__0_carry_n_4\,
O(2) => \g83__0_carry_n_5\,
O(1) => \g83__0_carry_n_6\,
O(0) => \g83__0_carry_n_7\,
S(3) => \g83__0_carry_i_4_n_0\,
S(2) => \g83__0_carry_i_5_n_0\,
S(1) => \g83__0_carry_i_6_n_0\,
S(0) => \g83__0_carry_i_7_n_0\
);
\g83__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry_n_0\,
CO(3) => \g83__0_carry__0_n_0\,
CO(2) => \g83__0_carry__0_n_1\,
CO(1) => \g83__0_carry__0_n_2\,
CO(0) => \g83__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry__0_i_1_n_0\,
DI(2) => \g83__0_carry__0_i_2_n_0\,
DI(1) => \g83__0_carry__0_i_3_n_0\,
DI(0) => \g83__0_carry__0_i_4_n_0\,
O(3) => \g83__0_carry__0_n_4\,
O(2) => \g83__0_carry__0_n_5\,
O(1) => \g83__0_carry__0_n_6\,
O(0) => \g83__0_carry__0_n_7\,
S(3) => \g83__0_carry__0_i_5_n_0\,
S(2) => \g83__0_carry__0_i_6_n_0\,
S(1) => \g83__0_carry__0_i_7_n_0\,
S(0) => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
O => \g83__0_carry__0_i_1_n_0\
);
\g83__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
O => \g83__0_carry__0_i_2_n_0\
);
\g83__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
O => \g83__0_carry__0_i_3_n_0\
);
\g83__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
O => \g83__0_carry__0_i_4_n_0\
);
\g83__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry__0_i_1_n_0\,
I1 => rgb888(7),
I2 => rgb888(15),
I3 => rgb888(23),
O => \g83__0_carry__0_i_5_n_0\
);
\g83__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
I3 => \g83__0_carry__0_i_2_n_0\,
O => \g83__0_carry__0_i_6_n_0\
);
\g83__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
I3 => \g83__0_carry__0_i_3_n_0\,
O => \g83__0_carry__0_i_7_n_0\
);
\g83__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
I3 => \g83__0_carry__0_i_4_n_0\,
O => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry__0_n_0\,
CO(3 downto 2) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \g83__0_carry__1_n_2\,
CO(0) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_g83__0_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \g83__0_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(15),
I1 => rgb888(7),
I2 => rgb888(23),
O => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
O => \g83__0_carry_i_1_n_0\
);
\g83__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
O => \g83__0_carry_i_2_n_0\
);
\g83__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_3_n_0\
);
\g83__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
I3 => \g83__0_carry_i_1_n_0\,
O => \g83__0_carry_i_4_n_0\
);
\g83__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
I3 => \g83__0_carry_i_2_n_0\,
O => \g83__0_carry_i_5_n_0\
);
\g83__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
I3 => \g83__0_carry_i_3_n_0\,
O => \g83__0_carry_i_6_n_0\
);
\g83__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_7_n_0\
);
g84_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g84_carry_n_0,
CO(2) => g84_carry_n_1,
CO(1) => g84_carry_n_2,
CO(0) => g84_carry_n_3,
CYINIT => '1',
DI(3) => g84_carry_i_1_n_0,
DI(2) => g84_carry_i_2_n_0,
DI(1) => g84_carry_i_3_n_0,
DI(0) => g84_carry_i_4_n_0,
O(3 downto 0) => NLW_g84_carry_O_UNCONNECTED(3 downto 0),
S(3) => g84_carry_i_5_n_0,
S(2) => g84_carry_i_6_n_0,
S(1) => g84_carry_i_7_n_0,
S(0) => g84_carry_i_8_n_0
);
\g84_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g84_carry_n_0,
CO(3 downto 1) => \NLW_g84_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => g84,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \g84_carry__0_i_1_n_0\,
O(3 downto 0) => \NLW_g84_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \g84_carry__0_i_2_n_0\
);
\g84_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_1_n_0\
);
\g84_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_2_n_0\
);
g84_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_1_n_0
);
g84_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_2_n_0
);
g84_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_3_n_0
);
g84_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_4_n_0
);
g84_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_5_n_0
);
g84_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_6_n_0
);
g84_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_7_n_0
);
g84_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_8_n_0
);
\g8[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_7\,
O => g810_in(0)
);
\g8[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_6\,
O => g810_in(1)
);
\g8[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_5\,
O => g810_in(2)
);
\g8[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_4\,
O => g810_in(3)
);
\g8[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_7\,
O => g810_in(4)
);
\g8[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_6\,
O => g810_in(5)
);
\g8[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_5\,
O => g810_in(6)
);
\g8[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_4\,
O => g810_in(7)
);
\g8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(0),
Q => g8(0),
R => '0'
);
\g8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(1),
Q => g8(1),
R => '0'
);
\g8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(2),
Q => g8(2),
R => '0'
);
\g8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(3),
Q => g8(3),
R => '0'
);
\g8_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(4),
Q => g8(4),
R => '0'
);
\g8_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(5),
Q => g8(5),
R => '0'
);
\g8_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(6),
Q => g8(6),
R => '0'
);
\g8_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(7),
Q => g8(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_g8_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_g8_0_0 : entity is "system_rgb888_to_g8_0_0,rgb888_to_g8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_g8_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_g8_0_0 : entity is "rgb888_to_g8,Vivado 2016.4";
end system_rgb888_to_g8_0_0;
architecture STRUCTURE of system_rgb888_to_g8_0_0 is
begin
U0: entity work.system_rgb888_to_g8_0_0_rgb888_to_g8
port map (
clk => clk,
g8(7 downto 0) => g8(7 downto 0),
rgb888(23 downto 0) => rgb888(23 downto 0)
);
end STRUCTURE;
| mit | 461e146a382ca1a5278ccdbc0b174659 | 0.491835 | 2.249335 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/clock_splitter/clock_splitter.srcs/sources_1/new/clock_splitter.vhd | 6 | 782 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_splitter is
port (
clk_in : in std_logic;
latch_edge : in std_logic;
clk_out : out std_logic
);
end clock_splitter;
architecture Behavioral of clock_splitter is
signal clk : std_logic := '0';
signal last_edge : std_logic := '0';
begin
clk_out <= clk;
process(clk_in)
begin
if rising_edge(clk_in) then
if clk = '0' then
last_edge <= latch_edge;
clk <= not clk;
else
if last_edge = latch_edge then
clk <= not clk;
else
last_edge <= latch_edge;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 47d6b23658226e6e93fc1a2268bbd097 | 0.496164 | 3.969543 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/vga_hdmi.vhd | 1 | 7,976 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Module Name: vga_hdmi - Behavioral
--
-- Description: A test of the Zedboard's VGA & HDMI interface
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity vga_hdmi is
port(
clk100 : in std_logic;
clk25 : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
vsync : in std_logic;
hsync : in std_logic;
active : in std_logic;
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic);
end vga_hdmi;
architecture Behavioral of vga_hdmi is
COMPONENT convert_444_422
PORT( clk : IN std_logic;
r_in : IN std_logic_vector(7 downto 0);
g_in : IN std_logic_vector(7 downto 0);
b_in : IN std_logic_vector(7 downto 0);
hsync_in : IN std_logic;
vsync_in : IN std_logic;
de_in : IN std_logic;
r1_out : OUT std_logic_vector(8 downto 0);
g1_out : OUT std_logic_vector(8 downto 0);
b1_out : OUT std_logic_vector(8 downto 0);
r2_out : OUT std_logic_vector(8 downto 0);
g2_out : OUT std_logic_vector(8 downto 0);
b2_out : OUT std_logic_vector(8 downto 0);
pair_start_out: OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic;
de_out : OUT std_logic
);
END COMPONENT;
COMPONENT colour_space_conversion
PORT( clk : IN std_logic;
r1_in : IN std_logic_vector(8 downto 0);
g1_in : IN std_logic_vector(8 downto 0);
b1_in : IN std_logic_vector(8 downto 0);
r2_in : IN std_logic_vector(8 downto 0);
g2_in : IN std_logic_vector(8 downto 0);
b2_in : IN std_logic_vector(8 downto 0);
pair_start_in: IN std_logic;
de_in : IN std_logic;
vsync_in : IN std_logic;
hsync_in : IN std_logic;
y_out : OUT std_logic_vector(7 downto 0);
c_out : OUT std_logic_vector(7 downto 0);
de_out : OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic
);
END COMPONENT;
COMPONENT hdmi_ddr_output
PORT(
clk : IN std_logic;
clk90 : IN std_logic;
y : IN std_logic_vector(7 downto 0);
c : IN std_logic_vector(7 downto 0);
hsync_in : IN std_logic;
vsync_in : IN std_logic;
de_in : IN std_logic;
hdmi_sda : INOUT std_logic;
hdmi_clk : OUT std_logic;
hdmi_hsync : OUT std_logic;
hdmi_vsync : OUT std_logic;
hdmi_d : OUT std_logic_vector(15 downto 0);
hdmi_de : OUT std_logic;
hdmi_scl : OUT std_logic
);
END COMPONENT;
-- Clocking
signal clk0 : std_logic;
signal clk90 : std_logic;
signal clkfb : std_logic;
-- Signals from the pixel pair convertor
signal c422_r1 : std_logic_vector(8 downto 0);
signal c422_g1 : std_logic_vector(8 downto 0);
signal c422_b1 : std_logic_vector(8 downto 0);
signal c422_r2 : std_logic_vector(8 downto 0);
signal c422_g2 : std_logic_vector(8 downto 0);
signal c422_b2 : std_logic_vector(8 downto 0);
signal c422_pair_start : std_logic;
signal c422_hsync : std_logic;
signal c422_vsync : std_logic;
signal c422_de : std_logic;
-- Signals from the colour space convertor
signal csc_y : std_logic_vector(7 downto 0);
signal csc_c : std_logic_vector(7 downto 0);
signal csc_hsync : std_logic;
signal csc_vsync : std_logic;
signal csc_de : std_logic;
-- signals from the output range clampler
signal clamper_c : std_logic_vector(7 downto 0);
signal clamper_y : std_logic_vector(7 downto 0);
signal clamper_hsync : std_logic;
signal clamper_vsync : std_logic;
signal clamper_de : std_logic;
begin
i_convert_444_422: convert_444_422 PORT MAP(
clk => clk25,
r_in => rgb888(23 downto 16),
g_in => rgb888(15 downto 8),
b_in => rgb888(7 downto 0),
hsync_in => hsync,
vsync_in => vsync,
de_in => active,
r1_out => c422_r1,
g1_out => c422_g1,
b1_out => c422_b1,
r2_out => c422_r2,
g2_out => c422_g2,
b2_out => c422_b2,
pair_start_out => c422_pair_start,
hsync_out => c422_hsync,
vsync_out => c422_vsync,
de_out => c422_de
);
i_csc: colour_space_conversion PORT MAP(
clk => clk25,
r1_in => c422_r1,
g1_in => c422_g1,
b1_in => c422_b1,
r2_in => c422_r2,
g2_in => c422_g2,
b2_in => c422_b2,
pair_start_in => c422_pair_start,
vsync_in => c422_vsync,
hsync_in => c422_hsync,
de_in => c422_de,
y_out => csc_y,
c_out => csc_c,
hsync_out => csc_hsync,
vsync_out => csc_vsync,
de_out => csc_de
);
clamper_y <= csc_y;
clamper_c <= csc_c;
clamper_de <= csc_de;
clamper_hsync <= csc_hsync;
clamper_vsync <= csc_vsync;
i_hdmi_ddr_output: hdmi_ddr_output PORT MAP(
clk => clk25,
clk90 => clk90,
y => clamper_y,
c => clamper_c,
hsync_in => clamper_hsync,
vsync_in => clamper_vsync,
de_in => clamper_de,
hdmi_clk => hdmi_clk,
hdmi_hsync => hdmi_hsync,
hdmi_vsync => hdmi_vsync,
hdmi_d => hdmi_d,
hdmi_de => hdmi_de,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
-- Generate a 75MHz pixel clock and one with 90 degree phase shift from the 100MHz system clock.
PLLE2_BASE_inst : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 9, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 10.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 9,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 12,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 135.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk0,
CLKOUT1 => open,
CLKOUT2 => clk90,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfb, -- 1-bit output: Feedback clock
LOCKED => open, -- 1-bit output: LOCK
CLKIN1 => clk100, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => clkfb -- 1-bit input: Feedback clock
);
end Behavioral;
| mit | 92ba409c6c5f2ea8eb526dbf6bacbb93 | 0.553159 | 3.054768 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/sim/system_vga_gaussian_blur_0_0.vhd | 1 | 3,890 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_0_0;
ARCHITECTURE system_vga_gaussian_blur_0_0_arch OF system_vga_gaussian_blur_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
clk_25 => clk_25,
hsync_in => hsync_in,
vsync_in => vsync_in,
rgb_in => rgb_in,
hsync_out => hsync_out,
vsync_out => vsync_out,
rgb_blur => rgb_blur,
rgb_pass => rgb_pass
);
END system_vga_gaussian_blur_0_0_arch;
| mit | bd108a5951da5f2f993e6a9626fd0386 | 0.703085 | 3.736792 | false | false | false | false |
quicky2000/bit_delay | bit_delay.vhd | 1 | 1,954 | --
-- This file is part of bit_delay
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bit_delay is
generic (
size : natural := 1); -- size of delay
port (
clk : in std_logic; -- clock
rst : in std_logic; --rst
input : in std_logic; -- input
output : out std_logic); -- output
end bit_delay;
architecture behavourial of bit_delay is
-- signal delayed_output : std_logic_vector(size downto 0) := (others => '0'); -- delayed output
type buffer_t is array (0 to size) of std_logic;
signal delayed_output : buffer_t := (others => '0'); -- delayed output
begin -- behavourial
delayed_output(0) <= input;
size_non_zero : if size > 0 generate
delay_loop: for i in 0 to size -1 generate
inst: entity work.single_delay
port map (
clk => clk,
rst => rst,
input => delayed_output(i),
output => delayed_output(i+1));
end generate delay_loop;
output <= delayed_output(size);
end generate size_non_zero;
size_zero: if size = 0 generate
output <= input;
end generate size_zero;
end behavourial;
| gpl-3.0 | 1fd54fcfb403872819715f61fa9fc471 | 0.634596 | 3.801556 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_2/synth/affine_block_ieee754_fp_multiplier_1_2.vhd | 2 | 4,008 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_2 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_2;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_2_arch OF affine_block_ieee754_fp_multiplier_1_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "ieee754_fp_multiplier,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_multiplier_1_2_arch : ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_2,ieee754_fp_multiplier,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_2,ieee754_fp_multiplier,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_multiplier,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_2_arch;
| mit | 006ed7e5d5ba62dd93e4ed5969bd7f90 | 0.749251 | 3.802657 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd | 1 | 8,495 | -- niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 101;
FIFO_DEPTH : integer := 2;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 1;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 1;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(100 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
out_data : out std_logic_vector(100 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
out_endofpacket : out std_logic; -- .endofpacket
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_error : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_error : out std_logic
);
end entity niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
architecture rtl of niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(100 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
out_endofpacket => out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
| apache-2.0 | 71cdda73e9cdb61b46aafe216cb50616 | 0.432137 | 3.96222 | false | false | false | false |
loa-org/loa-hdl | modules/encoder/tb/quadrature_decoder_tb.vhd | 2 | 4,087 | -------------------------------------------------------------------------------
-- Title : Testbench for design "quadrature_decoder"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.quadrature_decoder_pkg.all;
use work.encoder_module_pkg.all;
-------------------------------------------------------------------------------
entity quadrature_decoder_tb is
end quadrature_decoder_tb;
-------------------------------------------------------------------------------
architecture tb of quadrature_decoder_tb is
type input_type is record
a : std_logic;
b : std_logic;
end record;
type expect_type is record
step : std_logic;
dir : std_logic;
error : std_logic;
end record;
type stimulus_type is record
input : input_type;
expect : expect_type;
end record;
type stimuli_type is array (natural range <>) of stimulus_type;
constant stimuli : stimuli_type := (
(input => ('0', '0'), expect => ('0', '-', '0')),
(input => ('1', '0'), expect => ('1', '1', '0')),
(input => ('1', '0'), expect => ('0', '-', '0')),
(input => ('1', '1'), expect => ('1', '1', '0')),
(input => ('0', '1'), expect => ('1', '1', '0')),
(input => ('0', '0'), expect => ('1', '1', '0')),
(input => ('1', '0'), expect => ('1', '1', '0')),
(input => ('1', '1'), expect => ('1', '1', '0')),
(input => ('1', '1'), expect => ('0', '-', '0')),
(input => ('1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('1', '0', '0')),
(input => ('1', '0'), expect => ('1', '1', '0')),
(input => ('0', '0'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('0', '-', '0')),
(input => ('0', '1'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('1', '1', '0')),
(input => ('0', '1'), expect => ('1', '0', '0')),
(input => ('1', '1'), expect => ('1', '0', '0')),
(input => ('1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('1', '0', '0')),
(input => ('1', '1'), expect => ('0', '-', '1')),
(input => ('0', '0'), expect => ('0', '-', '1')),
(input => ('0', '1'), expect => ('1', '0', '0')),
(input => ('1', '1'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('0', '-', '1')),
(input => ('0', '0'), expect => ('0', '0', '0'))
);
-- component ports
signal ab : encoder_type := (a => '0', b => '0');
signal step : std_logic;
signal dir : std_logic;
signal error : std_logic;
-- clock
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : quadrature_decoder
port map (
encoder_p => ab,
step_p => step,
dir_p => dir,
error_p => error,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
wave : process
begin
wait for 20 ns;
for i in stimuli'left to (stimuli'right + 2) loop
wait until rising_edge(clk);
if i <= stimuli'right then
ab.a <= stimuli(i).input.a;
ab.b <= stimuli(i).input.b;
else
ab.a <= '0';
ab.b <= '0';
end if;
if i > (stimuli'left + 2) then
-- values are active at the output after two clock cycles
assert (step = stimuli(i-2).expect.step) report "Wrong value for 'step'" severity note;
if not (stimuli(i-2).expect.dir = '-') then
assert (dir = stimuli(i-2).expect.dir) report "Wrong value for 'dir'" severity note;
end if;
assert (error = stimuli(i-2).expect.error) report "Wrong value for 'error'" severity note;
end if;
end loop; -- i
end process wave;
end tb;
| bsd-3-clause | e7cdf8427141795a13222a421cfa1137 | 0.41473 | 3.544666 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/signalprocessing_pkg.vhd | 2 | 6,015 | -------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
package signalprocessing_pkg is
constant CALC_WIDTH : natural := 18; -- Width of all calculations.
constant INPUT_WIDTH : natural := 14; -- Width of ADC values
-- All calculations are based on that type:
subtype goertzel_data_type is signed(CALC_WIDTH-1 downto 0);
-- The result of the Goertzel Algorithm are always a pair of two values
type goertzel_result_type is array (1 downto 0) of goertzel_data_type;
-- The result for more channels and frequencies:
type goertzel_results_type is array (natural range <>, natural range <>) of goertzel_result_type;
-- One input to the algorithm.
subtype goertzel_input_type is signed(INPUT_WIDTH-1 downto 0);
-- The input for many different channels
type goertzel_inputs_type is array (natural range <>) of goertzel_input_type;
-- One goertzel coefficient corresponds to a certain frequency.
subtype goertzel_coef_type is signed(CALC_WIDTH-1 downto 0);
-- The input for different frequencies
type goertzel_coefs_type is array (natural range <>) of goertzel_coef_type;
component goertzel
generic (
Q : natural;
SAMPLES : natural
);
port (
clk : in std_logic;
coef_p : in unsigned(17 downto 0);
start_p : in std_logic;
adc_value_p : in signed(13 downto 0);
result_p : out goertzel_result_type;
done_p : out std_logic
);
end component;
component goertzel_pipelined
generic (
Q : natural;
CHANNELS : natural;
FREQUENCIES : natural;
SAMPLES : natural);
port (
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
start_p : in std_logic;
results_p : out goertzel_results_type;
done_p : out std_logic;
clk : in std_logic);
end component;
----------------------------------------------------------------------------
-- New version, consists of pipeline, muxes and control_unit
----------------------------------------------------------------------------
component goertzel_pipeline is
generic (
Q : natural);
port (
coef_p : in goertzel_coef_type;
input_p : in goertzel_input_type;
delay_p : in goertzel_result_type;
result_p : out goertzel_result_type;
clk : in std_logic);
end component goertzel_pipeline;
component goertzel_muxes is
generic (
CHANNELS : positive;
FREQUENCIES : positive);
port (
mux_delay1_p : in std_logic;
mux_delay2_p : in std_logic;
mux_coef : in natural range FREQUENCIES-1 downto 0;
mux_input : in natural range CHANNELS-1 downto 0;
bram_data : in goertzel_result_type;
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
delay1_p : out goertzel_data_type;
delay2_p : out goertzel_data_type;
coef_p : out goertzel_coef_type;
input_p : out goertzel_input_type);
end component goertzel_muxes;
component goertzel_control_unit is
generic (
SAMPLES : positive;
FREQUENCIES : positive;
CHANNELS : positive);
port (
start_p : in std_logic;
ready_p : out std_logic := '0';
bram_addr_p : out std_logic_vector(7 downto 0) := (others => '0');
bram_we_p : out std_logic := '0';
mux_delay1_p : out std_logic := '0';
mux_delay2_p : out std_logic := '0';
mux_coef_p : out natural range FREQUENCIES-1 downto 0 := 0;
mux_input_p : out natural range CHANNELS-1 downto 0 := 0;
clk : in std_logic);
end component goertzel_control_unit;
component goertzel_pipelined_v2 is
generic (
FREQUENCIES : positive;
CHANNELS : positive;
SAMPLES : positive;
Q : positive);
port (
start_p : in std_logic;
bram_addr_p : out std_logic_vector(7 downto 0);
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_we_p : out std_logic;
ready_p : out std_logic;
enable_p : in std_logic;
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
clk : in std_logic);
end component goertzel_pipelined_v2;
----------------------------------------------------------------------------
-- Helpers
----------------------------------------------------------------------------
constant TIMESTAMP_WIDTH : natural := 48; -- 2**48 - 1 * 20 us = 65 days. This counter will not overflow.
subtype timestamp_type is signed(TIMESTAMP_WIDTH-1 downto 0);
component timestamp_generator is
port (
timestamp_o_p : out timestamp_type;
clk : in std_logic);
end component timestamp_generator;
component timestamp_taker is
generic (
BASE_ADDRESS : integer);
port (
timestamp_i_p : in timestamp_type;
trigger_i_p : in std_logic;
bank_x_i_p : in std_logic;
bank_y_i_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
end signalprocessing_pkg;
| bsd-3-clause | 9e4a55749550651681aa452f2cf2813e | 0.5202 | 3.959842 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl | 1 | 17,775 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:48:16 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
active : out STD_LOGIC;
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync";
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active_INST_0_i_1_n_0 : STD_LOGIC;
signal h_count_next : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \h_count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[5]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal h_sync_next : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal v_sync_next : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair0";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"000002AA"
)
port map (
I0 => active_INST_0_i_1_n_0,
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
I3 => \^xaddr\(9),
I4 => \^yaddr\(9),
O => active
);
active_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
O => active_INST_0_i_1_n_0
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => h_count_next(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => h_count_next(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
I2 => \^xaddr\(2),
O => h_count_next(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(2),
O => h_count_next(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(1),
I3 => \^xaddr\(0),
I4 => \^xaddr\(3),
O => \h_count_reg[4]_i_1_n_0\
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00000000FFBF"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(8),
I2 => \^xaddr\(9),
I3 => \^xaddr\(7),
I4 => \h_count_reg[5]_i_2_n_0\,
I5 => \^xaddr\(5),
O => h_count_next(5)
);
\h_count_reg[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(3),
I4 => \^xaddr\(4),
O => \h_count_reg[5]_i_2_n_0\
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(4),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
O => h_count_next(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
I4 => \^xaddr\(6),
O => h_count_next(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0B00B0"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(4),
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => h_count_next(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FBFBFB0B000000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(4),
I2 => \h_count_reg[9]_i_3_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \^xaddr\(8),
I5 => \^xaddr\(9),
O => h_count_next(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFEFFF"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(2),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => \h_count_reg[4]_i_1_n_0\,
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(8),
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(9),
Q => \^xaddr\(9)
);
h_sync_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00002AA800000000"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
I4 => \^xaddr\(8),
I5 => \^xaddr\(9),
O => h_sync_next
);
h_sync_reg_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => h_sync_next,
PRE => rst,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => p_0_in(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55AA55AA45AA55AA"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFAA0045FFAA00"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(3)
);
\v_count_reg[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \v_count_reg[3]_i_2_n_0\
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => p_0_in(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => p_0_in(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_5_n_0\,
I2 => \^yaddr\(5),
O => \v_count_reg[6]_i_1_n_0\
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(6),
O => p_0_in(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(5),
I4 => \^yaddr\(7),
O => p_0_in(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[5]_i_2_n_0\,
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"D0D00DD0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => active_INST_0_i_1_n_0,
O => p_0_in(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(7),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
I4 => \^yaddr\(4),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => \v_count_reg[6]_i_1_n_0\,
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(9),
Q => \^yaddr\(9)
);
v_sync_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(3),
I2 => \^yaddr\(4),
I3 => \^yaddr\(2),
I4 => \^yaddr\(1),
I5 => active_INST_0_i_1_n_0,
O => v_sync_next
);
v_sync_reg_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => v_sync_next,
PRE => rst,
Q => vsync
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk_25 => clk_25,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 9fcec88c20e9ce2a9a1f05cb7454335f | 0.490577 | 2.755814 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s2.vhd | 2 | 3,979 | library ieee;
use ieee.std_logic_1164.all;
entity s2 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s2;
architecture behaviour of s2 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
end case;
end process;
end; | mit | 5674257af513986bec1b0738a787d783 | 0.673536 | 3.030465 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ipshared/xilinx.com/vga_gaussian_blur_v1_0/vga_gaussian_blur.vhd | 1 | 4,511 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_gaussian_blur - Structural
-- Description: Blur an input image stream and sync with output
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga_gaussian_blur is
generic(
H_SIZE : integer := 640;
H_DELAY : integer := 160;
KERNEL : integer := 3
);
port(
en : in std_logic;
clk_25 : in std_logic;
active_in : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
xaddr_in : in std_logic_vector(9 downto 0);
yaddr_in : in std_logic_vector(9 downto 0);
rgb_in : in std_logic_vector(23 downto 0);
active_out : out std_logic;
hsync_out : out std_logic;
vsync_out : out std_logic;
xaddr_out : out std_logic_vector(9 downto 0);
yaddr_out : out std_logic_vector(9 downto 0);
rgb_out : out std_logic_vector(23 downto 0)
);
end vga_gaussian_blur;
architecture Structural of vga_gaussian_blur is
type RGB_BUFFER is array ((H_SIZE+H_DELAY)*(KERNEL-1) + KERNEL - 1 downto 0) of std_logic_vector(23 downto 0);
type ADDR_BUFFER is array ((H_SIZE+H_DELAY)*(KERNEL-1) + KERNEL - 1 downto 0) of std_logic_vector(9 downto 0);
type FLAGS_BUFFER is array ((H_SIZE+H_DELAY)*(KERNEL-1) + KERNEL - 1 downto 0) of std_logic_vector(2 downto 0);
type INT_ARRAY is array (integer range<>) of integer;
begin
process(clk_25)
variable rgb_buffer_1 : RGB_BUFFER;
variable addr_buffer_x1 : ADDR_BUFFER;
variable addr_buffer_y1 : ADDR_BUFFER;
variable flags_buffer_1 : FLAGS_BUFFER;
variable temp : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable compute : integer := 0;
begin
if rising_edge(clk_25) then
if en = '1' then
temp(0) := to_integer(unsigned(rgb_buffer_1(0)));
temp(1) := to_integer(unsigned(rgb_buffer_1(1)));
temp(2) := to_integer(unsigned(rgb_buffer_1(2)));
temp(3) := to_integer(unsigned(rgb_buffer_1(H_SIZE+H_DELAY)));
temp(4) := to_integer(unsigned(rgb_buffer_1(H_SIZE+H_DELAY+1)));
temp(5) := to_integer(unsigned(rgb_buffer_1(H_SIZE+H_DELAY+2)));
temp(6) := to_integer(unsigned(rgb_buffer_1(2*(H_SIZE+H_DELAY))));
temp(7) := to_integer(unsigned(rgb_buffer_1(2*(H_SIZE+H_DELAY)+1)));
temp(8) := to_integer(unsigned(rgb_buffer_1(2*(H_SIZE+H_DELAY)+2)));
compute := (temp(0) + 2*temp(1) + temp(2) + 2*temp(3) + 4*temp(4) + 2*temp(5) + temp(6) + 2*temp(7) + temp(8))/16;
rgb_out <= std_logic_vector(to_unsigned(compute, 24));
xaddr_out <= addr_buffer_x1(H_SIZE+H_DELAY+1);
yaddr_out <= addr_buffer_y1(H_SIZE+H_DELAY+1);
active_out <= flags_buffer_1(H_SIZE+H_DELAY+1)(2);
hsync_out <= flags_buffer_1(H_SIZE+H_DELAY+1)(1);
vsync_out <= flags_buffer_1(H_SIZE+H_DELAY+1)(0);
for i in (H_SIZE+H_DELAY)*(KERNEL-1) + KERNEL - 1 downto 1 loop
rgb_buffer_1(i) := rgb_buffer_1(i-1);
addr_buffer_x1(i) := addr_buffer_x1(i-1);
addr_buffer_y1(i) := addr_buffer_y1(i-1);
flags_buffer_1(i) := flags_buffer_1(i-1);
end loop;
rgb_buffer_1(0) := rgb_in;
addr_buffer_x1(0) := xaddr_in;
addr_buffer_y1(0) := yaddr_in;
flags_buffer_1(0) := (2 => active_in, 1 => hsync_in, 0 => vsync_in);
else
rgb_out <= rgb_in;
xaddr_out <= xaddr_in;
yaddr_out <= yaddr_in;
active_out <= active_in;
hsync_out <= hsync_in;
vsync_out <= vsync_in;
end if;
end if;
end process;
end Structural;
| mit | 8ba4a37aa9f59446351bb6f9d4a9df07 | 0.532476 | 3.427812 | false | false | false | false |
loa-org/loa-hdl | modules/adc_mcp3008/hdl/adc_mcp3008_module.vhd | 2 | 5,337 | -------------------------------------------------------------------------------
-- Title : Bus Module for ADC MCP3008
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_mcp3008_pkg.all;
-------------------------------------------------------------------------------
entity adc_mcp3008_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
adc_out_p : out adc_mcp3008_spi_out_type;
adc_in_p : in adc_mcp3008_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- direct access to the read adc samples
adc_values_o : out adc_mcp3008_values_type(7 downto 0);
clk : in std_logic
);
end adc_mcp3008_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_mcp3008_module is
type adc_mcp3008_module_state_type is (IDLE, WAIT_FOR_ADC);
type adc_mcp3008_module_type is record
state : adc_mcp3008_module_state_type;
start : std_logic;
current_ch : integer range 0 to 7;
reg : reg_file_type(7 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_mcp3008_module_type := (state => IDLE,
current_ch => 7,
start => '0',
reg => (others => (others => '0')));
signal adc_mode_s : std_logic;
signal channel_s : std_logic_vector(2 downto 0);
signal value_s : std_logic_vector(9 downto 0);
signal done_s : std_logic;
signal reg_o : reg_file_type(7 downto 0);
signal reg_i : reg_file_type(7 downto 0);
signal mask_s : std_logic_vector(7 downto 0);
begin
-- mapping signals to adc i/f
adc_mode_s <= '1'; -- we don't use differential mode
channel_s <= std_logic_vector(to_unsigned(r.current_ch, 3));
reg_i <= r.reg;
-- present last value of each channel on this modules ports
copy_loop : for ii in 0 to 7 generate
adc_values_o(ii) <= r.reg(ii)(9 downto 0);
end generate copy_loop;
-- register for channel mask
mask_s <= reg_o(0)(7 downto 0);
-----------------------------------------------------------------------------
-- seq part of FSM
-----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actiosn of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, mask_s, r, value_s)
variable v : adc_mcp3008_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- in this state we iterate over the channels
if v.current_ch = 7 then
-- we wrap around (to 0)
v.current_ch := 0;
else
-- or increment the currently selected channel
v.current_ch := v.current_ch + 1;
end if;
-- if the channel isn't masked out, we take a sample
if mask_s(v.current_ch) = '0' then
v.start := '1';
v.state := WAIT_FOR_ADC;
end if;
when WAIT_FOR_ADC =>
-- adc i/f has already started conversion, we stay in this state until
-- the conversion is over.
v.start := '0';
if done_s = '1' then
-- if the conversion is done we put its result in the right register,
-- and return to the "idle" state.
v.reg(v.current_ch) := "000000" & value_s;
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-- and configuration
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => 3)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- ADC interface module
adc_mcp3008_1 : adc_mcp3008
generic map (
DELAY => 39)
port map (
adc_out => adc_out_p,
adc_in => adc_in_p,
start_p => r.start,
adc_mode_p => adc_mode_s,
channel_p => channel_s,
value_p => value_s,
done_p => done_s,
clk => clk);
end behavioral;
| bsd-3-clause | 120af670882d7a2e6de7d3047d963f38 | 0.423646 | 4.396211 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/dc_motor_module.vhd | 2 | 3,922 | -------------------------------------------------------------------------------
-- Title : Motor control for DC Motors
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a symmetric (center-aligned) PWM without deadtime
--
-- Register Map:
-- Base Address + 0 | W | PWM
-- Base Address + 0 | R | unused
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all;
use work.symmetric_pwm_pkg.all;
entity dc_motor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
WIDTH : positive := 12; -- Number of bits for the PWM generation (e.g. 12 => 0..4095)
PRESCALER : positive
);
port (
pwm1_p : out std_logic; -- Halfbridge 1
pwm2_p : out std_logic; -- Halfbridge 2
sd_p : out std_logic; -- Shutdown
-- Disable switching
break_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end dc_motor_module;
-------------------------------------------------------------------------------
architecture behavioral of dc_motor_module is
type dc_motor_module_type is record
data_out : std_logic_vector(15 downto 0); -- currently not used
pwm_value : std_logic_vector(WIDTH - 1 downto 0); -- PWM value
sd : std_logic; -- Shutdown
end record;
signal clk_en : std_logic := '1';
signal underflow : std_logic; -- currently not used
signal overflow : std_logic; -- currently not used
signal pwm : std_logic;
signal r, rin : dc_motor_module_type := (
data_out => (others => '0'),
pwm_value => (others => '0'),
sd => '1'
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i.addr, bus_i.data(15),
bus_i.data(WIDTH - 1 downto 0), bus_i.re, bus_i.we, pwm, break_p,
r, r.sd)
variable v : dc_motor_module_type;
begin
v := r;
-- Set default values
v.data_out := (others => '0');
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
v.pwm_value := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
elsif bus_i.re = '1' then
-- v.data_out := r.counter;
end if;
end if;
if r.sd = '1' then
pwm1_p <= '0';
pwm2_p <= '0';
sd_p <= '1';
else
if break_p = '1' then
pwm1_p <= '0';
pwm2_p <= '0';
else
pwm1_p <= pwm;
pwm2_p <= not pwm;
end if;
sd_p <= '0';
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
pwm_generator : symmetric_pwm
generic map (
WIDTH => WIDTH)
port map (
pwm_p => pwm,
underflow_p => underflow,
overflow_p => overflow,
clk_en_p => clk_en,
value_p => r.pwm_value,
reset => '0',
clk => clk);
end behavioral;
| bsd-3-clause | 8a2b22b9cc6686a9f792338423282a2b | 0.459714 | 3.763916 | false | false | false | false |
CampbellGroup/fpga | ltc1450/control2.vhd | 1 | 1,164 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY signal_generator IS
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC; --unused
led: OUT STD_LOGIC;
clock_out : OUT STD_LOGIC;
pin_0_out: OUT STD_LOGIC);
END signal_generator;
ARCHITECTURE behavior of signal_generator IS
SIGNAL clk_sig : std_logic;
SIGNAL led_sig : std_logic;
--pin 0
constant pin_0_vector: STD_LOGIC_VECTOR(15 downto 0):= "0000000000001010"; --assign 12 (decimal)
SIGNAL pin_0_sig: std_logic;
BEGIN
PROCESS(clk)
VARIABLE count1 : integer;
VARIABLE count2 : integer;
VARIABLE pin_0_index: integer;
BEGIN
IF rising_edge(clk) then
IF (count1=500) THEN
clk_sig<=NOT(clk_sig);
pin_0_sig<=pin_0_vector(pin_0_index);
pin_0_index:=pin_0_index+1;
IF (pin_0_index=16) THEN
pin_0_index:=0;
END IF;
count1:=0;
ELSE
count1:=count1+1;
END IF;
IF (count2=24999999) THEN --((input clock)/2-1)
led_sig<=NOT(led_sig);
count2:=0;
ELSE
count2:=count2+1;
END IF;
END IF;
END PROCESS;
--output values
clock_out <= clk_sig;
led <= led_sig;
pin_0_out <= pin_0_sig;
END behavior;
| mit | a3e2298bca21b44e8b13506488f13afe | 0.670103 | 2.62754 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_sync_reset/vga_sync_reset.srcs/sources_1/new/vga_sync.vhd | 3 | 2,999 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync_reset is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync_reset;
architecture Structural of vga_sync_reset is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk)
begin
if rising_edge(clk) then
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
| mit | a3c69025a363f72b2798749d0f06720b | 0.433478 | 4.102599 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/addsub-rtl.vhdl | 1 | 1,563 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of addsub is
begin
addsub : entity work.addsub_inferred(rtl)
generic map (
src_bits => src_bits
)
port map (
sub => sub,
carryin => carryin,
src1 => src1,
src2 => src2,
result => result,
carryout => carryout,
overflow => overflow
);
end;
| apache-2.0 | 12e9c5ba159b251c02418dc9f20936c5 | 0.475368 | 5.371134 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_2r1w-rtl.vhdl | 1 | 1,739 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_2r1w is
begin
rf : entity work.syncram_2r1w_inferred(rtl)
generic map (
addr_bits => addr_bits,
data_bits => data_bits,
write_first => write_first
)
port map (
clk => clk,
we => we,
waddr => waddr,
wdata => wdata,
re1 => re1,
raddr1 => raddr1,
rdata1 => rdata1,
re2 => re2,
raddr2 => raddr2,
rdata2 => rdata2
);
end;
| apache-2.0 | 1b77c51f3ea198a5602c104d19e0cac9 | 0.488787 | 4.777473 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_cdma_control/vga_cdma_control.srcs/sources_1/new/vga_cdma_control.vhd | 1 | 4,871 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_cdma_control is
port (
clk : in std_logic;
active : in std_logic;
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
rgb888_in : in std_logic_vector(23 downto 0);
rgb888_out : out std_logic_vector(23 downto 0);
aclk : in std_logic;
m_axi_lite_araddr : out std_logic_vector(5 downto 0);
m_axi_lite_arready : in std_logic;
m_axi_lite_arvalid : out std_logic;
m_axi_lite_awaddr : out std_logic_vector(5 downto 0);
m_axi_lite_awready : in std_logic;
m_axi_lite_awvalid : out std_logic;
m_axi_lite_rdata : in std_logic_vector(31 downto 0);
m_axi_lite_rready : out std_logic;
m_axi_lite_rvalid : in std_logic;
m_axi_lite_wdata : out std_logic_vector(31 downto 0);
m_axi_lite_wready : in std_logic;
m_axi_lite_wvalid : out std_logic;
s_axi_rready : out std_logic;
s_axi_rvalid : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_wready : in std_logic;
s_axi_wvalid : out std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0)
);
end vga_cdma_control;
architecture Behavioral of vga_cdma_control is
signal state : std_logic_vector(1 downto 0) := "00";
signal last_clk : std_logic := '1';
signal rgb : std_logic_vector(23 downto 0);
begin
process(aclk)
begin
if rising_edge(aclk) then
if s_axi_wready = '1' then
s_axi_wvalid <= '0';
end if;
if s_axi_rvalid = '1' then
-- read data
rgb <= s_axi_rdata(23 downto 0);
s_axi_rready <= '0';
end if;
if state = "00" then
m_axi_lite_arvalid <= '0';
m_axi_lite_awvalid <= '0';
m_axi_lite_rready <= '0';
m_axi_lite_wvalid <= '0';
if last_clk = '0' and clk = '1' and active = '1' then
-- latch on rising clock
rgb888_out <= rgb;
state <= "01";
end if;
elsif state = "01" then
if m_axi_lite_arready = '1' or m_axi_lite_rvalid = '1' then
if m_axi_lite_arready = '1' then
m_axi_lite_arvalid <= '0';
end if;
if m_axi_lite_rvalid = '1' then
m_axi_lite_rready <= '0';
if m_axi_lite_rdata(1) = '1' then
-- CDMASR.idle = 1
state <= "10";
end if;
end if;
else
-- select CDMASR register for read
m_axi_lite_arvalid <= '1';
m_axi_lite_araddr <= "000100"; -- x"04"
m_axi_lite_rready <= '1';
end if;
elsif state = "10" then
if m_axi_lite_awready = '1' and m_axi_lite_wready = '1' then
m_axi_lite_awvalid <= '0';
m_axi_lite_wvalid <= '0';
s_axi_rready <= '1';
state <= "11";
else
-- select source address
m_axi_lite_awvalid <= '1';
m_axi_lite_awaddr <= "011000"; -- x"18"
m_axi_lite_wvalid <= '1';
m_axi_lite_wdata(9 downto 0) <= x_addr_r;
m_axi_lite_wdata(19 downto 10) <= y_addr_r;
m_axi_lite_wdata(31 downto 20) <= (others => '0');
end if;
elsif state = "11" then
if m_axi_lite_awready = '1' and m_axi_lite_wready = '1' then
m_axi_lite_awvalid <= '0';
m_axi_lite_wvalid <= '0';
s_axi_wvalid <= '1';
s_axi_wdata(23 downto 0) <= rgb888_in;
state <= "00";
else
-- select destination address
m_axi_lite_awvalid <= '1';
m_axi_lite_awaddr <= "100000"; -- x"20"
m_axi_lite_wvalid <= '1';
m_axi_lite_wdata(9 downto 0) <= x_addr_w;
m_axi_lite_wdata(19 downto 10) <= y_addr_w;
m_axi_lite_wdata(31 downto 20) <= (others => '0');
end if;
end if;
last_clk <= clk;
end if;
end process;
end Behavioral;
| mit | adb86d859c6744e3a3fccdcf0178f99b | 0.435024 | 3.784771 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_green_leds_s1_translator.vhd | 1 | 14,502 | -- niosii_system_green_leds_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_green_leds_s1_translator;
architecture rtl of niosii_system_green_leds_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
green_leds_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_green_leds_s1_translator
| apache-2.0 | 80991a676f9fa8ecb75535c99bbda56f | 0.430975 | 4.327663 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/658b/ov7670_vga.vhd | 2 | 1,001 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: ov7670_vga - Structural
-- Description: The ov7670 can produce 8-bits of data - pclk runs two cycles to produce RGB565
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ov7670_vga is
port(
pclk : in std_logic;
data : in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(15 downto 0)
);
end ov7670_vga;
architecture Structural of ov7670_vga is
begin
process(pclk)
variable cycle : std_logic := '0';
begin
if rising_edge(pclk) then
if cycle = '0' then
rgb(15 downto 8) <= data;
cycle := '1';
else
rgb(7 downto 0) <= data;
cycle := '0';
end if;
end if;
end process;
end Structural;
| mit | 106d2121708738738d36214d944cab7c | 0.472527 | 4.429204 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/synth/system_ov7670_vga_0_0.vhd | 5 | 3,941 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 19
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_0_0 IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_0_0;
ARCHITECTURE system_ov7670_vga_0_0_arch OF system_ov7670_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_0_0_arch : ARCHITECTURE IS "system_ov7670_vga_0_0,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "system_ov7670_vga_0_0,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=19,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF active: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : ov7670_vga
PORT MAP (
clk_x2 => clk_x2,
active => active,
data => data,
rgb => rgb
);
END system_ov7670_vga_0_0_arch;
| mit | a98b78ece2791c811972cf423ac8b108 | 0.736869 | 3.785783 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_0/affine_block_ieee754_fp_adder_subtractor_0_0_sim_netlist.vhdl | 1 | 263,537 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top affine_block_ieee754_fp_adder_subtractor_0_0 -prefix
-- affine_block_ieee754_fp_adder_subtractor_0_0_ affine_block_ieee754_fp_adder_subtractor_0_1_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_adder_subtractor_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_adder_subtractor_0_0_ieee754_fp_adder_subtractor is
port (
z : out STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
x : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end affine_block_ieee754_fp_adder_subtractor_0_0_ieee754_fp_adder_subtractor;
architecture STRUCTURE of affine_block_ieee754_fp_adder_subtractor_0_0_ieee754_fp_adder_subtractor is
signal A : STD_LOGIC_VECTOR ( 19 downto 0 );
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal large_exp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal large_mant1_carry_i_1_n_0 : STD_LOGIC;
signal large_mant1_carry_i_2_n_0 : STD_LOGIC;
signal large_mant1_carry_i_3_n_0 : STD_LOGIC;
signal large_mant1_carry_i_4_n_0 : STD_LOGIC;
signal large_mant1_carry_i_5_n_0 : STD_LOGIC;
signal large_mant1_carry_i_6_n_0 : STD_LOGIC;
signal large_mant1_carry_i_7_n_0 : STD_LOGIC;
signal large_mant1_carry_i_8_n_0 : STD_LOGIC;
signal large_mant1_carry_n_0 : STD_LOGIC;
signal large_mant1_carry_n_1 : STD_LOGIC;
signal large_mant1_carry_n_2 : STD_LOGIC;
signal large_mant1_carry_n_3 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
signal sel0 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \sign00__0_carry__0_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_19_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_20_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_40_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_41_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_n_1\ : STD_LOGIC;
signal \sign00__0_carry__0_n_2\ : STD_LOGIC;
signal \sign00__0_carry__0_n_3\ : STD_LOGIC;
signal \sign00__0_carry__1_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_17_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_19_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_41_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_42_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_44_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_46_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_47_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_n_1\ : STD_LOGIC;
signal \sign00__0_carry__1_n_2\ : STD_LOGIC;
signal \sign00__0_carry__1_n_3\ : STD_LOGIC;
signal \sign00__0_carry__2_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_40_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_n_1\ : STD_LOGIC;
signal \sign00__0_carry__2_n_2\ : STD_LOGIC;
signal \sign00__0_carry__2_n_3\ : STD_LOGIC;
signal \sign00__0_carry__3_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_40_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_47_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_48_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_51_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_52_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_n_1\ : STD_LOGIC;
signal \sign00__0_carry__3_n_2\ : STD_LOGIC;
signal \sign00__0_carry__3_n_3\ : STD_LOGIC;
signal \sign00__0_carry__4_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_17_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_18_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_19_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_20_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_n_1\ : STD_LOGIC;
signal \sign00__0_carry__4_n_2\ : STD_LOGIC;
signal \sign00__0_carry__4_n_3\ : STD_LOGIC;
signal \sign00__0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_100_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_101_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_102_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_103_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_104_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_105_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_17_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_41_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_42_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_43_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_44_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_45_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_46_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_47_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_48_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_49_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_51_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_53_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_54_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_55_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_56_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_57_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_58_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_59_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_60_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_61_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_62_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_63_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_64_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_65_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_66_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_67_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_68_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_69_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_70_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_72_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_73_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_77_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_77_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_77_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_80_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_81_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_82_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_83_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_84_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_85_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_86_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_87_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_88_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_89_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_90_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_91_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_92_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_93_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_94_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_95_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_96_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_97_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_98_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_99_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry_n_0\ : STD_LOGIC;
signal \sign00__0_carry_n_1\ : STD_LOGIC;
signal \sign00__0_carry_n_2\ : STD_LOGIC;
signal \sign00__0_carry_n_3\ : STD_LOGIC;
signal \sign00__0_carry_n_7\ : STD_LOGIC;
signal small_mant : STD_LOGIC_VECTOR ( 22 downto 0 );
signal sum2 : STD_LOGIC_VECTOR ( 19 downto 18 );
signal sum3 : STD_LOGIC;
signal \sum3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_5_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_6_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_7_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_8_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_9_n_3\ : STD_LOGIC;
signal \sum3_carry__0_n_0\ : STD_LOGIC;
signal \sum3_carry__0_n_1\ : STD_LOGIC;
signal \sum3_carry__0_n_2\ : STD_LOGIC;
signal \sum3_carry__0_n_3\ : STD_LOGIC;
signal \sum3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_2_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_3_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_4_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_5_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_6_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_7_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_8_n_0\ : STD_LOGIC;
signal \sum3_carry__1_n_0\ : STD_LOGIC;
signal \sum3_carry__1_n_1\ : STD_LOGIC;
signal \sum3_carry__1_n_2\ : STD_LOGIC;
signal \sum3_carry__1_n_3\ : STD_LOGIC;
signal \sum3_carry__2_i_2_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_3_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_4_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_5_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_6_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_7_n_0\ : STD_LOGIC;
signal \sum3_carry__2_n_1\ : STD_LOGIC;
signal \sum3_carry__2_n_2\ : STD_LOGIC;
signal \sum3_carry__2_n_3\ : STD_LOGIC;
signal sum3_carry_i_1_n_0 : STD_LOGIC;
signal sum3_carry_i_2_n_0 : STD_LOGIC;
signal sum3_carry_i_3_n_0 : STD_LOGIC;
signal sum3_carry_i_4_n_0 : STD_LOGIC;
signal sum3_carry_i_5_n_0 : STD_LOGIC;
signal sum3_carry_i_6_n_0 : STD_LOGIC;
signal sum3_carry_i_7_n_0 : STD_LOGIC;
signal sum3_carry_i_8_n_0 : STD_LOGIC;
signal sum3_carry_n_0 : STD_LOGIC;
signal sum3_carry_n_1 : STD_LOGIC;
signal sum3_carry_n_2 : STD_LOGIC;
signal sum3_carry_n_3 : STD_LOGIC;
signal sum4 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \sum4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \sum4_carry__0_n_0\ : STD_LOGIC;
signal \sum4_carry__0_n_1\ : STD_LOGIC;
signal \sum4_carry__0_n_2\ : STD_LOGIC;
signal \sum4_carry__0_n_3\ : STD_LOGIC;
signal sum4_carry_i_1_n_0 : STD_LOGIC;
signal sum4_carry_i_2_n_0 : STD_LOGIC;
signal sum4_carry_i_3_n_0 : STD_LOGIC;
signal sum4_carry_i_4_n_0 : STD_LOGIC;
signal sum4_carry_i_5_n_0 : STD_LOGIC;
signal sum4_carry_i_6_n_0 : STD_LOGIC;
signal sum4_carry_i_7_n_0 : STD_LOGIC;
signal sum4_carry_i_8_n_0 : STD_LOGIC;
signal sum4_carry_n_0 : STD_LOGIC;
signal sum4_carry_n_1 : STD_LOGIC;
signal sum4_carry_n_2 : STD_LOGIC;
signal sum4_carry_n_3 : STD_LOGIC;
signal \z0_carry__0_n_1\ : STD_LOGIC;
signal \z0_carry__0_n_2\ : STD_LOGIC;
signal \z0_carry__0_n_3\ : STD_LOGIC;
signal z0_carry_i_10_n_0 : STD_LOGIC;
signal z0_carry_i_11_n_0 : STD_LOGIC;
signal z0_carry_i_12_n_0 : STD_LOGIC;
signal z0_carry_i_4_n_0 : STD_LOGIC;
signal \z0_carry_i_5__0_n_0\ : STD_LOGIC;
signal z0_carry_i_5_n_0 : STD_LOGIC;
signal \z0_carry_i_6__0_n_0\ : STD_LOGIC;
signal z0_carry_i_6_n_0 : STD_LOGIC;
signal \z0_carry_i_7__0_n_0\ : STD_LOGIC;
signal z0_carry_i_7_n_0 : STD_LOGIC;
signal \z0_carry_i_8__0_n_0\ : STD_LOGIC;
signal z0_carry_i_8_n_0 : STD_LOGIC;
signal z0_carry_i_9_n_0 : STD_LOGIC;
signal z0_carry_n_0 : STD_LOGIC;
signal z0_carry_n_1 : STD_LOGIC;
signal z0_carry_n_2 : STD_LOGIC;
signal z0_carry_n_3 : STD_LOGIC;
signal z1 : STD_LOGIC_VECTOR ( 7 to 7 );
signal z10_in : STD_LOGIC_VECTOR ( 22 downto 4 );
signal z2 : STD_LOGIC;
signal \z2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z2_carry__0_n_0\ : STD_LOGIC;
signal \z2_carry__0_n_1\ : STD_LOGIC;
signal \z2_carry__0_n_2\ : STD_LOGIC;
signal \z2_carry__0_n_3\ : STD_LOGIC;
signal \z2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_5_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_6_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_7_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_8_n_0\ : STD_LOGIC;
signal \z2_carry__1_n_0\ : STD_LOGIC;
signal \z2_carry__1_n_1\ : STD_LOGIC;
signal \z2_carry__1_n_2\ : STD_LOGIC;
signal \z2_carry__1_n_3\ : STD_LOGIC;
signal \z2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_5_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_6_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_7_n_0\ : STD_LOGIC;
signal \z2_carry__2_n_1\ : STD_LOGIC;
signal \z2_carry__2_n_2\ : STD_LOGIC;
signal \z2_carry__2_n_3\ : STD_LOGIC;
signal z2_carry_i_1_n_0 : STD_LOGIC;
signal z2_carry_i_2_n_0 : STD_LOGIC;
signal z2_carry_i_3_n_0 : STD_LOGIC;
signal z2_carry_i_4_n_0 : STD_LOGIC;
signal z2_carry_i_5_n_0 : STD_LOGIC;
signal z2_carry_i_6_n_0 : STD_LOGIC;
signal z2_carry_i_7_n_0 : STD_LOGIC;
signal z2_carry_i_8_n_0 : STD_LOGIC;
signal z2_carry_n_0 : STD_LOGIC;
signal z2_carry_n_1 : STD_LOGIC;
signal z2_carry_n_2 : STD_LOGIC;
signal z2_carry_n_3 : STD_LOGIC;
signal z3 : STD_LOGIC_VECTOR ( 30 downto 1 );
signal \z[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_large_mant1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sign00__0_carry__5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sign00__0_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_sign00__0_carry_i_77_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_sign00__0_carry_i_77_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_sum3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__0_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_sum3_carry__0_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_z2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \_carry\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_carry_i_15\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \_carry_i_16\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \_carry_i_5\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \_carry_i_7\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \_carry_i_9\ : label is "soft_lutpair14";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_17\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_18\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_36\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_37\ : label is "soft_lutpair39";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_18\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_20\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_22\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_23\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_24\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_36\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_38\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_39\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_40\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_43\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_45\ : label is "soft_lutpair33";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_17\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_18\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_19\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_20\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_22\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_24\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_26\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_33\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_34\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_36\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_38\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_41\ : label is "soft_lutpair39";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_18\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_20\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_41\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_42\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_43\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_44\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_45\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_46\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_49\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_50\ : label is "soft_lutpair40";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__4_i_22\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \sign00__0_carry__4_i_25\ : label is "soft_lutpair13";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry_i_18\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \sign00__0_carry_i_19\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \sign00__0_carry_i_20\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \sign00__0_carry_i_40\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \sign00__0_carry_i_50\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \sign00__0_carry_i_52\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \sign00__0_carry_i_54\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \sign00__0_carry_i_56\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \sign00__0_carry_i_67\ : label is "soft_lutpair20";
attribute METHODOLOGY_DRC_VIOS of z0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of z0_carry_i_12 : label is "soft_lutpair15";
attribute METHODOLOGY_DRC_VIOS of z2_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z2_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z2_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z2_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[0]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[10]_INST_0_i_10\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \z[10]_INST_0_i_8\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[10]_INST_0_i_9\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[13]_INST_0_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[13]_INST_0_i_5\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[14]_INST_0_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_5\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[16]_INST_0_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \z[16]_INST_0_i_7\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[17]_INST_0_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \z[18]_INST_0_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[19]_INST_0_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[1]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[20]_INST_0_i_5\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \z[21]_INST_0_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_11\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_12\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_20\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_23\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_25\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_26\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_27\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_28\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_29\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_30\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_31\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_32\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_33\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_40\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_9\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_4\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_6\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_7\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[4]_INST_0_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[5]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_6\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[8]_INST_0_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[8]_INST_0_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[9]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[9]_INST_0_i_7\ : label is "soft_lutpair46";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \z[22]_INST_0_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(4 downto 1),
S(3) => \_carry_i_1_n_0\,
S(2) => \_carry_i_2_n_0\,
S(1) => \_carry_i_3_n_0\,
S(0) => \_carry_i_4_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(12 downto 9),
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(16 downto 13),
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(20 downto 17),
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(24 downto 21),
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(28 downto 25),
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => z3(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFAFAE"
)
port map (
I0 => sel0(17),
I1 => sel0(13),
I2 => \_carry_i_15_n_0\,
I3 => sel0(14),
I4 => sel0(18),
I5 => \_carry_i_16_n_0\,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEF000000000000"
)
port map (
I0 => sel0(9),
I1 => sel0(10),
I2 => sel0(8),
I3 => sel0(7),
I4 => \_carry_i_17_n_0\,
I5 => \_carry_i_18_n_0\,
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(18),
I1 => sel0(17),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \_carry_i_19_n_0\,
I1 => sel0(14),
I2 => sel0(13),
I3 => sel0(2),
I4 => \_carry_i_16_n_0\,
I5 => \z[31]_INST_0_i_6_n_0\,
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(8),
I1 => sel0(7),
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(16),
I1 => sel0(15),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(21),
I1 => sel0(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEEEF"
)
port map (
I0 => sel0(10),
I1 => sel0(9),
I2 => sel0(3),
I3 => sel0(4),
I4 => sel0(5),
I5 => sel0(6),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(12),
I1 => sel0(11),
I2 => sel0(16),
I3 => sel0(15),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(10),
I1 => sel0(9),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => z0_carry_i_9_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554444400000000"
)
port map (
I0 => sel0(23),
I1 => \_carry_i_5_n_0\,
I2 => sel0(14),
I3 => \_carry_i_6_n_0\,
I4 => \_carry_i_7_n_0\,
I5 => \_carry_i_8_n_0\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8A8A8A800"
)
port map (
I0 => \_carry_i_9_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \_carry_i_11_n_0\,
I3 => \_carry_i_12_n_0\,
I4 => sel0(1),
I5 => \_carry_i_13_n_0\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(22),
I1 => sel0(21),
I2 => sel0(19),
I3 => sel0(20),
O => \_carry_i_5_n_0\
);
\_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEEEEEF"
)
port map (
I0 => sel0(12),
I1 => sel0(13),
I2 => sel0(10),
I3 => sel0(9),
I4 => \_carry_i_14_n_0\,
I5 => sel0(11),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(18),
I1 => sel0(17),
I2 => sel0(15),
I3 => sel0(16),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sel0(3),
I1 => sel0(5),
I2 => sel0(6),
I3 => \_carry_i_5_n_0\,
I4 => sel0(4),
I5 => \z[31]_INST_0_i_4_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"54545455"
)
port map (
I0 => sel0(23),
I1 => sel0(22),
I2 => sel0(21),
I3 => sel0(19),
I4 => sel0(20),
O => \_carry_i_9_n_0\
);
large_mant1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => large_mant1_carry_n_0,
CO(2) => large_mant1_carry_n_1,
CO(1) => large_mant1_carry_n_2,
CO(0) => large_mant1_carry_n_3,
CYINIT => '0',
DI(3) => large_mant1_carry_i_1_n_0,
DI(2) => large_mant1_carry_i_2_n_0,
DI(1) => large_mant1_carry_i_3_n_0,
DI(0) => large_mant1_carry_i_4_n_0,
O(3 downto 0) => NLW_large_mant1_carry_O_UNCONNECTED(3 downto 0),
S(3) => large_mant1_carry_i_5_n_0,
S(2) => large_mant1_carry_i_6_n_0,
S(1) => large_mant1_carry_i_7_n_0,
S(0) => large_mant1_carry_i_8_n_0
);
large_mant1_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => y(30),
I3 => x(30),
O => large_mant1_carry_i_1_n_0
);
large_mant1_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => y(28),
I3 => x(28),
O => large_mant1_carry_i_2_n_0
);
large_mant1_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => y(26),
I3 => x(26),
O => large_mant1_carry_i_3_n_0
);
large_mant1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => y(24),
I3 => x(24),
O => large_mant1_carry_i_4_n_0
);
large_mant1_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => x(30),
I3 => y(30),
O => large_mant1_carry_i_5_n_0
);
large_mant1_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => x(28),
I3 => y(28),
O => large_mant1_carry_i_6_n_0
);
large_mant1_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => x(26),
I3 => y(26),
O => large_mant1_carry_i_7_n_0
);
large_mant1_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => x(24),
I3 => y(24),
O => large_mant1_carry_i_8_n_0
);
\sign00__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \sign00__0_carry_n_0\,
CO(2) => \sign00__0_carry_n_1\,
CO(1) => \sign00__0_carry_n_2\,
CO(0) => \sign00__0_carry_n_3\,
CYINIT => A(0),
DI(3) => \sign00__0_carry_i_2_n_0\,
DI(2) => \sign00__0_carry_i_3_n_0\,
DI(1) => \sign00__0_carry_i_4_n_0\,
DI(0) => \sign00__0_carry_i_5_n_0\,
O(3 downto 1) => sel0(2 downto 0),
O(0) => \sign00__0_carry_n_7\,
S(3) => \sign00__0_carry_i_6_n_0\,
S(2) => \sign00__0_carry_i_7_n_0\,
S(1) => \sign00__0_carry_i_8_n_0\,
S(0) => \sign00__0_carry_i_9_n_0\
);
\sign00__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_n_0\,
CO(3) => \sign00__0_carry__0_n_0\,
CO(2) => \sign00__0_carry__0_n_1\,
CO(1) => \sign00__0_carry__0_n_2\,
CO(0) => \sign00__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__0_i_1_n_0\,
DI(2) => \sign00__0_carry__0_i_2_n_0\,
DI(1) => \sign00__0_carry__0_i_3_n_0\,
DI(0) => \sign00__0_carry__0_i_4_n_0\,
O(3 downto 0) => sel0(6 downto 3),
S(3) => \sign00__0_carry__0_i_5_n_0\,
S(2) => \sign00__0_carry__0_i_6_n_0\,
S(1) => \sign00__0_carry__0_i_7_n_0\,
S(0) => \sign00__0_carry__0_i_8_n_0\
);
\sign00__0_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sign00__0_carry__0_i_9_n_0\,
O => \sign00__0_carry__0_i_1_n_0\
);
\sign00__0_carry__0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__0_i_21_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__0_i_22_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_10_n_0\
);
\sign00__0_carry__0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__0_i_23_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_33_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__0_i_11_n_0\
);
\sign00__0_carry__0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__0_i_22_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__0_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_12_n_0\
);
\sign00__0_carry__0_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__0_i_25_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_35_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__0_i_13_n_0\
);
\sign00__0_carry__0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__0_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_23_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_14_n_0\
);
\sign00__0_carry__0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__0_i_26_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry__0_i_27_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__0_i_15_n_0\
);
\sign00__0_carry__0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555655AAAAAAAA"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__0_i_28_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__0_i_10_n_0\,
O => \sign00__0_carry__0_i_16_n_0\
);
\sign00__0_carry__0_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(5),
I1 => y(5),
I2 => large_mant1_carry_n_0,
O => A(5)
);
\sign00__0_carry__0_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(4),
I1 => y(4),
I2 => large_mant1_carry_n_0,
O => A(4)
);
\sign00__0_carry__0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_29_n_0\,
I1 => \sign00__0_carry_i_51_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_30_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_31_n_0\,
O => \sign00__0_carry__0_i_19_n_0\
);
\sign00__0_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_10_n_0\,
I1 => \sign00__0_carry__0_i_11_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__0_i_2_n_0\
);
\sign00__0_carry__0_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_32_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__0_i_21_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_20_n_0\
);
\sign00__0_carry__0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_32_n_0\,
I1 => \sign00__0_carry_i_47_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry__0_i_33_n_0\,
I4 => sum4(2),
I5 => \sign00__0_carry__0_i_34_n_0\,
O => \sign00__0_carry__0_i_21_n_0\
);
\sign00__0_carry__0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_35_n_0\,
I1 => \sign00__0_carry_i_45_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry_i_43_n_0\,
I4 => sum4(2),
I5 => \sign00__0_carry_i_44_n_0\,
O => \sign00__0_carry__0_i_22_n_0\
);
\sign00__0_carry__0_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(3),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(4),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_38_n_0\,
O => \sign00__0_carry__0_i_23_n_0\
);
\sign00__0_carry__0_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8FF33CC00"
)
port map (
I0 => \sign00__0_carry__0_i_33_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry__0_i_34_n_0\,
I3 => \sign00__0_carry_i_47_n_0\,
I4 => \sign00__0_carry_i_48_n_0\,
I5 => sum4(1),
O => \sign00__0_carry__0_i_24_n_0\
);
\sign00__0_carry__0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(2),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(3),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_30_n_0\,
O => \sign00__0_carry__0_i_25_n_0\
);
\sign00__0_carry__0_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(1),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(2),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_39_n_0\,
O => \sign00__0_carry__0_i_26_n_0\
);
\sign00__0_carry__0_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000044400400"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry_i_39_n_0\,
I2 => large_mant1_carry_n_0,
I3 => x(0),
I4 => y(0),
I5 => \sign00__0_carry_i_41_n_0\,
O => \sign00__0_carry__0_i_27_n_0\
);
\sign00__0_carry__0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_40_n_0\,
I1 => \sign00__0_carry__0_i_41_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_39_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_38_n_0\,
O => \sign00__0_carry__0_i_28_n_0\
);
\sign00__0_carry__0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(0),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(1),
O => \sign00__0_carry__0_i_29_n_0\
);
\sign00__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_12_n_0\,
I1 => \sign00__0_carry__0_i_13_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__0_i_3_n_0\
);
\sign00__0_carry__0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(4),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(5),
O => \sign00__0_carry__0_i_30_n_0\
);
\sign00__0_carry__0_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(6),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(7),
O => \sign00__0_carry__0_i_31_n_0\
);
\sign00__0_carry__0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(21),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(13),
I4 => y(13),
I5 => sum4(4),
O => \sign00__0_carry__0_i_32_n_0\
);
\sign00__0_carry__0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(19),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(11),
I4 => y(11),
I5 => sum4(4),
O => \sign00__0_carry__0_i_33_n_0\
);
\sign00__0_carry__0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00FFE4FFE400"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(15),
I2 => y(15),
I3 => sum4(3),
I4 => small_mant(7),
I5 => sum4(4),
O => \sign00__0_carry__0_i_34_n_0\
);
\sign00__0_carry__0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(20),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(12),
I4 => y(12),
I5 => sum4(4),
O => \sign00__0_carry__0_i_35_n_0\
);
\sign00__0_carry__0_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(3),
I1 => x(3),
I2 => large_mant1_carry_n_0,
O => small_mant(3)
);
\sign00__0_carry__0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(4),
I1 => x(4),
I2 => large_mant1_carry_n_0,
O => small_mant(4)
);
\sign00__0_carry__0_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(5),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(6),
O => \sign00__0_carry__0_i_38_n_0\
);
\sign00__0_carry__0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(3),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(4),
O => \sign00__0_carry__0_i_39_n_0\
);
\sign00__0_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_14_n_0\,
I1 => \sign00__0_carry__0_i_15_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__0_i_4_n_0\
);
\sign00__0_carry__0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => small_mant(0),
I1 => \sign00__0_carry_i_58_n_0\,
I2 => \sign00__0_carry_i_59_n_0\,
I3 => \sign00__0_carry_i_69_n_0\,
I4 => sum4(0),
O => \sign00__0_carry__0_i_40_n_0\
);
\sign00__0_carry__0_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(1),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(2),
O => \sign00__0_carry__0_i_41_n_0\
);
\sign00__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"A965"
)
port map (
I0 => \sign00__0_carry__0_i_9_n_0\,
I1 => large_mant1_carry_n_0,
I2 => y(7),
I3 => x(7),
O => \sign00__0_carry__0_i_5_n_0\
);
\sign00__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A965"
)
port map (
I0 => \sign00__0_carry__0_i_16_n_0\,
I1 => large_mant1_carry_n_0,
I2 => y(6),
I3 => x(6),
O => \sign00__0_carry__0_i_6_n_0\
);
\sign00__0_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_12_n_0\,
I1 => \sign00__0_carry__0_i_13_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(5),
O => \sign00__0_carry__0_i_7_n_0\
);
\sign00__0_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_14_n_0\,
I1 => \sign00__0_carry__0_i_15_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(4),
O => \sign00__0_carry__0_i_8_n_0\
);
\sign00__0_carry__0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555655AAAAAAAA"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__0_i_19_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__0_i_20_n_0\,
O => \sign00__0_carry__0_i_9_n_0\
);
\sign00__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__0_n_0\,
CO(3) => \sign00__0_carry__1_n_0\,
CO(2) => \sign00__0_carry__1_n_1\,
CO(1) => \sign00__0_carry__1_n_2\,
CO(0) => \sign00__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__1_i_1_n_0\,
DI(2) => \sign00__0_carry__1_i_2_n_0\,
DI(1) => \sign00__0_carry__1_i_3_n_0\,
DI(0) => \sign00__0_carry__1_i_4_n_0\,
O(3 downto 0) => sel0(10 downto 7),
S(3) => \sign00__0_carry__1_i_5_n_0\,
S(2) => \sign00__0_carry__1_i_6_n_0\,
S(1) => \sign00__0_carry__1_i_7_n_0\,
S(0) => \sign00__0_carry__1_i_8_n_0\
);
\sign00__0_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_9_n_0\,
I1 => \sign00__0_carry__1_i_10_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_1_n_0\
);
\sign00__0_carry__1_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry_i_26_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__1_i_26_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_27_n_0\,
O => \sign00__0_carry__1_i_10_n_0\
);
\sign00__0_carry__1_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_25_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_28_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_11_n_0\
);
\sign00__0_carry__1_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry_i_33_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__0_i_23_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_29_n_0\,
O => \sign00__0_carry__1_i_12_n_0\
);
\sign00__0_carry__1_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_28_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_30_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_13_n_0\
);
\sign00__0_carry__1_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry_i_35_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__0_i_25_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_31_n_0\,
O => \sign00__0_carry__1_i_14_n_0\
);
\sign00__0_carry__1_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_30_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_32_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_15_n_0\
);
\sign00__0_carry__1_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry__0_i_27_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__0_i_26_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_33_n_0\,
O => \sign00__0_carry__1_i_16_n_0\
);
\sign00__0_carry__1_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => \sign00__0_carry__1_i_27_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry__1_i_26_n_0\,
I3 => \sign00__0_carry_i_42_n_0\,
I4 => \sign00__0_carry_i_26_n_0\,
I5 => \sign00__0_carry_i_17_n_0\,
O => \sign00__0_carry__1_i_17_n_0\
);
\sign00__0_carry__1_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(11),
I1 => y(11),
I2 => large_mant1_carry_n_0,
O => A(11)
);
\sign00__0_carry__1_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => \sign00__0_carry__1_i_29_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry__0_i_23_n_0\,
I3 => \sign00__0_carry_i_42_n_0\,
I4 => \sign00__0_carry_i_33_n_0\,
I5 => \sign00__0_carry_i_17_n_0\,
O => \sign00__0_carry__1_i_19_n_0\
);
\sign00__0_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_11_n_0\,
I1 => \sign00__0_carry__1_i_12_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_2_n_0\
);
\sign00__0_carry__1_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(10),
I1 => y(10),
I2 => large_mant1_carry_n_0,
O => A(10)
);
\sign00__0_carry__1_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => \sign00__0_carry__1_i_31_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry__0_i_25_n_0\,
I3 => \sign00__0_carry_i_42_n_0\,
I4 => \sign00__0_carry_i_35_n_0\,
I5 => \sign00__0_carry_i_17_n_0\,
O => \sign00__0_carry__1_i_21_n_0\
);
\sign00__0_carry__1_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(9),
I1 => y(9),
I2 => large_mant1_carry_n_0,
O => A(9)
);
\sign00__0_carry__1_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(8),
I1 => y(8),
I2 => large_mant1_carry_n_0,
O => A(8)
);
\sign00__0_carry__1_i_24\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__1_i_34_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__1_i_35_n_0\,
O => \sign00__0_carry__1_i_24_n_0\
);
\sign00__0_carry__1_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B8B8"
)
port map (
I0 => \sign00__0_carry__1_i_36_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry__0_i_33_n_0\,
I3 => \sign00__0_carry__1_i_37_n_0\,
I4 => sum4(1),
O => \sign00__0_carry__1_i_25_n_0\
);
\sign00__0_carry__1_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(4),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(5),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_31_n_0\,
O => \sign00__0_carry__1_i_26_n_0\
);
\sign00__0_carry__1_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(8),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(9),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_41_n_0\,
O => \sign00__0_carry__1_i_27_n_0\
);
\sign00__0_carry__1_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B8B8"
)
port map (
I0 => \sign00__0_carry__1_i_42_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_43_n_0\,
I3 => \sign00__0_carry__1_i_35_n_0\,
I4 => sum4(1),
O => \sign00__0_carry__1_i_28_n_0\
);
\sign00__0_carry__1_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(7),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(8),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_44_n_0\,
O => \sign00__0_carry__1_i_29_n_0\
);
\sign00__0_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_13_n_0\,
I1 => \sign00__0_carry__1_i_14_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_3_n_0\
);
\sign00__0_carry__1_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF33CC00B8B8B8B8"
)
port map (
I0 => \sign00__0_carry__0_i_32_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_47_n_0\,
I3 => \sign00__0_carry__1_i_36_n_0\,
I4 => \sign00__0_carry__0_i_33_n_0\,
I5 => sum4(1),
O => \sign00__0_carry__1_i_30_n_0\
);
\sign00__0_carry__1_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(6),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(7),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_46_n_0\,
O => \sign00__0_carry__1_i_31_n_0\
);
\sign00__0_carry__1_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_42_n_0\,
I1 => \sign00__0_carry_i_43_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry__0_i_35_n_0\,
I4 => sum4(2),
I5 => \sign00__0_carry_i_45_n_0\,
O => \sign00__0_carry__1_i_32_n_0\
);
\sign00__0_carry__1_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(5),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(6),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_47_n_0\,
O => \sign00__0_carry__1_i_33_n_0\
);
\sign00__0_carry__1_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(18),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__1_i_42_n_0\,
O => \sign00__0_carry__1_i_34_n_0\
);
\sign00__0_carry__1_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(16),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__0_i_35_n_0\,
O => \sign00__0_carry__1_i_35_n_0\
);
\sign00__0_carry__1_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FEBA"
)
port map (
I0 => sum4(3),
I1 => large_mant1_carry_n_0,
I2 => x(15),
I3 => y(15),
I4 => sum4(4),
O => \sign00__0_carry__1_i_36_n_0\
);
\sign00__0_carry__1_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(17),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__0_i_32_n_0\,
O => \sign00__0_carry__1_i_37_n_0\
);
\sign00__0_carry__1_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(5),
I1 => x(5),
I2 => large_mant1_carry_n_0,
O => small_mant(5)
);
\sign00__0_carry__1_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(8),
I1 => x(8),
I2 => large_mant1_carry_n_0,
O => small_mant(8)
);
\sign00__0_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_15_n_0\,
I1 => \sign00__0_carry__1_i_16_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_4_n_0\
);
\sign00__0_carry__1_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(9),
I1 => x(9),
I2 => large_mant1_carry_n_0,
O => small_mant(9)
);
\sign00__0_carry__1_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(10),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(11),
O => \sign00__0_carry__1_i_41_n_0\
);
\sign00__0_carry__1_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(22),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(14),
I4 => y(14),
I5 => sum4(4),
O => \sign00__0_carry__1_i_42_n_0\
);
\sign00__0_carry__1_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(7),
I1 => x(7),
I2 => large_mant1_carry_n_0,
O => small_mant(7)
);
\sign00__0_carry__1_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(9),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(10),
O => \sign00__0_carry__1_i_44_n_0\
);
\sign00__0_carry__1_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(6),
I1 => x(6),
I2 => large_mant1_carry_n_0,
O => small_mant(6)
);
\sign00__0_carry__1_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(8),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(9),
O => \sign00__0_carry__1_i_46_n_0\
);
\sign00__0_carry__1_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(7),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(8),
O => \sign00__0_carry__1_i_47_n_0\
);
\sign00__0_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__1_i_9_n_0\,
I1 => \sign00__0_carry__1_i_17_n_0\,
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(11),
O => \sign00__0_carry__1_i_5_n_0\
);
\sign00__0_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__1_i_11_n_0\,
I1 => \sign00__0_carry__1_i_19_n_0\,
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(10),
O => \sign00__0_carry__1_i_6_n_0\
);
\sign00__0_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__1_i_13_n_0\,
I1 => \sign00__0_carry__1_i_21_n_0\,
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(9),
O => \sign00__0_carry__1_i_7_n_0\
);
\sign00__0_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_15_n_0\,
I1 => \sign00__0_carry__1_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(8),
O => \sign00__0_carry__1_i_8_n_0\
);
\sign00__0_carry__1_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_25_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_9_n_0\
);
\sign00__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__1_n_0\,
CO(3) => \sign00__0_carry__2_n_0\,
CO(2) => \sign00__0_carry__2_n_1\,
CO(1) => \sign00__0_carry__2_n_2\,
CO(0) => \sign00__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__2_i_1_n_0\,
DI(2) => \sign00__0_carry__2_i_2_n_0\,
DI(1) => \sign00__0_carry__2_i_3_n_0\,
DI(0) => \sign00__0_carry__2_i_4_n_0\,
O(3 downto 0) => sel0(14 downto 11),
S(3) => \sign00__0_carry__2_i_5_n_0\,
S(2) => \sign00__0_carry__2_i_6_n_0\,
S(1) => \sign00__0_carry__2_i_7_n_0\,
S(0) => \sign00__0_carry__2_i_8_n_0\
);
\sign00__0_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_9_n_0\,
I1 => \sign00__0_carry__2_i_10_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_1_n_0\
);
\sign00__0_carry__2_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_26_n_0\,
I1 => \sign00__0_carry__1_i_26_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_23_n_0\,
O => \sign00__0_carry__2_i_10_n_0\
);
\sign00__0_carry__2_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_22_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_11_n_0\
);
\sign00__0_carry__2_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_33_n_0\,
I1 => \sign00__0_carry__0_i_23_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_29_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_25_n_0\,
O => \sign00__0_carry__2_i_12_n_0\
);
\sign00__0_carry__2_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_26_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_13_n_0\
);
\sign00__0_carry__2_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_35_n_0\,
I1 => \sign00__0_carry__0_i_25_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_31_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_27_n_0\,
O => \sign00__0_carry__2_i_14_n_0\
);
\sign00__0_carry__2_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_26_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_15_n_0\
);
\sign00__0_carry__2_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_27_n_0\,
I1 => \sign00__0_carry__0_i_26_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_33_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_28_n_0\,
O => \sign00__0_carry__2_i_16_n_0\
);
\sign00__0_carry__2_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(15),
I1 => y(15),
I2 => large_mant1_carry_n_0,
O => A(15)
);
\sign00__0_carry__2_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(14),
I1 => y(14),
I2 => large_mant1_carry_n_0,
O => A(14)
);
\sign00__0_carry__2_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(13),
I1 => y(13),
I2 => large_mant1_carry_n_0,
O => A(13)
);
\sign00__0_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_11_n_0\,
I1 => \sign00__0_carry__2_i_12_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_2_n_0\
);
\sign00__0_carry__2_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(12),
I1 => y(12),
I2 => large_mant1_carry_n_0,
O => A(12)
);
\sign00__0_carry__2_i_21\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_29_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__2_i_30_n_0\,
O => \sign00__0_carry__2_i_21_n_0\
);
\sign00__0_carry__2_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_31_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__2_i_32_n_0\,
O => \sign00__0_carry__2_i_22_n_0\
);
\sign00__0_carry__2_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(12),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(13),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_35_n_0\,
O => \sign00__0_carry__2_i_23_n_0\
);
\sign00__0_carry__2_i_24\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_30_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__1_i_34_n_0\,
O => \sign00__0_carry__2_i_24_n_0\
);
\sign00__0_carry__2_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(11),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(12),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_37_n_0\,
O => \sign00__0_carry__2_i_25_n_0\
);
\sign00__0_carry__2_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_32_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__1_i_37_n_0\,
O => \sign00__0_carry__2_i_26_n_0\
);
\sign00__0_carry__2_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(10),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(11),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_39_n_0\,
O => \sign00__0_carry__2_i_27_n_0\
);
\sign00__0_carry__2_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(9),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(10),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_40_n_0\,
O => \sign00__0_carry__2_i_28_n_0\
);
\sign00__0_carry__2_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => small_mant(22),
I1 => sum4(2),
I2 => sum4(4),
I3 => small_mant(18),
I4 => sum4(3),
O => \sign00__0_carry__2_i_29_n_0\
);
\sign00__0_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_13_n_0\,
I1 => \sign00__0_carry__2_i_14_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_3_n_0\
);
\sign00__0_carry__2_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => small_mant(20),
I1 => sum4(2),
I2 => sum4(4),
I3 => small_mant(16),
I4 => sum4(3),
O => \sign00__0_carry__2_i_30_n_0\
);
\sign00__0_carry__2_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => small_mant(21),
I1 => sum4(2),
I2 => sum4(4),
I3 => small_mant(17),
I4 => sum4(3),
O => \sign00__0_carry__2_i_31_n_0\
);
\sign00__0_carry__2_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(19),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__1_i_36_n_0\,
O => \sign00__0_carry__2_i_32_n_0\
);
\sign00__0_carry__2_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(12),
I1 => x(12),
I2 => large_mant1_carry_n_0,
O => small_mant(12)
);
\sign00__0_carry__2_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(13),
I1 => x(13),
I2 => large_mant1_carry_n_0,
O => small_mant(13)
);
\sign00__0_carry__2_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(14),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(15),
O => \sign00__0_carry__2_i_35_n_0\
);
\sign00__0_carry__2_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(11),
I1 => x(11),
I2 => large_mant1_carry_n_0,
O => small_mant(11)
);
\sign00__0_carry__2_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(13),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(14),
O => \sign00__0_carry__2_i_37_n_0\
);
\sign00__0_carry__2_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(10),
I1 => x(10),
I2 => large_mant1_carry_n_0,
O => small_mant(10)
);
\sign00__0_carry__2_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(12),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(13),
O => \sign00__0_carry__2_i_39_n_0\
);
\sign00__0_carry__2_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_15_n_0\,
I1 => \sign00__0_carry__2_i_16_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_4_n_0\
);
\sign00__0_carry__2_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(11),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(12),
O => \sign00__0_carry__2_i_40_n_0\
);
\sign00__0_carry__2_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(14),
I1 => x(14),
I2 => large_mant1_carry_n_0,
O => small_mant(14)
);
\sign00__0_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_9_n_0\,
I1 => \sign00__0_carry__2_i_10_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(15),
O => \sign00__0_carry__2_i_5_n_0\
);
\sign00__0_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_11_n_0\,
I1 => \sign00__0_carry__2_i_12_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(14),
O => \sign00__0_carry__2_i_6_n_0\
);
\sign00__0_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_13_n_0\,
I1 => \sign00__0_carry__2_i_14_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(13),
O => \sign00__0_carry__2_i_7_n_0\
);
\sign00__0_carry__2_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_15_n_0\,
I1 => \sign00__0_carry__2_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(12),
O => \sign00__0_carry__2_i_8_n_0\
);
\sign00__0_carry__2_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_21_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_22_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_9_n_0\
);
\sign00__0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__2_n_0\,
CO(3) => \sign00__0_carry__3_n_0\,
CO(2) => \sign00__0_carry__3_n_1\,
CO(1) => \sign00__0_carry__3_n_2\,
CO(0) => \sign00__0_carry__3_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__3_i_1_n_0\,
DI(2) => \sign00__0_carry__3_i_2_n_0\,
DI(1) => \sign00__0_carry__3_i_3_n_0\,
DI(0) => \sign00__0_carry__3_i_4_n_0\,
O(3 downto 0) => sel0(18 downto 15),
S(3) => \sign00__0_carry__3_i_5_n_0\,
S(2) => \sign00__0_carry__3_i_6_n_0\,
S(1) => \sign00__0_carry__3_i_7_n_0\,
S(0) => \sign00__0_carry__3_i_8_n_0\
);
\sign00__0_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_9_n_0\,
I1 => \sign00__0_carry_i_11_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_10_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_1_n_0\
);
\sign00__0_carry__3_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_26_n_0\,
I1 => \sign00__0_carry__1_i_27_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_23_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_25_n_0\,
O => \sign00__0_carry__3_i_10_n_0\
);
\sign00__0_carry__3_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_26_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_11_n_0\
);
\sign00__0_carry__3_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_23_n_0\,
I1 => \sign00__0_carry__1_i_29_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_25_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_27_n_0\,
O => \sign00__0_carry__3_i_12_n_0\
);
\sign00__0_carry__3_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_26_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_28_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_13_n_0\
);
\sign00__0_carry__3_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_25_n_0\,
I1 => \sign00__0_carry__1_i_31_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_29_n_0\,
O => \sign00__0_carry__3_i_14_n_0\
);
\sign00__0_carry__3_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_28_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_21_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_15_n_0\
);
\sign00__0_carry__3_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_26_n_0\,
I1 => \sign00__0_carry__1_i_33_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_28_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_30_n_0\,
O => \sign00__0_carry__3_i_16_n_0\
);
\sign00__0_carry__3_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => \sign00__0_carry_i_38_n_0\,
I1 => \sign00__0_carry_i_26_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_31_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__3_i_32_n_0\,
O => sum2(19)
);
\sign00__0_carry__3_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(19),
I1 => y(19),
I2 => large_mant1_carry_n_0,
O => A(19)
);
\sign00__0_carry__3_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => \sign00__0_carry_i_38_n_0\,
I1 => \sign00__0_carry_i_33_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_33_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__3_i_34_n_0\,
O => sum2(18)
);
\sign00__0_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_11_n_0\,
I1 => \sign00__0_carry_i_14_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_12_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_2_n_0\
);
\sign00__0_carry__3_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(18),
I1 => y(18),
I2 => large_mant1_carry_n_0,
O => A(18)
);
\sign00__0_carry__3_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__3_i_35_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_36_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__3_i_37_n_0\,
O => \sign00__0_carry__3_i_21_n_0\
);
\sign00__0_carry__3_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__3_i_38_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_39_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__3_i_40_n_0\,
O => \sign00__0_carry__3_i_22_n_0\
);
\sign00__0_carry__3_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000B08"
)
port map (
I0 => small_mant(22),
I1 => sum4(1),
I2 => sum4(3),
I3 => small_mant(20),
I4 => sum4(4),
I5 => sum4(2),
O => \sign00__0_carry__3_i_23_n_0\
);
\sign00__0_carry__3_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000003B0038"
)
port map (
I0 => small_mant(21),
I1 => sum4(1),
I2 => sum4(2),
I3 => sum4(4),
I4 => small_mant(19),
I5 => sum4(3),
O => \sign00__0_carry__3_i_24_n_0\
);
\sign00__0_carry__3_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(16),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(17),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_47_n_0\,
O => \sign00__0_carry__3_i_25_n_0\
);
\sign00__0_carry__3_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => sum4(3),
I1 => small_mant(20),
I2 => sum4(4),
I3 => sum4(2),
I4 => sum4(1),
I5 => \sign00__0_carry__2_i_29_n_0\,
O => \sign00__0_carry__3_i_26_n_0\
);
\sign00__0_carry__3_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC5C0C0CAC0C0C0"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__3_i_48_n_0\,
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(17),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(18),
O => \sign00__0_carry__3_i_27_n_0\
);
\sign00__0_carry__3_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0032FFFF00320000"
)
port map (
I0 => sum4(2),
I1 => sum4(4),
I2 => small_mant(19),
I3 => sum4(3),
I4 => sum4(1),
I5 => \sign00__0_carry__2_i_31_n_0\,
O => \sign00__0_carry__3_i_28_n_0\
);
\sign00__0_carry__3_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC5C0C0CAC0C0C0"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__2_i_35_n_0\,
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(16),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(17),
O => \sign00__0_carry__3_i_29_n_0\
);
\sign00__0_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_13_n_0\,
I1 => \sign00__0_carry_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_14_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_3_n_0\
);
\sign00__0_carry__3_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC5C0C0CAC0C0C0"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__2_i_37_n_0\,
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(15),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(16),
O => \sign00__0_carry__3_i_30_n_0\
);
\sign00__0_carry__3_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_30_n_0\,
I1 => \sign00__0_carry__0_i_31_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_46_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_41_n_0\,
O => \sign00__0_carry__3_i_31_n_0\
);
\sign00__0_carry__3_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_39_n_0\,
I1 => \sign00__0_carry__2_i_35_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_51_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_47_n_0\,
O => \sign00__0_carry__3_i_32_n_0\
);
\sign00__0_carry__3_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_39_n_0\,
I1 => \sign00__0_carry__0_i_38_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_47_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_44_n_0\,
O => \sign00__0_carry__3_i_33_n_0\
);
\sign00__0_carry__3_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_40_n_0\,
I1 => \sign00__0_carry__2_i_37_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_48_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_52_n_0\,
O => \sign00__0_carry__3_i_34_n_0\
);
\sign00__0_carry__3_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_41_n_0\,
I1 => \sign00__0_carry__2_i_39_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__2_i_35_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_51_n_0\,
O => \sign00__0_carry__3_i_35_n_0\
);
\sign00__0_carry__3_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_51_n_0\,
I1 => \sign00__0_carry__0_i_30_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_31_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_46_n_0\,
O => \sign00__0_carry__3_i_36_n_0\
);
\sign00__0_carry__3_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000031002000"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry_i_41_n_0\,
I2 => small_mant(0),
I3 => \sign00__0_carry_i_39_n_0\,
I4 => small_mant(1),
I5 => \sign00__0_carry_i_38_n_0\,
O => \sign00__0_carry__3_i_37_n_0\
);
\sign00__0_carry__3_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_44_n_0\,
I1 => \sign00__0_carry__2_i_40_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__2_i_37_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_48_n_0\,
O => \sign00__0_carry__3_i_38_n_0\
);
\sign00__0_carry__3_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_41_n_0\,
I1 => \sign00__0_carry__0_i_39_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_38_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_47_n_0\,
O => \sign00__0_carry__3_i_39_n_0\
);
\sign00__0_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_15_n_0\,
I1 => \sign00__0_carry_i_22_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_16_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_4_n_0\
);
\sign00__0_carry__3_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => \sign00__0_carry_i_41_n_0\,
I1 => small_mant(0),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => sum4(0),
I4 => \sign00__0_carry_i_38_n_0\,
O => \sign00__0_carry__3_i_40_n_0\
);
\sign00__0_carry__3_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => large_mant1_carry_n_0,
O => small_mant(22)
);
\sign00__0_carry__3_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => large_mant1_carry_n_0,
O => small_mant(20)
);
\sign00__0_carry__3_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(21),
I1 => x(21),
I2 => large_mant1_carry_n_0,
O => small_mant(21)
);
\sign00__0_carry__3_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(19),
I1 => x(19),
I2 => large_mant1_carry_n_0,
O => small_mant(19)
);
\sign00__0_carry__3_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => large_mant1_carry_n_0,
O => small_mant(16)
);
\sign00__0_carry__3_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(17),
I1 => x(17),
I2 => large_mant1_carry_n_0,
O => small_mant(17)
);
\sign00__0_carry__3_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(18),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(19),
O => \sign00__0_carry__3_i_47_n_0\
);
\sign00__0_carry__3_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(15),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(16),
O => \sign00__0_carry__3_i_48_n_0\
);
\sign00__0_carry__3_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => large_mant1_carry_n_0,
O => small_mant(18)
);
\sign00__0_carry__3_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__3_i_9_n_0\,
I1 => sum2(19),
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(19),
O => \sign00__0_carry__3_i_5_n_0\
);
\sign00__0_carry__3_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(15),
I1 => x(15),
I2 => large_mant1_carry_n_0,
O => small_mant(15)
);
\sign00__0_carry__3_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(16),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(17),
O => \sign00__0_carry__3_i_51_n_0\
);
\sign00__0_carry__3_i_52\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(17),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(18),
O => \sign00__0_carry__3_i_52_n_0\
);
\sign00__0_carry__3_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__3_i_11_n_0\,
I1 => sum2(18),
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(18),
O => \sign00__0_carry__3_i_6_n_0\
);
\sign00__0_carry__3_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__3_i_13_n_0\,
I1 => \sign00__0_carry__3_i_21_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(17),
I5 => x(17),
O => \sign00__0_carry__3_i_7_n_0\
);
\sign00__0_carry__3_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__3_i_15_n_0\,
I1 => \sign00__0_carry__3_i_22_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(16),
I5 => x(16),
O => \sign00__0_carry__3_i_8_n_0\
);
\sign00__0_carry__3_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_23_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_9_n_0\
);
\sign00__0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__3_n_0\,
CO(3) => \sign00__0_carry__4_n_0\,
CO(2) => \sign00__0_carry__4_n_1\,
CO(1) => \sign00__0_carry__4_n_2\,
CO(0) => \sign00__0_carry__4_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__4_i_1_n_0\,
DI(2) => \sign00__0_carry__4_i_2_n_0\,
DI(1) => \sign00__0_carry__4_i_3_n_0\,
DI(0) => \sign00__0_carry__4_i_4_n_0\,
O(3 downto 0) => sel0(22 downto 19),
S(3) => \sign00__0_carry__4_i_5_n_0\,
S(2) => \sign00__0_carry__4_i_6_n_0\,
S(1) => \sign00__0_carry__4_i_7_n_0\,
S(0) => \sign00__0_carry__4_i_8_n_0\
);
\sign00__0_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555303FAAAACFC0"
)
port map (
I0 => \sign00__0_carry__4_i_9_n_0\,
I1 => \sign00__0_carry__4_i_10_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_11_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_1_n_0\
);
\sign00__0_carry__4_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__1_i_26_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_26_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__4_i_10_n_0\
);
\sign00__0_carry__4_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_27_n_0\,
I1 => \sign00__0_carry__2_i_23_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_25_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_21_n_0\,
O => \sign00__0_carry__4_i_11_n_0\
);
\sign00__0_carry__4_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"7747FFFFFFFFFFFF"
)
port map (
I0 => \sign00__0_carry__4_i_22_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__4_i_23_n_0\,
I3 => sum4(1),
I4 => \sign00__0_carry_i_25_n_0\,
I5 => sum3,
O => \sign00__0_carry__4_i_12_n_0\
);
\sign00__0_carry__4_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_29_n_0\,
I1 => \sign00__0_carry__2_i_25_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_24_n_0\,
O => \sign00__0_carry__4_i_13_n_0\
);
\sign00__0_carry__4_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0DFFFFFFFFFFFFF"
)
port map (
I0 => \sign00__0_carry__4_i_23_n_0\,
I1 => sum4(1),
I2 => sum4(0),
I3 => \sign00__0_carry__4_i_25_n_0\,
I4 => \sign00__0_carry_i_25_n_0\,
I5 => sum3,
O => \sign00__0_carry__4_i_14_n_0\
);
\sign00__0_carry__4_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_31_n_0\,
I1 => \sign00__0_carry__2_i_27_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_29_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_26_n_0\,
O => \sign00__0_carry__4_i_15_n_0\
);
\sign00__0_carry__4_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__4_i_25_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_23_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__4_i_16_n_0\
);
\sign00__0_carry__4_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_33_n_0\,
I1 => \sign00__0_carry__2_i_28_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_30_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_27_n_0\,
O => \sign00__0_carry__4_i_17_n_0\
);
\sign00__0_carry__4_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__4_i_28_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_29_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__0_i_28_n_0\,
O => \sign00__0_carry__4_i_18_n_0\
);
\sign00__0_carry__4_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__4_i_30_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_31_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__4_i_32_n_0\,
O => \sign00__0_carry__4_i_19_n_0\
);
\sign00__0_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__4_i_12_n_0\,
I1 => \sign00__0_carry__0_i_11_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_13_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_2_n_0\
);
\sign00__0_carry__4_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__4_i_33_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_34_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__4_i_35_n_0\,
O => \sign00__0_carry__4_i_20_n_0\
);
\sign00__0_carry__4_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"D8FFD85500000000"
)
port map (
I0 => sum4(0),
I1 => small_mant(20),
I2 => small_mant(21),
I3 => \sign00__0_carry_i_41_n_0\,
I4 => small_mant(22),
I5 => \sign00__0_carry_i_39_n_0\,
O => \sign00__0_carry__4_i_21_n_0\
);
\sign00__0_carry__4_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sum4(2),
I1 => sum4(4),
I2 => sum4(3),
I3 => sum4(1),
O => \sign00__0_carry__4_i_22_n_0\
);
\sign00__0_carry__4_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000005410"
)
port map (
I0 => sum4(3),
I1 => large_mant1_carry_n_0,
I2 => x(22),
I3 => y(22),
I4 => sum4(4),
I5 => sum4(2),
O => \sign00__0_carry__4_i_23_n_0\
);
\sign00__0_carry__4_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(19),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(20),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_36_n_0\,
O => \sign00__0_carry__4_i_24_n_0\
);
\sign00__0_carry__4_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000032"
)
port map (
I0 => sum4(1),
I1 => sum4(3),
I2 => small_mant(21),
I3 => sum4(4),
I4 => sum4(2),
O => \sign00__0_carry__4_i_25_n_0\
);
\sign00__0_carry__4_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(18),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(19),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_37_n_0\,
O => \sign00__0_carry__4_i_26_n_0\
);
\sign00__0_carry__4_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(17),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(18),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_38_n_0\,
O => \sign00__0_carry__4_i_27_n_0\
);
\sign00__0_carry__4_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__3_i_48_n_0\,
I1 => \sign00__0_carry__3_i_52_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__4_i_38_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_36_n_0\,
O => \sign00__0_carry__4_i_28_n_0\
);
\sign00__0_carry__4_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_47_n_0\,
I1 => \sign00__0_carry__1_i_44_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__2_i_40_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_37_n_0\,
O => \sign00__0_carry__4_i_29_n_0\
);
\sign00__0_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__4_i_14_n_0\,
I1 => \sign00__0_carry__0_i_13_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_15_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_3_n_0\
);
\sign00__0_carry__4_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_35_n_0\,
I1 => \sign00__0_carry__3_i_51_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_47_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_37_n_0\,
O => \sign00__0_carry__4_i_30_n_0\
);
\sign00__0_carry__4_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_31_n_0\,
I1 => \sign00__0_carry__1_i_46_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_41_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_39_n_0\,
O => \sign00__0_carry__4_i_31_n_0\
);
\sign00__0_carry__4_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry__0_i_29_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry_i_51_n_0\,
I3 => \sign00__0_carry_i_41_n_0\,
I4 => \sign00__0_carry__0_i_30_n_0\,
O => \sign00__0_carry__4_i_32_n_0\
);
\sign00__0_carry__4_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_37_n_0\,
I1 => \sign00__0_carry__3_i_48_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_52_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_38_n_0\,
O => \sign00__0_carry__4_i_33_n_0\
);
\sign00__0_carry__4_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_38_n_0\,
I1 => \sign00__0_carry__1_i_47_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_44_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_40_n_0\,
O => \sign00__0_carry__4_i_34_n_0\
);
\sign00__0_carry__4_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__4_i_39_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_41_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_39_n_0\,
O => \sign00__0_carry__4_i_35_n_0\
);
\sign00__0_carry__4_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(21),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(22),
O => \sign00__0_carry__4_i_36_n_0\
);
\sign00__0_carry__4_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(20),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(21),
O => \sign00__0_carry__4_i_37_n_0\
);
\sign00__0_carry__4_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(19),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(20),
O => \sign00__0_carry__4_i_38_n_0\
);
\sign00__0_carry__4_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101010000010000"
)
port map (
I0 => \sign00__0_carry_i_69_n_0\,
I1 => \sign00__0_carry_i_59_n_0\,
I2 => \sign00__0_carry_i_58_n_0\,
I3 => large_mant1_carry_n_0,
I4 => x(0),
I5 => y(0),
O => \sign00__0_carry__4_i_39_n_0\
);
\sign00__0_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__4_i_16_n_0\,
I1 => \sign00__0_carry__0_i_15_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_17_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_4_n_0\
);
\sign00__0_carry__4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA999A966655565"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry__4_i_11_n_0\,
I3 => \sign00__0_carry_i_17_n_0\,
I4 => \sign00__0_carry__4_i_10_n_0\,
I5 => \sign00__0_carry__4_i_9_n_0\,
O => \sign00__0_carry__4_i_5_n_0\
);
\sign00__0_carry__4_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__4_i_12_n_0\,
I1 => \sign00__0_carry__4_i_18_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(22),
I5 => x(22),
O => \sign00__0_carry__4_i_6_n_0\
);
\sign00__0_carry__4_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__4_i_14_n_0\,
I1 => \sign00__0_carry__4_i_19_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(21),
I5 => x(21),
O => \sign00__0_carry__4_i_7_n_0\
);
\sign00__0_carry__4_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__4_i_16_n_0\,
I1 => \sign00__0_carry__4_i_20_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(20),
I5 => x(20),
O => \sign00__0_carry__4_i_8_n_0\
);
\sign00__0_carry__4_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \sign00__0_carry_i_25_n_0\,
I1 => sum4(0),
I2 => sum4(2),
I3 => sum4(4),
I4 => sum4(3),
I5 => sum4(1),
O => \sign00__0_carry__4_i_9_n_0\
);
\sign00__0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__4_n_0\,
CO(3 downto 0) => \NLW_sign00__0_carry__5_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_sign00__0_carry__5_O_UNCONNECTED\(3 downto 1),
O(0) => sel0(23),
S(3 downto 1) => B"000",
S(0) => \sign00__0_carry__5_i_1_n_0\
);
\sign00__0_carry__5_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9A999AAA"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry__1_i_16_n_0\,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry__5_i_2_n_0\,
O => \sign00__0_carry__5_i_1_n_0\
);
\sign00__0_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_28_n_0\,
I1 => \sign00__0_carry__3_i_30_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__5_i_3_n_0\,
O => \sign00__0_carry__5_i_2_n_0\
);
\sign00__0_carry__5_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFC00000"
)
port map (
I0 => small_mant(21),
I1 => small_mant(22),
I2 => \sign00__0_carry_i_41_n_0\,
I3 => sum4(0),
I4 => \sign00__0_carry_i_39_n_0\,
O => \sign00__0_carry__5_i_3_n_0\
);
\sign00__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(0),
I1 => y(0),
I2 => large_mant1_carry_n_0,
O => A(0)
);
\sign00__0_carry_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry_i_23_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry_i_10_n_0\
);
\sign00__0_carry_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_100_n_0\
);
\sign00__0_carry_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_101_n_0\
);
\sign00__0_carry_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_102_n_0\
);
\sign00__0_carry_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_103_n_0\
);
\sign00__0_carry_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_104_n_0\
);
\sign00__0_carry_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_105_n_0\
);
\sign00__0_carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050005030"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => \sign00__0_carry_i_26_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_12_n_5\,
I5 => sum4(3),
O => \sign00__0_carry_i_11_n_0\
);
\sign00__0_carry_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \sign00__0_carry_i_12_n_0\,
CO(2) => \sign00__0_carry_i_12_n_1\,
CO(1) => \sign00__0_carry_i_12_n_2\,
CO(0) => \sign00__0_carry_i_12_n_3\,
CYINIT => p_0_in(0),
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_12_n_4\,
O(2) => \sign00__0_carry_i_12_n_5\,
O(1) => \sign00__0_carry_i_12_n_6\,
O(0) => \sign00__0_carry_i_12_n_7\,
S(3 downto 0) => p_0_in(4 downto 1)
);
\sign00__0_carry_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_32_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry_i_13_n_0\
);
\sign00__0_carry_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050005030"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => \sign00__0_carry_i_33_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_12_n_5\,
I5 => sum4(3),
O => \sign00__0_carry_i_14_n_0\
);
\sign00__0_carry_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry_i_32_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_34_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry_i_15_n_0\
);
\sign00__0_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050005030"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => \sign00__0_carry_i_35_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_12_n_5\,
I5 => sum4(3),
O => \sign00__0_carry_i_16_n_0\
);
\sign00__0_carry_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(4),
I1 => \sign00__0_carry_i_12_n_4\,
I2 => sum3,
O => \sign00__0_carry_i_17_n_0\
);
\sign00__0_carry_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(3),
I1 => y(3),
I2 => large_mant1_carry_n_0,
O => A(3)
);
\sign00__0_carry_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(2),
I1 => y(2),
I2 => large_mant1_carry_n_0,
O => A(2)
);
\sign00__0_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_10_n_0\,
I1 => \sign00__0_carry_i_11_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry_i_2_n_0\
);
\sign00__0_carry_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(1),
I1 => y(1),
I2 => large_mant1_carry_n_0,
O => A(1)
);
\sign00__0_carry_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \sign00__0_carry_i_25_n_0\,
I1 => \sign00__0_carry_i_36_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry_i_37_n_0\,
I4 => sum4(0),
I5 => \sign00__0_carry_i_34_n_0\,
O => \sign00__0_carry_i_21_n_0\
);
\sign00__0_carry_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(0),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry_i_22_n_0\
);
\sign00__0_carry_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8FF33CC00"
)
port map (
I0 => \sign00__0_carry_i_43_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_44_n_0\,
I3 => \sign00__0_carry_i_45_n_0\,
I4 => \sign00__0_carry_i_46_n_0\,
I5 => sum4(1),
O => \sign00__0_carry_i_23_n_0\
);
\sign00__0_carry_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \sign00__0_carry_i_47_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_48_n_0\,
I3 => sum4(1),
I4 => \sign00__0_carry_i_49_n_0\,
O => \sign00__0_carry_i_24_n_0\
);
\sign00__0_carry_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
I1 => sum4(6),
I2 => sum4(5),
I3 => sum4(7),
O => \sign00__0_carry_i_25_n_0\
);
\sign00__0_carry_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(0),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(1),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry_i_51_n_0\,
O => \sign00__0_carry_i_26_n_0\
);
\sign00__0_carry_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(0),
O => p_0_in(0)
);
\sign00__0_carry_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(4),
O => p_0_in(4)
);
\sign00__0_carry_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(3),
O => p_0_in(3)
);
\sign00__0_carry_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_13_n_0\,
I1 => \sign00__0_carry_i_14_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry_i_3_n_0\
);
\sign00__0_carry_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(2),
O => p_0_in(2)
);
\sign00__0_carry_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(1),
O => p_0_in(1)
);
\sign00__0_carry_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \sign00__0_carry_i_45_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_46_n_0\,
I3 => sum4(1),
I4 => \sign00__0_carry_i_37_n_0\,
O => \sign00__0_carry_i_32_n_0\
);
\sign00__0_carry_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F4500004A400000"
)
port map (
I0 => sum4(0),
I1 => small_mant(0),
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(1),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(2),
O => \sign00__0_carry_i_33_n_0\
);
\sign00__0_carry_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry_i_49_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry_i_48_n_0\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_53_n_0\,
O => \sign00__0_carry_i_34_n_0\
);
\sign00__0_carry_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C808"
)
port map (
I0 => small_mant(1),
I1 => \sign00__0_carry_i_39_n_0\,
I2 => sum4(0),
I3 => small_mant(0),
I4 => \sign00__0_carry_i_41_n_0\,
O => \sign00__0_carry_i_35_n_0\
);
\sign00__0_carry_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry_i_46_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_54_n_0\,
I3 => sum4(3),
I4 => \sign00__0_carry_i_55_n_0\,
O => \sign00__0_carry_i_36_n_0\
);
\sign00__0_carry_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry_i_44_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_56_n_0\,
I3 => sum4(3),
I4 => \sign00__0_carry_i_57_n_0\,
O => \sign00__0_carry_i_37_n_0\
);
\sign00__0_carry_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => sum3,
O => \sign00__0_carry_i_38_n_0\
);
\sign00__0_carry_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \sign00__0_carry_i_58_n_0\,
I1 => \sign00__0_carry_i_59_n_0\,
I2 => \sign00__0_carry_i_60_n_0\,
I3 => \sign00__0_carry_i_61_n_0\,
I4 => \sign00__0_carry_i_62_n_0\,
I5 => \sign00__0_carry_i_63_n_0\,
O => \sign00__0_carry_i_39_n_0\
);
\sign00__0_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_15_n_0\,
I1 => \sign00__0_carry_i_16_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry_i_4_n_0\
);
\sign00__0_carry_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(0),
I1 => x(0),
I2 => large_mant1_carry_n_0,
O => small_mant(0)
);
\sign00__0_carry_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(1),
I1 => \sign00__0_carry_i_12_n_7\,
I2 => sum3,
O => \sign00__0_carry_i_41_n_0\
);
\sign00__0_carry_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(3),
I1 => \sign00__0_carry_i_12_n_5\,
I2 => sum3,
O => \sign00__0_carry_i_42_n_0\
);
\sign00__0_carry_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(18),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(10),
I4 => y(10),
I5 => sum4(4),
O => \sign00__0_carry_i_43_n_0\
);
\sign00__0_carry_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(14),
I2 => y(14),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_64_n_0\,
O => \sign00__0_carry_i_44_n_0\
);
\sign00__0_carry_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(16),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(8),
I4 => y(8),
I5 => sum4(4),
O => \sign00__0_carry_i_45_n_0\
);
\sign00__0_carry_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(12),
I2 => y(12),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_65_n_0\,
O => \sign00__0_carry_i_46_n_0\
);
\sign00__0_carry_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(17),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(9),
I4 => y(9),
I5 => sum4(4),
O => \sign00__0_carry_i_47_n_0\
);
\sign00__0_carry_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(13),
I2 => y(13),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_66_n_0\,
O => \sign00__0_carry_i_48_n_0\
);
\sign00__0_carry_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry__0_i_34_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_67_n_0\,
I3 => sum4(3),
I4 => \sign00__0_carry_i_68_n_0\,
O => \sign00__0_carry_i_49_n_0\
);
\sign00__0_carry_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => x(31),
I1 => y(31),
O => \sign00__0_carry_i_5_n_0\
);
\sign00__0_carry_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(1),
I1 => x(1),
I2 => large_mant1_carry_n_0,
O => small_mant(1)
);
\sign00__0_carry_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(2),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(3),
O => \sign00__0_carry_i_51_n_0\
);
\sign00__0_carry_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(2),
I1 => x(2),
I2 => large_mant1_carry_n_0,
O => small_mant(2)
);
\sign00__0_carry_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(9),
I2 => y(9),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_70_n_0\,
O => \sign00__0_carry_i_53_n_0\
);
\sign00__0_carry_i_54\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(8),
I2 => y(8),
I3 => sum4(4),
O => \sign00__0_carry_i_54_n_0\
);
\sign00__0_carry_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => sum4(4),
I3 => y(0),
I4 => x(0),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_55_n_0\
);
\sign00__0_carry_i_56\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(10),
I2 => y(10),
I3 => sum4(4),
O => \sign00__0_carry_i_56_n_0\
);
\sign00__0_carry_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => sum4(4),
I3 => y(2),
I4 => x(2),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_57_n_0\
);
\sign00__0_carry_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF32FE"
)
port map (
I0 => \sign00__0_carry_i_71_n_7\,
I1 => sum3,
I2 => \sign00__0_carry_i_71_n_6\,
I3 => \sum3_carry__0_i_9_n_3\,
I4 => \sign00__0_carry_i_72_n_0\,
I5 => \sign00__0_carry_i_73_n_0\,
O => \sign00__0_carry_i_58_n_0\
);
\sign00__0_carry_i_59\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACFCA"
)
port map (
I0 => \sign00__0_carry_i_74_n_7\,
I1 => sum4(5),
I2 => sum3,
I3 => \sign00__0_carry_i_74_n_6\,
I4 => sum4(6),
O => \sign00__0_carry_i_59_n_0\
);
\sign00__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_10_n_0\,
I1 => \sign00__0_carry_i_11_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(3),
O => \sign00__0_carry_i_6_n_0\
);
\sign00__0_carry_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_75_n_4\,
I1 => \sign00__0_carry_i_75_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_76_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_76_n_7\,
O => \sign00__0_carry_i_60_n_0\
);
\sign00__0_carry_i_61\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_76_n_4\,
I1 => \sign00__0_carry_i_76_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_77_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_77_n_7\,
O => \sign00__0_carry_i_61_n_0\
);
\sign00__0_carry_i_62\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_78_n_4\,
I1 => \sign00__0_carry_i_78_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_79_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_79_n_7\,
O => \sign00__0_carry_i_62_n_0\
);
\sign00__0_carry_i_63\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_79_n_4\,
I1 => \sign00__0_carry_i_79_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_75_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_75_n_7\,
O => \sign00__0_carry_i_63_n_0\
);
\sign00__0_carry_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => sum4(4),
I3 => y(6),
I4 => x(6),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_64_n_0\
);
\sign00__0_carry_i_65\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => sum4(4),
I3 => y(4),
I4 => x(4),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_65_n_0\
);
\sign00__0_carry_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(21),
I1 => x(21),
I2 => sum4(4),
I3 => y(5),
I4 => x(5),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_66_n_0\
);
\sign00__0_carry_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(11),
I2 => y(11),
I3 => sum4(4),
O => \sign00__0_carry_i_67_n_0\
);
\sign00__0_carry_i_68\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(19),
I1 => x(19),
I2 => sum4(4),
I3 => y(3),
I4 => x(3),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_68_n_0\
);
\sign00__0_carry_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \sign00__0_carry_i_63_n_0\,
I1 => \sign00__0_carry_i_62_n_0\,
I2 => \sign00__0_carry_i_61_n_0\,
I3 => \sign00__0_carry_i_60_n_0\,
O => \sign00__0_carry_i_69_n_0\
);
\sign00__0_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_13_n_0\,
I1 => \sign00__0_carry_i_14_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(2),
O => \sign00__0_carry_i_7_n_0\
);
\sign00__0_carry_i_70\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(17),
I1 => x(17),
I2 => sum4(4),
I3 => y(1),
I4 => x(1),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_70_n_0\
);
\sign00__0_carry_i_71\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_74_n_0\,
CO(3) => \sign00__0_carry_i_71_n_0\,
CO(2) => \sign00__0_carry_i_71_n_1\,
CO(1) => \sign00__0_carry_i_71_n_2\,
CO(0) => \sign00__0_carry_i_71_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_71_n_4\,
O(2) => \sign00__0_carry_i_71_n_5\,
O(1) => \sign00__0_carry_i_71_n_6\,
O(0) => \sign00__0_carry_i_71_n_7\,
S(3) => \sign00__0_carry_i_80_n_0\,
S(2) => \sign00__0_carry_i_81_n_0\,
S(1) => \sign00__0_carry_i_82_n_0\,
S(0) => \sign00__0_carry_i_83_n_0\
);
\sign00__0_carry_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"CFCAFFFA"
)
port map (
I0 => \sign00__0_carry_i_74_n_5\,
I1 => sum4(7),
I2 => sum3,
I3 => \sign00__0_carry_i_74_n_4\,
I4 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_72_n_0\
);
\sign00__0_carry_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_71_n_4\,
I1 => \sign00__0_carry_i_71_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_78_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_78_n_7\,
O => \sign00__0_carry_i_73_n_0\
);
\sign00__0_carry_i_74\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_12_n_0\,
CO(3) => \sign00__0_carry_i_74_n_0\,
CO(2) => \sign00__0_carry_i_74_n_1\,
CO(1) => \sign00__0_carry_i_74_n_2\,
CO(0) => \sign00__0_carry_i_74_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_74_n_4\,
O(2) => \sign00__0_carry_i_74_n_5\,
O(1) => \sign00__0_carry_i_74_n_6\,
O(0) => \sign00__0_carry_i_74_n_7\,
S(3) => \sign00__0_carry_i_84_n_0\,
S(2) => \sign00__0_carry_i_85_n_0\,
S(1) => \sign00__0_carry_i_86_n_0\,
S(0) => \sign00__0_carry_i_87_n_0\
);
\sign00__0_carry_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_79_n_0\,
CO(3) => \sign00__0_carry_i_75_n_0\,
CO(2) => \sign00__0_carry_i_75_n_1\,
CO(1) => \sign00__0_carry_i_75_n_2\,
CO(0) => \sign00__0_carry_i_75_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_75_n_4\,
O(2) => \sign00__0_carry_i_75_n_5\,
O(1) => \sign00__0_carry_i_75_n_6\,
O(0) => \sign00__0_carry_i_75_n_7\,
S(3) => \sign00__0_carry_i_88_n_0\,
S(2) => \sign00__0_carry_i_89_n_0\,
S(1) => \sign00__0_carry_i_90_n_0\,
S(0) => \sign00__0_carry_i_91_n_0\
);
\sign00__0_carry_i_76\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_75_n_0\,
CO(3) => \sign00__0_carry_i_76_n_0\,
CO(2) => \sign00__0_carry_i_76_n_1\,
CO(1) => \sign00__0_carry_i_76_n_2\,
CO(0) => \sign00__0_carry_i_76_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_76_n_4\,
O(2) => \sign00__0_carry_i_76_n_5\,
O(1) => \sign00__0_carry_i_76_n_6\,
O(0) => \sign00__0_carry_i_76_n_7\,
S(3) => \sign00__0_carry_i_92_n_0\,
S(2) => \sign00__0_carry_i_93_n_0\,
S(1) => \sign00__0_carry_i_94_n_0\,
S(0) => \sign00__0_carry_i_95_n_0\
);
\sign00__0_carry_i_77\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_76_n_0\,
CO(3 downto 1) => \NLW_sign00__0_carry_i_77_CO_UNCONNECTED\(3 downto 1),
CO(0) => \sign00__0_carry_i_77_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_sign00__0_carry_i_77_O_UNCONNECTED\(3 downto 2),
O(1) => \sign00__0_carry_i_77_n_6\,
O(0) => \sign00__0_carry_i_77_n_7\,
S(3 downto 2) => B"00",
S(1) => \sign00__0_carry_i_96_n_0\,
S(0) => \sign00__0_carry_i_97_n_0\
);
\sign00__0_carry_i_78\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_71_n_0\,
CO(3) => \sign00__0_carry_i_78_n_0\,
CO(2) => \sign00__0_carry_i_78_n_1\,
CO(1) => \sign00__0_carry_i_78_n_2\,
CO(0) => \sign00__0_carry_i_78_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_78_n_4\,
O(2) => \sign00__0_carry_i_78_n_5\,
O(1) => \sign00__0_carry_i_78_n_6\,
O(0) => \sign00__0_carry_i_78_n_7\,
S(3) => \sign00__0_carry_i_98_n_0\,
S(2) => \sign00__0_carry_i_99_n_0\,
S(1) => \sign00__0_carry_i_100_n_0\,
S(0) => \sign00__0_carry_i_101_n_0\
);
\sign00__0_carry_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_78_n_0\,
CO(3) => \sign00__0_carry_i_79_n_0\,
CO(2) => \sign00__0_carry_i_79_n_1\,
CO(1) => \sign00__0_carry_i_79_n_2\,
CO(0) => \sign00__0_carry_i_79_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_79_n_4\,
O(2) => \sign00__0_carry_i_79_n_5\,
O(1) => \sign00__0_carry_i_79_n_6\,
O(0) => \sign00__0_carry_i_79_n_7\,
S(3) => \sign00__0_carry_i_102_n_0\,
S(2) => \sign00__0_carry_i_103_n_0\,
S(1) => \sign00__0_carry_i_104_n_0\,
S(0) => \sign00__0_carry_i_105_n_0\
);
\sign00__0_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_15_n_0\,
I1 => \sign00__0_carry_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(1),
O => \sign00__0_carry_i_8_n_0\
);
\sign00__0_carry_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_80_n_0\
);
\sign00__0_carry_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_81_n_0\
);
\sign00__0_carry_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_82_n_0\
);
\sign00__0_carry_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_83_n_0\
);
\sign00__0_carry_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_84_n_0\
);
\sign00__0_carry_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(7),
O => \sign00__0_carry_i_85_n_0\
);
\sign00__0_carry_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(6),
O => \sign00__0_carry_i_86_n_0\
);
\sign00__0_carry_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(5),
O => \sign00__0_carry_i_87_n_0\
);
\sign00__0_carry_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_88_n_0\
);
\sign00__0_carry_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_89_n_0\
);
\sign00__0_carry_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"A0AC"
)
port map (
I0 => \sign00__0_carry_i_21_n_0\,
I1 => \sign00__0_carry_i_22_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
O => \sign00__0_carry_i_9_n_0\
);
\sign00__0_carry_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_90_n_0\
);
\sign00__0_carry_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_91_n_0\
);
\sign00__0_carry_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_92_n_0\
);
\sign00__0_carry_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_93_n_0\
);
\sign00__0_carry_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_94_n_0\
);
\sign00__0_carry_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_95_n_0\
);
\sign00__0_carry_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_96_n_0\
);
\sign00__0_carry_i_97\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_97_n_0\
);
\sign00__0_carry_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_98_n_0\
);
\sign00__0_carry_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_99_n_0\
);
sum3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sum3_carry_n_0,
CO(2) => sum3_carry_n_1,
CO(1) => sum3_carry_n_2,
CO(0) => sum3_carry_n_3,
CYINIT => '1',
DI(3) => sum3_carry_i_1_n_0,
DI(2) => sum3_carry_i_2_n_0,
DI(1) => sum3_carry_i_3_n_0,
DI(0) => sum3_carry_i_4_n_0,
O(3 downto 0) => NLW_sum3_carry_O_UNCONNECTED(3 downto 0),
S(3) => sum3_carry_i_5_n_0,
S(2) => sum3_carry_i_6_n_0,
S(1) => sum3_carry_i_7_n_0,
S(0) => sum3_carry_i_8_n_0
);
\sum3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sum3_carry_n_0,
CO(3) => \sum3_carry__0_n_0\,
CO(2) => \sum3_carry__0_n_1\,
CO(1) => \sum3_carry__0_n_2\,
CO(0) => \sum3_carry__0_n_3\,
CYINIT => '0',
DI(3) => \sum3_carry__0_i_1_n_0\,
DI(2) => \sum3_carry__0_i_2_n_0\,
DI(1) => \sum3_carry__0_i_3_n_0\,
DI(0) => \sum3_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_sum3_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \sum3_carry__0_i_5_n_0\,
S(2) => \sum3_carry__0_i_6_n_0\,
S(1) => \sum3_carry__0_i_7_n_0\,
S(0) => \sum3_carry__0_i_8_n_0\
);
\sum3_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_1_n_0\
);
\sum3_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_2_n_0\
);
\sum3_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_3_n_0\
);
\sum3_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_4_n_0\
);
\sum3_carry__0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_5_n_0\
);
\sum3_carry__0_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_6_n_0\
);
\sum3_carry__0_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_7_n_0\
);
\sum3_carry__0_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_8_n_0\
);
\sum3_carry__0_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \sum4_carry__0_n_0\,
CO(3 downto 1) => \NLW_sum3_carry__0_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \sum3_carry__0_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_sum3_carry__0_i_9_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => B"0001"
);
\sum3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sum3_carry__0_n_0\,
CO(3) => \sum3_carry__1_n_0\,
CO(2) => \sum3_carry__1_n_1\,
CO(1) => \sum3_carry__1_n_2\,
CO(0) => \sum3_carry__1_n_3\,
CYINIT => '0',
DI(3) => \sum3_carry__1_i_1_n_0\,
DI(2) => \sum3_carry__1_i_2_n_0\,
DI(1) => \sum3_carry__1_i_3_n_0\,
DI(0) => \sum3_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_sum3_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \sum3_carry__1_i_5_n_0\,
S(2) => \sum3_carry__1_i_6_n_0\,
S(1) => \sum3_carry__1_i_7_n_0\,
S(0) => \sum3_carry__1_i_8_n_0\
);
\sum3_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_1_n_0\
);
\sum3_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_2_n_0\
);
\sum3_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_3_n_0\
);
\sum3_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_4_n_0\
);
\sum3_carry__1_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_5_n_0\
);
\sum3_carry__1_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_6_n_0\
);
\sum3_carry__1_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_7_n_0\
);
\sum3_carry__1_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_8_n_0\
);
\sum3_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sum3_carry__1_n_0\,
CO(3) => sum3,
CO(2) => \sum3_carry__2_n_1\,
CO(1) => \sum3_carry__2_n_2\,
CO(0) => \sum3_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => sum4(31),
DI(1) => \sum3_carry__2_i_2_n_0\,
DI(0) => \sum3_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_sum3_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \sum3_carry__2_i_4_n_0\,
S(2) => \sum3_carry__2_i_5_n_0\,
S(1) => \sum3_carry__2_i_6_n_0\,
S(0) => \sum3_carry__2_i_7_n_0\
);
\sum3_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => sum4(31)
);
\sum3_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_2_n_0\
);
\sum3_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_3_n_0\
);
\sum3_carry__2_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_4_n_0\
);
\sum3_carry__2_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_5_n_0\
);
\sum3_carry__2_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_6_n_0\
);
\sum3_carry__2_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_7_n_0\
);
sum3_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(6),
I1 => sum4(7),
O => sum3_carry_i_1_n_0
);
sum3_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(4),
I1 => sum4(5),
O => sum3_carry_i_2_n_0
);
sum3_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(2),
I1 => sum4(3),
O => sum3_carry_i_3_n_0
);
sum3_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(0),
I1 => sum4(1),
O => sum3_carry_i_4_n_0
);
sum3_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(6),
I1 => sum4(7),
O => sum3_carry_i_5_n_0
);
sum3_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(4),
I1 => sum4(5),
O => sum3_carry_i_6_n_0
);
sum3_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(2),
I1 => sum4(3),
O => sum3_carry_i_7_n_0
);
sum3_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(0),
I1 => sum4(1),
O => sum3_carry_i_8_n_0
);
sum4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sum4_carry_n_0,
CO(2) => sum4_carry_n_1,
CO(1) => sum4_carry_n_2,
CO(0) => sum4_carry_n_3,
CYINIT => '1',
DI(3) => sum4_carry_i_1_n_0,
DI(2) => sum4_carry_i_2_n_0,
DI(1) => sum4_carry_i_3_n_0,
DI(0) => sum4_carry_i_4_n_0,
O(3 downto 0) => sum4(3 downto 0),
S(3) => sum4_carry_i_5_n_0,
S(2) => sum4_carry_i_6_n_0,
S(1) => sum4_carry_i_7_n_0,
S(0) => sum4_carry_i_8_n_0
);
\sum4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sum4_carry_n_0,
CO(3) => \sum4_carry__0_n_0\,
CO(2) => \sum4_carry__0_n_1\,
CO(1) => \sum4_carry__0_n_2\,
CO(0) => \sum4_carry__0_n_3\,
CYINIT => '0',
DI(3) => large_exp(7),
DI(2) => \sum4_carry__0_i_2_n_0\,
DI(1) => \sum4_carry__0_i_3_n_0\,
DI(0) => \sum4_carry__0_i_4_n_0\,
O(3 downto 0) => sum4(7 downto 4),
S(3) => \sum4_carry__0_i_5_n_0\,
S(2) => \sum4_carry__0_i_6_n_0\,
S(1) => \sum4_carry__0_i_7_n_0\,
S(0) => \sum4_carry__0_i_8_n_0\
);
\sum4_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => large_mant1_carry_n_0,
O => large_exp(7)
);
\sum4_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => large_mant1_carry_n_0,
O => \sum4_carry__0_i_2_n_0\
);
\sum4_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(28),
I1 => y(28),
I2 => large_mant1_carry_n_0,
O => \sum4_carry__0_i_3_n_0\
);
\sum4_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => large_mant1_carry_n_0,
O => \sum4_carry__0_i_4_n_0\
);
\sum4_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(30),
I1 => y(30),
O => \sum4_carry__0_i_5_n_0\
);
\sum4_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(29),
I1 => y(29),
O => \sum4_carry__0_i_6_n_0\
);
\sum4_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(28),
I1 => y(28),
O => \sum4_carry__0_i_7_n_0\
);
\sum4_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(27),
I1 => y(27),
O => \sum4_carry__0_i_8_n_0\
);
sum4_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(26),
I1 => y(26),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_1_n_0
);
sum4_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_2_n_0
);
sum4_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(24),
I1 => y(24),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_3_n_0
);
sum4_carry_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_4_n_0
);
sum4_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(26),
I1 => y(26),
O => sum4_carry_i_5_n_0
);
sum4_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(25),
I1 => y(25),
O => sum4_carry_i_6_n_0
);
sum4_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(24),
I1 => y(24),
O => sum4_carry_i_7_n_0
);
sum4_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(23),
I1 => y(23),
O => sum4_carry_i_8_n_0
);
z0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z0_carry_n_0,
CO(2) => z0_carry_n_1,
CO(1) => z0_carry_n_2,
CO(0) => z0_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => large_exp(3 downto 0),
O(3 downto 0) => z(26 downto 23),
S(3) => \z0_carry_i_5__0_n_0\,
S(2) => z0_carry_i_6_n_0,
S(1) => z0_carry_i_7_n_0,
S(0) => z0_carry_i_8_n_0
);
\z0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z0_carry_n_0,
CO(3) => \NLW_z0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z0_carry__0_n_1\,
CO(1) => \z0_carry__0_n_2\,
CO(0) => \z0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => large_exp(6 downto 4),
O(3 downto 0) => z(30 downto 27),
S(3) => z0_carry_i_4_n_0,
S(2) => z0_carry_i_5_n_0,
S(1) => \z0_carry_i_6__0_n_0\,
S(0) => \z0_carry_i_7__0_n_0\
);
z0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(26),
I1 => y(26),
I2 => large_mant1_carry_n_0,
O => large_exp(3)
);
z0_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"5554444400000000"
)
port map (
I0 => sel0(23),
I1 => \_carry_i_5_n_0\,
I2 => sel0(14),
I3 => \_carry_i_6_n_0\,
I4 => \_carry_i_7_n_0\,
I5 => \_carry_i_8_n_0\,
O => z0_carry_i_10_n_0
);
z0_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8A8A8A800"
)
port map (
I0 => \_carry_i_9_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \_carry_i_11_n_0\,
I3 => \_carry_i_12_n_0\,
I4 => sel0(1),
I5 => \_carry_i_13_n_0\,
O => z0_carry_i_11_n_0
);
z0_carry_i_12: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(13),
I1 => sel0(23),
I2 => sel0(11),
I3 => sel0(12),
O => z0_carry_i_12_n_0
);
\z0_carry_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => large_mant1_carry_n_0,
O => large_exp(6)
);
z0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => large_mant1_carry_n_0,
O => large_exp(2)
);
\z0_carry_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(28),
I1 => y(28),
I2 => large_mant1_carry_n_0,
O => large_exp(5)
);
z0_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(24),
I1 => y(24),
I2 => large_mant1_carry_n_0,
O => large_exp(1)
);
\z0_carry_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => large_mant1_carry_n_0,
O => large_exp(4)
);
z0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(30),
I2 => x(30),
I3 => \z[18]_INST_0_i_1_n_0\,
O => z0_carry_i_4_n_0
);
\z0_carry_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => large_mant1_carry_n_0,
O => large_exp(0)
);
z0_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(29),
I2 => x(29),
I3 => \z[18]_INST_0_i_1_n_0\,
O => z0_carry_i_5_n_0
);
\z0_carry_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E41B"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(26),
I2 => x(26),
I3 => z0_carry_i_9_n_0,
O => \z0_carry_i_5__0_n_0\
);
z0_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(25),
I2 => x(25),
I3 => z0_carry_i_10_n_0,
O => z0_carry_i_6_n_0
);
\z0_carry_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(28),
I2 => x(28),
I3 => \z[18]_INST_0_i_1_n_0\,
O => \z0_carry_i_6__0_n_0\
);
z0_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(24),
I2 => x(24),
I3 => z0_carry_i_11_n_0,
O => z0_carry_i_7_n_0
);
\z0_carry_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(27),
I2 => x(27),
I3 => \z0_carry_i_8__0_n_0\,
O => \z0_carry_i_7__0_n_0\
);
z0_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(23),
I2 => x(23),
I3 => \z[22]_INST_0_i_1_n_0\,
O => z0_carry_i_8_n_0
);
\z0_carry_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z0_carry_i_8__0_n_0\
);
z0_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"F1F1F1F1F1F1F100"
)
port map (
I0 => \_carry_i_5_n_0\,
I1 => \z[31]_INST_0_i_7_n_0\,
I2 => sel0(23),
I3 => z0_carry_i_12_n_0,
I4 => \z[31]_INST_0_i_3_n_0\,
I5 => sel0(14),
O => z0_carry_i_9_n_0
);
z2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z2_carry_n_0,
CO(2) => z2_carry_n_1,
CO(1) => z2_carry_n_2,
CO(0) => z2_carry_n_3,
CYINIT => '1',
DI(3) => z2_carry_i_1_n_0,
DI(2) => z2_carry_i_2_n_0,
DI(1) => z2_carry_i_3_n_0,
DI(0) => z2_carry_i_4_n_0,
O(3 downto 0) => NLW_z2_carry_O_UNCONNECTED(3 downto 0),
S(3) => z2_carry_i_5_n_0,
S(2) => z2_carry_i_6_n_0,
S(1) => z2_carry_i_7_n_0,
S(0) => z2_carry_i_8_n_0
);
\z2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z2_carry_n_0,
CO(3) => \z2_carry__0_n_0\,
CO(2) => \z2_carry__0_n_1\,
CO(1) => \z2_carry__0_n_2\,
CO(0) => \z2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \z2_carry__0_i_1_n_0\,
DI(2) => \z2_carry__0_i_2_n_0\,
DI(1) => \z2_carry__0_i_3_n_0\,
DI(0) => \z2_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_z2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \z2_carry__0_i_5_n_0\,
S(2) => \z2_carry__0_i_6_n_0\,
S(1) => \z2_carry__0_i_7_n_0\,
S(0) => \z2_carry__0_i_8_n_0\
);
\z2_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_1_n_0\
);
\z2_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_2_n_0\
);
\z2_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_3_n_0\
);
\z2_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_4_n_0\
);
\z2_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_5_n_0\
);
\z2_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_6_n_0\
);
\z2_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_7_n_0\
);
\z2_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_8_n_0\
);
\z2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \z2_carry__0_n_0\,
CO(3) => \z2_carry__1_n_0\,
CO(2) => \z2_carry__1_n_1\,
CO(1) => \z2_carry__1_n_2\,
CO(0) => \z2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \z2_carry__1_i_1_n_0\,
DI(2) => \z2_carry__1_i_2_n_0\,
DI(1) => \z2_carry__1_i_3_n_0\,
DI(0) => \z2_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_z2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \z2_carry__1_i_5_n_0\,
S(2) => \z2_carry__1_i_6_n_0\,
S(1) => \z2_carry__1_i_7_n_0\,
S(0) => \z2_carry__1_i_8_n_0\
);
\z2_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_1_n_0\
);
\z2_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_2_n_0\
);
\z2_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_3_n_0\
);
\z2_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_4_n_0\
);
\z2_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_5_n_0\
);
\z2_carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_6_n_0\
);
\z2_carry__1_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_7_n_0\
);
\z2_carry__1_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_8_n_0\
);
\z2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \z2_carry__1_n_0\,
CO(3) => z2,
CO(2) => \z2_carry__2_n_1\,
CO(1) => \z2_carry__2_n_2\,
CO(0) => \z2_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => z1(7),
DI(1) => \z2_carry__2_i_2_n_0\,
DI(0) => \z2_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_z2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \z2_carry__2_i_4_n_0\,
S(2) => \z2_carry__2_i_5_n_0\,
S(1) => \z2_carry__2_i_6_n_0\,
S(0) => \z2_carry__2_i_7_n_0\
);
\z2_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => z1(7)
);
\z2_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__2_i_2_n_0\
);
\z2_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__2_i_3_n_0\
);
\z2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_4_n_0\
);
\z2_carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_5_n_0\
);
\z2_carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_6_n_0\
);
\z2_carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_7_n_0\
);
z2_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => z2_carry_i_1_n_0
);
z2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \z0_carry_i_8__0_n_0\,
I1 => \z[18]_INST_0_i_1_n_0\,
O => z2_carry_i_2_n_0
);
z2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => z0_carry_i_9_n_0,
O => z2_carry_i_3_n_0
);
z2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z0_carry_i_11_n_0,
O => z2_carry_i_4_n_0
);
z2_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => z2_carry_i_5_n_0
);
z2_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \z0_carry_i_8__0_n_0\,
I1 => \z[18]_INST_0_i_1_n_0\,
O => z2_carry_i_6_n_0
);
z2_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => z0_carry_i_9_n_0,
O => z2_carry_i_7_n_0
);
z2_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z0_carry_i_11_n_0,
O => z2_carry_i_8_n_0
);
\z[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[0]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[0]_INST_0_i_2_n_0\,
I4 => \z[1]_INST_0_i_2_n_0\,
I5 => z2,
O => z(0)
);
\z[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \z[1]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z2,
O => \z[0]_INST_0_i_1_n_0\
);
\z[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[6]_INST_0_i_5_n_0\,
I1 => \z[2]_INST_0_i_4_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[4]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[0]_INST_0_i_3_n_0\,
O => \z[0]_INST_0_i_2_n_0\
);
\z[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => sel0(23),
I1 => sel0(7),
I2 => \z[22]_INST_0_i_19_n_0\,
I3 => sel0(15),
I4 => \z[22]_INST_0_i_20_n_0\,
I5 => \sign00__0_carry_n_7\,
O => \z[0]_INST_0_i_3_n_0\
);
\z[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(10),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[10]_INST_0_i_2_n_0\,
I4 => \z[11]_INST_0_i_2_n_0\,
I5 => z2,
O => z(10)
);
\z[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[10]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[10]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[10]_INST_0_i_5_n_0\,
O => z10_in(10)
);
\z[10]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(2),
I2 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_10_n_0\
);
\z[10]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[12]_INST_0_i_4_n_0\,
I1 => \z[12]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[10]_INST_0_i_6_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[10]_INST_0_i_7_n_0\,
O => \z[10]_INST_0_i_2_n_0\
);
\z[10]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[16]_INST_0_i_7_n_0\,
I1 => \z[10]_INST_0_i_8_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[10]_INST_0_i_9_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[10]_INST_0_i_10_n_0\,
O => \z[10]_INST_0_i_3_n_0\
);
\z[10]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => \sign00__0_carry_n_7\,
I1 => sel0(7),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(3),
I5 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_4_n_0\
);
\z[10]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => sel0(1),
I1 => sel0(9),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(5),
I5 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_5_n_0\
);
\z[10]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(21),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(13),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[10]_INST_0_i_6_n_0\
);
\z[10]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(17),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(9),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[10]_INST_0_i_7_n_0\
);
\z[10]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(4),
I2 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_8_n_0\
);
\z[10]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(6),
I2 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_9_n_0\
);
\z[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(11),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[11]_INST_0_i_2_n_0\,
I4 => \z[12]_INST_0_i_2_n_0\,
I5 => z2,
O => z(11)
);
\z[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[11]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[12]_INST_0_i_3_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[14]_INST_0_i_3_n_0\,
O => z10_in(11)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[13]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[11]_INST_0_i_4_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[11]_INST_0_i_5_n_0\,
O => \z[11]_INST_0_i_2_n_0\
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[17]_INST_0_i_5_n_0\,
I1 => \z[13]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[15]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[11]_INST_0_i_6_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(22),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(14),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[11]_INST_0_i_4_n_0\
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(18),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(10),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[11]_INST_0_i_5_n_0\
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(3),
I2 => z0_carry_i_9_n_0,
O => \z[11]_INST_0_i_6_n_0\
);
\z[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(12),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[12]_INST_0_i_2_n_0\,
I4 => \z[13]_INST_0_i_2_n_0\,
I5 => z2,
O => z(12)
);
\z[12]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[12]_INST_0_i_3_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[14]_INST_0_i_3_n_0\,
I4 => \z[22]_INST_0_i_1_n_0\,
I5 => \z[13]_INST_0_i_3_n_0\,
O => z10_in(12)
);
\z[12]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[14]_INST_0_i_5_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[12]_INST_0_i_4_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[12]_INST_0_i_5_n_0\,
O => \z[12]_INST_0_i_2_n_0\
);
\z[12]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => sel0(0),
I1 => sel0(8),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(4),
I5 => z0_carry_i_9_n_0,
O => \z[12]_INST_0_i_3_n_0\
);
\z[12]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(15),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[12]_INST_0_i_4_n_0\
);
\z[12]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(19),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(11),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[12]_INST_0_i_5_n_0\
);
\z[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(13),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[13]_INST_0_i_2_n_0\,
I4 => \z[14]_INST_0_i_2_n_0\,
I5 => z2,
O => z(13)
);
\z[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[13]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[14]_INST_0_i_3_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[14]_INST_0_i_4_n_0\,
O => z10_in(13)
);
\z[13]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[15]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[13]_INST_0_i_4_n_0\,
O => \z[13]_INST_0_i_2_n_0\
);
\z[13]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[19]_INST_0_i_5_n_0\,
I1 => \z[15]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[17]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[13]_INST_0_i_5_n_0\,
O => \z[13]_INST_0_i_3_n_0\
);
\z[13]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(16),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(20),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(12),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[13]_INST_0_i_4_n_0\
);
\z[13]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(5),
I2 => z0_carry_i_9_n_0,
O => \z[13]_INST_0_i_5_n_0\
);
\z[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(14),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[14]_INST_0_i_2_n_0\,
I4 => \z[15]_INST_0_i_2_n_0\,
I5 => z2,
O => z(14)
);
\z[14]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[14]_INST_0_i_3_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[14]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_1_n_0\,
I5 => \z[15]_INST_0_i_3_n_0\,
O => z10_in(14)
);
\z[14]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[16]_INST_0_i_6_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[14]_INST_0_i_5_n_0\,
O => \z[14]_INST_0_i_2_n_0\
);
\z[14]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => sel0(2),
I1 => sel0(10),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(6),
I5 => z0_carry_i_9_n_0,
O => \z[14]_INST_0_i_3_n_0\
);
\z[14]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800FFFFB8000000"
)
port map (
I0 => sel0(4),
I1 => z0_carry_i_9_n_0,
I2 => sel0(12),
I3 => \z0_carry_i_8__0_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[16]_INST_0_i_7_n_0\,
O => \z[14]_INST_0_i_4_n_0\
);
\z[14]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(17),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(21),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(13),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[14]_INST_0_i_5_n_0\
);
\z[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[15]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[15]_INST_0_i_2_n_0\,
I4 => \z[16]_INST_0_i_2_n_0\,
I5 => z2,
O => z(15)
);
\z[15]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[16]_INST_0_i_5_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[15]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[15]_INST_0_i_1_n_0\
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[17]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[15]_INST_0_i_4_n_0\,
O => \z[15]_INST_0_i_2_n_0\
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[21]_INST_0_i_4_n_0\,
I1 => \z[17]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[19]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[15]_INST_0_i_5_n_0\,
O => \z[15]_INST_0_i_3_n_0\
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(18),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(22),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(14),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[15]_INST_0_i_4_n_0\
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => \sign00__0_carry_n_7\,
I1 => z0_carry_i_9_n_0,
I2 => sel0(7),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[15]_INST_0_i_5_n_0\
);
\z[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[16]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[16]_INST_0_i_2_n_0\,
I4 => \z[16]_INST_0_i_3_n_0\,
I5 => z2,
O => z(16)
);
\z[16]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[16]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[16]_INST_0_i_5_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[16]_INST_0_i_1_n_0\
);
\z[16]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[18]_INST_0_i_9_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[16]_INST_0_i_6_n_0\,
O => \z[16]_INST_0_i_2_n_0\
);
\z[16]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[19]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[17]_INST_0_i_4_n_0\,
O => \z[16]_INST_0_i_3_n_0\
);
\z[16]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_31_n_0\,
I1 => \z[19]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[21]_INST_0_i_4_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[17]_INST_0_i_5_n_0\,
O => \z[16]_INST_0_i_4_n_0\
);
\z[16]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_29_n_0\,
I1 => \z[18]_INST_0_i_10_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[20]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[16]_INST_0_i_7_n_0\,
O => \z[16]_INST_0_i_5_n_0\
);
\z[16]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(19),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(23),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(15),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[16]_INST_0_i_6_n_0\
);
\z[16]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(0),
I1 => z0_carry_i_9_n_0,
I2 => sel0(8),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[16]_INST_0_i_7_n_0\
);
\z[17]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888F000"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[17]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[17]_INST_0_i_2_n_0\,
I4 => z2,
O => z(17)
);
\z[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[18]_INST_0_i_6_n_0\,
I1 => \z[18]_INST_0_i_7_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[18]_INST_0_i_5_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[17]_INST_0_i_3_n_0\,
O => \z[17]_INST_0_i_1_n_0\
);
\z[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE44FAFAEE445050"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[20]_INST_0_i_4_n_0\,
I2 => \z[18]_INST_0_i_9_n_0\,
I3 => \z[19]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[17]_INST_0_i_4_n_0\,
O => \z[17]_INST_0_i_2_n_0\
);
\z[17]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800FFFFB8000000"
)
port map (
I0 => sel0(5),
I1 => z0_carry_i_9_n_0,
I2 => sel0(13),
I3 => \z0_carry_i_8__0_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[17]_INST_0_i_5_n_0\,
O => \z[17]_INST_0_i_3_n_0\
);
\z[17]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(20),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(16),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[17]_INST_0_i_4_n_0\
);
\z[17]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(1),
I1 => z0_carry_i_9_n_0,
I2 => sel0(9),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[17]_INST_0_i_5_n_0\
);
\z[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888F000"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[18]_INST_0_i_2_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_3_n_0\,
I4 => z2,
O => z(18)
);
\z[18]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z[18]_INST_0_i_1_n_0\
);
\z[18]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(2),
I1 => z0_carry_i_9_n_0,
I2 => sel0(10),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[18]_INST_0_i_10_n_0\
);
\z[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[18]_INST_0_i_4_n_0\,
I1 => \z[18]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[18]_INST_0_i_6_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[18]_INST_0_i_7_n_0\,
O => \z[18]_INST_0_i_2_n_0\
);
\z[18]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE44FAFAEE445050"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[18]_INST_0_i_8_n_0\,
I2 => \z[19]_INST_0_i_4_n_0\,
I3 => \z[20]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[18]_INST_0_i_9_n_0\,
O => \z[18]_INST_0_i_3_n_0\
);
\z[18]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB88888888888"
)
port map (
I0 => \z[22]_INST_0_i_33_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => sel0(5),
I3 => z0_carry_i_9_n_0,
I4 => sel0(13),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[18]_INST_0_i_4_n_0\
);
\z[18]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB88888888888"
)
port map (
I0 => \z[22]_INST_0_i_31_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => sel0(3),
I3 => z0_carry_i_9_n_0,
I4 => sel0(11),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[18]_INST_0_i_5_n_0\
);
\z[18]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB88888888888"
)
port map (
I0 => \z[22]_INST_0_i_27_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => sel0(4),
I3 => z0_carry_i_9_n_0,
I4 => sel0(12),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[18]_INST_0_i_6_n_0\
);
\z[18]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800FFFFB8000000"
)
port map (
I0 => sel0(6),
I1 => z0_carry_i_9_n_0,
I2 => sel0(14),
I3 => \z0_carry_i_8__0_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[18]_INST_0_i_10_n_0\,
O => \z[18]_INST_0_i_7_n_0\
);
\z[18]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400040400000004"
)
port map (
I0 => \z[22]_INST_0_i_19_n_0\,
I1 => sel0(20),
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => z2,
I4 => z3(2),
I5 => z0_carry_i_10_n_0,
O => \z[18]_INST_0_i_8_n_0\
);
\z[18]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(21),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(17),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[18]_INST_0_i_9_n_0\
);
\z[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[19]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[19]_INST_0_i_2_n_0\,
I4 => \z[20]_INST_0_i_2_n_0\,
I5 => z2,
O => z(19)
);
\z[19]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[20]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[19]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[19]_INST_0_i_1_n_0\
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => \z[22]_INST_0_i_19_n_0\,
I1 => sel0(20),
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[19]_INST_0_i_4_n_0\,
O => \z[19]_INST_0_i_2_n_0\
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_33_n_0\,
I1 => \z[21]_INST_0_i_4_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_31_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[19]_INST_0_i_5_n_0\,
O => \z[19]_INST_0_i_3_n_0\
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(22),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(18),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[19]_INST_0_i_4_n_0\
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(3),
I1 => z0_carry_i_9_n_0,
I2 => sel0(11),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[19]_INST_0_i_5_n_0\
);
\z[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[1]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[1]_INST_0_i_2_n_0\,
I4 => \z[2]_INST_0_i_2_n_0\,
I5 => z2,
O => z(1)
);
\z[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[2]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[1]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[1]_INST_0_i_1_n_0\
);
\z[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[7]_INST_0_i_5_n_0\,
I1 => \z[3]_INST_0_i_4_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[5]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[1]_INST_0_i_4_n_0\,
O => \z[1]_INST_0_i_2_n_0\
);
\z[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => \z0_carry_i_8__0_n_0\,
I2 => \sign00__0_carry_n_7\,
I3 => z0_carry_i_9_n_0,
I4 => z0_carry_i_11_n_0,
O => \z[1]_INST_0_i_3_n_0\
);
\z[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(8),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(16),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(0),
O => \z[1]_INST_0_i_4_n_0\
);
\z[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[20]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[20]_INST_0_i_2_n_0\,
I4 => \z[21]_INST_0_i_2_n_0\,
I5 => z2,
O => z(20)
);
\z[20]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[21]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[20]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[20]_INST_0_i_1_n_0\
);
\z[20]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => \z[22]_INST_0_i_19_n_0\,
I1 => sel0(21),
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[20]_INST_0_i_4_n_0\,
O => \z[20]_INST_0_i_2_n_0\
);
\z[20]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_28_n_0\,
I1 => \z[22]_INST_0_i_29_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_27_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[20]_INST_0_i_5_n_0\,
O => \z[20]_INST_0_i_3_n_0\
);
\z[20]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(19),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[20]_INST_0_i_4_n_0\
);
\z[20]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(4),
I1 => z0_carry_i_9_n_0,
I2 => sel0(12),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[20]_INST_0_i_5_n_0\
);
\z[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[21]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[21]_INST_0_i_2_n_0\,
I4 => \z[22]_INST_0_i_4_n_0\,
I5 => z2,
O => z(21)
);
\z[21]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[22]_INST_0_i_10_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[21]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[21]_INST_0_i_1_n_0\
);
\z[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000B08"
)
port map (
I0 => sel0(22),
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[22]_INST_0_i_19_n_0\,
I3 => sel0(20),
I4 => \z[22]_INST_0_i_20_n_0\,
I5 => \z[22]_INST_0_i_21_n_0\,
O => \z[21]_INST_0_i_2_n_0\
);
\z[21]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_30_n_0\,
I1 => \z[22]_INST_0_i_31_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_33_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[21]_INST_0_i_4_n_0\,
O => \z[21]_INST_0_i_3_n_0\
);
\z[21]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(5),
I1 => z0_carry_i_9_n_0,
I2 => sel0(13),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[21]_INST_0_i_4_n_0\
);
\z[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(22),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[22]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_5_n_0\,
I5 => z2,
O => z(22)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555544444440"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_6_n_0\,
I2 => sel0(14),
I3 => \z[22]_INST_0_i_7_n_0\,
I4 => \z[22]_INST_0_i_8_n_0\,
I5 => \z[22]_INST_0_i_9_n_0\,
O => \z[22]_INST_0_i_1_n_0\
);
\z[22]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_26_n_0\,
I1 => \z[22]_INST_0_i_27_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_28_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[22]_INST_0_i_29_n_0\,
O => \z[22]_INST_0_i_10_n_0\
);
\z[22]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[22]_INST_0_i_30_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => \z[22]_INST_0_i_31_n_0\,
O => \z[22]_INST_0_i_11_n_0\
);
\z[22]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[22]_INST_0_i_32_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => \z[22]_INST_0_i_33_n_0\,
O => \z[22]_INST_0_i_12_n_0\
);
\z[22]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \z[22]_INST_0_i_34_n_0\,
I1 => \z[22]_INST_0_i_35_n_0\,
I2 => \z[22]_INST_0_i_36_n_0\,
I3 => \z[22]_INST_0_i_37_n_0\,
I4 => \z[22]_INST_0_i_38_n_0\,
O => \z[22]_INST_0_i_13_n_0\
);
\z[22]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(11),
I1 => z3(12),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(9),
I4 => z2,
I5 => z3(10),
O => \z[22]_INST_0_i_14_n_0\
);
\z[22]_INST_0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(7),
I1 => z3(8),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(5),
I4 => z2,
I5 => z3(6),
O => \z[22]_INST_0_i_15_n_0\
);
\z[22]_INST_0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(19),
I1 => z3(20),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(17),
I4 => z2,
I5 => z3(18),
O => \z[22]_INST_0_i_16_n_0\
);
\z[22]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(15),
I1 => z3(16),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(13),
I4 => z2,
I5 => z3(14),
O => \z[22]_INST_0_i_17_n_0\
);
\z[22]_INST_0_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"5C"
)
port map (
I0 => z0_carry_i_11_n_0,
I1 => z3(1),
I2 => z2,
O => \z[22]_INST_0_i_18_n_0\
);
\z[22]_INST_0_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => z3(3),
I2 => z2,
O => \z[22]_INST_0_i_19_n_0\
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[22]_INST_0_i_10_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[22]_INST_0_i_11_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[22]_INST_0_i_12_n_0\,
O => z10_in(22)
);
\z[22]_INST_0_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"99F0"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
I2 => z3(4),
I3 => z2,
O => \z[22]_INST_0_i_20_n_0\
);
\z[22]_INST_0_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBFFF00"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_39_n_0\,
I2 => \_carry_i_8_n_0\,
I3 => z3(2),
I4 => z2,
O => \z[22]_INST_0_i_21_n_0\
);
\z[22]_INST_0_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(19),
I1 => sel0(21),
O => \z[22]_INST_0_i_22_n_0\
);
\z[22]_INST_0_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sel0(9),
I1 => sel0(11),
O => \z[22]_INST_0_i_23_n_0\
);
\z[22]_INST_0_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFEEEFEFFFFEEFE"
)
port map (
I0 => sel0(6),
I1 => sel0(2),
I2 => sel0(4),
I3 => sel0(5),
I4 => sel0(0),
I5 => sel0(1),
O => \z[22]_INST_0_i_24_n_0\
);
\z[22]_INST_0_i_25\: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => sel0(6),
I1 => sel0(5),
I2 => sel0(4),
O => \z[22]_INST_0_i_25_n_0\
);
\z[22]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(12),
I1 => z0_carry_i_9_n_0,
I2 => sel0(20),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(4),
O => \z[22]_INST_0_i_26_n_0\
);
\z[22]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(8),
I1 => z0_carry_i_9_n_0,
I2 => sel0(16),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(0),
O => \z[22]_INST_0_i_27_n_0\
);
\z[22]_INST_0_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(10),
I1 => z0_carry_i_9_n_0,
I2 => sel0(18),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(2),
O => \z[22]_INST_0_i_28_n_0\
);
\z[22]_INST_0_i_29\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(6),
I1 => z0_carry_i_9_n_0,
I2 => sel0(14),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[22]_INST_0_i_29_n_0\
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \z[22]_INST_0_i_13_n_0\,
I1 => \z[22]_INST_0_i_14_n_0\,
I2 => \z[22]_INST_0_i_15_n_0\,
I3 => \z[22]_INST_0_i_16_n_0\,
I4 => \z[22]_INST_0_i_17_n_0\,
O => \z[22]_INST_0_i_3_n_0\
);
\z[22]_INST_0_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(11),
I1 => z0_carry_i_9_n_0,
I2 => sel0(19),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(3),
O => \z[22]_INST_0_i_30_n_0\
);
\z[22]_INST_0_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(7),
I1 => z0_carry_i_9_n_0,
I2 => sel0(15),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => \sign00__0_carry_n_7\,
O => \z[22]_INST_0_i_31_n_0\
);
\z[22]_INST_0_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(13),
I1 => z0_carry_i_9_n_0,
I2 => sel0(21),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(5),
O => \z[22]_INST_0_i_32_n_0\
);
\z[22]_INST_0_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(9),
I1 => z0_carry_i_9_n_0,
I2 => sel0(17),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(1),
O => \z[22]_INST_0_i_33_n_0\
);
\z[22]_INST_0_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(30),
I1 => z2,
I2 => z3(29),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_34_n_0\
);
\z[22]_INST_0_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(24),
I1 => z2,
I2 => z3(23),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_35_n_0\
);
\z[22]_INST_0_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(22),
I1 => z2,
I2 => z3(21),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_36_n_0\
);
\z[22]_INST_0_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(28),
I1 => z2,
I2 => z3(27),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_37_n_0\
);
\z[22]_INST_0_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(26),
I1 => z2,
I2 => z3(25),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_38_n_0\
);
\z[22]_INST_0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \_carry_i_5_n_0\,
I1 => sel0(14),
I2 => \z[22]_INST_0_i_40_n_0\,
I3 => sel0(13),
I4 => sel0(12),
I5 => \_carry_i_7_n_0\,
O => \z[22]_INST_0_i_39_n_0\
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000B08"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[22]_INST_0_i_19_n_0\,
I3 => sel0(21),
I4 => \z[22]_INST_0_i_20_n_0\,
I5 => \z[22]_INST_0_i_21_n_0\,
O => \z[22]_INST_0_i_4_n_0\
);
\z[22]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => sel0(11),
I1 => sel0(8),
I2 => sel0(7),
I3 => sel0(9),
I4 => sel0(10),
O => \z[22]_INST_0_i_40_n_0\
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \z[22]_INST_0_i_21_n_0\,
I1 => \z[22]_INST_0_i_20_n_0\,
I2 => sel0(22),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000F000F0B"
)
port map (
I0 => sel0(14),
I1 => sel0(13),
I2 => sel0(17),
I3 => sel0(16),
I4 => sel0(15),
I5 => \z[22]_INST_0_i_22_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[22]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFFEEFFEEEEEEFE"
)
port map (
I0 => sel0(12),
I1 => sel0(16),
I2 => sel0(8),
I3 => sel0(11),
I4 => sel0(9),
I5 => sel0(10),
O => \z[22]_INST_0_i_7_n_0\
);
\z[22]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000004000C000C00"
)
port map (
I0 => sel0(5),
I1 => \z[22]_INST_0_i_23_n_0\,
I2 => sel0(7),
I3 => \z[22]_INST_0_i_24_n_0\,
I4 => sel0(3),
I5 => \z[22]_INST_0_i_25_n_0\,
O => \z[22]_INST_0_i_8_n_0\
);
\z[22]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFAFAAAE"
)
port map (
I0 => sel0(22),
I1 => sel0(18),
I2 => sel0(21),
I3 => sel0(19),
I4 => sel0(20),
O => \z[22]_INST_0_i_9_n_0\
);
\z[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[2]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[2]_INST_0_i_2_n_0\,
I4 => \z[3]_INST_0_i_2_n_0\,
I5 => z2,
O => z(2)
);
\z[2]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[3]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[2]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[2]_INST_0_i_1_n_0\
);
\z[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[8]_INST_0_i_5_n_0\,
I1 => \z[4]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[6]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[2]_INST_0_i_4_n_0\,
O => \z[2]_INST_0_i_2_n_0\
);
\z[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => \z0_carry_i_8__0_n_0\,
I2 => sel0(0),
I3 => z0_carry_i_9_n_0,
I4 => z0_carry_i_11_n_0,
O => \z[2]_INST_0_i_3_n_0\
);
\z[2]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(9),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(17),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(1),
O => \z[2]_INST_0_i_4_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"E2E2E200"
)
port map (
I0 => y(31),
I1 => large_mant1_carry_n_0,
I2 => x(31),
I3 => \z[31]_INST_0_i_1_n_0\,
I4 => \z[31]_INST_0_i_2_n_0\,
O => z(31)
);
\z[31]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[31]_INST_0_i_3_n_0\,
I1 => \z[31]_INST_0_i_4_n_0\,
I2 => \z[31]_INST_0_i_5_n_0\,
I3 => \z[31]_INST_0_i_6_n_0\,
I4 => sel0(3),
I5 => sel0(4),
O => \z[31]_INST_0_i_1_n_0\
);
\z[31]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sel0(22),
I1 => \z[31]_INST_0_i_7_n_0\,
I2 => sel0(21),
I3 => sel0(23),
I4 => sel0(19),
I5 => sel0(20),
O => \z[31]_INST_0_i_2_n_0\
);
\z[31]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(9),
I1 => sel0(10),
I2 => sel0(7),
I3 => sel0(8),
O => \z[31]_INST_0_i_3_n_0\
);
\z[31]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(13),
I1 => sel0(14),
I2 => sel0(11),
I3 => sel0(12),
O => \z[31]_INST_0_i_4_n_0\
);
\z[31]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(1),
I1 => sel0(2),
I2 => \sign00__0_carry_n_7\,
I3 => sel0(0),
O => \z[31]_INST_0_i_5_n_0\
);
\z[31]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(6),
I1 => sel0(5),
O => \z[31]_INST_0_i_6_n_0\
);
\z[31]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(17),
I1 => sel0(18),
I2 => sel0(15),
I3 => sel0(16),
O => \z[31]_INST_0_i_7_n_0\
);
\z[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[3]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[3]_INST_0_i_2_n_0\,
I4 => \z[4]_INST_0_i_2_n_0\,
I5 => z2,
O => z(3)
);
\z[3]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[4]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[3]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[3]_INST_0_i_1_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[9]_INST_0_i_6_n_0\,
I1 => \z[5]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[7]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[3]_INST_0_i_4_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0B08000000000000"
)
port map (
I0 => sel0(1),
I1 => z0_carry_i_11_n_0,
I2 => z0_carry_i_9_n_0,
I3 => \sign00__0_carry_n_7\,
I4 => \z0_carry_i_8__0_n_0\,
I5 => z0_carry_i_10_n_0,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(10),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(18),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(2),
O => \z[3]_INST_0_i_4_n_0\
);
\z[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(4),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[4]_INST_0_i_2_n_0\,
I4 => \z[5]_INST_0_i_2_n_0\,
I5 => z2,
O => z(4)
);
\z[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[4]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[4]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[6]_INST_0_i_4_n_0\,
O => z10_in(4)
);
\z[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_7_n_0\,
I1 => \z[6]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[8]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[4]_INST_0_i_5_n_0\,
O => \z[4]_INST_0_i_2_n_0\
);
\z[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0B08000000000000"
)
port map (
I0 => sel0(2),
I1 => z0_carry_i_11_n_0,
I2 => z0_carry_i_9_n_0,
I3 => sel0(0),
I4 => \z0_carry_i_8__0_n_0\,
I5 => z0_carry_i_10_n_0,
O => \z[4]_INST_0_i_3_n_0\
);
\z[4]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => sel0(1),
I2 => \z0_carry_i_8__0_n_0\,
I3 => z0_carry_i_10_n_0,
O => \z[4]_INST_0_i_4_n_0\
);
\z[4]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(11),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(19),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(3),
O => \z[4]_INST_0_i_5_n_0\
);
\z[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(5),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[5]_INST_0_i_2_n_0\,
I4 => \z[6]_INST_0_i_2_n_0\,
I5 => z2,
O => z(5)
);
\z[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[5]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[5]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[7]_INST_0_i_4_n_0\,
O => z10_in(5)
);
\z[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[11]_INST_0_i_5_n_0\,
I1 => \z[7]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[9]_INST_0_i_6_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[5]_INST_0_i_5_n_0\,
O => \z[5]_INST_0_i_2_n_0\
);
\z[5]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFA0C0C0"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
I1 => \z[7]_INST_0_i_6_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[9]_INST_0_i_7_n_0\,
I4 => z0_carry_i_10_n_0,
O => \z[5]_INST_0_i_3_n_0\
);
\z[5]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => sel0(2),
I2 => \z0_carry_i_8__0_n_0\,
I3 => z0_carry_i_10_n_0,
O => \z[5]_INST_0_i_4_n_0\
);
\z[5]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(12),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(20),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(4),
O => \z[5]_INST_0_i_5_n_0\
);
\z[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(6),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[6]_INST_0_i_2_n_0\,
I4 => \z[7]_INST_0_i_2_n_0\,
I5 => z2,
O => z(6)
);
\z[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[6]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[6]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[8]_INST_0_i_4_n_0\,
O => z10_in(6)
);
\z[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[12]_INST_0_i_5_n_0\,
I1 => \z[8]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[10]_INST_0_i_7_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[6]_INST_0_i_5_n_0\,
O => \z[6]_INST_0_i_2_n_0\
);
\z[6]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_8_n_0\,
I1 => \z[8]_INST_0_i_6_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[10]_INST_0_i_10_n_0\,
I4 => z0_carry_i_10_n_0,
O => \z[6]_INST_0_i_3_n_0\
);
\z[6]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(3),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => \sign00__0_carry_n_7\,
I4 => z0_carry_i_9_n_0,
O => \z[6]_INST_0_i_4_n_0\
);
\z[6]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(13),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(21),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(5),
O => \z[6]_INST_0_i_5_n_0\
);
\z[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(7),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[7]_INST_0_i_2_n_0\,
I4 => \z[8]_INST_0_i_2_n_0\,
I5 => z2,
O => z(7)
);
\z[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[7]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[7]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[9]_INST_0_i_4_n_0\,
O => z10_in(7)
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[9]_INST_0_i_5_n_0\,
I1 => \z[9]_INST_0_i_6_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[11]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[7]_INST_0_i_5_n_0\,
O => \z[7]_INST_0_i_2_n_0\
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[13]_INST_0_i_5_n_0\,
I1 => \z[9]_INST_0_i_7_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[11]_INST_0_i_6_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[7]_INST_0_i_6_n_0\,
O => \z[7]_INST_0_i_3_n_0\
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(4),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => sel0(0),
I4 => z0_carry_i_9_n_0,
O => \z[7]_INST_0_i_4_n_0\
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(14),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(22),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(6),
O => \z[7]_INST_0_i_5_n_0\
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => \sign00__0_carry_n_7\,
I2 => z0_carry_i_9_n_0,
O => \z[7]_INST_0_i_6_n_0\
);
\z[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(8),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[8]_INST_0_i_2_n_0\,
I4 => \z[9]_INST_0_i_2_n_0\,
I5 => z2,
O => z(8)
);
\z[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[8]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[8]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[10]_INST_0_i_4_n_0\,
O => z10_in(8)
);
\z[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_6_n_0\,
I1 => \z[10]_INST_0_i_7_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[12]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[8]_INST_0_i_5_n_0\,
O => \z[8]_INST_0_i_2_n_0\
);
\z[8]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_9_n_0\,
I1 => \z[10]_INST_0_i_10_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[10]_INST_0_i_8_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[8]_INST_0_i_6_n_0\,
O => \z[8]_INST_0_i_3_n_0\
);
\z[8]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(5),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => sel0(1),
I4 => z0_carry_i_9_n_0,
O => \z[8]_INST_0_i_4_n_0\
);
\z[8]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(15),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(23),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(7),
O => \z[8]_INST_0_i_5_n_0\
);
\z[8]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(0),
I2 => z0_carry_i_9_n_0,
O => \z[8]_INST_0_i_6_n_0\
);
\z[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(9),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[9]_INST_0_i_2_n_0\,
I4 => \z[10]_INST_0_i_2_n_0\,
I5 => z2,
O => z(9)
);
\z[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[9]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[9]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[12]_INST_0_i_3_n_0\,
O => z10_in(9)
);
\z[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[11]_INST_0_i_4_n_0\,
I1 => \z[11]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[9]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[9]_INST_0_i_6_n_0\,
O => \z[9]_INST_0_i_2_n_0\
);
\z[9]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[15]_INST_0_i_5_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[13]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[9]_INST_0_i_7_n_0\,
O => \z[9]_INST_0_i_3_n_0\
);
\z[9]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(6),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => sel0(2),
I4 => z0_carry_i_9_n_0,
O => \z[9]_INST_0_i_4_n_0\
);
\z[9]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(20),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(12),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[9]_INST_0_i_5_n_0\
);
\z[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(16),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(8),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[9]_INST_0_i_6_n_0\
);
\z[9]_INST_0_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(1),
I2 => z0_carry_i_9_n_0,
O => \z[9]_INST_0_i_7_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_adder_subtractor_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_adder_subtractor_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_adder_subtractor_0_0 : entity is "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_adder_subtractor_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_adder_subtractor_0_0 : entity is "ieee754_fp_adder_subtractor,Vivado 2016.4";
end affine_block_ieee754_fp_adder_subtractor_0_0;
architecture STRUCTURE of affine_block_ieee754_fp_adder_subtractor_0_0 is
begin
U0: entity work.affine_block_ieee754_fp_adder_subtractor_0_0_ieee754_fp_adder_subtractor
port map (
x(31 downto 0) => x(31 downto 0),
y(31 downto 0) => y(31 downto 0),
z(31 downto 0) => z(31 downto 0)
);
end STRUCTURE;
| mit | c2573b100cdcbb0014b3b51d78e0290d | 0.493718 | 2.281508 | false | false | false | false |
ameyagadkari/portfolio | Other Projects Source Code/FPGABasedVideoGame/sync.vhd | 1 | 271,661 | --sync.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.game.all;
entity sync is
port(clk_s:in std_logic;
r_shift,l_shift,start,resetgame,pause:in std_logic;
level_select:in std_logic_vector(2 downto 0);
hsync,vsync:out std_logic;
r,g,b:out std_logic_vector(3 downto 0));
end sync;
architecture sync_arch of sync is
signal notstarted:std_logic:='1';--to check if game is not yet started and to display welcome message
signal hpos:integer range 1 to 800:=1;--pixel position including fp, bp and hsync
signal vpos:integer range 1 to 525:=1;--pixel position including fp,bp and vsync
signal hpos_scr:integer range 1 to 640:=1;--cursor position on screen
signal vpos_scr:integer range 1 to 480:=1;--cursor position on screen
signal r_bat,g_bat,b_bat,r_ball,g_ball,b_ball,r_gameover,g_gameover,b_gameover,r_lives,b_lives,g_lives,r_welmes,g_welmes,b_welmes,r_winmes,g_winmes,b_winmes,r_paused,g_paused,b_paused:std_logic_vector(3 downto 0);--rgb signals
signal draw_bat:std_logic; --validity signals
signal isalive:integer:=3;--to check if lives are over
signal bat_x:integer:=275; --starting x coordinate for bat
signal bat_y:integer:=460; --y coordinate of bat is fixed
signal ball_x:integer:=299;--starting coordinates for ball
signal ball_y:integer:=450;
signal lives_x:integer:=550;--fixed coordinates to display lives
signal lives_y:integer:=0;
signal welmes_x:integer:=72;--fixed coordinates to display welcome message
signal welmes_y:integer:=45;
signal gameover_x:integer:=84;--fixed coordinates to display gameover
signal gameover_y:integer:=195;
signal winmes_x:integer:=90;--fixed coordinates to display winning message
signal winmes_y:integer:=175;
signal paused_x:integer:=128;--fixed coordinates to display paused message
signal paused_y:integer:=202;
signal rand_x:integer range 26 to 611:=26;--used to randomly assign x cood to bat and ball;
signal stopball:std_logic:='0';--to stop the ball after gameover or game has been won
signal l2notstarted,l3notstarted,l4notstarted,l5notstarted:std_logic:='1';--to reposition bat,ball and give initial velocity to ball at start of each level except 1st
signal l1complete,l2complete,l3complete,l4complete,l5complete:std_logic:='0';--to say that level is completed
signal level_selected:std_logic:='0';--to select level at start of the game
type rom_lives is array (24 downto 0)of std_logic_vector(91 downto 0);-- ROM definition of lives
signal lives_row,lives_col: integer;--signals required by lives ROM
signal lives_single_row: std_logic_vector(91 downto 0);
signal lives_validity_bit: std_logic;
type rom_gameover is array (89 downto 0)of std_logic_vector(471 downto 0);--ROM definition of gameover
signal gameover_row,gameover_col: integer;--signals required by gameover ROM
signal gameover_single_row: std_logic_vector(471 downto 0);
signal gameover_validity_bit: std_logic;
type rom_welmes is array (389 downto 0)of std_logic_vector(495 downto 0);--ROM definition of welcome message
signal welmes_row,welmes_col: integer;--signals required by welcome ROM
signal welmes_single_row: std_logic_vector(495 downto 0);
signal welmes_validity_bit: std_logic;
type rom_paused is array (75 downto 0)of std_logic_vector(383 downto 0);--ROM definition of pause message
signal paused_row,paused_col: integer;--signals required by pause ROM
signal paused_single_row: std_logic_vector(383 downto 0);
signal paused_validity_bit: std_logic;
type rom_winmes is array (129 downto 0)of std_logic_vector(459 downto 0);--ROM definition of winning message
signal winmes_row,winmes_col: integer;--signals required by win ROM
signal winmes_single_row: std_logic_vector(459 downto 0);
signal winmes_validity_bit: std_logic;
type rom_ball is array (12 downto 0)of std_logic_vector(12 downto 0);-- ROM definition of ball
signal ball_row,ball_col: integer;--signals required by ball ROM
signal ball_single_row: std_logic_vector(12 downto 0);
signal ball_validity_bit: std_logic;
signal ball_x_vel:std_logic:='1';--used to change ball movements in x and y direction after hitting a wall or brick
signal ball_y_vel:std_logic:='0';
signal ball_x_vel_rand:std_logic:='0';
type brick_cood is array (71 downto 0) of integer;--array to store coordinates of bricks
type brick_color is array (71 downto 0) of std_logic_vector(3 downto 0);--array to give color to each brick
signal x_cood_l1:brick_cood:=--x coordinates of bricks in level1
(20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580);
signal y_cood_l1:brick_cood:=--y coordinates of bricks in level1
(25,25,25,25,25,25,25,25,
65,65,65,65,65,65,65,65,
105,105,105,105,105,105,105,105,
145,145,145,145,145,145,145,145,
185,185,185,185,185,185,185,185,
225,225,225,225,225,225,225,225,
265,265,265,265,265,265,265,265,
305,305,305,305,305,305,305,305,
345,345,345,345,345,345,345,345);
signal x_cood_l2:brick_cood:=--x coordinates of bricks in level2
(40,80,120,160,200,240,280,
560,520,480,440,400,360,320,
280,240,200,160,120,80,40,
320,360,400,440,480,520,560,others=>0);
signal y_cood_l2:brick_cood:=--y coordinates of bricks in level2
(40,60,80,100,120,140,160,
40,60,80,100,120,140,160,
180,200,220,240,260,280,300,
180,200,220,240,260,280,300,others=>0);
signal x_cood_l3:brick_cood:=--x coordinates of bricks in level3
(300,260,220,180,140,100,60,20,
340,380,420,460,500,540,580,
300,260,220,180,140,100,60,20,
340,380,420,460,500,540,580,
300,260,220,180,140,100,
340,380,420,460,500,
300,260,220,180,140,100,
340,380,420,460,500,
300,260,220,180,
340,380,420,
300,260,220,180,
340,380,420,
300,260,
340,
300,260,
340);
signal y_cood_l3:brick_cood:=--y coordinates of bricks in level3
(25,45,65,85,105,125,145,165,
45,65,85,105,125,145,165,
325,305,285,265,245,225,205,185,
305,285,265,245,225,205,185,
65,85,105,125,145,165,
85,105,125,145,165,
285,265,245,225,205,185,
265,245,225,205,185,
105,125,145,165,
125,145,165,
245,225,205,185,
225,205,185,
145,165,
165,
205,185,
185);
signal x_cood_l4:brick_cood:=--x coordinates of bricks in level4
(40,80,120,160,200,240,280,
560,520,480,440,400,360,320,
280,240,200,160,120,80,40,
320,360,400,440,480,520,560,
40,40,40,40,40,40,40,40,40,
560,560,560,560,560,560,560,560,560,
100,150,200,250,300,350,400,450,500,
100,150,200,250,300,350,400,450,500,others=>0);
signal y_cood_l4:brick_cood:=--y coordinates of bricks in level4
(40,60,80,100,120,140,160,
40,60,80,100,120,140,160,
180,200,220,240,260,280,300,
180,200,220,240,260,280,300,
70,95,120,145,170,195,220,245,270,
70,95,120,145,170,195,220,245,270,
40,40,40,40,40,40,40,40,40,
300,300,300,300,300,300,300,300,300,others=>0);
signal x_cood_l5:brick_cood:=--x coordinates of bricks in level5
(20,60,100,140,180,220,260,
340,380,420,460,500,540,580,
140,140,140,140,140,140,140,140,140,140,140,
460,460,460,460,460,460,460,460,460,460,460,others=>0);
signal y_cood_l5:brick_cood:=--y coordinates of bricks in level5
(85,65,45,25,45,65,85,
85,65,45,25,45,65,85,
65,90,115,140,165,190,215,240,265,290,315,
65,90,115,140,165,190,215,240,265,290,315,others=>0);
signal is_destroyed_l1,coll_x_l1,coll_y_l1,draw_l1:std_logic_vector(71 downto 0):=x"000000000000000000";--for level 1
signal is_destroyed_l2,coll_x_l2,coll_y_l2,draw_l2:std_logic_vector(71 downto 44):=x"0000000";--for level 2
signal is_destroyed_l3,coll_x_l3,coll_y_l3,draw_l3:std_logic_vector(71 downto 0):=x"000000000000000000";--for level 3
signal is_destroyed_l4,coll_x_l4,coll_y_l4,draw_l4:std_logic_vector(71 downto 8):=x"0000000000000000";--for level 4
signal is_destroyed_l5,coll_x_l5,coll_y_l5,draw_l5:std_logic_vector(71 downto 36):=x"000000000";--for level 5
signal r_brick,g_brick,b_brick:brick_color;--rgb for bricks
constant lives0_rom: rom_lives:= --lives 0 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"000780f0038747c020f3ffe",
x"0018c318038cc9e07073078",
x"0018c318038c40e07072078",
x"0038e71c000e00707872078",
x"0038e71c000f0070b870078",
x"0038e71c0007cff0b870078",
x"0038e71c0003cc711c70078",
x"0038e71c0388cc611c70078",
x"0038e71c038cc6e31e70078",
x"0038e71c038b8387bf70078",
x"0038e71c000000000000078",
x"0018c318000000000060078",
x"0018c318000000000070078",
x"000780f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant lives1_rom: rom_lives:= --lives 1 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"001fc0f0038747c020f3ffe",
x"00070318038cc9e07073078",
x"00070318038c40e07072078",
x"0007071c000e00707872078",
x"0007071c000f0070b870078",
x"0007071c0007cff0b870078",
x"0007071c0003cc711c70078",
x"0007071c0388cc611c70078",
x"0007071c038cc6e31e70078",
x"0007071c038b8387bf70078",
x"0007071c000000000000078",
x"0007c318000000000060078",
x"00078318000000000070078",
x"000600f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant lives2_rom: rom_lives:= --lives 2 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"001fe0f0038747c020f3ffe",
x"001fc318038cc9e07073078",
x"003fc318038c40e07072078",
x"0020871c000e00707872078",
x"0001071c000f0070b870078",
x"0002071c0007cff0b870078",
x"0006071c0003cc711c70078",
x"000c071c0388cc611c70078",
x"001c071c038cc6e31e70078",
x"001c071c038b8387bf70078",
x"001c071c000000000000078",
x"001e2318000000000060078",
x"000fc318000000000070078",
x"000780f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant lives3_rom: rom_lives := --lives 3 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"0007e0f0038747c020f3ffe",
x"0008f318038cc9e07073078",
x"00186318038c40e07072078",
x"0038071c000e00707872078",
x"0038071c000f0070b870078",
x"003c071c0007cff0b870078",
x"003e071c0003cc711c70078",
x"001f871c0388cc611c70078",
x"0006071c038cc6e31e70078",
x"001c071c038b8387bf70078",
x"001c071c000000000000078",
x"001e2318000000000060078",
x"001fc318000000000070078",
x"000f80f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant winmes_rom: rom_winmes:= --winning image
(
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000780000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000fc0000000000000000000000000000000000",
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x"00e000603f81fc00301f81f801fc003000003f8003f80060f80fe0000fc0003c3c27c0001fff00e0063f03fc03f0001c1c70718fc007c0003f0",
x"00f000601f80fc00203f007e00fc002000001f8001f80040e007e0000fc0007c3c07c0003c3f01f0001f81fc03f0003c0cf03007e007c0003f0",
x"00f800601f80fe00603f003f00fe006000001f8001fc00c0c007e0000fc0007c3e07c000381f01f0080f80fe03f0003e04f81203e007c0003f0",
x"00f800601f80fe00403f003f80fe004000001f8001fc0080c007e0000fc0007c3e07c000780701f8000f807f03f0003f00fc0003e007c0003f0",
x"00fc00601f807e00c03f001f807e00c000001f8000fc01818007e0000fc000fc3f07c000700003f8000fc07f83f0003fc0ff0003f007c0003f0",
x"00fe00601f807fffc03f001fc07fffc000001f8000ffff818007e0000fc000f83f07c000f80002fc0007c03f83f0001fe07f8001f007c0003f0",
x"00ff00601f803fff803f000fc03fff8000001f80007fff010007e0000fc000f83f07c000f80006fc0007c01fc3f0001ff07fc001f007c0003f0",
x"00ff80601f803f81807f800fc03f818000001f80007f03000007e0000fc000f83f07c000f800047c0fffc00fe3f0000ff83fe3fff007c0003f0",
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x"00dfc0601f801f830000000fe01f830000003fc0003f06000007e003ffc0007c3e07c000ff00083e0f078007fff00001fc07f3c1e00fc00fff0",
x"00dfe0601f801fc20000000fe01fc20000006fc0003f84000007e01fffc0007c3e07c0007fc0083f0f078003fff000107c41f3c1e30fc07fff0",
x"00cff0601f800fc60000000fc00fc60000004fe0001f8c000007e03f8fc0007c3c07c0003ff0181f070f0001fff000183860e1c3c78fc0fe3f0",
x"00c7f8601f800fe60000000fc00fe6000000c7e0001fcc000007e07e0fc0003c3c07c0001fc0181f878f0000f3f0001c3870e1e3c7d7c1f83f0",
x"00c3fc601f8007ec0000000fc007ec00000187f0000fd8000007e07e0fc0001e787ff8000f00381fc39e0000e3f0001e3078c0e787e7c1f83f0",
x"00c1fe601f8007fc0000001fc007fc00000183f0000ff8000007e0fc0fc00007e07fe0001e007e3fe0f8000183f00013e04f803e03c7f3f03f0",
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x"07f807feffe0004000207f8000004000007f01ffe0008000007ffc07fff800000000000007e0000000000ff81ffe0000000000000000001fffe",
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x"003ffff80ff00c03c1fe003c03fff800007fc07c3f07e0000c000f001fff00003800c000007fc003807f7f83fc07f8000fffc03cf0003f80000",
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x"003801f807e01e01807e00101f803f000003f07c1f01f0000f000600fc07e0003801e0000003f007c01f0f81f803f0000fc3e0f878001f80000",
x"003001f807e01f01807f00301f801f800101f07c1f01f0000f800601f803f0007c03e0000101f007c01f0f81f803f0000f83e0f87c001f80000",
x"002001f807e03f01807f00201f801fc00001f07c1f01f0000f800603f001f8007c03f0000001f007c01f0f81f803f0000f83e0f87c001f80000",
x"002041f807e03f81803f00601f800fc00001f87c1f01f0000fc00603f001f800fc03f0000001f80fe01f0f01f803f0000f83e1f87e001f80000",
x"002041f807e07f81803fffe01f800fe00000f87c1f01f0000fe00607e001fc00fe07f0000000f80be01f1c01f803f0000f83e1f07e001f80000",
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x"000061f807e0cfe1800fc080fff007e001e0f87c1f01f0000ffc060fe000fc01bf0dfc0001e0f831f81f0f01f803f0000f83e1f07e003f80000",
x"000071f807e08fe1800fc180000007f001e0f07c1f01f0000dfc060fe000fe013f08fc0001e0f021f81f0f81f803f0000f83e0f87c003fc0000",
x"00007ff807e187e1800fe100000007f001e0f07c1f01f0000dfe060fe000fe031f98fc0001e0f060f81f0f81fffff0000f83e0f87c006fc0000",
x"00007ff807e107f18007e300000007e000e1e07c3f01f0000cff060fe000fe021f907e0000e1e040fc1f0f81fffff0000f83e0f878004fe0000",
x"000071f807e303f18007f300000007e000f1e07e7f01f0000c7f860fe000fc061fb07e0000f1e0c07c1f0701f803f0000f83e0787800c7e0000",
x"000061f807e303f98003f600000007e00073c03fdf1ffe000c3fc607e000fc060ff07f000073c0c0fe0f8e01f803f0000fc3e03cf00187f0000",
x"000041f807e603f98003fe0000000fe0001f001f1f1ff8000c1fe607e000fc040fe03f00001f01f1ff03f801f803f0000fe3f80fc00183f0000",
x"001041f807e601fd8001fc0010000fc0000000001f01f0000c0fe607e001fc0c0fe03f000000000000000001f803f00000000000000301f8000",
x"001841f807e401fd8001fc0018000fc0000000001f01e0000c0ff603f001f80c07e01f800000000000000001f803f00000000000000201fc000",
x"001841f807ec00ff8001f80018001f80000000001f01c0000c07fe03f001f80807e01f800000000000000001f803f00000000000000600fc000",
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x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
constant gameover_rom: rom_gameover:= --gameover image
(
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
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x"00000000000000000000000000000000000000000000000000000000000000000000000000000001f8000000000000000000000000000000000000",
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x"0010007f9ffdfff07fc01ff001fff07fc0003fff03ffe0ff9fffff801fff0000fc01e000003f8008001f03ffe3ffc000f983e607c003fe007ffc00",
x"0018001e07f07f800f00fffe007f800f000007f000ff001e1ffffe0003fc0003cf03f00000ffe01c007fc0ff80fe0001c7871e1ff001f8000ff000",
x"001c000c07f03f800603f03f003f8006000007f0007f000c1f01fc0001f800078784f80003ffe01c00c7e07f807e0003838e0e31f800f80007e000",
x"001e000c03f01f800407e00fc01f8004000003f0003f00081c00fc0001f8000f8780f8000787e03e0003f03f807e0007819e0600fc00f80007e000",
x"001f000c03f01fc00c07e007e01fc00c000003f0003f80181800fc0001f8000f87c0f8000703e03e0101f01fc07e0007c09f02407c00f80007e000",
x"001f000c03f01fc00807e007f01fc008000003f0003f80101800fc0001f8000f87c0f8000f00e03f0001f00fe07e0007e01f80007c00f80007e000",
x"001f800c03f00fc01807e003f00fc018000003f0001f80303000fc0001f8001f87e0f8000e00007f0001f80ff07e0007f81fe0007e00f80007e000",
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x"0018ff0c03f001fcc0000001f801fcc0000018fc0003f9800000fc0fc1f800078780f80003f80303f0f1e0001e7e0003870e1c3c78faf83f07e000",
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x"0000000000000000000007c0f81f01f80fc06107e00801fc07e003f03083f00fd801ff0003f00030003f01f03e07c0000000000000000000000000",
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x"000000000000000000000fe1fc3f81fc0fc07007e01800fe01f00fc03803f00ff000ff0001f0003e007c03f87f0fe0000000000000000000000000",
x"000000000000000000000fe1fc3f80fe0fc07c07e030007e00fc1f803e03f00ff000ff0000e0003f81f803f87f0fe0000000000000000000000000",
x"0000000000000000000007c0f81f007fffe07fffe078007f007ffe003ffff01fe000ff0000e00033ffe001f03e07c0000000000000000000000000",
x"000000000000000000000380700e000ffff87ffffdff03ffc00ff8003ffffeffe0007fe0004000207f8000e01c0380000000000000000000000000",
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x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
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x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
constant welmes_rom: rom_welmes:= --welcome message image
(
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x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000078000000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000000000000000000000000000000000000000000000fc000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000013c000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000013c000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000238000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000200000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000400000000000000000000000000000000000000000",
x"000000000000000000000000000000000001e001000c0000fc103c01f003e67f3f00f078007ffc01804003c1e3fe007ffc00000000000000000000000000",
x"00000000000000000000000000000000001f8003800c0003ff107e07fc071e1fff83fbfc000ff00380e00feff0fc000ff000000000000000000000000000",
x"00000000000000000000000000000000007c0003801c000783f07e0c7e0e0e1fcf80fcfc0007e00300e003f3f0f80007e000000000000000000000000000",
x"0000000000000000000000000000000000f80003801e000f00f07e003f1e061f87c0f87c0007e00301f003e1f0f80007e000000000000000000000000000",
x"0000000000000000000000000000000001f00007c03e001e00703c101f1f021f07c0f87c0007e00701f003e1f0f80007e000000000000000000000000000",
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);
constant paused_rom: rom_paused :=
(
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000003ff8000c00000001fff800000000000000000000000000000000000000",
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x"0000001ffffffffff807fffffffffffff00007ffffe01c0000007fffffe000007fffffff0001fffff0000007fffffffc",
x"000000fffffffffe0007fffffffffffe00001ff00ff87c000001fffffff800001fffffc000001fffc00000003fffff00",
x"000003ffe03ffffc0007fff0007ffff800007fc001fffc000003f803fffc000007ffff80000003ff000000000ffffc00",
x"00000fff000ffff8000fff80003ffff00000ff00007ffc000007c000ffff000003ffff00000001fe0000000007fffc00",
x"00003ffe000ffff0000ffe00001fffe00001fe00003ffc00001f80003fff800001ffff00000001fc0000000007fff800",
x"00007ff8000ffff0000ff800001fffe00003fc00000ffc00001e00001fff800000ffff00000001f80000000003fff800",
x"0001fff0000ffff0000ff000001fffe00007fc000007fc00003c00000fffc00000ffff80000001f80000000003fff800",
x"0003fff0000ffff0000fe000000fffe00007f8000003fc00007800000fffe000007fff80000001f00000000003fff800",
x"0007ffe0000ffff0000fc000000fffe0000ff8000001fc0000f8000007ffe000007fffc0000001f00000000003fff800",
x"000fffc0000ffff0000f8000000fffe0000ff8000001fc0000f0000007fff000003fffc0000001e00000000003fff800",
x"001fffc0000ffff0001f0000000fffe0001ff8000000fc0001f0000007fff000003fffc0000003e00000000003fff800",
x"001fff80000ffff0001e0000000fffe0001ff80000007c0001e0000003fff800001fffe0000003c00000000003fff800",
x"003fff80000ffff0001e0000000fffe0001ff80000007c0001e0000003fff800001fffe0000007c00000000003fff800",
x"007fff80000ffff0001c0000000fffe0003ff80000003c0001e0000003fff800000ffff0000007800000000003fff800",
x"007fff00000ffff0001c0000000fffe0003ffc0000003c0003c0000003fff800000ffff0000007800000000003fff800",
x"00ffff00000ffff00018000c000fffe0003ffc0000001c0003c0000003fff800000ffff800000f000000000003fff800",
x"00ffff00000ffff00018000c000fffe0003ffe0000001c0003c0000003fff8000007fff800000f000000000003fff800",
x"01fffe00000ffff00038000e000fffe0003fff0000001c0003c0000003fffc000007fffffffffe000000000003fff800",
x"01fffe00000ffff00030000e000fffe0003fff8000000c0003c0000003fffc000003fffffffffe000000000003fff800",
x"01fffe00000ffff00000000e000fffe0003fffc000000c0003c0000003fffc000003fffffffffc000000000003fff800",
x"03fffe00000ffff00000000e000fffe0003ffff000000c0003c0000003fffc000001fffffffffc000000000003fff800",
x"03fffe00000ffff00000000f000fffe0003ffff800000c0003c0000003fffc000001fffe00007c000000000003fff800",
x"03fffe00000ffff00000000f000fffe0001ffffe0000000003c0000003fffc000001ffff000078000000000003fff800",
x"03fffc00000ffff00000000f000fffe0001fffff8000000003c0000003fffc000000ffff000078000000000003fff800",
x"07fffc00000ffff00000000f800fffe0001fffffe000000003c0000003fffc000000ffff0000f0000000000003fff800",
x"07fffc00000ffff00000000f800fffe0000ffffff800000003c0000003fffc0000007fff8000f0000000000003fff800",
x"07fffc00000ffff00000000fc00fffe0000ffffffe00000003c0000003fffc0000007fff8001e0000000000003fff800",
x"07fffc00000ffff00000000fe00fffe00007ffffff80000003c0000003fffc0000003fffc001e0000000000003fff800",
x"07fffc00000ffff00000000ff00fffe00003ffffffc0000003c0000003fffc0000003fffc003c0000000000003fff800",
x"07fffc00000ffff00000000ffe0fffe00001fffffff0000003c0000003fffc0000001fffe003c0000000003ffffff800",
x"07fffc00000ffff00000000fffffffe00000fffffff8000003c0000003fffc0000001fffe007c000000007fffffff800",
x"07fffc00000ffff00000000fffffffe000007ffffffe000003c0000003fffc0000001fffe007800000003ffffffff800",
x"07fffc00000ffff00000000fffffffe000003fffffff000003c0000003fffc0000000ffff00f80000000fffe03fff800",
x"07fffc00000ffff00000000ffe0fffe000001fffffff800003c0000003fffc0000000ffff00f00000001fff803fff800",
x"07fffc00000ffff00000000ff00fffe0000007ffffffc00003c0000003fffc00000007fff80f00000007fff003fff800",
x"07fffc00000ffff00000000fe00fffe0000001ffffffe00003c0000003fffc00000007fff81e0000000fffe003fff800",
x"07fffc00000ffff00000000fc00fffe0000000ffffffe00003c0000003fffc00000003fffc1e0000001fffc003fff800",
x"07fffc00000ffff00000000f800fffe00000003ffffff00003c0000003fffc00000003fffc3c0000001fff8003fff800",
x"03fffe00000ffff00000000f800fffe00000000ffffff00003c0000003fffc00000003fffc3c0000003fff8003fff800",
x"03fffe00000ffff00000000f000fffe000000003fffff80003c0000003fffc00000001fffe7c0000007fff8003fff800",
x"03fffe00000ffff00000000f000fffe000000000fffff80003c0000003fffc00000001fffe780000007fff0003fff800",
x"03fffe00000ffff00000000f000fffe0000000003ffffc0003c0000003fffc00000000fffff80000007fff0003fff800",
x"01fffe00000ffff00000000e000fffe0000000000ffffc0003c0000003fffc00000000fffff0000000ffff0003fff800",
x"01fffe00000ffff00000000e000fffe00003000007fffc0003c0000003fffc000000007ffff0000000ffff0003fff800",
x"01ffff00000ffff00001800e000fffe00003000001fffc0003c0000003fffc000000007fffe0000000ffff0003fff800",
x"00ffff00000ffff00001800e000fffe00003000000fffc0003c0000003fffc000000007fffe0000000ffff0003fff800",
x"00ffff00000ffff00001800c000fffe000038000007ffc0003c0000003fffc000000003fffc0000000ffff0003fff800",
x"007fff80000ffff00001800c000fffe000038000003ffc0003c0000003fffc000000003fffc0000000ffff0003fff800",
x"007fff80000ffff00001c000000fffe000038000001ffc0003c0000003fffc000000001fffc0000000ffff0003fff800",
x"003fff80000ffff00001c000000fffe00003c000001ffc0003c0000003fffc000000001fff80000000ffff0003fff800",
x"001fffc0000ffff00001e000000fffe00003c000000ffc0003c0000003fffc000000000fff80000000ffff0003fff800",
x"001fffc0000ffff00001e000000fffe00003e000000ff80003c0000003fffc000000000fff000000007fff0003fff800",
x"000fffe0000ffff00001f000000fffe00003e000000ff80003c0000003fffc000000000fff000000007fff0003fff800",
x"0007fff0000ffff00001f000000fffe00003f000000ff00003c0000003fffc0000000007fe000000003fff8003fff800",
x"0003fff0000ffff00001f800000fffe00003f800000ff00007c0000003fffc0000000007fe000000003fff8003fff800",
x"0001fff8000ffff00001fc00000fffe00003fc00001fe00007c0000003fffc0000000003fc000000001fffc003fff800",
x"0000fffc000ffff00001ff00000fffe00003fe00001fe00007c0000003fffc0000000003fc000000000fffe003fff800",
x"00003fff000ffff00001ffc0000fffe00003ff00003fc00007c0000003fffc0000000001fc0000000007fff003fff800",
x"00001fff800ffff80001fff8000ffff00003ffc0007f80000fe0000003fffc0000000001f80000000003fff803fffc00",
x"000007fff80ffffc0001fffffffffff80003ffe000ff00001ff0000007fffe0000000000f80000000000ffff03fffc00",
x"000000fffffffffe0001fffffffffffe000387fc07fe00007ffc00001fffff8000000000f000000000003fffffffff00",
x"0000001ffffffffff801fffffffffffff00380fffff80007ffffe007fffffffc00000000f0000000000007fffffffffc",
x"00000000fffffffff801fffffffffffff003003fffe00007ffffe007fffffffc00000000600000000000003ffffffffc",
x"0000000000000000000000000000000000030007ff000000000000000000000000000000600000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
constant ball_rom: rom_ball :=
(
"0000000000000",
"0000000000000",
"0000000000000",
"0000111110000",
"0001111111000",
"0011111111100",
"0011111111100",
"0011111111100",
"0011111111100",
"0001111111000",
"0000111110000",
"0000000000000",
"0000000000000"
);
begin
ball_single_row <= ball_rom(ball_row);--to determine which pixel to color with ball color
ball_validity_bit <= ball_single_row(ball_col);
r_ball<="0000";--ball color
g_ball<="1111";
b_ball<="0000";
welmes_single_row <= welmes_rom(welmes_row);--to determine which pixel to color with welcome message color
welmes_validity_bit <= welmes_single_row(welmes_col);
r_welmes<="1111";--welcome message color
g_welmes<="1111";
b_welmes<="0000";
paused_single_row <= paused_rom(paused_row);--to determine which pixel to color with pause message color
paused_validity_bit <= paused_single_row(paused_col);
r_paused<="1111";--pause message color
g_paused<="1000";
b_paused<="0000";
winmes_single_row <= winmes_rom(winmes_row);--to determine which pixel to color with win message color
winmes_validity_bit <= winmes_single_row(winmes_col);
r_winmes<="0000";--win message color
g_winmes<="0000";
b_winmes<="1111";
gameover_single_row <= gameover_rom(gameover_row);--to determine which pixel to color with gameover message color
gameover_validity_bit <= gameover_single_row(gameover_col);
r_gameover<="1111";--gameover message color
g_gameover<="0000";
b_gameover<="0000";
lives_single_row <=lives3_rom(lives_row)when isalive=3 else--to determine which pixel to color with lives message color
lives2_rom(lives_row)when isalive=2 else
lives1_rom(lives_row)when isalive=1 else
lives0_rom(lives_row);
lives_validity_bit <= lives_single_row(lives_col);
r_lives<="0000";--lives message color
g_lives<="1111";
b_lives<="1111";
hpos_scr<=hpos-152 when (hpos>152 and hpos<793)else
1;--bring x and y position inside screen by
vpos_scr<=vpos-37 when (vpos>37 and vpos<518)else
1;--subtracting fp,bp and sync period
process(clk_s)--process to generate random postion of x for ball and bat
begin
if(clk_s'event and clk_s='0') then
ball_x_vel_rand<=not ball_x_vel_rand;
if(rand_x=611)then
rand_x<=26;
else
rand_x<=rand_x+3;
end if;
end if;
end process;
process(clk_s)--main synchronization process
begin
if(clk_s'event and clk_s='1') then
if(resetgame='0') then--to reset game after key3 has been pressed
notstarted<='1';
isalive<=3;
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
is_destroyed_l1<=x"000000000000000000";
coll_x_l1<=x"000000000000000000";
coll_y_l1<=x"000000000000000000";
is_destroyed_l2<=x"0000000";
coll_x_l2<=x"0000000";
coll_y_l2<=x"0000000";
is_destroyed_l3<=x"000000000000000000";
coll_x_l3<=x"000000000000000000";
coll_y_l3<=x"000000000000000000";
is_destroyed_l4<=x"0000000000000000";
coll_x_l4<=x"0000000000000000";
coll_y_l4<=x"0000000000000000";
is_destroyed_l5<=x"000000000";
coll_x_l5<=x"000000000";
coll_y_l5<=x"000000000";
l1complete<='0';
l2complete<='0';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='1';
l3notstarted<='1';
l4notstarted<='1';
l5notstarted<='1';
level_selected<='0';
stopball<='0';
else
null;
end if;
if(level_selected='0')then--to select level at the start of the game
case level_select is
when "010"=>l1complete<='1';
l2complete<='0';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='1';
l4notstarted<='1';
l5notstarted<='1';
when "011"=>l1complete<='1';
l2complete<='1';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='0';
l4notstarted<='1';
l5notstarted<='1';
when "100"=>l1complete<='1';
l2complete<='1';
l3complete<='1';
l4complete<='0';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='0';
l4notstarted<='0';
l5notstarted<='1';
when "101"=>l1complete<='1';
l2complete<='1';
l3complete<='1';
l4complete<='1';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='0';
l4notstarted<='0';
l5notstarted<='0';
when others=>l1complete<='0';
l2complete<='0';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='1';
l3notstarted<='1';
l4notstarted<='1';
l5notstarted<='1';
end case;
else
null;
end if;
if(l2notstarted='1'and is_destroyed_l1=x"ffffffffffffffffff")then--to start level 2
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l1complete<='1';
l2notstarted<='0';
elsif(l3notstarted='1'and is_destroyed_l2=x"fffffff")then--to start level 3
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l2complete<='1';
l3notstarted<='0';
elsif(l4notstarted='1'and is_destroyed_l3=x"ffffffffffffffffff")then--to start level 4
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l3complete<='1';
l4notstarted<='0';
elsif(l5notstarted='1'and is_destroyed_l4=x"ffffffffffffffff")then--to start level 5
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l4complete<='1';
l5notstarted<='0';
elsif(is_destroyed_l5=x"fffffffff")then--to complete level 5
l5complete<='1';
else
null;
end if;
if(start='0' and level_select/="000" and level_select/="110" and level_select/="111") then--start the game and stop level selection only if valid level is selected
notstarted<='0';
level_selected<='1';
else
null;
end if;
if(notstarted='0') then
if(l1complete='0')then--display bricks of level 1
brick(hpos_scr,vpos_scr,x_cood_l1(71),y_cood_l1(71),ball_x,ball_y,draw_l1(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l1(71),coll_y_l1(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(70),y_cood_l1(70),ball_x,ball_y,draw_l1(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l1(70),coll_y_l1(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(69),y_cood_l1(69),ball_x,ball_y,draw_l1(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l1(69),coll_y_l1(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(68),y_cood_l1(68),ball_x,ball_y,draw_l1(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l1(68),coll_y_l1(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(67),y_cood_l1(67),ball_x,ball_y,draw_l1(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l1(67),coll_y_l1(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(66),y_cood_l1(66),ball_x,ball_y,draw_l1(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l1(66),coll_y_l1(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(65),y_cood_l1(65),ball_x,ball_y,draw_l1(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l1(65),coll_y_l1(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(64),y_cood_l1(64),ball_x,ball_y,draw_l1(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l1(64),coll_y_l1(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(63),y_cood_l1(63),ball_x,ball_y,draw_l1(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l1(63),coll_y_l1(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(62),y_cood_l1(62),ball_x,ball_y,draw_l1(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l1(62),coll_y_l1(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(61),y_cood_l1(61),ball_x,ball_y,draw_l1(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l1(61),coll_y_l1(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(60),y_cood_l1(60),ball_x,ball_y,draw_l1(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l1(60),coll_y_l1(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(59),y_cood_l1(59),ball_x,ball_y,draw_l1(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l1(59),coll_y_l1(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(58),y_cood_l1(58),ball_x,ball_y,draw_l1(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l1(58),coll_y_l1(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(57),y_cood_l1(57),ball_x,ball_y,draw_l1(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l1(57),coll_y_l1(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(56),y_cood_l1(56),ball_x,ball_y,draw_l1(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l1(56),coll_y_l1(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(55),y_cood_l1(55),ball_x,ball_y,draw_l1(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l1(55),coll_y_l1(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(54),y_cood_l1(54),ball_x,ball_y,draw_l1(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l1(54),coll_y_l1(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(53),y_cood_l1(53),ball_x,ball_y,draw_l1(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l1(53),coll_y_l1(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(52),y_cood_l1(52),ball_x,ball_y,draw_l1(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l1(52),coll_y_l1(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(51),y_cood_l1(51),ball_x,ball_y,draw_l1(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l1(51),coll_y_l1(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(50),y_cood_l1(50),ball_x,ball_y,draw_l1(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l1(50),coll_y_l1(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(49),y_cood_l1(49),ball_x,ball_y,draw_l1(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l1(49),coll_y_l1(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(48),y_cood_l1(48),ball_x,ball_y,draw_l1(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l1(48),coll_y_l1(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(47),y_cood_l1(47),ball_x,ball_y,draw_l1(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l1(47),coll_y_l1(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(46),y_cood_l1(46),ball_x,ball_y,draw_l1(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l1(46),coll_y_l1(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(45),y_cood_l1(45),ball_x,ball_y,draw_l1(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l1(45),coll_y_l1(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(44),y_cood_l1(44),ball_x,ball_y,draw_l1(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l1(44),coll_y_l1(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(43),y_cood_l1(43),ball_x,ball_y,draw_l1(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l1(43),coll_y_l1(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(42),y_cood_l1(42),ball_x,ball_y,draw_l1(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l1(42),coll_y_l1(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(41),y_cood_l1(41),ball_x,ball_y,draw_l1(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l1(41),coll_y_l1(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(40),y_cood_l1(40),ball_x,ball_y,draw_l1(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l1(40),coll_y_l1(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(39),y_cood_l1(39),ball_x,ball_y,draw_l1(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l1(39),coll_y_l1(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(38),y_cood_l1(38),ball_x,ball_y,draw_l1(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l1(38),coll_y_l1(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(37),y_cood_l1(37),ball_x,ball_y,draw_l1(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l1(37),coll_y_l1(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(36),y_cood_l1(36),ball_x,ball_y,draw_l1(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l1(36),coll_y_l1(36),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(35),y_cood_l1(35),ball_x,ball_y,draw_l1(35),r_brick(35),g_brick(35),b_brick(35),coll_x_l1(35),coll_y_l1(35),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(34),y_cood_l1(34),ball_x,ball_y,draw_l1(34),r_brick(34),g_brick(34),b_brick(34),coll_x_l1(34),coll_y_l1(34),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(33),y_cood_l1(33),ball_x,ball_y,draw_l1(33),r_brick(33),g_brick(33),b_brick(33),coll_x_l1(33),coll_y_l1(33),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(32),y_cood_l1(32),ball_x,ball_y,draw_l1(32),r_brick(32),g_brick(32),b_brick(32),coll_x_l1(32),coll_y_l1(32),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(31),y_cood_l1(31),ball_x,ball_y,draw_l1(31),r_brick(31),g_brick(31),b_brick(31),coll_x_l1(31),coll_y_l1(31),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(30),y_cood_l1(30),ball_x,ball_y,draw_l1(30),r_brick(30),g_brick(30),b_brick(30),coll_x_l1(30),coll_y_l1(30),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(29),y_cood_l1(29),ball_x,ball_y,draw_l1(29),r_brick(29),g_brick(29),b_brick(29),coll_x_l1(29),coll_y_l1(29),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(28),y_cood_l1(28),ball_x,ball_y,draw_l1(28),r_brick(28),g_brick(28),b_brick(28),coll_x_l1(28),coll_y_l1(28),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(27),y_cood_l1(27),ball_x,ball_y,draw_l1(27),r_brick(27),g_brick(27),b_brick(27),coll_x_l1(27),coll_y_l1(27),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(26),y_cood_l1(26),ball_x,ball_y,draw_l1(26),r_brick(26),g_brick(26),b_brick(26),coll_x_l1(26),coll_y_l1(26),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(25),y_cood_l1(25),ball_x,ball_y,draw_l1(25),r_brick(25),g_brick(25),b_brick(25),coll_x_l1(25),coll_y_l1(25),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(24),y_cood_l1(24),ball_x,ball_y,draw_l1(24),r_brick(24),g_brick(24),b_brick(24),coll_x_l1(24),coll_y_l1(24),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(23),y_cood_l1(23),ball_x,ball_y,draw_l1(23),r_brick(23),g_brick(23),b_brick(23),coll_x_l1(23),coll_y_l1(23),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(22),y_cood_l1(22),ball_x,ball_y,draw_l1(22),r_brick(22),g_brick(22),b_brick(22),coll_x_l1(22),coll_y_l1(22),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(21),y_cood_l1(21),ball_x,ball_y,draw_l1(21),r_brick(21),g_brick(21),b_brick(21),coll_x_l1(21),coll_y_l1(21),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(20),y_cood_l1(20),ball_x,ball_y,draw_l1(20),r_brick(20),g_brick(20),b_brick(20),coll_x_l1(20),coll_y_l1(20),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(19),y_cood_l1(19),ball_x,ball_y,draw_l1(19),r_brick(19),g_brick(19),b_brick(19),coll_x_l1(19),coll_y_l1(19),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(18),y_cood_l1(18),ball_x,ball_y,draw_l1(18),r_brick(18),g_brick(18),b_brick(18),coll_x_l1(18),coll_y_l1(18),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(17),y_cood_l1(17),ball_x,ball_y,draw_l1(17),r_brick(17),g_brick(17),b_brick(17),coll_x_l1(17),coll_y_l1(17),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(16),y_cood_l1(16),ball_x,ball_y,draw_l1(16),r_brick(16),g_brick(16),b_brick(16),coll_x_l1(16),coll_y_l1(16),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(15),y_cood_l1(15),ball_x,ball_y,draw_l1(15),r_brick(15),g_brick(15),b_brick(15),coll_x_l1(15),coll_y_l1(15),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(14),y_cood_l1(14),ball_x,ball_y,draw_l1(14),r_brick(14),g_brick(14),b_brick(14),coll_x_l1(14),coll_y_l1(14),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(13),y_cood_l1(13),ball_x,ball_y,draw_l1(13),r_brick(13),g_brick(13),b_brick(13),coll_x_l1(13),coll_y_l1(13),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(12),y_cood_l1(12),ball_x,ball_y,draw_l1(12),r_brick(12),g_brick(12),b_brick(12),coll_x_l1(12),coll_y_l1(12),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(11),y_cood_l1(11),ball_x,ball_y,draw_l1(11),r_brick(11),g_brick(11),b_brick(11),coll_x_l1(11),coll_y_l1(11),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(10),y_cood_l1(10),ball_x,ball_y,draw_l1(10),r_brick(10),g_brick(10),b_brick(10),coll_x_l1(10),coll_y_l1(10),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(9),y_cood_l1(9),ball_x,ball_y,draw_l1(9),r_brick(9),g_brick(9),b_brick(9),coll_x_l1(9),coll_y_l1(9),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(8),y_cood_l1(8),ball_x,ball_y,draw_l1(8),r_brick(8),g_brick(8),b_brick(8),coll_x_l1(8),coll_y_l1(8),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(7),y_cood_l1(7),ball_x,ball_y,draw_l1(7),r_brick(7),g_brick(7),b_brick(7),coll_x_l1(7),coll_y_l1(7),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(6),y_cood_l1(6),ball_x,ball_y,draw_l1(6),r_brick(6),g_brick(6),b_brick(6),coll_x_l1(6),coll_y_l1(6),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(5),y_cood_l1(5),ball_x,ball_y,draw_l1(5),r_brick(5),g_brick(5),b_brick(5),coll_x_l1(5),coll_y_l1(5),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(4),y_cood_l1(4),ball_x,ball_y,draw_l1(4),r_brick(4),g_brick(4),b_brick(4),coll_x_l1(4),coll_y_l1(4),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(3),y_cood_l1(3),ball_x,ball_y,draw_l1(3),r_brick(3),g_brick(3),b_brick(3),coll_x_l1(3),coll_y_l1(3),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(2),y_cood_l1(2),ball_x,ball_y,draw_l1(2),r_brick(2),g_brick(2),b_brick(2),coll_x_l1(2),coll_y_l1(2),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(1),y_cood_l1(1),ball_x,ball_y,draw_l1(1),r_brick(1),g_brick(1),b_brick(1),coll_x_l1(1),coll_y_l1(1),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(0),y_cood_l1(0),ball_x,ball_y,draw_l1(0),r_brick(0),g_brick(0),b_brick(0),coll_x_l1(0),coll_y_l1(0),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l2complete='0')then--display bricks of level 2
brick(hpos_scr,vpos_scr,x_cood_l2(71),y_cood_l2(71),ball_x,ball_y,draw_l2(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l2(71),coll_y_l2(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(70),y_cood_l2(70),ball_x,ball_y,draw_l2(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l2(70),coll_y_l2(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(69),y_cood_l2(69),ball_x,ball_y,draw_l2(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l2(69),coll_y_l2(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(68),y_cood_l2(68),ball_x,ball_y,draw_l2(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l2(68),coll_y_l2(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(67),y_cood_l2(67),ball_x,ball_y,draw_l2(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l2(67),coll_y_l2(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(66),y_cood_l2(66),ball_x,ball_y,draw_l2(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l2(66),coll_y_l2(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(65),y_cood_l2(65),ball_x,ball_y,draw_l2(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l2(65),coll_y_l2(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(64),y_cood_l2(64),ball_x,ball_y,draw_l2(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l2(64),coll_y_l2(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(63),y_cood_l2(63),ball_x,ball_y,draw_l2(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l2(63),coll_y_l2(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(62),y_cood_l2(62),ball_x,ball_y,draw_l2(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l2(62),coll_y_l2(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(61),y_cood_l2(61),ball_x,ball_y,draw_l2(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l2(61),coll_y_l2(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(60),y_cood_l2(60),ball_x,ball_y,draw_l2(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l2(60),coll_y_l2(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(59),y_cood_l2(59),ball_x,ball_y,draw_l2(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l2(59),coll_y_l2(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(58),y_cood_l2(58),ball_x,ball_y,draw_l2(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l2(58),coll_y_l2(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(57),y_cood_l2(57),ball_x,ball_y,draw_l2(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l2(57),coll_y_l2(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(56),y_cood_l2(56),ball_x,ball_y,draw_l2(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l2(56),coll_y_l2(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(55),y_cood_l2(55),ball_x,ball_y,draw_l2(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l2(55),coll_y_l2(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(54),y_cood_l2(54),ball_x,ball_y,draw_l2(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l2(54),coll_y_l2(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(53),y_cood_l2(53),ball_x,ball_y,draw_l2(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l2(53),coll_y_l2(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(52),y_cood_l2(52),ball_x,ball_y,draw_l2(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l2(52),coll_y_l2(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(51),y_cood_l2(51),ball_x,ball_y,draw_l2(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l2(51),coll_y_l2(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(50),y_cood_l2(50),ball_x,ball_y,draw_l2(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l2(50),coll_y_l2(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(49),y_cood_l2(49),ball_x,ball_y,draw_l2(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l2(49),coll_y_l2(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(48),y_cood_l2(48),ball_x,ball_y,draw_l2(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l2(48),coll_y_l2(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(47),y_cood_l2(47),ball_x,ball_y,draw_l2(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l2(47),coll_y_l2(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(46),y_cood_l2(46),ball_x,ball_y,draw_l2(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l2(46),coll_y_l2(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(45),y_cood_l2(45),ball_x,ball_y,draw_l2(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l2(45),coll_y_l2(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(44),y_cood_l2(44),ball_x,ball_y,draw_l2(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l2(44),coll_y_l2(44),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l3complete='0')then--display bricks of level 3
brick(hpos_scr,vpos_scr,x_cood_l3(71),y_cood_l3(71),ball_x,ball_y,draw_l3(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l3(71),coll_y_l3(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(70),y_cood_l3(70),ball_x,ball_y,draw_l3(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l3(70),coll_y_l3(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(69),y_cood_l3(69),ball_x,ball_y,draw_l3(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l3(69),coll_y_l3(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(68),y_cood_l3(68),ball_x,ball_y,draw_l3(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l3(68),coll_y_l3(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(67),y_cood_l3(67),ball_x,ball_y,draw_l3(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l3(67),coll_y_l3(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(66),y_cood_l3(66),ball_x,ball_y,draw_l3(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l3(66),coll_y_l3(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(65),y_cood_l3(65),ball_x,ball_y,draw_l3(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l3(65),coll_y_l3(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(64),y_cood_l3(64),ball_x,ball_y,draw_l3(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l3(64),coll_y_l3(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(63),y_cood_l3(63),ball_x,ball_y,draw_l3(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l3(63),coll_y_l3(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(62),y_cood_l3(62),ball_x,ball_y,draw_l3(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l3(62),coll_y_l3(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(61),y_cood_l3(61),ball_x,ball_y,draw_l3(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l3(61),coll_y_l3(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(60),y_cood_l3(60),ball_x,ball_y,draw_l3(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l3(60),coll_y_l3(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(59),y_cood_l3(59),ball_x,ball_y,draw_l3(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l3(59),coll_y_l3(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(58),y_cood_l3(58),ball_x,ball_y,draw_l3(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l3(58),coll_y_l3(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(57),y_cood_l3(57),ball_x,ball_y,draw_l3(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l3(57),coll_y_l3(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(56),y_cood_l3(56),ball_x,ball_y,draw_l3(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l3(56),coll_y_l3(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(55),y_cood_l3(55),ball_x,ball_y,draw_l3(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l3(55),coll_y_l3(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(54),y_cood_l3(54),ball_x,ball_y,draw_l3(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l3(54),coll_y_l3(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(53),y_cood_l3(53),ball_x,ball_y,draw_l3(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l3(53),coll_y_l3(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(52),y_cood_l3(52),ball_x,ball_y,draw_l3(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l3(52),coll_y_l3(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(51),y_cood_l3(51),ball_x,ball_y,draw_l3(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l3(51),coll_y_l3(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(50),y_cood_l3(50),ball_x,ball_y,draw_l3(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l3(50),coll_y_l3(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(49),y_cood_l3(49),ball_x,ball_y,draw_l3(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l3(49),coll_y_l3(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(48),y_cood_l3(48),ball_x,ball_y,draw_l3(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l3(48),coll_y_l3(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(47),y_cood_l3(47),ball_x,ball_y,draw_l3(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l3(47),coll_y_l3(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(46),y_cood_l3(46),ball_x,ball_y,draw_l3(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l3(46),coll_y_l3(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(45),y_cood_l3(45),ball_x,ball_y,draw_l3(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l3(45),coll_y_l3(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(44),y_cood_l3(44),ball_x,ball_y,draw_l3(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l3(44),coll_y_l3(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(43),y_cood_l3(43),ball_x,ball_y,draw_l3(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l3(43),coll_y_l3(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(42),y_cood_l3(42),ball_x,ball_y,draw_l3(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l3(42),coll_y_l3(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(41),y_cood_l3(41),ball_x,ball_y,draw_l3(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l3(41),coll_y_l3(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(40),y_cood_l3(40),ball_x,ball_y,draw_l3(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l3(40),coll_y_l3(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(39),y_cood_l3(39),ball_x,ball_y,draw_l3(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l3(39),coll_y_l3(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(38),y_cood_l3(38),ball_x,ball_y,draw_l3(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l3(38),coll_y_l3(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(37),y_cood_l3(37),ball_x,ball_y,draw_l3(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l3(37),coll_y_l3(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(36),y_cood_l3(36),ball_x,ball_y,draw_l3(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l3(36),coll_y_l3(36),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(35),y_cood_l3(35),ball_x,ball_y,draw_l3(35),r_brick(35),g_brick(35),b_brick(35),coll_x_l3(35),coll_y_l3(35),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(34),y_cood_l3(34),ball_x,ball_y,draw_l3(34),r_brick(34),g_brick(34),b_brick(34),coll_x_l3(34),coll_y_l3(34),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(33),y_cood_l3(33),ball_x,ball_y,draw_l3(33),r_brick(33),g_brick(33),b_brick(33),coll_x_l3(33),coll_y_l3(33),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(32),y_cood_l3(32),ball_x,ball_y,draw_l3(32),r_brick(32),g_brick(32),b_brick(32),coll_x_l3(32),coll_y_l3(32),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(31),y_cood_l3(31),ball_x,ball_y,draw_l3(31),r_brick(31),g_brick(31),b_brick(31),coll_x_l3(31),coll_y_l3(31),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(30),y_cood_l3(30),ball_x,ball_y,draw_l3(30),r_brick(30),g_brick(30),b_brick(30),coll_x_l3(30),coll_y_l3(30),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(29),y_cood_l3(29),ball_x,ball_y,draw_l3(29),r_brick(29),g_brick(29),b_brick(29),coll_x_l3(29),coll_y_l3(29),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(28),y_cood_l3(28),ball_x,ball_y,draw_l3(28),r_brick(28),g_brick(28),b_brick(28),coll_x_l3(28),coll_y_l3(28),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(27),y_cood_l3(27),ball_x,ball_y,draw_l3(27),r_brick(27),g_brick(27),b_brick(27),coll_x_l3(27),coll_y_l3(27),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(26),y_cood_l3(26),ball_x,ball_y,draw_l3(26),r_brick(26),g_brick(26),b_brick(26),coll_x_l3(26),coll_y_l3(26),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(25),y_cood_l3(25),ball_x,ball_y,draw_l3(25),r_brick(25),g_brick(25),b_brick(25),coll_x_l3(25),coll_y_l3(25),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(24),y_cood_l3(24),ball_x,ball_y,draw_l3(24),r_brick(24),g_brick(24),b_brick(24),coll_x_l3(24),coll_y_l3(24),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(23),y_cood_l3(23),ball_x,ball_y,draw_l3(23),r_brick(23),g_brick(23),b_brick(23),coll_x_l3(23),coll_y_l3(23),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(22),y_cood_l3(22),ball_x,ball_y,draw_l3(22),r_brick(22),g_brick(22),b_brick(22),coll_x_l3(22),coll_y_l3(22),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(21),y_cood_l3(21),ball_x,ball_y,draw_l3(21),r_brick(21),g_brick(21),b_brick(21),coll_x_l3(21),coll_y_l3(21),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(20),y_cood_l3(20),ball_x,ball_y,draw_l3(20),r_brick(20),g_brick(20),b_brick(20),coll_x_l3(20),coll_y_l3(20),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(19),y_cood_l3(19),ball_x,ball_y,draw_l3(19),r_brick(19),g_brick(19),b_brick(19),coll_x_l3(19),coll_y_l3(19),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(18),y_cood_l3(18),ball_x,ball_y,draw_l3(18),r_brick(18),g_brick(18),b_brick(18),coll_x_l3(18),coll_y_l3(18),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(17),y_cood_l3(17),ball_x,ball_y,draw_l3(17),r_brick(17),g_brick(17),b_brick(17),coll_x_l3(17),coll_y_l3(17),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(16),y_cood_l3(16),ball_x,ball_y,draw_l3(16),r_brick(16),g_brick(16),b_brick(16),coll_x_l3(16),coll_y_l3(16),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(15),y_cood_l3(15),ball_x,ball_y,draw_l3(15),r_brick(15),g_brick(15),b_brick(15),coll_x_l3(15),coll_y_l3(15),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(14),y_cood_l3(14),ball_x,ball_y,draw_l3(14),r_brick(14),g_brick(14),b_brick(14),coll_x_l3(14),coll_y_l3(14),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(13),y_cood_l3(13),ball_x,ball_y,draw_l3(13),r_brick(13),g_brick(13),b_brick(13),coll_x_l3(13),coll_y_l3(13),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(12),y_cood_l3(12),ball_x,ball_y,draw_l3(12),r_brick(12),g_brick(12),b_brick(12),coll_x_l3(12),coll_y_l3(12),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(11),y_cood_l3(11),ball_x,ball_y,draw_l3(11),r_brick(11),g_brick(11),b_brick(11),coll_x_l3(11),coll_y_l3(11),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(10),y_cood_l3(10),ball_x,ball_y,draw_l3(10),r_brick(10),g_brick(10),b_brick(10),coll_x_l3(10),coll_y_l3(10),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(9),y_cood_l3(9),ball_x,ball_y,draw_l3(9),r_brick(9),g_brick(9),b_brick(9),coll_x_l3(9),coll_y_l3(9),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(8),y_cood_l3(8),ball_x,ball_y,draw_l3(8),r_brick(8),g_brick(8),b_brick(8),coll_x_l3(8),coll_y_l3(8),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(7),y_cood_l3(7),ball_x,ball_y,draw_l3(7),r_brick(7),g_brick(7),b_brick(7),coll_x_l3(7),coll_y_l3(7),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(6),y_cood_l3(6),ball_x,ball_y,draw_l3(6),r_brick(6),g_brick(6),b_brick(6),coll_x_l3(6),coll_y_l3(6),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(5),y_cood_l3(5),ball_x,ball_y,draw_l3(5),r_brick(5),g_brick(5),b_brick(5),coll_x_l3(5),coll_y_l3(5),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(4),y_cood_l3(4),ball_x,ball_y,draw_l3(4),r_brick(4),g_brick(4),b_brick(4),coll_x_l3(4),coll_y_l3(4),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(3),y_cood_l3(3),ball_x,ball_y,draw_l3(3),r_brick(3),g_brick(3),b_brick(3),coll_x_l3(3),coll_y_l3(3),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(2),y_cood_l3(2),ball_x,ball_y,draw_l3(2),r_brick(2),g_brick(2),b_brick(2),coll_x_l3(2),coll_y_l3(2),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(1),y_cood_l3(1),ball_x,ball_y,draw_l3(1),r_brick(1),g_brick(1),b_brick(1),coll_x_l3(1),coll_y_l3(1),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(0),y_cood_l3(0),ball_x,ball_y,draw_l3(0),r_brick(0),g_brick(0),b_brick(0),coll_x_l3(0),coll_y_l3(0),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l4complete='0')then--display bricks of level 4
brick(hpos_scr,vpos_scr,x_cood_l4(71),y_cood_l4(71),ball_x,ball_y,draw_l4(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l4(71),coll_y_l4(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(70),y_cood_l4(70),ball_x,ball_y,draw_l4(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l4(70),coll_y_l4(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(69),y_cood_l4(69),ball_x,ball_y,draw_l4(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l4(69),coll_y_l4(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(68),y_cood_l4(68),ball_x,ball_y,draw_l4(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l4(68),coll_y_l4(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(67),y_cood_l4(67),ball_x,ball_y,draw_l4(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l4(67),coll_y_l4(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(66),y_cood_l4(66),ball_x,ball_y,draw_l4(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l4(66),coll_y_l4(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(65),y_cood_l4(65),ball_x,ball_y,draw_l4(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l4(65),coll_y_l4(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(64),y_cood_l4(64),ball_x,ball_y,draw_l4(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l4(64),coll_y_l4(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(63),y_cood_l4(63),ball_x,ball_y,draw_l4(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l4(63),coll_y_l4(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(62),y_cood_l4(62),ball_x,ball_y,draw_l4(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l4(62),coll_y_l4(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(61),y_cood_l4(61),ball_x,ball_y,draw_l4(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l4(61),coll_y_l4(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(60),y_cood_l4(60),ball_x,ball_y,draw_l4(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l4(60),coll_y_l4(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(59),y_cood_l4(59),ball_x,ball_y,draw_l4(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l4(59),coll_y_l4(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(58),y_cood_l4(58),ball_x,ball_y,draw_l4(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l4(58),coll_y_l4(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(57),y_cood_l4(57),ball_x,ball_y,draw_l4(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l4(57),coll_y_l4(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(56),y_cood_l4(56),ball_x,ball_y,draw_l4(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l4(56),coll_y_l4(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(55),y_cood_l4(55),ball_x,ball_y,draw_l4(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l4(55),coll_y_l4(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(54),y_cood_l4(54),ball_x,ball_y,draw_l4(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l4(54),coll_y_l4(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(53),y_cood_l4(53),ball_x,ball_y,draw_l4(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l4(53),coll_y_l4(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(52),y_cood_l4(52),ball_x,ball_y,draw_l4(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l4(52),coll_y_l4(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(51),y_cood_l4(51),ball_x,ball_y,draw_l4(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l4(51),coll_y_l4(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(50),y_cood_l4(50),ball_x,ball_y,draw_l4(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l4(50),coll_y_l4(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(49),y_cood_l4(49),ball_x,ball_y,draw_l4(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l4(49),coll_y_l4(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(48),y_cood_l4(48),ball_x,ball_y,draw_l4(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l4(48),coll_y_l4(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(47),y_cood_l4(47),ball_x,ball_y,draw_l4(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l4(47),coll_y_l4(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(46),y_cood_l4(46),ball_x,ball_y,draw_l4(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l4(46),coll_y_l4(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(45),y_cood_l4(45),ball_x,ball_y,draw_l4(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l4(45),coll_y_l4(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(44),y_cood_l4(44),ball_x,ball_y,draw_l4(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l4(44),coll_y_l4(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(43),y_cood_l4(43),ball_x,ball_y,draw_l4(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l4(43),coll_y_l4(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(42),y_cood_l4(42),ball_x,ball_y,draw_l4(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l4(42),coll_y_l4(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(41),y_cood_l4(41),ball_x,ball_y,draw_l4(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l4(41),coll_y_l4(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(40),y_cood_l4(40),ball_x,ball_y,draw_l4(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l4(40),coll_y_l4(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(39),y_cood_l4(39),ball_x,ball_y,draw_l4(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l4(39),coll_y_l4(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(38),y_cood_l4(38),ball_x,ball_y,draw_l4(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l4(38),coll_y_l4(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(37),y_cood_l4(37),ball_x,ball_y,draw_l4(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l4(37),coll_y_l4(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(36),y_cood_l4(36),ball_x,ball_y,draw_l4(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l4(36),coll_y_l4(36),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(35),y_cood_l4(35),ball_x,ball_y,draw_l4(35),r_brick(35),g_brick(35),b_brick(35),coll_x_l4(35),coll_y_l4(35),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(34),y_cood_l4(34),ball_x,ball_y,draw_l4(34),r_brick(34),g_brick(34),b_brick(34),coll_x_l4(34),coll_y_l4(34),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(33),y_cood_l4(33),ball_x,ball_y,draw_l4(33),r_brick(33),g_brick(33),b_brick(33),coll_x_l4(33),coll_y_l4(33),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(32),y_cood_l4(32),ball_x,ball_y,draw_l4(32),r_brick(32),g_brick(32),b_brick(32),coll_x_l4(32),coll_y_l4(32),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(31),y_cood_l4(31),ball_x,ball_y,draw_l4(31),r_brick(31),g_brick(31),b_brick(31),coll_x_l4(31),coll_y_l4(31),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(30),y_cood_l4(30),ball_x,ball_y,draw_l4(30),r_brick(30),g_brick(30),b_brick(30),coll_x_l4(30),coll_y_l4(30),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(29),y_cood_l4(29),ball_x,ball_y,draw_l4(29),r_brick(29),g_brick(29),b_brick(29),coll_x_l4(29),coll_y_l4(29),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(28),y_cood_l4(28),ball_x,ball_y,draw_l4(28),r_brick(28),g_brick(28),b_brick(28),coll_x_l4(28),coll_y_l4(28),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(27),y_cood_l4(27),ball_x,ball_y,draw_l4(27),r_brick(27),g_brick(27),b_brick(27),coll_x_l4(27),coll_y_l4(27),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(26),y_cood_l4(26),ball_x,ball_y,draw_l4(26),r_brick(26),g_brick(26),b_brick(26),coll_x_l4(26),coll_y_l4(26),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(25),y_cood_l4(25),ball_x,ball_y,draw_l4(25),r_brick(25),g_brick(25),b_brick(25),coll_x_l4(25),coll_y_l4(25),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(24),y_cood_l4(24),ball_x,ball_y,draw_l4(24),r_brick(24),g_brick(24),b_brick(24),coll_x_l4(24),coll_y_l4(24),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(23),y_cood_l4(23),ball_x,ball_y,draw_l4(23),r_brick(23),g_brick(23),b_brick(23),coll_x_l4(23),coll_y_l4(23),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(22),y_cood_l4(22),ball_x,ball_y,draw_l4(22),r_brick(22),g_brick(22),b_brick(22),coll_x_l4(22),coll_y_l4(22),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(21),y_cood_l4(21),ball_x,ball_y,draw_l4(21),r_brick(21),g_brick(21),b_brick(21),coll_x_l4(21),coll_y_l4(21),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(20),y_cood_l4(20),ball_x,ball_y,draw_l4(20),r_brick(20),g_brick(20),b_brick(20),coll_x_l4(20),coll_y_l4(20),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(19),y_cood_l4(19),ball_x,ball_y,draw_l4(19),r_brick(19),g_brick(19),b_brick(19),coll_x_l4(19),coll_y_l4(19),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(18),y_cood_l4(18),ball_x,ball_y,draw_l4(18),r_brick(18),g_brick(18),b_brick(18),coll_x_l4(18),coll_y_l4(18),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(17),y_cood_l4(17),ball_x,ball_y,draw_l4(17),r_brick(17),g_brick(17),b_brick(17),coll_x_l4(17),coll_y_l4(17),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(16),y_cood_l4(16),ball_x,ball_y,draw_l4(16),r_brick(16),g_brick(16),b_brick(16),coll_x_l4(16),coll_y_l4(16),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(15),y_cood_l4(15),ball_x,ball_y,draw_l4(15),r_brick(15),g_brick(15),b_brick(15),coll_x_l4(15),coll_y_l4(15),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(14),y_cood_l4(14),ball_x,ball_y,draw_l4(14),r_brick(14),g_brick(14),b_brick(14),coll_x_l4(14),coll_y_l4(14),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(13),y_cood_l4(13),ball_x,ball_y,draw_l4(13),r_brick(13),g_brick(13),b_brick(13),coll_x_l4(13),coll_y_l4(13),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(12),y_cood_l4(12),ball_x,ball_y,draw_l4(12),r_brick(12),g_brick(12),b_brick(12),coll_x_l4(12),coll_y_l4(12),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(11),y_cood_l4(11),ball_x,ball_y,draw_l4(11),r_brick(11),g_brick(11),b_brick(11),coll_x_l4(11),coll_y_l4(11),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(10),y_cood_l4(10),ball_x,ball_y,draw_l4(10),r_brick(10),g_brick(10),b_brick(10),coll_x_l4(10),coll_y_l4(10),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(9),y_cood_l4(9),ball_x,ball_y,draw_l4(9),r_brick(9),g_brick(9),b_brick(9),coll_x_l4(9),coll_y_l4(9),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(8),y_cood_l4(8),ball_x,ball_y,draw_l4(8),r_brick(8),g_brick(8),b_brick(8),coll_x_l4(8),coll_y_l4(8),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l5complete='0')then--display bricks of level 5
brick(hpos_scr,vpos_scr,x_cood_l5(71),y_cood_l5(71),ball_x,ball_y,draw_l5(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l5(71),coll_y_l5(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(70),y_cood_l5(70),ball_x,ball_y,draw_l5(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l5(70),coll_y_l5(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(69),y_cood_l5(69),ball_x,ball_y,draw_l5(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l5(69),coll_y_l5(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(68),y_cood_l5(68),ball_x,ball_y,draw_l5(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l5(68),coll_y_l5(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(67),y_cood_l5(67),ball_x,ball_y,draw_l5(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l5(67),coll_y_l5(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(66),y_cood_l5(66),ball_x,ball_y,draw_l5(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l5(66),coll_y_l5(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(65),y_cood_l5(65),ball_x,ball_y,draw_l5(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l5(65),coll_y_l5(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(64),y_cood_l5(64),ball_x,ball_y,draw_l5(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l5(64),coll_y_l5(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(63),y_cood_l5(63),ball_x,ball_y,draw_l5(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l5(63),coll_y_l5(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(62),y_cood_l5(62),ball_x,ball_y,draw_l5(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l5(62),coll_y_l5(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(61),y_cood_l5(61),ball_x,ball_y,draw_l5(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l5(61),coll_y_l5(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(60),y_cood_l5(60),ball_x,ball_y,draw_l5(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l5(60),coll_y_l5(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(59),y_cood_l5(59),ball_x,ball_y,draw_l5(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l5(59),coll_y_l5(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(58),y_cood_l5(58),ball_x,ball_y,draw_l5(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l5(58),coll_y_l5(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(57),y_cood_l5(57),ball_x,ball_y,draw_l5(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l5(57),coll_y_l5(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(56),y_cood_l5(56),ball_x,ball_y,draw_l5(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l5(56),coll_y_l5(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(55),y_cood_l5(55),ball_x,ball_y,draw_l5(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l5(55),coll_y_l5(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(54),y_cood_l5(54),ball_x,ball_y,draw_l5(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l5(54),coll_y_l5(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(53),y_cood_l5(53),ball_x,ball_y,draw_l5(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l5(53),coll_y_l5(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(52),y_cood_l5(52),ball_x,ball_y,draw_l5(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l5(52),coll_y_l5(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(51),y_cood_l5(51),ball_x,ball_y,draw_l5(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l5(51),coll_y_l5(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(50),y_cood_l5(50),ball_x,ball_y,draw_l5(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l5(50),coll_y_l5(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(49),y_cood_l5(49),ball_x,ball_y,draw_l5(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l5(49),coll_y_l5(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(48),y_cood_l5(48),ball_x,ball_y,draw_l5(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l5(48),coll_y_l5(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(47),y_cood_l5(47),ball_x,ball_y,draw_l5(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l5(47),coll_y_l5(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(46),y_cood_l5(46),ball_x,ball_y,draw_l5(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l5(46),coll_y_l5(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(45),y_cood_l5(45),ball_x,ball_y,draw_l5(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l5(45),coll_y_l5(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(44),y_cood_l5(44),ball_x,ball_y,draw_l5(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l5(44),coll_y_l5(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(43),y_cood_l5(43),ball_x,ball_y,draw_l5(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l5(43),coll_y_l5(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(42),y_cood_l5(42),ball_x,ball_y,draw_l5(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l5(42),coll_y_l5(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(41),y_cood_l5(41),ball_x,ball_y,draw_l5(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l5(41),coll_y_l5(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(40),y_cood_l5(40),ball_x,ball_y,draw_l5(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l5(40),coll_y_l5(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(39),y_cood_l5(39),ball_x,ball_y,draw_l5(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l5(39),coll_y_l5(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(38),y_cood_l5(38),ball_x,ball_y,draw_l5(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l5(38),coll_y_l5(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(37),y_cood_l5(37),ball_x,ball_y,draw_l5(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l5(37),coll_y_l5(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(36),y_cood_l5(36),ball_x,ball_y,draw_l5(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l5(36),coll_y_l5(36),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
else--all levels are completed sucessfully
winmes(hpos_scr,vpos_scr,winmes_x,winmes_y,winmes_row,winmes_col);--get gameover image
stopball<='1';--to stop the ball motion
end if;
bat(hpos_scr,vpos_scr,bat_x,bat_y,draw_bat,r_bat,g_bat,b_bat);--display bat
lives(hpos_scr,vpos_scr,lives_x,lives_y,lives_row,lives_col);--get lives image
else--game has not started yet
welmes(hpos_scr,vpos_scr,welmes_x,welmes_y,welmes_row,welmes_col);--welcome message
end if;
if(ball_y>480 and isalive=0) then--if last life is used uo
gameover(hpos_scr,vpos_scr,gameover_x,gameover_y,gameover_row,gameover_col);--get gameover image
stopball<='1';--to stop the ball motion
else
null;
end if;
if(pause='1' and stopball='0' and notstarted='0')then--if pause switch is on
paused(hpos_scr,vpos_scr,paused_x,paused_y,paused_row,paused_col);--get paused image
else
null;
end if;
if(hpos>152 and hpos<793 and vpos>37 and vpos<518) then
if(welmes_validity_bit='1') then
r<=r_welmes; --display welcome message
g<=g_welmes;
b<=b_welmes;
elsif(lives_validity_bit='1') then
r<=r_lives; --display lives
g<=g_lives;
b<=b_lives;
elsif(ball_validity_bit='1') then
r<=r_ball; --display ball
g<=g_ball;
b<=b_ball;
elsif(draw_bat='1') then
r<=r_bat; --display bat
g<=g_bat;
b<=b_bat;
elsif(paused_validity_bit='1') then
r<=r_paused; --display pause message
g<=g_paused;
b<=b_paused;
elsif(gameover_validity_bit='1') then
r<=r_gameover; --display gameover
g<=g_gameover;
b<=b_gameover;
elsif(winmes_validity_bit='1') then
r<=r_winmes; --display winning message
g<=g_winmes;
b<=b_winmes;
elsif(draw_l1(71)='1' and is_destroyed_l1(71)='0') then--display bricks of level1
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l1(70)='1' and is_destroyed_l1(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l1(69)='1' and is_destroyed_l1(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l1(68)='1' and is_destroyed_l1(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l1(67)='1' and is_destroyed_l1(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l1(66)='1' and is_destroyed_l1(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l1(65)='1' and is_destroyed_l1(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l1(64)='1' and is_destroyed_l1(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l1(63)='1' and is_destroyed_l1(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l1(62)='1' and is_destroyed_l1(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l1(61)='1' and is_destroyed_l1(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l1(60)='1' and is_destroyed_l1(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l1(59)='1' and is_destroyed_l1(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l1(58)='1' and is_destroyed_l1(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l1(57)='1' and is_destroyed_l1(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l1(56)='1' and is_destroyed_l1(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l1(55)='1' and is_destroyed_l1(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l1(54)='1' and is_destroyed_l1(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l1(53)='1' and is_destroyed_l1(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l1(52)='1' and is_destroyed_l1(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l1(51)='1' and is_destroyed_l1(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l1(50)='1' and is_destroyed_l1(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l1(49)='1' and is_destroyed_l1(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l1(48)='1' and is_destroyed_l1(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l1(47)='1' and is_destroyed_l1(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l1(46)='1' and is_destroyed_l1(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l1(45)='1' and is_destroyed_l1(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l1(44)='1' and is_destroyed_l1(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l1(43)='1' and is_destroyed_l1(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l1(42)='1' and is_destroyed_l1(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l1(41)='1' and is_destroyed_l1(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l1(40)='1' and is_destroyed_l1(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l1(39)='1' and is_destroyed_l1(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l1(38)='1' and is_destroyed_l1(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l1(37)='1' and is_destroyed_l1(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l1(36)='1' and is_destroyed_l1(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
elsif(draw_l1(35)='1' and is_destroyed_l1(35)='0') then
r<=r_brick(35);
g<=g_brick(35);
b<=b_brick(35);
elsif(draw_l1(34)='1' and is_destroyed_l1(34)='0') then
r<=r_brick(34);
g<=g_brick(34);
b<=b_brick(34);
elsif(draw_l1(33)='1' and is_destroyed_l1(33)='0') then
r<=r_brick(33);
g<=g_brick(33);
b<=b_brick(33);
elsif(draw_l1(32)='1' and is_destroyed_l1(32)='0') then
r<=r_brick(32);
g<=g_brick(32);
b<=b_brick(32);
elsif(draw_l1(31)='1' and is_destroyed_l1(31)='0') then
r<=r_brick(31);
g<=g_brick(31);
b<=b_brick(31);
elsif(draw_l1(30)='1' and is_destroyed_l1(30)='0') then
r<=r_brick(30);
g<=g_brick(30);
b<=b_brick(30);
elsif(draw_l1(29)='1' and is_destroyed_l1(29)='0') then
r<=r_brick(29);
g<=g_brick(29);
b<=b_brick(29);
elsif(draw_l1(28)='1' and is_destroyed_l1(28)='0') then
r<=r_brick(28);
g<=g_brick(28);
b<=b_brick(28);
elsif(draw_l1(27)='1' and is_destroyed_l1(27)='0') then
r<=r_brick(27);
g<=g_brick(27);
b<=b_brick(27);
elsif(draw_l1(26)='1' and is_destroyed_l1(26)='0') then
r<=r_brick(26);
g<=g_brick(26);
b<=b_brick(26);
elsif(draw_l1(25)='1' and is_destroyed_l1(25)='0') then
r<=r_brick(25);
g<=g_brick(25);
b<=b_brick(25);
elsif(draw_l1(24)='1' and is_destroyed_l1(24)='0') then
r<=r_brick(24);
g<=g_brick(24);
b<=b_brick(24);
elsif(draw_l1(23)='1' and is_destroyed_l1(23)='0') then
r<=r_brick(23);
g<=g_brick(23);
b<=b_brick(23);
elsif(draw_l1(22)='1' and is_destroyed_l1(22)='0') then
r<=r_brick(22);
g<=g_brick(22);
b<=b_brick(22);
elsif(draw_l1(21)='1' and is_destroyed_l1(21)='0') then
r<=r_brick(21);
g<=g_brick(21);
b<=b_brick(21);
elsif(draw_l1(20)='1' and is_destroyed_l1(20)='0') then
r<=r_brick(20);
g<=g_brick(20);
b<=b_brick(20);
elsif(draw_l1(19)='1' and is_destroyed_l1(19)='0') then
r<=r_brick(19);
g<=g_brick(19);
b<=b_brick(19);
elsif(draw_l1(18)='1' and is_destroyed_l1(18)='0') then
r<=r_brick(18);
g<=g_brick(18);
b<=b_brick(18);
elsif(draw_l1(17)='1' and is_destroyed_l1(17)='0') then
r<=r_brick(17);
g<=g_brick(17);
b<=b_brick(17);
elsif(draw_l1(16)='1' and is_destroyed_l1(16)='0') then
r<=r_brick(16);
g<=g_brick(16);
b<=b_brick(16);
elsif(draw_l1(15)='1' and is_destroyed_l1(15)='0') then
r<=r_brick(15);
g<=g_brick(15);
b<=b_brick(15);
elsif(draw_l1(14)='1' and is_destroyed_l1(14)='0') then
r<=r_brick(14);
g<=g_brick(14);
b<=b_brick(14);
elsif(draw_l1(13)='1' and is_destroyed_l1(13)='0') then
r<=r_brick(13);
g<=g_brick(13);
b<=b_brick(13);
elsif(draw_l1(12)='1' and is_destroyed_l1(12)='0') then
r<=r_brick(12);
g<=g_brick(12);
b<=b_brick(12);
elsif(draw_l1(11)='1' and is_destroyed_l1(11)='0') then
r<=r_brick(11);
g<=g_brick(11);
b<=b_brick(11);
elsif(draw_l1(10)='1' and is_destroyed_l1(10)='0') then
r<=r_brick(10);
g<=g_brick(10);
b<=b_brick(10);
elsif(draw_l1(9)='1' and is_destroyed_l1(9)='0') then
r<=r_brick(9);
g<=g_brick(9);
b<=b_brick(9);
elsif(draw_l1(8)='1' and is_destroyed_l1(8)='0') then
r<=r_brick(8);
g<=g_brick(8);
b<=b_brick(8);
elsif(draw_l1(7)='1' and is_destroyed_l1(7)='0') then
r<=r_brick(7);
g<=g_brick(7);
b<=b_brick(7);
elsif(draw_l1(6)='1' and is_destroyed_l1(6)='0') then
r<=r_brick(6);
g<=g_brick(6);
b<=b_brick(6);
elsif(draw_l1(5)='1' and is_destroyed_l1(5)='0') then
r<=r_brick(5);
g<=g_brick(5);
b<=b_brick(5);
elsif(draw_l1(4)='1' and is_destroyed_l1(4)='0') then
r<=r_brick(4);
g<=g_brick(4);
b<=b_brick(4);
elsif(draw_l1(3)='1' and is_destroyed_l1(3)='0') then
r<=r_brick(3);
g<=g_brick(3);
b<=b_brick(3);
elsif(draw_l1(2)='1' and is_destroyed_l1(2)='0') then
r<=r_brick(2);
g<=g_brick(2);
b<=b_brick(2);
elsif(draw_l1(1)='1' and is_destroyed_l1(1)='0') then
r<=r_brick(1);
g<=g_brick(1);
b<=b_brick(1);
elsif(draw_l1(0)='1' and is_destroyed_l1(0)='0') then
r<=r_brick(0);
g<=g_brick(0);
b<=b_brick(0);
elsif(draw_l2(71)='1' and is_destroyed_l2(71)='0') then--display bricks of level2
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l2(70)='1' and is_destroyed_l2(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l2(69)='1' and is_destroyed_l2(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l2(68)='1' and is_destroyed_l2(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l2(67)='1' and is_destroyed_l2(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l2(66)='1' and is_destroyed_l2(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l2(65)='1' and is_destroyed_l2(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l2(64)='1' and is_destroyed_l2(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l2(63)='1' and is_destroyed_l2(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l2(62)='1' and is_destroyed_l2(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l2(61)='1' and is_destroyed_l2(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l2(60)='1' and is_destroyed_l2(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l2(59)='1' and is_destroyed_l2(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l2(58)='1' and is_destroyed_l2(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l2(57)='1' and is_destroyed_l2(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l2(56)='1' and is_destroyed_l2(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l2(55)='1' and is_destroyed_l2(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l2(54)='1' and is_destroyed_l2(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l2(53)='1' and is_destroyed_l2(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l2(52)='1' and is_destroyed_l2(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l2(51)='1' and is_destroyed_l2(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l2(50)='1' and is_destroyed_l2(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l2(49)='1' and is_destroyed_l2(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l2(48)='1' and is_destroyed_l2(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l2(47)='1' and is_destroyed_l2(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l2(46)='1' and is_destroyed_l2(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l2(45)='1' and is_destroyed_l2(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l2(44)='1' and is_destroyed_l2(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l3(71)='1' and is_destroyed_l3(71)='0') then--display bricks of level3
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l3(70)='1' and is_destroyed_l3(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l3(69)='1' and is_destroyed_l3(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l3(68)='1' and is_destroyed_l3(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l3(67)='1' and is_destroyed_l3(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l3(66)='1' and is_destroyed_l3(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l3(65)='1' and is_destroyed_l3(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l3(64)='1' and is_destroyed_l3(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l3(63)='1' and is_destroyed_l3(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l3(62)='1' and is_destroyed_l3(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l3(61)='1' and is_destroyed_l3(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l3(60)='1' and is_destroyed_l3(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l3(59)='1' and is_destroyed_l3(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l3(58)='1' and is_destroyed_l3(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l3(57)='1' and is_destroyed_l3(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l3(56)='1' and is_destroyed_l3(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l3(55)='1' and is_destroyed_l3(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l3(54)='1' and is_destroyed_l3(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l3(53)='1' and is_destroyed_l3(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l3(52)='1' and is_destroyed_l3(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l3(51)='1' and is_destroyed_l3(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l3(50)='1' and is_destroyed_l3(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l3(49)='1' and is_destroyed_l3(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l3(48)='1' and is_destroyed_l3(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l3(47)='1' and is_destroyed_l3(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l3(46)='1' and is_destroyed_l3(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l3(45)='1' and is_destroyed_l3(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l3(44)='1' and is_destroyed_l3(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l3(43)='1' and is_destroyed_l3(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l3(42)='1' and is_destroyed_l3(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l3(41)='1' and is_destroyed_l3(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l3(40)='1' and is_destroyed_l3(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l3(39)='1' and is_destroyed_l3(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l3(38)='1' and is_destroyed_l3(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l3(37)='1' and is_destroyed_l3(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l3(36)='1' and is_destroyed_l3(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
elsif(draw_l3(35)='1' and is_destroyed_l3(35)='0') then
r<=r_brick(35);
g<=g_brick(35);
b<=b_brick(35);
elsif(draw_l3(34)='1' and is_destroyed_l3(34)='0') then
r<=r_brick(34);
g<=g_brick(34);
b<=b_brick(34);
elsif(draw_l3(33)='1' and is_destroyed_l3(33)='0') then
r<=r_brick(33);
g<=g_brick(33);
b<=b_brick(33);
elsif(draw_l3(32)='1' and is_destroyed_l3(32)='0') then
r<=r_brick(32);
g<=g_brick(32);
b<=b_brick(32);
elsif(draw_l3(31)='1' and is_destroyed_l3(31)='0') then
r<=r_brick(31);
g<=g_brick(31);
b<=b_brick(31);
elsif(draw_l3(30)='1' and is_destroyed_l3(30)='0') then
r<=r_brick(30);
g<=g_brick(30);
b<=b_brick(30);
elsif(draw_l3(29)='1' and is_destroyed_l3(29)='0') then
r<=r_brick(29);
g<=g_brick(29);
b<=b_brick(29);
elsif(draw_l3(28)='1' and is_destroyed_l3(28)='0') then
r<=r_brick(28);
g<=g_brick(28);
b<=b_brick(28);
elsif(draw_l3(27)='1' and is_destroyed_l3(27)='0') then
r<=r_brick(27);
g<=g_brick(27);
b<=b_brick(27);
elsif(draw_l3(26)='1' and is_destroyed_l3(26)='0') then
r<=r_brick(26);
g<=g_brick(26);
b<=b_brick(26);
elsif(draw_l3(25)='1' and is_destroyed_l3(25)='0') then
r<=r_brick(25);
g<=g_brick(25);
b<=b_brick(25);
elsif(draw_l3(24)='1' and is_destroyed_l3(24)='0') then
r<=r_brick(24);
g<=g_brick(24);
b<=b_brick(24);
elsif(draw_l3(23)='1' and is_destroyed_l3(23)='0') then
r<=r_brick(23);
g<=g_brick(23);
b<=b_brick(23);
elsif(draw_l3(22)='1' and is_destroyed_l3(22)='0') then
r<=r_brick(22);
g<=g_brick(22);
b<=b_brick(22);
elsif(draw_l3(21)='1' and is_destroyed_l3(21)='0') then
r<=r_brick(21);
g<=g_brick(21);
b<=b_brick(21);
elsif(draw_l3(20)='1' and is_destroyed_l3(20)='0') then
r<=r_brick(20);
g<=g_brick(20);
b<=b_brick(20);
elsif(draw_l3(19)='1' and is_destroyed_l3(19)='0') then
r<=r_brick(19);
g<=g_brick(19);
b<=b_brick(19);
elsif(draw_l3(18)='1' and is_destroyed_l3(18)='0') then
r<=r_brick(18);
g<=g_brick(18);
b<=b_brick(18);
elsif(draw_l3(17)='1' and is_destroyed_l3(17)='0') then
r<=r_brick(17);
g<=g_brick(17);
b<=b_brick(17);
elsif(draw_l3(16)='1' and is_destroyed_l3(16)='0') then
r<=r_brick(16);
g<=g_brick(16);
b<=b_brick(16);
elsif(draw_l3(15)='1' and is_destroyed_l3(15)='0') then
r<=r_brick(15);
g<=g_brick(15);
b<=b_brick(15);
elsif(draw_l3(14)='1' and is_destroyed_l3(14)='0') then
r<=r_brick(14);
g<=g_brick(14);
b<=b_brick(14);
elsif(draw_l3(13)='1' and is_destroyed_l3(13)='0') then
r<=r_brick(13);
g<=g_brick(13);
b<=b_brick(13);
elsif(draw_l3(12)='1' and is_destroyed_l3(12)='0') then
r<=r_brick(12);
g<=g_brick(12);
b<=b_brick(12);
elsif(draw_l3(11)='1' and is_destroyed_l3(11)='0') then
r<=r_brick(11);
g<=g_brick(11);
b<=b_brick(11);
elsif(draw_l3(10)='1' and is_destroyed_l3(10)='0') then
r<=r_brick(10);
g<=g_brick(10);
b<=b_brick(10);
elsif(draw_l3(9)='1' and is_destroyed_l3(9)='0') then
r<=r_brick(9);
g<=g_brick(9);
b<=b_brick(9);
elsif(draw_l3(8)='1' and is_destroyed_l3(8)='0') then
r<=r_brick(8);
g<=g_brick(8);
b<=b_brick(8);
elsif(draw_l3(7)='1' and is_destroyed_l3(7)='0') then
r<=r_brick(7);
g<=g_brick(7);
b<=b_brick(7);
elsif(draw_l3(6)='1' and is_destroyed_l3(6)='0') then
r<=r_brick(6);
g<=g_brick(6);
b<=b_brick(6);
elsif(draw_l3(5)='1' and is_destroyed_l3(5)='0') then
r<=r_brick(5);
g<=g_brick(5);
b<=b_brick(5);
elsif(draw_l3(4)='1' and is_destroyed_l3(4)='0') then
r<=r_brick(4);
g<=g_brick(4);
b<=b_brick(4);
elsif(draw_l3(3)='1' and is_destroyed_l3(3)='0') then
r<=r_brick(3);
g<=g_brick(3);
b<=b_brick(3);
elsif(draw_l3(2)='1' and is_destroyed_l3(2)='0') then
r<=r_brick(2);
g<=g_brick(2);
b<=b_brick(2);
elsif(draw_l3(1)='1' and is_destroyed_l3(1)='0') then
r<=r_brick(1);
g<=g_brick(1);
b<=b_brick(1);
elsif(draw_l3(0)='1' and is_destroyed_l3(0)='0') then
r<=r_brick(0);
g<=g_brick(0);
b<=b_brick(0);
elsif(draw_l4(71)='1' and is_destroyed_l4(71)='0') then--display bricks of level4
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l4(70)='1' and is_destroyed_l4(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l4(69)='1' and is_destroyed_l4(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l4(68)='1' and is_destroyed_l4(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l4(67)='1' and is_destroyed_l4(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l4(66)='1' and is_destroyed_l4(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l4(65)='1' and is_destroyed_l4(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l4(64)='1' and is_destroyed_l4(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l4(63)='1' and is_destroyed_l4(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l4(62)='1' and is_destroyed_l4(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l4(61)='1' and is_destroyed_l4(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l4(60)='1' and is_destroyed_l4(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l4(59)='1' and is_destroyed_l4(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l4(58)='1' and is_destroyed_l4(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l4(57)='1' and is_destroyed_l4(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l4(56)='1' and is_destroyed_l4(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l4(55)='1' and is_destroyed_l4(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l4(54)='1' and is_destroyed_l4(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l4(53)='1' and is_destroyed_l4(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l4(52)='1' and is_destroyed_l4(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l4(51)='1' and is_destroyed_l4(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l4(50)='1' and is_destroyed_l4(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l4(49)='1' and is_destroyed_l4(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l4(48)='1' and is_destroyed_l4(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l4(47)='1' and is_destroyed_l4(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l4(46)='1' and is_destroyed_l4(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l4(45)='1' and is_destroyed_l4(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l4(44)='1' and is_destroyed_l4(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l4(43)='1' and is_destroyed_l4(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l4(42)='1' and is_destroyed_l4(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l4(41)='1' and is_destroyed_l4(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l4(40)='1' and is_destroyed_l4(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l4(39)='1' and is_destroyed_l4(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l4(38)='1' and is_destroyed_l4(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l4(37)='1' and is_destroyed_l4(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l4(36)='1' and is_destroyed_l4(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
elsif(draw_l4(35)='1' and is_destroyed_l4(35)='0') then
r<=r_brick(35);
g<=g_brick(35);
b<=b_brick(35);
elsif(draw_l4(34)='1' and is_destroyed_l4(34)='0') then
r<=r_brick(34);
g<=g_brick(34);
b<=b_brick(34);
elsif(draw_l4(33)='1' and is_destroyed_l4(33)='0') then
r<=r_brick(33);
g<=g_brick(33);
b<=b_brick(33);
elsif(draw_l4(32)='1' and is_destroyed_l4(32)='0') then
r<=r_brick(32);
g<=g_brick(32);
b<=b_brick(32);
elsif(draw_l4(31)='1' and is_destroyed_l4(31)='0') then
r<=r_brick(31);
g<=g_brick(31);
b<=b_brick(31);
elsif(draw_l4(30)='1' and is_destroyed_l4(30)='0') then
r<=r_brick(30);
g<=g_brick(30);
b<=b_brick(30);
elsif(draw_l4(29)='1' and is_destroyed_l4(29)='0') then
r<=r_brick(29);
g<=g_brick(29);
b<=b_brick(29);
elsif(draw_l4(28)='1' and is_destroyed_l4(28)='0') then
r<=r_brick(28);
g<=g_brick(28);
b<=b_brick(28);
elsif(draw_l4(27)='1' and is_destroyed_l4(27)='0') then
r<=r_brick(27);
g<=g_brick(27);
b<=b_brick(27);
elsif(draw_l4(26)='1' and is_destroyed_l4(26)='0') then
r<=r_brick(26);
g<=g_brick(26);
b<=b_brick(26);
elsif(draw_l4(25)='1' and is_destroyed_l4(25)='0') then
r<=r_brick(25);
g<=g_brick(25);
b<=b_brick(25);
elsif(draw_l4(24)='1' and is_destroyed_l4(24)='0') then
r<=r_brick(24);
g<=g_brick(24);
b<=b_brick(24);
elsif(draw_l4(23)='1' and is_destroyed_l4(23)='0') then
r<=r_brick(23);
g<=g_brick(23);
b<=b_brick(23);
elsif(draw_l4(22)='1' and is_destroyed_l4(22)='0') then
r<=r_brick(22);
g<=g_brick(22);
b<=b_brick(22);
elsif(draw_l4(21)='1' and is_destroyed_l4(21)='0') then
r<=r_brick(21);
g<=g_brick(21);
b<=b_brick(21);
elsif(draw_l4(20)='1' and is_destroyed_l4(20)='0') then
r<=r_brick(20);
g<=g_brick(20);
b<=b_brick(20);
elsif(draw_l4(19)='1' and is_destroyed_l4(19)='0') then
r<=r_brick(19);
g<=g_brick(19);
b<=b_brick(19);
elsif(draw_l4(18)='1' and is_destroyed_l4(18)='0') then
r<=r_brick(18);
g<=g_brick(18);
b<=b_brick(18);
elsif(draw_l4(17)='1' and is_destroyed_l4(17)='0') then
r<=r_brick(17);
g<=g_brick(17);
b<=b_brick(17);
elsif(draw_l4(16)='1' and is_destroyed_l4(16)='0') then
r<=r_brick(16);
g<=g_brick(16);
b<=b_brick(16);
elsif(draw_l4(15)='1' and is_destroyed_l4(15)='0') then
r<=r_brick(15);
g<=g_brick(15);
b<=b_brick(15);
elsif(draw_l4(14)='1' and is_destroyed_l4(14)='0') then
r<=r_brick(14);
g<=g_brick(14);
b<=b_brick(14);
elsif(draw_l4(13)='1' and is_destroyed_l4(13)='0') then
r<=r_brick(13);
g<=g_brick(13);
b<=b_brick(13);
elsif(draw_l4(12)='1' and is_destroyed_l4(12)='0') then
r<=r_brick(12);
g<=g_brick(12);
b<=b_brick(12);
elsif(draw_l4(11)='1' and is_destroyed_l4(11)='0') then
r<=r_brick(11);
g<=g_brick(11);
b<=b_brick(11);
elsif(draw_l4(10)='1' and is_destroyed_l4(10)='0') then
r<=r_brick(10);
g<=g_brick(10);
b<=b_brick(10);
elsif(draw_l4(9)='1' and is_destroyed_l4(9)='0') then
r<=r_brick(9);
g<=g_brick(9);
b<=b_brick(9);
elsif(draw_l4(8)='1' and is_destroyed_l4(8)='0') then
r<=r_brick(8);
g<=g_brick(8);
b<=b_brick(8);
elsif(draw_l5(71)='1' and is_destroyed_l5(71)='0') then--display bricks of level5
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l5(70)='1' and is_destroyed_l5(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l5(69)='1' and is_destroyed_l5(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l5(68)='1' and is_destroyed_l5(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l5(67)='1' and is_destroyed_l5(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l5(66)='1' and is_destroyed_l5(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l5(65)='1' and is_destroyed_l5(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l5(64)='1' and is_destroyed_l5(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l5(63)='1' and is_destroyed_l5(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l5(62)='1' and is_destroyed_l5(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l5(61)='1' and is_destroyed_l5(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l5(60)='1' and is_destroyed_l5(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l5(59)='1' and is_destroyed_l5(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l5(58)='1' and is_destroyed_l5(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l5(57)='1' and is_destroyed_l5(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l5(56)='1' and is_destroyed_l5(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l5(55)='1' and is_destroyed_l5(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l5(54)='1' and is_destroyed_l5(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l5(53)='1' and is_destroyed_l5(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l5(52)='1' and is_destroyed_l5(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l5(51)='1' and is_destroyed_l5(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l5(50)='1' and is_destroyed_l5(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l5(49)='1' and is_destroyed_l5(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l5(48)='1' and is_destroyed_l5(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l5(47)='1' and is_destroyed_l5(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l5(46)='1' and is_destroyed_l5(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l5(45)='1' and is_destroyed_l5(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l5(44)='1' and is_destroyed_l5(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l5(43)='1' and is_destroyed_l5(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l5(42)='1' and is_destroyed_l5(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l5(41)='1' and is_destroyed_l5(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l5(40)='1' and is_destroyed_l5(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l5(39)='1' and is_destroyed_l5(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l5(38)='1' and is_destroyed_l5(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l5(37)='1' and is_destroyed_l5(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l5(36)='1' and is_destroyed_l5(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
else
r<="0000"; --if nothing then black screen
g<="0000";
b<="0000";
end if;
else
r<="0000"; --make rgb 0 for period of fp,bp and sync duration
g<="0000";
b<="0000";
end if;
if(hpos<800) then
hpos<=hpos+1; --increment the horizontal pixel
else
hpos<=1; --if entire line covered then reset
if(vpos<525) then
vpos<=vpos+1; --increment the vertical pixel
else
vpos<=1; --if entire screen covered then reset
--1 means right direction or downwards
--0 means left direction or upwards
if(ball_x=5) then
ball_x_vel<='1'; --if reached left edge then change direction to right
elsif(ball_x=623) then
ball_x_vel<='0'; --if reached right end then change direction to left
else
null;
end if;
if(ball_y=2) then
ball_y_vel<='1'; --if reached top then reverse direction
elsif(ball_y=448 and (ball_x>=bat_x-14 and ball_x<=bat_x+51)) then --if reached bat height then check if hit the bat and then reverse direction else don't change
ball_y_vel<='0';
else
null;
end if;
if(is_destroyed_l1(71)='0')then--detect collision for ball and bricks of level1
if(coll_x_l1(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(71)<='1';
end if;
if(coll_y_l1(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(71)<='1';
end if;
end if;
if(is_destroyed_l1(70)='0')then
if(coll_x_l1(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(70)<='1';
end if;
if(coll_y_l1(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(70)<='1';
end if;
end if;
if(is_destroyed_l1(69)='0')then
if(coll_x_l1(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(69)<='1';
end if;
if(coll_y_l1(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(69)<='1';
end if;
end if;
if(is_destroyed_l1(68)='0')then
if(coll_x_l1(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(68)<='1';
end if;
if(coll_y_l1(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(68)<='1';
end if;
end if;
if(is_destroyed_l1(67)='0')then
if(coll_x_l1(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(67)<='1';
end if;
if(coll_y_l1(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(67)<='1';
end if;
end if;
if(is_destroyed_l1(66)='0')then
if(coll_x_l1(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(66)<='1';
end if;
if(coll_y_l1(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(66)<='1';
end if;
end if;
if(is_destroyed_l1(65)='0')then
if(coll_x_l1(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(65)<='1';
end if;
if(coll_y_l1(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(65)<='1';
end if;
end if;
if(is_destroyed_l1(64)='0')then
if(coll_x_l1(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(64)<='1';
end if;
if(coll_y_l1(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(64)<='1';
end if;
end if;
if(is_destroyed_l1(63)='0')then
if(coll_x_l1(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(63)<='1';
end if;
if(coll_y_l1(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(63)<='1';
end if;
end if;
if(is_destroyed_l1(62)='0')then
if(coll_x_l1(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(62)<='1';
end if;
if(coll_y_l1(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(62)<='1';
end if;
end if;
if(is_destroyed_l1(61)='0')then
if(coll_x_l1(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(61)<='1';
end if;
if(coll_y_l1(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(61)<='1';
end if;
end if;
if(is_destroyed_l1(60)='0')then
if(coll_x_l1(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(60)<='1';
end if;
if(coll_y_l1(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(60)<='1';
end if;
end if;
if(is_destroyed_l1(59)='0')then
if(coll_x_l1(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(59)<='1';
end if;
if(coll_y_l1(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(59)<='1';
end if;
end if;
if(is_destroyed_l1(58)='0')then
if(coll_x_l1(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(58)<='1';
end if;
if(coll_y_l1(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(58)<='1';
end if;
end if;
if(is_destroyed_l1(57)='0')then
if(coll_x_l1(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(57)<='1';
end if;
if(coll_y_l1(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(57)<='1';
end if;
end if;
if(is_destroyed_l1(56)='0')then
if(coll_x_l1(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(56)<='1';
end if;
if(coll_y_l1(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(56)<='1';
end if;
end if;
if(is_destroyed_l1(55)='0')then
if(coll_x_l1(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(55)<='1';
end if;
if(coll_y_l1(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(55)<='1';
end if;
end if;
if(is_destroyed_l1(54)='0')then
if(coll_x_l1(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(54)<='1';
end if;
if(coll_y_l1(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(54)<='1';
end if;
end if;
if(is_destroyed_l1(53)='0')then
if(coll_x_l1(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(53)<='1';
end if;
if(coll_y_l1(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(53)<='1';
end if;
end if;
if(is_destroyed_l1(52)='0')then
if(coll_x_l1(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(52)<='1';
end if;
if(coll_y_l1(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(52)<='1';
end if;
end if;
if(is_destroyed_l1(51)='0')then
if(coll_x_l1(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(51)<='1';
end if;
if(coll_y_l1(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(51)<='1';
end if;
end if;
if(is_destroyed_l1(50)='0')then
if(coll_x_l1(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(50)<='1';
end if;
if(coll_y_l1(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(50)<='1';
end if;
end if;
if(is_destroyed_l1(49)='0')then
if(coll_x_l1(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(49)<='1';
end if;
if(coll_y_l1(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(49)<='1';
end if;
end if;
if(is_destroyed_l1(48)='0')then
if(coll_x_l1(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(48)<='1';
end if;
if(coll_y_l1(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(48)<='1';
end if;
end if;
if(is_destroyed_l1(47)='0')then
if(coll_x_l1(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(47)<='1';
end if;
if(coll_y_l1(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(47)<='1';
end if;
end if;
if(is_destroyed_l1(46)='0')then
if(coll_x_l1(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(46)<='1';
end if;
if(coll_y_l1(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(46)<='1';
end if;
end if;
if(is_destroyed_l1(45)='0')then
if(coll_x_l1(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(45)<='1';
end if;
if(coll_y_l1(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(45)<='1';
end if;
end if;
if(is_destroyed_l1(44)='0')then
if(coll_x_l1(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(44)<='1';
end if;
if(coll_y_l1(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(44)<='1';
end if;
end if;
if(is_destroyed_l1(43)='0')then
if(coll_x_l1(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(43)<='1';
end if;
if(coll_y_l1(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(43)<='1';
end if;
end if;
if(is_destroyed_l1(42)='0')then
if(coll_x_l1(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(42)<='1';
end if;
if(coll_y_l1(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(42)<='1';
end if;
end if;
if(is_destroyed_l1(41)='0')then
if(coll_x_l1(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(41)<='1';
end if;
if(coll_y_l1(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(41)<='1';
end if;
end if;
if(is_destroyed_l1(40)='0')then
if(coll_x_l1(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(40)<='1';
end if;
if(coll_y_l1(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(40)<='1';
end if;
end if;
if(is_destroyed_l1(39)='0')then
if(coll_x_l1(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(39)<='1';
end if;
if(coll_y_l1(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(39)<='1';
end if;
end if;
if(is_destroyed_l1(38)='0')then
if(coll_x_l1(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(38)<='1';
end if;
if(coll_y_l1(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(38)<='1';
end if;
end if;
if(is_destroyed_l1(37)='0')then
if(coll_x_l1(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(37)<='1';
end if;
if(coll_y_l1(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(37)<='1';
end if;
end if;
if(is_destroyed_l1(36)='0')then
if(coll_x_l1(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(36)<='1';
end if;
if(coll_y_l1(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(36)<='1';
end if;
end if;
if(is_destroyed_l1(35)='0')then
if(coll_x_l1(35)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(35)<='1';
end if;
if(coll_y_l1(35)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(35)<='1';
end if;
end if;
if(is_destroyed_l1(34)='0')then
if(coll_x_l1(34)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(34)<='1';
end if;
if(coll_y_l1(34)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(34)<='1';
end if;
end if;
if(is_destroyed_l1(33)='0')then
if(coll_x_l1(33)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(33)<='1';
end if;
if(coll_y_l1(33)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(33)<='1';
end if;
end if;
if(is_destroyed_l1(32)='0')then
if(coll_x_l1(32)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(32)<='1';
end if;
if(coll_y_l1(32)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(32)<='1';
end if;
end if;
if(is_destroyed_l1(31)='0')then
if(coll_x_l1(31)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(31)<='1';
end if;
if(coll_y_l1(31)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(31)<='1';
end if;
end if;
if(is_destroyed_l1(30)='0')then
if(coll_x_l1(30)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(30)<='1';
end if;
if(coll_y_l1(30)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(30)<='1';
end if;
end if;
if(is_destroyed_l1(29)='0')then
if(coll_x_l1(29)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(29)<='1';
end if;
if(coll_y_l1(29)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(29)<='1';
end if;
end if;
if(is_destroyed_l1(28)='0')then
if(coll_x_l1(28)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(28)<='1';
end if;
if(coll_y_l1(28)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(28)<='1';
end if;
end if;
if(is_destroyed_l1(27)='0')then
if(coll_x_l1(27)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(27)<='1';
end if;
if(coll_y_l1(27)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(27)<='1';
end if;
end if;
if(is_destroyed_l1(26)='0')then
if(coll_x_l1(26)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(26)<='1';
end if;
if(coll_y_l1(26)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(26)<='1';
end if;
end if;
if(is_destroyed_l1(25)='0')then
if(coll_x_l1(25)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(25)<='1';
end if;
if(coll_y_l1(25)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(25)<='1';
end if;
end if;
if(is_destroyed_l1(24)='0')then
if(coll_x_l1(24)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(24)<='1';
end if;
if(coll_y_l1(24)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(24)<='1';
end if;
end if;
if(is_destroyed_l1(23)='0')then
if(coll_x_l1(23)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(23)<='1';
end if;
if(coll_y_l1(23)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(23)<='1';
end if;
end if;
if(is_destroyed_l1(22)='0')then
if(coll_x_l1(22)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(22)<='1';
end if;
if(coll_y_l1(22)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(22)<='1';
end if;
end if;
if(is_destroyed_l1(21)='0')then
if(coll_x_l1(21)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(21)<='1';
end if;
if(coll_y_l1(21)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(21)<='1';
end if;
end if;
if(is_destroyed_l1(20)='0')then
if(coll_x_l1(20)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(20)<='1';
end if;
if(coll_y_l1(20)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(20)<='1';
end if;
end if;
if(is_destroyed_l1(19)='0')then
if(coll_x_l1(19)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(19)<='1';
end if;
if(coll_y_l1(19)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(19)<='1';
end if;
end if;
if(is_destroyed_l1(18)='0')then
if(coll_x_l1(18)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(18)<='1';
end if;
if(coll_y_l1(18)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(18)<='1';
end if;
end if;
if(is_destroyed_l1(17)='0')then
if(coll_x_l1(17)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(17)<='1';
end if;
if(coll_y_l1(17)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(17)<='1';
end if;
end if;
if(is_destroyed_l1(16)='0')then
if(coll_x_l1(16)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(16)<='1';
end if;
if(coll_y_l1(16)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(16)<='1';
end if;
end if;
if(is_destroyed_l1(15)='0')then
if(coll_x_l1(15)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(15)<='1';
end if;
if(coll_y_l1(15)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(15)<='1';
end if;
end if;
if(is_destroyed_l1(14)='0')then
if(coll_x_l1(14)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(14)<='1';
end if;
if(coll_y_l1(14)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(14)<='1';
end if;
end if;
if(is_destroyed_l1(13)='0')then
if(coll_x_l1(13)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(13)<='1';
end if;
if(coll_y_l1(13)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(13)<='1';
end if;
end if;
if(is_destroyed_l1(12)='0')then
if(coll_x_l1(12)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(12)<='1';
end if;
if(coll_y_l1(12)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(12)<='1';
end if;
end if;
if(is_destroyed_l1(11)='0')then
if(coll_x_l1(11)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(11)<='1';
end if;
if(coll_y_l1(11)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(11)<='1';
end if;
end if;
if(is_destroyed_l1(10)='0')then
if(coll_x_l1(10)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(10)<='1';
end if;
if(coll_y_l1(10)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(10)<='1';
end if;
end if;
if(is_destroyed_l1(9)='0')then
if(coll_x_l1(9)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(9)<='1';
end if;
if(coll_y_l1(9)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(9)<='1';
end if;
end if;
if(is_destroyed_l1(8)='0')then
if(coll_x_l1(8)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(8)<='1';
end if;
if(coll_y_l1(8)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(8)<='1';
end if;
end if;
if(is_destroyed_l1(7)='0')then
if(coll_x_l1(7)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(7)<='1';
end if;
if(coll_y_l1(7)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(7)<='1';
end if;
end if;
if(is_destroyed_l1(6)='0')then
if(coll_x_l1(6)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(6)<='1';
end if;
if(coll_y_l1(6)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(6)<='1';
end if;
end if;
if(is_destroyed_l1(5)='0')then
if(coll_x_l1(5)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(5)<='1';
end if;
if(coll_y_l1(5)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(5)<='1';
end if;
end if;
if(is_destroyed_l1(4)='0')then
if(coll_x_l1(4)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(4)<='1';
end if;
if(coll_y_l1(4)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(4)<='1';
end if;
end if;
if(is_destroyed_l1(3)='0')then
if(coll_x_l1(3)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(3)<='1';
end if;
if(coll_y_l1(3)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(3)<='1';
end if;
end if;
if(is_destroyed_l1(2)='0')then
if(coll_x_l1(2)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(2)<='1';
end if;
if(coll_y_l1(2)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(2)<='1';
end if;
end if;
if(is_destroyed_l1(1)='0')then
if(coll_x_l1(1)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(1)<='1';
end if;
if(coll_y_l1(1)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(1)<='1';
end if;
end if;
if(is_destroyed_l1(0)='0')then
if(coll_x_l1(0)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(0)<='1';
end if;
if(coll_y_l1(0)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(0)<='1';
end if;
end if;
if(is_destroyed_l2(71)='0')then--detect collision for ball and bricks of level2
if(coll_x_l2(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(71)<='1';
end if;
if(coll_y_l2(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(71)<='1';
end if;
end if;
if(is_destroyed_l2(70)='0')then
if(coll_x_l2(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(70)<='1';
end if;
if(coll_y_l2(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(70)<='1';
end if;
end if;
if(is_destroyed_l2(69)='0')then
if(coll_x_l2(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(69)<='1';
end if;
if(coll_y_l2(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(69)<='1';
end if;
end if;
if(is_destroyed_l2(68)='0')then
if(coll_x_l2(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(68)<='1';
end if;
if(coll_y_l2(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(68)<='1';
end if;
end if;
if(is_destroyed_l2(67)='0')then
if(coll_x_l2(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(67)<='1';
end if;
if(coll_y_l2(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(67)<='1';
end if;
end if;
if(is_destroyed_l2(66)='0')then
if(coll_x_l2(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(66)<='1';
end if;
if(coll_y_l2(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(66)<='1';
end if;
end if;
if(is_destroyed_l2(65)='0')then
if(coll_x_l2(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(65)<='1';
end if;
if(coll_y_l2(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(65)<='1';
end if;
end if;
if(is_destroyed_l2(64)='0')then
if(coll_x_l2(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(64)<='1';
end if;
if(coll_y_l2(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(64)<='1';
end if;
end if;
if(is_destroyed_l2(63)='0')then
if(coll_x_l2(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(63)<='1';
end if;
if(coll_y_l2(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(63)<='1';
end if;
end if;
if(is_destroyed_l2(62)='0')then
if(coll_x_l2(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(62)<='1';
end if;
if(coll_y_l2(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(62)<='1';
end if;
end if;
if(is_destroyed_l2(61)='0')then
if(coll_x_l2(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(61)<='1';
end if;
if(coll_y_l2(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(61)<='1';
end if;
end if;
if(is_destroyed_l2(60)='0')then
if(coll_x_l2(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(60)<='1';
end if;
if(coll_y_l2(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(60)<='1';
end if;
end if;
if(is_destroyed_l2(59)='0')then
if(coll_x_l2(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(59)<='1';
end if;
if(coll_y_l2(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(59)<='1';
end if;
end if;
if(is_destroyed_l2(58)='0')then
if(coll_x_l2(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(58)<='1';
end if;
if(coll_y_l2(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(58)<='1';
end if;
end if;
if(is_destroyed_l2(57)='0')then
if(coll_x_l2(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(57)<='1';
end if;
if(coll_y_l2(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(57)<='1';
end if;
end if;
if(is_destroyed_l2(56)='0')then
if(coll_x_l2(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(56)<='1';
end if;
if(coll_y_l2(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(56)<='1';
end if;
end if;
if(is_destroyed_l2(55)='0')then
if(coll_x_l2(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(55)<='1';
end if;
if(coll_y_l2(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(55)<='1';
end if;
end if;
if(is_destroyed_l2(54)='0')then
if(coll_x_l2(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(54)<='1';
end if;
if(coll_y_l2(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(54)<='1';
end if;
end if;
if(is_destroyed_l2(53)='0')then
if(coll_x_l2(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(53)<='1';
end if;
if(coll_y_l2(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(53)<='1';
end if;
end if;
if(is_destroyed_l2(52)='0')then
if(coll_x_l2(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(52)<='1';
end if;
if(coll_y_l2(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(52)<='1';
end if;
end if;
if(is_destroyed_l2(51)='0')then
if(coll_x_l2(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(51)<='1';
end if;
if(coll_y_l2(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(51)<='1';
end if;
end if;
if(is_destroyed_l2(50)='0')then
if(coll_x_l2(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(50)<='1';
end if;
if(coll_y_l2(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(50)<='1';
end if;
end if;
if(is_destroyed_l2(49)='0')then
if(coll_x_l2(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(49)<='1';
end if;
if(coll_y_l2(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(49)<='1';
end if;
end if;
if(is_destroyed_l2(48)='0')then
if(coll_x_l2(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(48)<='1';
end if;
if(coll_y_l2(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(48)<='1';
end if;
end if;
if(is_destroyed_l2(47)='0')then
if(coll_x_l2(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(47)<='1';
end if;
if(coll_y_l2(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(47)<='1';
end if;
end if;
if(is_destroyed_l2(46)='0')then
if(coll_x_l2(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(46)<='1';
end if;
if(coll_y_l2(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(46)<='1';
end if;
end if;
if(is_destroyed_l2(45)='0')then
if(coll_x_l2(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(45)<='1';
end if;
if(coll_y_l2(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(45)<='1';
end if;
end if;
if(is_destroyed_l2(44)='0')then
if(coll_x_l2(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(44)<='1';
end if;
if(coll_y_l2(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(44)<='1';
end if;
end if;
if(is_destroyed_l3(71)='0')then--detect collision for ball and bricks of level3
if(coll_x_l3(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(71)<='1';
end if;
if(coll_y_l3(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(71)<='1';
end if;
end if;
if(is_destroyed_l3(70)='0')then
if(coll_x_l3(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(70)<='1';
end if;
if(coll_y_l3(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(70)<='1';
end if;
end if;
if(is_destroyed_l3(69)='0')then
if(coll_x_l3(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(69)<='1';
end if;
if(coll_y_l3(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(69)<='1';
end if;
end if;
if(is_destroyed_l3(68)='0')then
if(coll_x_l3(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(68)<='1';
end if;
if(coll_y_l3(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(68)<='1';
end if;
end if;
if(is_destroyed_l3(67)='0')then
if(coll_x_l3(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(67)<='1';
end if;
if(coll_y_l3(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(67)<='1';
end if;
end if;
if(is_destroyed_l3(66)='0')then
if(coll_x_l3(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(66)<='1';
end if;
if(coll_y_l3(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(66)<='1';
end if;
end if;
if(is_destroyed_l3(65)='0')then
if(coll_x_l3(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(65)<='1';
end if;
if(coll_y_l3(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(65)<='1';
end if;
end if;
if(is_destroyed_l3(64)='0')then
if(coll_x_l3(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(64)<='1';
end if;
if(coll_y_l3(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(64)<='1';
end if;
end if;
if(is_destroyed_l3(63)='0')then
if(coll_x_l3(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(63)<='1';
end if;
if(coll_y_l3(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(63)<='1';
end if;
end if;
if(is_destroyed_l3(62)='0')then
if(coll_x_l3(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(62)<='1';
end if;
if(coll_y_l3(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(62)<='1';
end if;
end if;
if(is_destroyed_l3(61)='0')then
if(coll_x_l3(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(61)<='1';
end if;
if(coll_y_l3(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(61)<='1';
end if;
end if;
if(is_destroyed_l3(60)='0')then
if(coll_x_l3(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(60)<='1';
end if;
if(coll_y_l3(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(60)<='1';
end if;
end if;
if(is_destroyed_l3(59)='0')then
if(coll_x_l3(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(59)<='1';
end if;
if(coll_y_l3(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(59)<='1';
end if;
end if;
if(is_destroyed_l3(58)='0')then
if(coll_x_l3(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(58)<='1';
end if;
if(coll_y_l3(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(58)<='1';
end if;
end if;
if(is_destroyed_l3(57)='0')then
if(coll_x_l3(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(57)<='1';
end if;
if(coll_y_l3(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(57)<='1';
end if;
end if;
if(is_destroyed_l3(56)='0')then
if(coll_x_l3(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(56)<='1';
end if;
if(coll_y_l3(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(56)<='1';
end if;
end if;
if(is_destroyed_l3(55)='0')then
if(coll_x_l3(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(55)<='1';
end if;
if(coll_y_l3(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(55)<='1';
end if;
end if;
if(is_destroyed_l3(54)='0')then
if(coll_x_l3(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(54)<='1';
end if;
if(coll_y_l3(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(54)<='1';
end if;
end if;
if(is_destroyed_l3(53)='0')then
if(coll_x_l3(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(53)<='1';
end if;
if(coll_y_l3(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(53)<='1';
end if;
end if;
if(is_destroyed_l3(52)='0')then
if(coll_x_l3(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(52)<='1';
end if;
if(coll_y_l3(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(52)<='1';
end if;
end if;
if(is_destroyed_l3(51)='0')then
if(coll_x_l3(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(51)<='1';
end if;
if(coll_y_l3(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(51)<='1';
end if;
end if;
if(is_destroyed_l3(50)='0')then
if(coll_x_l3(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(50)<='1';
end if;
if(coll_y_l3(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(50)<='1';
end if;
end if;
if(is_destroyed_l3(49)='0')then
if(coll_x_l3(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(49)<='1';
end if;
if(coll_y_l3(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(49)<='1';
end if;
end if;
if(is_destroyed_l3(48)='0')then
if(coll_x_l3(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(48)<='1';
end if;
if(coll_y_l3(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(48)<='1';
end if;
end if;
if(is_destroyed_l3(47)='0')then
if(coll_x_l3(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(47)<='1';
end if;
if(coll_y_l3(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(47)<='1';
end if;
end if;
if(is_destroyed_l3(46)='0')then
if(coll_x_l3(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(46)<='1';
end if;
if(coll_y_l3(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(46)<='1';
end if;
end if;
if(is_destroyed_l3(45)='0')then
if(coll_x_l3(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(45)<='1';
end if;
if(coll_y_l3(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(45)<='1';
end if;
end if;
if(is_destroyed_l3(44)='0')then
if(coll_x_l3(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(44)<='1';
end if;
if(coll_y_l3(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(44)<='1';
end if;
end if;
if(is_destroyed_l3(43)='0')then
if(coll_x_l3(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(43)<='1';
end if;
if(coll_y_l3(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(43)<='1';
end if;
end if;
if(is_destroyed_l3(42)='0')then
if(coll_x_l3(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(42)<='1';
end if;
if(coll_y_l3(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(42)<='1';
end if;
end if;
if(is_destroyed_l3(41)='0')then
if(coll_x_l3(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(41)<='1';
end if;
if(coll_y_l3(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(41)<='1';
end if;
end if;
if(is_destroyed_l3(40)='0')then
if(coll_x_l3(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(40)<='1';
end if;
if(coll_y_l3(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(40)<='1';
end if;
end if;
if(is_destroyed_l3(39)='0')then
if(coll_x_l3(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(39)<='1';
end if;
if(coll_y_l3(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(39)<='1';
end if;
end if;
if(is_destroyed_l3(38)='0')then
if(coll_x_l3(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(38)<='1';
end if;
if(coll_y_l3(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(38)<='1';
end if;
end if;
if(is_destroyed_l3(37)='0')then
if(coll_x_l3(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(37)<='1';
end if;
if(coll_y_l3(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(37)<='1';
end if;
end if;
if(is_destroyed_l3(36)='0')then
if(coll_x_l3(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(36)<='1';
end if;
if(coll_y_l3(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(36)<='1';
end if;
end if;
if(is_destroyed_l3(35)='0')then
if(coll_x_l3(35)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(35)<='1';
end if;
if(coll_y_l3(35)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(35)<='1';
end if;
end if;
if(is_destroyed_l3(34)='0')then
if(coll_x_l3(34)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(34)<='1';
end if;
if(coll_y_l3(34)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(34)<='1';
end if;
end if;
if(is_destroyed_l3(33)='0')then
if(coll_x_l3(33)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(33)<='1';
end if;
if(coll_y_l3(33)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(33)<='1';
end if;
end if;
if(is_destroyed_l3(32)='0')then
if(coll_x_l3(32)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(32)<='1';
end if;
if(coll_y_l3(32)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(32)<='1';
end if;
end if;
if(is_destroyed_l3(31)='0')then
if(coll_x_l3(31)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(31)<='1';
end if;
if(coll_y_l3(31)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(31)<='1';
end if;
end if;
if(is_destroyed_l3(30)='0')then
if(coll_x_l3(30)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(30)<='1';
end if;
if(coll_y_l3(30)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(30)<='1';
end if;
end if;
if(is_destroyed_l3(29)='0')then
if(coll_x_l3(29)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(29)<='1';
end if;
if(coll_y_l3(29)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(29)<='1';
end if;
end if;
if(is_destroyed_l3(28)='0')then
if(coll_x_l3(28)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(28)<='1';
end if;
if(coll_y_l3(28)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(28)<='1';
end if;
end if;
if(is_destroyed_l3(27)='0')then
if(coll_x_l3(27)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(27)<='1';
end if;
if(coll_y_l3(27)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(27)<='1';
end if;
end if;
if(is_destroyed_l3(26)='0')then
if(coll_x_l3(26)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(26)<='1';
end if;
if(coll_y_l3(26)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(26)<='1';
end if;
end if;
if(is_destroyed_l3(25)='0')then
if(coll_x_l3(25)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(25)<='1';
end if;
if(coll_y_l3(25)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(25)<='1';
end if;
end if;
if(is_destroyed_l3(24)='0')then
if(coll_x_l3(24)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(24)<='1';
end if;
if(coll_y_l3(24)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(24)<='1';
end if;
end if;
if(is_destroyed_l3(23)='0')then
if(coll_x_l3(23)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(23)<='1';
end if;
if(coll_y_l3(23)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(23)<='1';
end if;
end if;
if(is_destroyed_l3(22)='0')then
if(coll_x_l3(22)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(22)<='1';
end if;
if(coll_y_l3(22)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(22)<='1';
end if;
end if;
if(is_destroyed_l3(21)='0')then
if(coll_x_l3(21)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(21)<='1';
end if;
if(coll_y_l3(21)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(21)<='1';
end if;
end if;
if(is_destroyed_l3(20)='0')then
if(coll_x_l3(20)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(20)<='1';
end if;
if(coll_y_l3(20)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(20)<='1';
end if;
end if;
if(is_destroyed_l3(19)='0')then
if(coll_x_l3(19)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(19)<='1';
end if;
if(coll_y_l3(19)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(19)<='1';
end if;
end if;
if(is_destroyed_l3(18)='0')then
if(coll_x_l3(18)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(18)<='1';
end if;
if(coll_y_l3(18)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(18)<='1';
end if;
end if;
if(is_destroyed_l3(17)='0')then
if(coll_x_l3(17)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(17)<='1';
end if;
if(coll_y_l3(17)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(17)<='1';
end if;
end if;
if(is_destroyed_l3(16)='0')then
if(coll_x_l3(16)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(16)<='1';
end if;
if(coll_y_l3(16)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(16)<='1';
end if;
end if;
if(is_destroyed_l3(15)='0')then
if(coll_x_l3(15)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(15)<='1';
end if;
if(coll_y_l3(15)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(15)<='1';
end if;
end if;
if(is_destroyed_l3(14)='0')then
if(coll_x_l3(14)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(14)<='1';
end if;
if(coll_y_l3(14)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(14)<='1';
end if;
end if;
if(is_destroyed_l3(13)='0')then
if(coll_x_l3(13)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(13)<='1';
end if;
if(coll_y_l3(13)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(13)<='1';
end if;
end if;
if(is_destroyed_l3(12)='0')then
if(coll_x_l3(12)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(12)<='1';
end if;
if(coll_y_l3(12)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(12)<='1';
end if;
end if;
if(is_destroyed_l3(11)='0')then
if(coll_x_l3(11)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(11)<='1';
end if;
if(coll_y_l3(11)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(11)<='1';
end if;
end if;
if(is_destroyed_l3(10)='0')then
if(coll_x_l3(10)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(10)<='1';
end if;
if(coll_y_l3(10)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(10)<='1';
end if;
end if;
if(is_destroyed_l3(9)='0')then
if(coll_x_l3(9)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(9)<='1';
end if;
if(coll_y_l3(9)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(9)<='1';
end if;
end if;
if(is_destroyed_l3(8)='0')then
if(coll_x_l3(8)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(8)<='1';
end if;
if(coll_y_l3(8)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(8)<='1';
end if;
end if;
if(is_destroyed_l3(7)='0')then
if(coll_x_l3(7)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(7)<='1';
end if;
if(coll_y_l3(7)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(7)<='1';
end if;
end if;
if(is_destroyed_l3(6)='0')then
if(coll_x_l3(6)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(6)<='1';
end if;
if(coll_y_l3(6)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(6)<='1';
end if;
end if;
if(is_destroyed_l3(5)='0')then
if(coll_x_l3(5)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(5)<='1';
end if;
if(coll_y_l3(5)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(5)<='1';
end if;
end if;
if(is_destroyed_l3(4)='0')then
if(coll_x_l3(4)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(4)<='1';
end if;
if(coll_y_l3(4)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(4)<='1';
end if;
end if;
if(is_destroyed_l3(3)='0')then
if(coll_x_l3(3)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(3)<='1';
end if;
if(coll_y_l3(3)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(3)<='1';
end if;
end if;
if(is_destroyed_l3(2)='0')then
if(coll_x_l3(2)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(2)<='1';
end if;
if(coll_y_l3(2)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(2)<='1';
end if;
end if;
if(is_destroyed_l3(1)='0')then
if(coll_x_l3(1)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(1)<='1';
end if;
if(coll_y_l3(1)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(1)<='1';
end if;
end if;
if(is_destroyed_l3(0)='0')then
if(coll_x_l3(0)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(0)<='1';
end if;
if(coll_y_l3(0)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(0)<='1';
end if;
end if;
if(is_destroyed_l4(71)='0')then--detect collision for ball and bricks of level4
if(coll_x_l4(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(71)<='1';
end if;
if(coll_y_l4(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(71)<='1';
end if;
end if;
if(is_destroyed_l4(70)='0')then
if(coll_x_l4(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(70)<='1';
end if;
if(coll_y_l4(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(70)<='1';
end if;
end if;
if(is_destroyed_l4(69)='0')then
if(coll_x_l4(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(69)<='1';
end if;
if(coll_y_l4(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(69)<='1';
end if;
end if;
if(is_destroyed_l4(68)='0')then
if(coll_x_l4(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(68)<='1';
end if;
if(coll_y_l4(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(68)<='1';
end if;
end if;
if(is_destroyed_l4(67)='0')then
if(coll_x_l4(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(67)<='1';
end if;
if(coll_y_l4(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(67)<='1';
end if;
end if;
if(is_destroyed_l4(66)='0')then
if(coll_x_l4(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(66)<='1';
end if;
if(coll_y_l4(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(66)<='1';
end if;
end if;
if(is_destroyed_l4(65)='0')then
if(coll_x_l4(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(65)<='1';
end if;
if(coll_y_l4(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(65)<='1';
end if;
end if;
if(is_destroyed_l4(64)='0')then
if(coll_x_l4(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(64)<='1';
end if;
if(coll_y_l4(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(64)<='1';
end if;
end if;
if(is_destroyed_l4(63)='0')then
if(coll_x_l4(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(63)<='1';
end if;
if(coll_y_l4(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(63)<='1';
end if;
end if;
if(is_destroyed_l4(62)='0')then
if(coll_x_l4(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(62)<='1';
end if;
if(coll_y_l4(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(62)<='1';
end if;
end if;
if(is_destroyed_l4(61)='0')then
if(coll_x_l4(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(61)<='1';
end if;
if(coll_y_l4(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(61)<='1';
end if;
end if;
if(is_destroyed_l4(60)='0')then
if(coll_x_l4(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(60)<='1';
end if;
if(coll_y_l4(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(60)<='1';
end if;
end if;
if(is_destroyed_l4(59)='0')then
if(coll_x_l4(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(59)<='1';
end if;
if(coll_y_l4(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(59)<='1';
end if;
end if;
if(is_destroyed_l4(58)='0')then
if(coll_x_l4(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(58)<='1';
end if;
if(coll_y_l4(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(58)<='1';
end if;
end if;
if(is_destroyed_l4(57)='0')then
if(coll_x_l4(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(57)<='1';
end if;
if(coll_y_l4(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(57)<='1';
end if;
end if;
if(is_destroyed_l4(56)='0')then
if(coll_x_l4(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(56)<='1';
end if;
if(coll_y_l4(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(56)<='1';
end if;
end if;
if(is_destroyed_l4(55)='0')then
if(coll_x_l4(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(55)<='1';
end if;
if(coll_y_l4(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(55)<='1';
end if;
end if;
if(is_destroyed_l4(54)='0')then
if(coll_x_l4(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(54)<='1';
end if;
if(coll_y_l4(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(54)<='1';
end if;
end if;
if(is_destroyed_l4(53)='0')then
if(coll_x_l4(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(53)<='1';
end if;
if(coll_y_l4(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(53)<='1';
end if;
end if;
if(is_destroyed_l4(52)='0')then
if(coll_x_l4(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(52)<='1';
end if;
if(coll_y_l4(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(52)<='1';
end if;
end if;
if(is_destroyed_l4(51)='0')then
if(coll_x_l4(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(51)<='1';
end if;
if(coll_y_l4(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(51)<='1';
end if;
end if;
if(is_destroyed_l4(50)='0')then
if(coll_x_l4(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(50)<='1';
end if;
if(coll_y_l4(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(50)<='1';
end if;
end if;
if(is_destroyed_l4(49)='0')then
if(coll_x_l4(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(49)<='1';
end if;
if(coll_y_l4(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(49)<='1';
end if;
end if;
if(is_destroyed_l4(48)='0')then
if(coll_x_l4(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(48)<='1';
end if;
if(coll_y_l4(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(48)<='1';
end if;
end if;
if(is_destroyed_l4(47)='0')then
if(coll_x_l4(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(47)<='1';
end if;
if(coll_y_l4(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(47)<='1';
end if;
end if;
if(is_destroyed_l4(46)='0')then
if(coll_x_l4(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(46)<='1';
end if;
if(coll_y_l4(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(46)<='1';
end if;
end if;
if(is_destroyed_l4(45)='0')then
if(coll_x_l4(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(45)<='1';
end if;
if(coll_y_l4(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(45)<='1';
end if;
end if;
if(is_destroyed_l4(44)='0')then
if(coll_x_l4(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(44)<='1';
end if;
if(coll_y_l4(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(44)<='1';
end if;
end if;
if(is_destroyed_l4(43)='0')then
if(coll_x_l4(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(43)<='1';
end if;
if(coll_y_l4(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(43)<='1';
end if;
end if;
if(is_destroyed_l4(42)='0')then
if(coll_x_l4(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(42)<='1';
end if;
if(coll_y_l4(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(42)<='1';
end if;
end if;
if(is_destroyed_l4(41)='0')then
if(coll_x_l4(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(41)<='1';
end if;
if(coll_y_l4(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(41)<='1';
end if;
end if;
if(is_destroyed_l4(40)='0')then
if(coll_x_l4(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(40)<='1';
end if;
if(coll_y_l4(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(40)<='1';
end if;
end if;
if(is_destroyed_l4(39)='0')then
if(coll_x_l4(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(39)<='1';
end if;
if(coll_y_l4(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(39)<='1';
end if;
end if;
if(is_destroyed_l4(38)='0')then
if(coll_x_l4(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(38)<='1';
end if;
if(coll_y_l4(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(38)<='1';
end if;
end if;
if(is_destroyed_l4(37)='0')then
if(coll_x_l4(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(37)<='1';
end if;
if(coll_y_l4(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(37)<='1';
end if;
end if;
if(is_destroyed_l4(36)='0')then
if(coll_x_l4(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(36)<='1';
end if;
if(coll_y_l4(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(36)<='1';
end if;
end if;
if(is_destroyed_l4(35)='0')then
if(coll_x_l4(35)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(35)<='1';
end if;
if(coll_y_l4(35)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(35)<='1';
end if;
end if;
if(is_destroyed_l4(34)='0')then
if(coll_x_l4(34)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(34)<='1';
end if;
if(coll_y_l4(34)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(34)<='1';
end if;
end if;
if(is_destroyed_l4(33)='0')then
if(coll_x_l4(33)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(33)<='1';
end if;
if(coll_y_l4(33)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(33)<='1';
end if;
end if;
if(is_destroyed_l4(32)='0')then
if(coll_x_l4(32)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(32)<='1';
end if;
if(coll_y_l4(32)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(32)<='1';
end if;
end if;
if(is_destroyed_l4(31)='0')then
if(coll_x_l4(31)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(31)<='1';
end if;
if(coll_y_l4(31)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(31)<='1';
end if;
end if;
if(is_destroyed_l4(30)='0')then
if(coll_x_l4(30)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(30)<='1';
end if;
if(coll_y_l4(30)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(30)<='1';
end if;
end if;
if(is_destroyed_l4(29)='0')then
if(coll_x_l4(29)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(29)<='1';
end if;
if(coll_y_l4(29)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(29)<='1';
end if;
end if;
if(is_destroyed_l4(28)='0')then
if(coll_x_l4(28)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(28)<='1';
end if;
if(coll_y_l4(28)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(28)<='1';
end if;
end if;
if(is_destroyed_l4(27)='0')then
if(coll_x_l4(27)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(27)<='1';
end if;
if(coll_y_l4(27)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(27)<='1';
end if;
end if;
if(is_destroyed_l4(26)='0')then
if(coll_x_l4(26)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(26)<='1';
end if;
if(coll_y_l4(26)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(26)<='1';
end if;
end if;
if(is_destroyed_l4(25)='0')then
if(coll_x_l4(25)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(25)<='1';
end if;
if(coll_y_l4(25)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(25)<='1';
end if;
end if;
if(is_destroyed_l4(24)='0')then
if(coll_x_l4(24)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(24)<='1';
end if;
if(coll_y_l4(24)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(24)<='1';
end if;
end if;
if(is_destroyed_l4(23)='0')then
if(coll_x_l4(23)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(23)<='1';
end if;
if(coll_y_l4(23)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(23)<='1';
end if;
end if;
if(is_destroyed_l4(22)='0')then
if(coll_x_l4(22)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(22)<='1';
end if;
if(coll_y_l4(22)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(22)<='1';
end if;
end if;
if(is_destroyed_l4(21)='0')then
if(coll_x_l4(21)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(21)<='1';
end if;
if(coll_y_l4(21)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(21)<='1';
end if;
end if;
if(is_destroyed_l4(20)='0')then
if(coll_x_l4(20)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(20)<='1';
end if;
if(coll_y_l4(20)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(20)<='1';
end if;
end if;
if(is_destroyed_l4(19)='0')then
if(coll_x_l4(19)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(19)<='1';
end if;
if(coll_y_l4(19)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(19)<='1';
end if;
end if;
if(is_destroyed_l4(18)='0')then
if(coll_x_l4(18)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(18)<='1';
end if;
if(coll_y_l4(18)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(18)<='1';
end if;
end if;
if(is_destroyed_l4(17)='0')then
if(coll_x_l4(17)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(17)<='1';
end if;
if(coll_y_l4(17)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(17)<='1';
end if;
end if;
if(is_destroyed_l4(16)='0')then
if(coll_x_l4(16)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(16)<='1';
end if;
if(coll_y_l4(16)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(16)<='1';
end if;
end if;
if(is_destroyed_l4(15)='0')then
if(coll_x_l4(15)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(15)<='1';
end if;
if(coll_y_l4(15)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(15)<='1';
end if;
end if;
if(is_destroyed_l4(14)='0')then
if(coll_x_l4(14)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(14)<='1';
end if;
if(coll_y_l4(14)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(14)<='1';
end if;
end if;
if(is_destroyed_l4(13)='0')then
if(coll_x_l4(13)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(13)<='1';
end if;
if(coll_y_l4(13)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(13)<='1';
end if;
end if;
if(is_destroyed_l4(12)='0')then
if(coll_x_l4(12)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(12)<='1';
end if;
if(coll_y_l4(12)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(12)<='1';
end if;
end if;
if(is_destroyed_l4(11)='0')then
if(coll_x_l4(11)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(11)<='1';
end if;
if(coll_y_l4(11)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(11)<='1';
end if;
end if;
if(is_destroyed_l4(10)='0')then
if(coll_x_l4(10)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(10)<='1';
end if;
if(coll_y_l4(10)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(10)<='1';
end if;
end if;
if(is_destroyed_l4(9)='0')then
if(coll_x_l4(9)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(9)<='1';
end if;
if(coll_y_l4(9)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(9)<='1';
end if;
end if;
if(is_destroyed_l4(8)='0')then
if(coll_x_l4(8)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(8)<='1';
end if;
if(coll_y_l4(8)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(8)<='1';
end if;
end if;
if(is_destroyed_l5(71)='0')then--detect collision for ball and bricks of level5
if(coll_x_l5(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(71)<='1';
end if;
if(coll_y_l5(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(71)<='1';
end if;
end if;
if(is_destroyed_l5(70)='0')then
if(coll_x_l5(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(70)<='1';
end if;
if(coll_y_l5(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(70)<='1';
end if;
end if;
if(is_destroyed_l5(69)='0')then
if(coll_x_l5(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(69)<='1';
end if;
if(coll_y_l5(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(69)<='1';
end if;
end if;
if(is_destroyed_l5(68)='0')then
if(coll_x_l5(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(68)<='1';
end if;
if(coll_y_l5(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(68)<='1';
end if;
end if;
if(is_destroyed_l5(67)='0')then
if(coll_x_l5(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(67)<='1';
end if;
if(coll_y_l5(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(67)<='1';
end if;
end if;
if(is_destroyed_l5(66)='0')then
if(coll_x_l5(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(66)<='1';
end if;
if(coll_y_l5(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(66)<='1';
end if;
end if;
if(is_destroyed_l5(65)='0')then
if(coll_x_l5(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(65)<='1';
end if;
if(coll_y_l5(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(65)<='1';
end if;
end if;
if(is_destroyed_l5(64)='0')then
if(coll_x_l5(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(64)<='1';
end if;
if(coll_y_l5(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(64)<='1';
end if;
end if;
if(is_destroyed_l5(63)='0')then
if(coll_x_l5(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(63)<='1';
end if;
if(coll_y_l5(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(63)<='1';
end if;
end if;
if(is_destroyed_l5(62)='0')then
if(coll_x_l5(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(62)<='1';
end if;
if(coll_y_l5(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(62)<='1';
end if;
end if;
if(is_destroyed_l5(61)='0')then
if(coll_x_l5(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(61)<='1';
end if;
if(coll_y_l5(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(61)<='1';
end if;
end if;
if(is_destroyed_l5(60)='0')then
if(coll_x_l5(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(60)<='1';
end if;
if(coll_y_l5(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(60)<='1';
end if;
end if;
if(is_destroyed_l5(59)='0')then
if(coll_x_l5(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(59)<='1';
end if;
if(coll_y_l5(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(59)<='1';
end if;
end if;
if(is_destroyed_l5(58)='0')then
if(coll_x_l5(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(58)<='1';
end if;
if(coll_y_l5(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(58)<='1';
end if;
end if;
if(is_destroyed_l5(57)='0')then
if(coll_x_l5(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(57)<='1';
end if;
if(coll_y_l5(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(57)<='1';
end if;
end if;
if(is_destroyed_l5(56)='0')then
if(coll_x_l5(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(56)<='1';
end if;
if(coll_y_l5(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(56)<='1';
end if;
end if;
if(is_destroyed_l5(55)='0')then
if(coll_x_l5(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(55)<='1';
end if;
if(coll_y_l5(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(55)<='1';
end if;
end if;
if(is_destroyed_l5(54)='0')then
if(coll_x_l5(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(54)<='1';
end if;
if(coll_y_l5(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(54)<='1';
end if;
end if;
if(is_destroyed_l5(53)='0')then
if(coll_x_l5(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(53)<='1';
end if;
if(coll_y_l5(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(53)<='1';
end if;
end if;
if(is_destroyed_l5(52)='0')then
if(coll_x_l5(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(52)<='1';
end if;
if(coll_y_l5(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(52)<='1';
end if;
end if;
if(is_destroyed_l5(51)='0')then
if(coll_x_l5(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(51)<='1';
end if;
if(coll_y_l5(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(51)<='1';
end if;
end if;
if(is_destroyed_l5(50)='0')then
if(coll_x_l5(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(50)<='1';
end if;
if(coll_y_l5(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(50)<='1';
end if;
end if;
if(is_destroyed_l5(49)='0')then
if(coll_x_l5(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(49)<='1';
end if;
if(coll_y_l5(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(49)<='1';
end if;
end if;
if(is_destroyed_l5(48)='0')then
if(coll_x_l5(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(48)<='1';
end if;
if(coll_y_l5(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(48)<='1';
end if;
end if;
if(is_destroyed_l5(47)='0')then
if(coll_x_l5(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(47)<='1';
end if;
if(coll_y_l5(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(47)<='1';
end if;
end if;
if(is_destroyed_l5(46)='0')then
if(coll_x_l5(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(46)<='1';
end if;
if(coll_y_l5(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(46)<='1';
end if;
end if;
if(is_destroyed_l5(45)='0')then
if(coll_x_l5(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(45)<='1';
end if;
if(coll_y_l5(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(45)<='1';
end if;
end if;
if(is_destroyed_l5(44)='0')then
if(coll_x_l5(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(44)<='1';
end if;
if(coll_y_l5(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(44)<='1';
end if;
end if;
if(is_destroyed_l5(43)='0')then
if(coll_x_l5(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(43)<='1';
end if;
if(coll_y_l5(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(43)<='1';
end if;
end if;
if(is_destroyed_l5(42)='0')then
if(coll_x_l5(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(42)<='1';
end if;
if(coll_y_l5(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(42)<='1';
end if;
end if;
if(is_destroyed_l5(41)='0')then
if(coll_x_l5(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(41)<='1';
end if;
if(coll_y_l5(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(41)<='1';
end if;
end if;
if(is_destroyed_l5(40)='0')then
if(coll_x_l5(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(40)<='1';
end if;
if(coll_y_l5(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(40)<='1';
end if;
end if;
if(is_destroyed_l5(39)='0')then
if(coll_x_l5(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(39)<='1';
end if;
if(coll_y_l5(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(39)<='1';
end if;
end if;
if(is_destroyed_l5(38)='0')then
if(coll_x_l5(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(38)<='1';
end if;
if(coll_y_l5(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(38)<='1';
end if;
end if;
if(is_destroyed_l5(37)='0')then
if(coll_x_l5(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(37)<='1';
end if;
if(coll_y_l5(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(37)<='1';
end if;
end if;
if(is_destroyed_l5(36)='0')then
if(coll_x_l5(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(36)<='1';
end if;
if(coll_y_l5(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(36)<='1';
end if;
end if;
if(ball_y>480 and isalive/=0) then--respawn ball
ball_x<=rand_x;
ball_x_vel<=ball_x_vel_rand;
bat_x<=rand_x-25;
elsif(ball_x_vel='1' and notstarted='0' and pause='0' and stopball='0') then
ball_x <= ball_x + 3;--move ball right
elsif(ball_x_vel='0' and notstarted='0' and pause='0' and stopball='0') then
ball_x <= ball_x - 3;--move ball left
else
null;
end if;
if(ball_y>480 and isalive/=0) then--respawn ball and decrement lives
ball_y<=450;
ball_y_vel<='0';
bat_y<=460;
isalive<=isalive-1;
elsif(ball_y_vel='1' and notstarted='0' and pause='0' and stopball='0') then
ball_y <= ball_y + 1;--move ball down
elsif(ball_y_vel='0' and notstarted='0' and pause='0' and stopball='0') then
ball_y <= ball_y - 1;--move ball up
else
null;
end if;
if(r_shift='0' and bat_x<590 and pause='0' and stopball='0' and ball_y<470) then
bat_x<=bat_x+3;--move bat right
elsif(l_shift='0' and bat_x>3 and pause='0' and stopball='0' and ball_y<470) then
bat_x<=bat_x-3;--move bat left
else
null;
end if;
end if;
end if;
if(hpos>7 and hpos<104) then
hsync<='0'; --generate the horizontal sync
else
hsync<='1';
end if;
if(vpos>2 and vpos<5) then
vsync<='0'; --generate vertical sync
else
vsync<='1';
end if;
end if;
end process;
end sync_arch; | gpl-2.0 | df0a3648a317ad25dd1cb1ff94405689 | 0.675058 | 2.703579 | false | false | false | false |
loa-org/loa-hdl | modules/utils/tb/event_hold_stage_tb.vhd | 2 | 1,172 |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity event_hold_stage_tb is
end event_hold_stage_tb;
architecture tb of event_hold_stage_tb is
signal dout : std_logic := '0';
signal din : std_logic := '0';
signal period : std_logic := '0';
signal clk : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : event_hold_stage
port map (
dout_p => dout,
din_p => din,
period_p => period,
clk => clk);
process
begin
wait for 10 NS;
din <= '1';
wait for 20 NS;
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
din <= '1';
wait for 20 NS;
period <= '0';
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 US;
end process;
end tb;
| bsd-3-clause | e8a88e8db4e34c05db3baf3bf0772c63 | 0.476109 | 3.447059 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_2_0/sim/system_vga_gaussian_blur_2_0.vhd | 1 | 4,527 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_2_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_2_0;
ARCHITECTURE system_vga_gaussian_blur_2_0_arch OF system_vga_gaussian_blur_2_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_2_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_2_0_arch;
| mit | 20bd68689abbe851aa9d177a3b967d40 | 0.685885 | 3.630313 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/tb/reg_file_tb.vhd | 2 | 3,324 | -------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_tb is
end reg_file_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 16#0010#;
constant REG_ADDR_BIT : natural := 1;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
-- clock
signal clk : std_logic := '1';
type comment_type is (idle, write, read);
signal comment : comment_type := idle;
begin -- tb
-- component instantiation
DUT : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- Reset
reg_i <= (others => (others => '0'));
reg_i(0)(3 downto 0) <= "0001";
reg_i(1)(3 downto 0) <= "0010";
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
comment <= write;
writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
writeWord(addr => 16#0011#, data => 16#005f#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
-- expected data is the input to the register_file reg_i(0) and reg_i(1)
comment <= read;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
-- do the same reads, but the DUT shouldn't react
-- bus data should be 0000
readWord(addr => BASE_ADDRESS + 2, bus_i => bus_i, clk => clk);
-- read from correct address again
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
wait for 1000 ns;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
| bsd-3-clause | 030ea2051c8fa8c72f80997a2a683dc3 | 0.419976 | 4.134328 | false | false | false | false |
adelapie/xtea | xtea.vhd | 1 | 3,162 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity xtea is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
block_in : in std_logic_vector(63 downto 0);
key : in std_logic_vector(127 downto 0);
v_0_out : out std_logic_vector(31 downto 0);
v_1_out : out std_logic_vector(31 downto 0));
end xtea;
architecture Behavioral of xtea is
signal delta_s : unsigned(31 downto 0);
component round_f is
port(v_in : in std_logic_vector(31 downto 0);
last_val : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(31 downto 0));
end component;
component key_schedule is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0, enc) (1, dec)
val : in std_logic_vector(1 downto 0);
key : in std_logic_vector(127 downto 0);
subkey : out std_logic_vector(31 downto 0));
end component;
signal subkey_s : std_logic_vector(31 downto 0);
signal cnt_s : unsigned(1 downto 0);
signal v_0_s, v_1_s : unsigned(31 downto 0);
signal output_s : std_logic_vector(31 downto 0);
signal input_a_s : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (clk, rst, enc, std_logic_vector(cnt_s), key, subkey_s);
pr_cnt : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
cnt_s <= (others => '0');
else
cnt_s <= cnt_s + 1;
end if;
end if;
end process;
ROUND_F_0 : round_f port map (input_a_s, subkey_s, output_s);
pr_macc : process(clk, rst, enc, block_in, output_s, cnt_s)
begin
if rising_edge(clk) then
if rst = '1' then
if enc = '0' then
v_1_s <= unsigned(block_in(63 downto 32));
v_0_s <= unsigned(block_in(31 downto 0));
else
v_0_s <= unsigned(block_in(63 downto 32));
v_1_s <= unsigned(block_in(31 downto 0));
end if;
else
if cnt_s = "00" then -- v_0
input_a_s <= std_logic_vector(v_1_s);
elsif cnt_s = "01" then -- v_0
if enc = '0' then
v_0_s <= v_0_s + unsigned(output_s);
else
v_0_s <= v_0_s - unsigned(output_s);
end if;
elsif cnt_s = "10" then -- v_1
input_a_s <= std_logic_vector(v_0_s);
else -- v_1
if enc = '0' then
v_1_s <= v_1_s + unsigned(output_s);
else
v_1_s <= v_1_s - unsigned(output_s);
end if;
end if;
end if;
end if;
end process;
v_0_out <= std_logic_vector(v_0_s);
v_1_out <= std_logic_vector(v_1_s);
end Behavioral;
| gpl-3.0 | 3846fce00895cb58924673716971435d | 0.63093 | 2.858951 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 2 | 7,148 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 19:34:37 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 44.625000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 75.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
| mit | 2b381909fd2f02011d76a2a170f9be7e | 0.637661 | 3.297048 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_processing_system7_0_0_1/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 194,877 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:04:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_processing_system7_0_0_1/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | d1d0e03c9ca0a18315eb5df8b2eae2e1 | 0.634108 | 2.76018 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/synth/system_vga_buffer_1_0.vhd | 2 | 4,630 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_1_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_1_0;
ARCHITECTURE system_vga_buffer_1_0_arch OF system_vga_buffer_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_buffer_1_0_arch: ARCHITECTURE IS "vga_buffer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_buffer_1_0_arch : ARCHITECTURE IS "system_vga_buffer_1_0,vga_buffer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_buffer_1_0_arch: ARCHITECTURE IS "system_vga_buffer_1_0,vga_buffer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_buffer,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE_POW2=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_1_0_arch;
| mit | bb2d0fd72140bbafced7f4540e718163 | 0.707127 | 3.58082 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/add_inferred-rtl.vhdl | 1 | 2,345 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of add_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src_bits downto 0);
src2_tmp : std_ulogic_vector(src_bits downto 0);
result_tmp : std_ulogic_vector(src_bits downto 0);
result_msb : std_ulogic;
result_msb_carryin : std_ulogic;
carryout : std_ulogic;
end record;
signal c : comb_type;
begin
c.src1_tmp <= '0' & src1(src_bits-2 downto 0) & '1';
c.src2_tmp <= '0' & src2(src_bits-2 downto 0) & carryin;
c.result_tmp <= std_ulogic_vector(unsigned(c.src1_tmp) + unsigned(c.src2_tmp));
c.result_msb_carryin <= c.result_tmp(src_bits);
c.result_msb <= (src1(src_bits-1) xor
src2(src_bits-1) xor
c.result_msb_carryin
);
c.carryout <= ((src1(src_bits-1) and (src2(src_bits-1) or c.result_msb_carryin)) or
(src2(src_bits-1) and c.result_msb_carryin));
carryout <= c.carryout;
overflow <= c.carryout xor c.result_msb_carryin;
result <= c.result_msb & c.result_tmp(src_bits-1 downto 1);
end;
| apache-2.0 | bb4e0d28db27a662b61b30c3bf7ecadc | 0.540299 | 3.981324 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 13 | 30,077 | `protect begin_protected
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`protect end_protected
| mit | 66034d7c795576675f5ed16df0f6daa0 | 0.943545 | 1.84397 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_line_buffer.vhd | 1 | 2,304 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 Rx Line Buffer
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
entity csi_rx_line_buffer is
generic(
line_width : natural := 3840; --width of a single line
pixels_per_clock : natural := 2 --number of pixels output every clock cycle; either 1, 2 or 4
);
port(
write_clock : in std_logic;
write_addr : in natural range 0 to (line_width / 4) - 1;
write_data : in std_logic_vector(39 downto 0); --write port is always 4 pixels wide
write_en : in std_logic;
read_clock : in std_logic;
read_addr : in natural range 0 to (line_width / pixels_per_clock) - 1;
read_q : out std_logic_vector((10 * pixels_per_clock) - 1 downto 0)
);
end csi_rx_line_buffer;
architecture Behavioral of csi_rx_line_buffer is
type linebuf_t is array(0 to (line_width / 4) - 1) of std_logic_vector(39 downto 0);
signal linebuf : linebuf_t;
signal linebuf_read_address : natural range 0 to (line_width / 4) - 1;
signal read_address_lat : natural range 0 to (line_width / pixels_per_clock) - 1;
signal linebuf_read_q : std_logic_vector(39 downto 0);
begin
process(write_clock)
begin
if rising_edge(write_clock) then
if write_en = '1' then
linebuf(write_addr) <= write_data;
end if;
end if;
end process;
process(read_clock)
begin
if rising_edge(read_clock) then
read_address_lat <= read_addr;
linebuf_read_q <= linebuf(linebuf_read_address);
end if;
end process;
sppc : if pixels_per_clock = 1 generate
linebuf_read_address <= read_addr / 4;
read_q <= linebuf_read_q(9 downto 0) when read_address_lat mod 4 = 0 else
linebuf_read_q(19 downto 10) when read_address_lat mod 4 = 1 else
linebuf_read_q(29 downto 20) when read_address_lat mod 4 = 2 else
linebuf_read_q(39 downto 30);
end generate;
dppc : if pixels_per_clock = 2 generate
linebuf_read_address <= read_addr / 2;
read_q <= linebuf_read_q(19 downto 0) when read_address_lat mod 2 = 0 else
linebuf_read_q(39 downto 20);
end generate;
qppc : if pixels_per_clock = 4 generate
linebuf_read_address <= read_addr;
read_q <= linebuf_read_q;
end generate;
end architecture;
| mit | 78cc5743d12f7527f7e59b58f96267ed | 0.655816 | 3.310345 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/synth/sqrt.vhd | 1 | 8,353 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY sqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END sqrt;
ARCHITECTURE sqrt_arch OF sqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sqrt_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sqrt_arch: ARCHITECTURE IS "cordic_v6_0_11,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sqrt_arch : ARCHITECTURE IS "sqrt,cordic_v6_0_11,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sqrt_arch: ARCHITECTURE IS "sqrt,cordic_v6_0_11,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cordic,x_ipVersion=6.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ARCHITECTURE=2,C_CORDIC_FUNCTION=6,C_COARSE_ROTATE=0,C_DATA_FORMAT=1,C_XDEVICEFAMILY=zynq,C_HAS_ACLKEN=0,C_HAS_ACLK=1,C_HAS_S_AXIS_CARTESIAN=1,C_HAS_S_AXIS_PHASE=0,C_HAS_ARESETN=0,C_INPUT_WIDTH=16,C_ITERATIONS=0,C_OUTPUT_WIDTH=16,C_PHASE_FORMAT=0,C_PIPELINE_MODE=-2,C_PRECISION=0,C_ROUND_MODE=0,C_SCALE_COMP=0,C_THROTTLE_S" &
"CHEME=3,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_PHASE_TUSER=0,C_HAS_S_AXIS_PHASE_TLAST=0,C_S_AXIS_PHASE_TDATA_WIDTH=16,C_S_AXIS_PHASE_TUSER_WIDTH=1,C_HAS_S_AXIS_CARTESIAN_TUSER=0,C_HAS_S_AXIS_CARTESIAN_TLAST=0,C_S_AXIS_CARTESIAN_TDATA_WIDTH=16,C_S_AXIS_CARTESIAN_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=16,C_M_AXIS_DOUT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 6,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 16,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END sqrt_arch;
| mit | c6d89ac0117e0eb5ae18d1c74d4b6a86 | 0.68215 | 3.227589 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_usb_0_avalon_usb_slave_translator.vhd | 1 | 14,632 | -- niosii_system_usb_0_avalon_usb_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_usb_0_avalon_usb_slave_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 16;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 5;
AV_WRITE_WAIT_CYCLES : integer := 5;
AV_SETUP_WAIT_CYCLES : integer := 5;
AV_DATA_HOLD_CYCLES : integer := 5
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(15 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_usb_0_avalon_usb_slave_translator;
architecture rtl of niosii_system_usb_0_avalon_usb_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
usb_0_avalon_usb_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_usb_0_avalon_usb_slave_translator
| apache-2.0 | 95bdf3743625b66f4f8142c52f63885b | 0.430016 | 4.335407 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_1rw_inferred-rtl.vhdl | 1 | 2,118 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_1rw_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
signal memory : memory_type
-- pragma translate_off
:= (others => (others => '0'));
-- pragma translate_on
;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
begin
main : process(clk)
begin
if rising_edge(clk) then
if en = '1' then
if we = '1' then
memory(conv_addr(addr)) <= wdata;
else
rdata <= memory(conv_addr(addr))
end if;
end if;
end if;
end process;
end;
| apache-2.0 | 092ca965e3693b29ea6b9818d22cacc9 | 0.524551 | 4.584416 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_0_0/sim/system_util_ds_buf_0_0.vhd | 1 | 5,806 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_ds_buf:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_ds_buf_v2_01_a;
USE util_ds_buf_v2_01_a.util_ds_buf;
ENTITY system_util_ds_buf_0_0 IS
PORT (
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_ds_buf_0_0;
ARCHITECTURE system_util_ds_buf_0_0_arch OF system_util_ds_buf_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_ds_buf IS
GENERIC (
C_BUF_TYPE : STRING;
C_SIZE : INTEGER
);
PORT (
IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_ds_buf;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK";
ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK";
BEGIN
U0 : util_ds_buf
GENERIC MAP (
C_BUF_TYPE => "BUFG",
C_SIZE => 1
)
PORT MAP (
IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_I => BUFG_I,
BUFG_O => BUFG_O,
BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3))
);
END system_util_ds_buf_0_0_arch;
| mit | 5ee3696746069f342dec50d3325d3d64 | 0.680331 | 3.356069 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/synth/system_vga_sync_0_0.vhd | 2 | 4,746 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
| mit | 1a3aee41f7fe80b957bb38fb16920f3b | 0.702065 | 3.662037 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/sim/arctan.vhd | 1 | 7,172 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY arctan IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END arctan;
ARCHITECTURE arctan_arch OF arctan IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF arctan_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 3,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 0,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END arctan_arch;
| mit | 71706485fb003b92f62768b41d6c8c61 | 0.669269 | 3.410366 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ad7266/hdl/adc_ad7266_module.vhd | 2 | 6,288 | -------------------------------------------------------------------------------
-- Title : Bus Module for ADC AD7266
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- TODO mask does not work here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ad7266_pkg.all;
-------------------------------------------------------------------------------
entity adc_ad7266_single_ended_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive := 12); -- AD7266 has 12 single ended channels
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- direct access to the read adc samples
adc_values_o : out adc_ad7266_values_type(CHANNELS - 1 downto 0);
clk : in std_logic
);
end adc_ad7266_single_ended_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_ad7266_single_ended_module is
constant REG_ADDR_BIT : positive := required_bits(CHANNELS);
type adc_ad7266_module_state_type is (IDLE, WAIT_FOR_ADC);
type adc_ad7266_module_type is record
state : adc_ad7266_module_state_type;
start : std_logic;
current_ch : integer range 0 to (CHANNELS / 2) - 1;
reg : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_ad7266_module_type := (state => IDLE,
current_ch => (CHANNELS / 2) - 1,
start => '0',
reg => (others => (others => '0')));
signal adc_mode_s : std_logic;
signal channel_s : std_logic_vector(2 downto 0);
signal value_a_s : std_logic_vector(11 downto 0); --AD7266 converts two
--channels a,b at one
--address (12 channels
--vs 6 addresses)
signal value_b_s : std_logic_vector(11 downto 0);
signal done_s : std_logic;
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal mask_s : std_logic_vector(((CHANNELS / 2) - 1) downto 0);
begin
-- mapping signals to adc i/f
adc_mode_s <= '1'; -- we don't use differential mode
channel_s <= std_logic_vector(to_unsigned(r.current_ch, 3));
reg_i <= r.reg;
-- present last value of each channel on this modules ports
copy_loop : for ii in 0 to 11 generate -- (2**REG_ADDR_BIT-1)
adc_values_o(ii) <= r.reg(ii)(11 downto 0); --12bit ADC (AD7266)
end generate copy_loop;
-- register for channel mask
-- you will always mask out two channels at once
mask_s <= reg_o(0)((CHANNELS / 2) - 1 downto 0);
-------------------------------------------------------------------------------
---- seq part of FSM
-------------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, mask_s, r, value_a_s, value_b_s)
variable v : adc_ad7266_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- in this state we iterate over the channels
if v.current_ch = ((CHANNELS / 2)-1) then
-- we wrap around (to 0)
v.current_ch := 0;
else
-- or increment the currently selected channel
v.current_ch := v.current_ch + 1;
end if;
-- if the channel isn't masked out, we take a sample
-- if mask_s(v.current_ch) = '0' then
v.start := '1';
v.state := WAIT_FOR_ADC;
-- end if;
when WAIT_FOR_ADC =>
-- adc i/f has already started conversion, we stay in this state until
-- the conversion is over.
v.start := '0';
if done_s = '1' then
-- if the conversion is done we put its result in the right register,
-- for each value a,b
-- and return to the "idle" state.
v.reg(v.current_ch) := ("0000") & value_a_s;
v.reg(v.current_ch + (CHANNELS / 2)) := ("0000") & value_b_s;
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-- and configuration
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- ADC interface module
adc_ad7266_1 : adc_ad7266_single_ended
generic map (
DELAY => 1)
port map (
adc_out => adc_out_p,
adc_in => adc_in_p,
start_p => r.start,
adc_mode_p => adc_mode_s,
channel_p => channel_s,
value_a_p => value_a_s,
value_b_p => value_b_s,
done_p => done_s,
clk => clk);
end behavioral;
| bsd-3-clause | ff4ecad201fe38b23f840b1e316c89d0 | 0.437977 | 4.231494 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_0/synth/affine_block_ieee754_fp_multiplier_1_0.vhd | 2 | 4,008 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_0;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_0_arch OF affine_block_ieee754_fp_multiplier_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_multiplier_1_0_arch: ARCHITECTURE IS "ieee754_fp_multiplier,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_multiplier_1_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_0,ieee754_fp_multiplier,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_multiplier_1_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_0,ieee754_fp_multiplier,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_multiplier,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_0_arch;
| mit | 4e6d878650f574976b50d3f2185ffb84 | 0.749251 | 3.802657 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 194,641 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:04:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_processing_system7_0_0 -prefix
-- system_processing_system7_0_0_ system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | e56b1867287ad466ffa428c2d24c6e04 | 0.633905 | 2.760121 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_split_controller_0_0/system_vga_split_controller_0_0_sim_netlist.vhdl | 1 | 39,188 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:07 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_split_controller_0_0/system_vga_split_controller_0_0_sim_netlist.vhdl
-- Design : system_vga_split_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_split_controller_0_0_vga_split_controller is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clock : in STD_LOGIC;
hsync : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_split_controller_0_0_vga_split_controller : entity is "vga_split_controller";
end system_vga_split_controller_0_0_vga_split_controller;
architecture STRUCTURE of system_vga_split_controller_0_0_vga_split_controller is
signal \counter[0]_i_2_n_0\ : STD_LOGIC;
signal \counter[0]_i_3_n_0\ : STD_LOGIC;
signal \counter[0]_i_4_n_0\ : STD_LOGIC;
signal \counter[0]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_2_n_0\ : STD_LOGIC;
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_2_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_2_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_2_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_2_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_2_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_2_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal counter_reg : STD_LOGIC_VECTOR ( 31 downto 6 );
signal \counter_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg_n_0_[0]\ : STD_LOGIC;
signal \counter_reg_n_0_[1]\ : STD_LOGIC;
signal \counter_reg_n_0_[2]\ : STD_LOGIC;
signal \counter_reg_n_0_[3]\ : STD_LOGIC;
signal \counter_reg_n_0_[4]\ : STD_LOGIC;
signal \counter_reg_n_0_[5]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rgb1 : STD_LOGIC;
signal \rgb1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \rgb1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \rgb1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \rgb1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \rgb1_carry__0_n_0\ : STD_LOGIC;
signal \rgb1_carry__0_n_1\ : STD_LOGIC;
signal \rgb1_carry__0_n_2\ : STD_LOGIC;
signal \rgb1_carry__0_n_3\ : STD_LOGIC;
signal \rgb1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \rgb1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \rgb1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \rgb1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \rgb1_carry__1_n_0\ : STD_LOGIC;
signal \rgb1_carry__1_n_1\ : STD_LOGIC;
signal \rgb1_carry__1_n_2\ : STD_LOGIC;
signal \rgb1_carry__1_n_3\ : STD_LOGIC;
signal \rgb1_carry__2_i_1_n_0\ : STD_LOGIC;
signal rgb1_carry_i_1_n_0 : STD_LOGIC;
signal rgb1_carry_i_2_n_0 : STD_LOGIC;
signal rgb1_carry_i_3_n_0 : STD_LOGIC;
signal rgb1_carry_i_4_n_0 : STD_LOGIC;
signal rgb1_carry_i_5_n_0 : STD_LOGIC;
signal rgb1_carry_i_6_n_0 : STD_LOGIC;
signal rgb1_carry_n_0 : STD_LOGIC;
signal rgb1_carry_n_1 : STD_LOGIC;
signal rgb1_carry_n_2 : STD_LOGIC;
signal rgb1_carry_n_3 : STD_LOGIC;
signal \NLW_counter_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_rgb1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[10]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[11]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[12]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[13]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[9]_i_1\ : label is "soft_lutpair4";
begin
\counter[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[3]\,
O => \counter[0]_i_2_n_0\
);
\counter[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[2]\,
O => \counter[0]_i_3_n_0\
);
\counter[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[1]\,
O => \counter[0]_i_4_n_0\
);
\counter[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[0]\,
O => \counter[0]_i_5_n_0\
);
\counter[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(15),
O => \counter[12]_i_2_n_0\
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(14),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(13),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(12),
O => \counter[12]_i_5_n_0\
);
\counter[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(19),
O => \counter[16]_i_2_n_0\
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(18),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(17),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(16),
O => \counter[16]_i_5_n_0\
);
\counter[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(23),
O => \counter[20]_i_2_n_0\
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(22),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(21),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(20),
O => \counter[20]_i_5_n_0\
);
\counter[24]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(27),
O => \counter[24]_i_2_n_0\
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(26),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(25),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(24),
O => \counter[24]_i_5_n_0\
);
\counter[28]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(31),
O => \counter[28]_i_2_n_0\
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(30),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(29),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(28),
O => \counter[28]_i_5_n_0\
);
\counter[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(7),
O => \counter[4]_i_2_n_0\
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(6),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[5]\,
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[4]\,
O => \counter[4]_i_5_n_0\
);
\counter[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(11),
O => \counter[8]_i_2_n_0\
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(10),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(9),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(8),
O => \counter[8]_i_5_n_0\
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[0]_i_1_n_7\,
Q => \counter_reg_n_0_[0]\,
R => hsync
);
\counter_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[0]_i_1_n_0\,
CO(2) => \counter_reg[0]_i_1_n_1\,
CO(1) => \counter_reg[0]_i_1_n_2\,
CO(0) => \counter_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \counter_reg[0]_i_1_n_4\,
O(2) => \counter_reg[0]_i_1_n_5\,
O(1) => \counter_reg[0]_i_1_n_6\,
O(0) => \counter_reg[0]_i_1_n_7\,
S(3) => \counter[0]_i_2_n_0\,
S(2) => \counter[0]_i_3_n_0\,
S(1) => \counter[0]_i_4_n_0\,
S(0) => \counter[0]_i_5_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[8]_i_1_n_5\,
Q => counter_reg(10),
R => hsync
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[8]_i_1_n_4\,
Q => counter_reg(11),
R => hsync
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[12]_i_1_n_7\,
Q => counter_reg(12),
R => hsync
);
\counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_1_n_0\,
CO(3) => \counter_reg[12]_i_1_n_0\,
CO(2) => \counter_reg[12]_i_1_n_1\,
CO(1) => \counter_reg[12]_i_1_n_2\,
CO(0) => \counter_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_1_n_4\,
O(2) => \counter_reg[12]_i_1_n_5\,
O(1) => \counter_reg[12]_i_1_n_6\,
O(0) => \counter_reg[12]_i_1_n_7\,
S(3) => \counter[12]_i_2_n_0\,
S(2) => \counter[12]_i_3_n_0\,
S(1) => \counter[12]_i_4_n_0\,
S(0) => \counter[12]_i_5_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[12]_i_1_n_6\,
Q => counter_reg(13),
R => hsync
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[12]_i_1_n_5\,
Q => counter_reg(14),
R => hsync
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[12]_i_1_n_4\,
Q => counter_reg(15),
R => hsync
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[16]_i_1_n_7\,
Q => counter_reg(16),
R => hsync
);
\counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_1_n_0\,
CO(3) => \counter_reg[16]_i_1_n_0\,
CO(2) => \counter_reg[16]_i_1_n_1\,
CO(1) => \counter_reg[16]_i_1_n_2\,
CO(0) => \counter_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_1_n_4\,
O(2) => \counter_reg[16]_i_1_n_5\,
O(1) => \counter_reg[16]_i_1_n_6\,
O(0) => \counter_reg[16]_i_1_n_7\,
S(3) => \counter[16]_i_2_n_0\,
S(2) => \counter[16]_i_3_n_0\,
S(1) => \counter[16]_i_4_n_0\,
S(0) => \counter[16]_i_5_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[16]_i_1_n_6\,
Q => counter_reg(17),
R => hsync
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[16]_i_1_n_5\,
Q => counter_reg(18),
R => hsync
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[16]_i_1_n_4\,
Q => counter_reg(19),
R => hsync
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[0]_i_1_n_6\,
Q => \counter_reg_n_0_[1]\,
R => hsync
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[20]_i_1_n_7\,
Q => counter_reg(20),
R => hsync
);
\counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_1_n_0\,
CO(3) => \counter_reg[20]_i_1_n_0\,
CO(2) => \counter_reg[20]_i_1_n_1\,
CO(1) => \counter_reg[20]_i_1_n_2\,
CO(0) => \counter_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_1_n_4\,
O(2) => \counter_reg[20]_i_1_n_5\,
O(1) => \counter_reg[20]_i_1_n_6\,
O(0) => \counter_reg[20]_i_1_n_7\,
S(3) => \counter[20]_i_2_n_0\,
S(2) => \counter[20]_i_3_n_0\,
S(1) => \counter[20]_i_4_n_0\,
S(0) => \counter[20]_i_5_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[20]_i_1_n_6\,
Q => counter_reg(21),
R => hsync
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[20]_i_1_n_5\,
Q => counter_reg(22),
R => hsync
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[20]_i_1_n_4\,
Q => counter_reg(23),
R => hsync
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[24]_i_1_n_7\,
Q => counter_reg(24),
R => hsync
);
\counter_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_1_n_0\,
CO(3) => \counter_reg[24]_i_1_n_0\,
CO(2) => \counter_reg[24]_i_1_n_1\,
CO(1) => \counter_reg[24]_i_1_n_2\,
CO(0) => \counter_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_1_n_4\,
O(2) => \counter_reg[24]_i_1_n_5\,
O(1) => \counter_reg[24]_i_1_n_6\,
O(0) => \counter_reg[24]_i_1_n_7\,
S(3) => \counter[24]_i_2_n_0\,
S(2) => \counter[24]_i_3_n_0\,
S(1) => \counter[24]_i_4_n_0\,
S(0) => \counter[24]_i_5_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[24]_i_1_n_6\,
Q => counter_reg(25),
R => hsync
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[24]_i_1_n_5\,
Q => counter_reg(26),
R => hsync
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[24]_i_1_n_4\,
Q => counter_reg(27),
R => hsync
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[28]_i_1_n_7\,
Q => counter_reg(28),
R => hsync
);
\counter_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_1_n_0\,
CO(3) => \NLW_counter_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \counter_reg[28]_i_1_n_1\,
CO(1) => \counter_reg[28]_i_1_n_2\,
CO(0) => \counter_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_1_n_4\,
O(2) => \counter_reg[28]_i_1_n_5\,
O(1) => \counter_reg[28]_i_1_n_6\,
O(0) => \counter_reg[28]_i_1_n_7\,
S(3) => \counter[28]_i_2_n_0\,
S(2) => \counter[28]_i_3_n_0\,
S(1) => \counter[28]_i_4_n_0\,
S(0) => \counter[28]_i_5_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[28]_i_1_n_6\,
Q => counter_reg(29),
R => hsync
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[0]_i_1_n_5\,
Q => \counter_reg_n_0_[2]\,
R => hsync
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[28]_i_1_n_5\,
Q => counter_reg(30),
R => hsync
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[28]_i_1_n_4\,
Q => counter_reg(31),
R => hsync
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[0]_i_1_n_4\,
Q => \counter_reg_n_0_[3]\,
R => hsync
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[4]_i_1_n_7\,
Q => \counter_reg_n_0_[4]\,
R => hsync
);
\counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[0]_i_1_n_0\,
CO(3) => \counter_reg[4]_i_1_n_0\,
CO(2) => \counter_reg[4]_i_1_n_1\,
CO(1) => \counter_reg[4]_i_1_n_2\,
CO(0) => \counter_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_1_n_4\,
O(2) => \counter_reg[4]_i_1_n_5\,
O(1) => \counter_reg[4]_i_1_n_6\,
O(0) => \counter_reg[4]_i_1_n_7\,
S(3) => \counter[4]_i_2_n_0\,
S(2) => \counter[4]_i_3_n_0\,
S(1) => \counter[4]_i_4_n_0\,
S(0) => \counter[4]_i_5_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[4]_i_1_n_6\,
Q => \counter_reg_n_0_[5]\,
R => hsync
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[4]_i_1_n_5\,
Q => counter_reg(6),
R => hsync
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[4]_i_1_n_4\,
Q => counter_reg(7),
R => hsync
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[8]_i_1_n_7\,
Q => counter_reg(8),
R => hsync
);
\counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_1_n_0\,
CO(3) => \counter_reg[8]_i_1_n_0\,
CO(2) => \counter_reg[8]_i_1_n_1\,
CO(1) => \counter_reg[8]_i_1_n_2\,
CO(0) => \counter_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_1_n_4\,
O(2) => \counter_reg[8]_i_1_n_5\,
O(1) => \counter_reg[8]_i_1_n_6\,
O(0) => \counter_reg[8]_i_1_n_7\,
S(3) => \counter[8]_i_2_n_0\,
S(2) => \counter[8]_i_3_n_0\,
S(1) => \counter[8]_i_4_n_0\,
S(0) => \counter[8]_i_5_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clock,
CE => '1',
D => \counter_reg[8]_i_1_n_6\,
Q => counter_reg(9),
R => hsync
);
rgb1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => rgb1_carry_n_0,
CO(2) => rgb1_carry_n_1,
CO(1) => rgb1_carry_n_2,
CO(0) => rgb1_carry_n_3,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb1_carry_i_1_n_0,
DI(0) => rgb1_carry_i_2_n_0,
O(3 downto 0) => NLW_rgb1_carry_O_UNCONNECTED(3 downto 0),
S(3) => rgb1_carry_i_3_n_0,
S(2) => rgb1_carry_i_4_n_0,
S(1) => rgb1_carry_i_5_n_0,
S(0) => rgb1_carry_i_6_n_0
);
\rgb1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => rgb1_carry_n_0,
CO(3) => \rgb1_carry__0_n_0\,
CO(2) => \rgb1_carry__0_n_1\,
CO(1) => \rgb1_carry__0_n_2\,
CO(0) => \rgb1_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_rgb1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \rgb1_carry__0_i_1_n_0\,
S(2) => \rgb1_carry__0_i_2_n_0\,
S(1) => \rgb1_carry__0_i_3_n_0\,
S(0) => \rgb1_carry__0_i_4_n_0\
);
\rgb1_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(20),
I1 => counter_reg(21),
O => \rgb1_carry__0_i_1_n_0\
);
\rgb1_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(18),
I1 => counter_reg(19),
O => \rgb1_carry__0_i_2_n_0\
);
\rgb1_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(16),
I1 => counter_reg(17),
O => \rgb1_carry__0_i_3_n_0\
);
\rgb1_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(14),
I1 => counter_reg(15),
O => \rgb1_carry__0_i_4_n_0\
);
\rgb1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb1_carry__0_n_0\,
CO(3) => \rgb1_carry__1_n_0\,
CO(2) => \rgb1_carry__1_n_1\,
CO(1) => \rgb1_carry__1_n_2\,
CO(0) => \rgb1_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_rgb1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \rgb1_carry__1_i_1_n_0\,
S(2) => \rgb1_carry__1_i_2_n_0\,
S(1) => \rgb1_carry__1_i_3_n_0\,
S(0) => \rgb1_carry__1_i_4_n_0\
);
\rgb1_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(28),
I1 => counter_reg(29),
O => \rgb1_carry__1_i_1_n_0\
);
\rgb1_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(26),
I1 => counter_reg(27),
O => \rgb1_carry__1_i_2_n_0\
);
\rgb1_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(24),
I1 => counter_reg(25),
O => \rgb1_carry__1_i_3_n_0\
);
\rgb1_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(22),
I1 => counter_reg(23),
O => \rgb1_carry__1_i_4_n_0\
);
\rgb1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb1_carry__1_n_0\,
CO(3 downto 1) => \NLW_rgb1_carry__2_CO_UNCONNECTED\(3 downto 1),
CO(0) => rgb1,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => counter_reg(31),
O(3 downto 0) => \NLW_rgb1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \rgb1_carry__2_i_1_n_0\
);
\rgb1_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(30),
I1 => counter_reg(31),
O => \rgb1_carry__2_i_1_n_0\
);
rgb1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(8),
I1 => counter_reg(9),
O => rgb1_carry_i_1_n_0
);
rgb1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(6),
I1 => counter_reg(7),
O => rgb1_carry_i_2_n_0
);
rgb1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(12),
I1 => counter_reg(13),
O => rgb1_carry_i_3_n_0
);
rgb1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => counter_reg(10),
I1 => counter_reg(11),
O => rgb1_carry_i_4_n_0
);
rgb1_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(8),
I1 => counter_reg(9),
O => rgb1_carry_i_5_n_0
);
rgb1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => counter_reg(6),
I1 => counter_reg(7),
O => rgb1_carry_i_6_n_0
);
\rgb[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(0),
I1 => rgb_1(0),
I2 => rgb1,
O => p_1_in(0)
);
\rgb[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(10),
I1 => rgb_1(10),
I2 => rgb1,
O => p_1_in(10)
);
\rgb[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(11),
I1 => rgb_1(11),
I2 => rgb1,
O => p_1_in(11)
);
\rgb[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(12),
I1 => rgb_1(12),
I2 => rgb1,
O => p_1_in(12)
);
\rgb[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(13),
I1 => rgb_1(13),
I2 => rgb1,
O => p_1_in(13)
);
\rgb[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(14),
I1 => rgb_1(14),
I2 => rgb1,
O => p_1_in(14)
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
\rgb[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(15),
I1 => rgb_1(15),
I2 => rgb1,
O => p_1_in(15)
);
\rgb[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(1),
I1 => rgb_1(1),
I2 => rgb1,
O => p_1_in(1)
);
\rgb[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(2),
I1 => rgb_1(2),
I2 => rgb1,
O => p_1_in(2)
);
\rgb[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(3),
I1 => rgb_1(3),
I2 => rgb1,
O => p_1_in(3)
);
\rgb[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(4),
I1 => rgb_1(4),
I2 => rgb1,
O => p_1_in(4)
);
\rgb[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(5),
I1 => rgb_1(5),
I2 => rgb1,
O => p_1_in(5)
);
\rgb[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(6),
I1 => rgb_1(6),
I2 => rgb1,
O => p_1_in(6)
);
\rgb[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(7),
I1 => rgb_1(7),
I2 => rgb1,
O => p_1_in(7)
);
\rgb[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(8),
I1 => rgb_1(8),
I2 => rgb1,
O => p_1_in(8)
);
\rgb[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rgb_0(9),
I1 => rgb_1(9),
I2 => rgb1,
O => p_1_in(9)
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(10),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(11),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(12),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(13),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(14),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(15),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(8),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clock,
CE => p_0_in,
D => p_1_in(9),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_split_controller_0_0 is
port (
rgb_0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clock : in STD_LOGIC;
hsync : in STD_LOGIC;
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_split_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_split_controller_0_0 : entity is "system_vga_split_controller_0_0,vga_split_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_split_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_split_controller_0_0 : entity is "vga_split_controller,Vivado 2016.4";
end system_vga_split_controller_0_0;
architecture STRUCTURE of system_vga_split_controller_0_0 is
begin
U0: entity work.system_vga_split_controller_0_0_vga_split_controller
port map (
clock => clock,
hsync => hsync,
rgb(15 downto 0) => rgb(15 downto 0),
rgb_0(15 downto 0) => rgb_0(15 downto 0),
rgb_1(15 downto 0) => rgb_1(15 downto 0)
);
end STRUCTURE;
| mit | a3c16ba718a36adb33d4c3f5a4a32a35 | 0.500255 | 2.614799 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_hessian/vga_hessian.srcs/sources_1/new/vga_hessian.vhd | 4 | 27,351 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_hessian is
generic (
ROW_WIDTH: integer := 10
);
port (
clk_x16: in std_logic;
active: in std_logic;
rst: in std_logic;
x_addr: in std_logic_vector(9 downto 0);
y_addr: in std_logic_vector(9 downto 0);
g_in: in std_logic_vector(7 downto 0);
hessian_out: out std_logic_vector(31 downto 0)
);
end vga_hessian;
architecture Structural of vga_hessian is
component blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END component;
signal addr_0, addr_1 : std_logic_vector(13 downto 0);
signal x, x0, x1, y_actual : unsigned(9 downto 0);
signal y, y1, y2, y3, y4, y5, y6, y7, y8, y9 : unsigned(3 downto 0);
signal compute_addr_0, compute_addr_1, compute_addr_2, compute_addr_3 : std_logic_vector(13 downto 0);
signal din : std_logic_vector(15 downto 0) := x"0000";
signal dout_0, dout_1 : std_logic_vector(15 downto 0);
signal cycle : std_logic_vector(3 downto 0) := "0000";
signal top_left_0, top_left_1, top_right_0, top_right_1, bottom_left_0, bottom_left_1, bottom_right_0, bottom_right_1, top, left, corner, value, last_value, Lyy_2_top_left, Lyy_2_top_right, Lyy_2_bottom_left, Lyy_2_bottom_right, Lxx_0, Lxx_1, Lxx_2, Lyy_0, Lyy_1, Lyy_2, Lxy_0, Lxy_1, Lxy_2, Lxy_3 : unsigned(15 downto 0) := (others => '0');
signal Lxx, Lyy, Lxy : signed(15 downto 0) := (others => '0');
signal det_0, det_1, det_abs, det : signed(31 downto 0) := (others => '0');
signal wen : std_logic := '0';
type CACHE_TYPE is array(ROW_WIDTH downto 0) of std_logic_vector(15 downto 0);
signal cache : CACHE_TYPE := (others => x"0000");
begin
bram_0 : blk_mem_gen_0 port map(
clka => clk_x16,
ena => '1',
wea(0) => wen,
addra => addr_0,
dina => din,
douta => dout_0,
clkb => clk_x16,
enb => '1',
web => "0",
addrb => addr_1,
dinb => x"0000",
doutb => dout_1
);
process(clk_x16)
begin
if rising_edge(clk_x16) then
if rst = '0' then
-- clear cache
cache <= (others => x"0000");
cycle <= "0000";
else
if active = '0' then
cycle <= "0000";
else
if cycle = "0000" then
-- store x and y for next iteration
x <= unsigned(x_addr);
y <= unsigned(y_addr(3 downto 0));
y_actual <= unsigned(y_addr);
-- get value
last_value <= value;
value(7 downto 0) <= unsigned(g_in);
-- get integral top and corner from cache
if y_actual = 0 then
top <= (others => '0');
else
top <= unsigned(cache(ROW_WIDTH - 1));
end if;
if x = 0 then
left <= (others => '0');
else
left <= unsigned(cache(0));
end if;
if x = 0 or y_actual = 0 then
corner <= (others => '0');
else
corner <= unsigned(cache(ROW_WIDTH));
end if;
-- compute addresses for top left and top right for Lyy_2/Lyy_1
compute_addr_0(13 downto 10) <= std_logic_vector(y3);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y3);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read top left and top right for Lyy_1/Lyy_0
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top right corner for Lxx_2/Lxx_1
bottom_right_1 <= bottom_left_0;
top_right_1 <= top_left_0;
bottom_left_1 <= unsigned(dout_0);
top_left_1 <= unsigned(dout_1);
-- compute Lxx_0
Lxx_0 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "0001";
elsif cycle = "0001" then
-- compute (x, y) bottom right corner and top left corner for Lxy_0
x0 <= x-3;
y5 <= y-5;
x1 <= x-6;
y8 <= y-8;
-- write addresses to read top left corner and top right corner for Lyy_2/Lyy_1
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top left corner for Lxx_2
top_right_0 <= top_left_1;
bottom_right_0 <= bottom_left_1;
bottom_left_0 <= unsigned(dout_0);
top_left_0 <= unsigned(dout_1);
-- compute Lxx_1, Lxx_2
Lxx_1 <= (bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1) sll 1;
-- compute integral
Lyy_2_bottom_right <= last_value + left + top - corner;
Lyy_2_bottom_left <= unsigned(cache(4));
cycle <= "0010";
elsif cycle = "0010" then
-- compute (x, y) bottom left corner and top right corner for Lxy_0
x0 <= x1;
x1 <= x0;
-- compute addresses for bottom right corner and top left corner for Lxy_0
compute_addr_0(13 downto 10) <= std_logic_vector(y5);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y8);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- data ready, top left corner and top right corner for Lyy_0
top_left_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
-- compute Lxx_2
Lxx_2 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "0011";
elsif cycle = "0011" then
-- compute (x, y) bottom right corner and top left corner for Lxy_1
x0 <= x+1;
x1 <= x-2;
-- compute addresses for bottom left corner and top right corner for Lxy_0
compute_addr_2(13 downto 10) <= std_logic_vector(y5);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y8);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom right corner and top left corner for Lxy_0
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, top left corner and top right corner for Lyy_1/Lyy_0
bottom_left_0 <= unsigned(dout_0);
bottom_right_0 <= unsigned(dout_1);
-- compute Lxx
Lxx <= signed(Lxx_0 - Lxx_1 + Lxx_2);
cycle <= "0100";
elsif cycle = "0100" then
-- compute (x, y) bottom left corner and top right corner for Lxy_1
x0 <= x1;
x1 <= x0;
-- compute addresses for bottom right corner and top left corner for Lxy_1
compute_addr_0(13 downto 10) <= std_logic_vector(y5);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y8);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top right corner for Lxy_0
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, top left corner and top right corner for Lyy_2/Lyy_1
top_left_1 <= bottom_left_0;
top_right_1 <= bottom_right_0;
bottom_left_1 <= unsigned(dout_0);
bottom_right_1 <= unsigned(dout_1);
-- compute Lyy_0
Lyy_0 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "0101";
elsif cycle = "0101" then
-- compute (x, y) bottom right corner and top left corner for Lxy_2
x0 <= x1;
y1 <= y-1;
x1 <= x0;
y4 <= y-4;
-- compute addresses for bottom left corner and top right corner for Lxy_1
compute_addr_2(13 downto 10) <= std_logic_vector(y5);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y8);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom right corner and top left corner for Lxy_1
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
Lyy_2_top_left <= bottom_left_1;
Lyy_2_top_right <= bottom_right_1;
-- compute Lyy_1
Lyy_1 <= (bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1) sll 1;
cycle <= "0110";
elsif cycle = "0110" then
-- compute (x, y) bottom left corner and top right corner for Lxy_2
x0 <= x1;
x1 <= x0;
-- compute address to write above point to cache
compute_addr_0(13 downto 10) <= std_logic_vector(y1);
compute_addr_0(9 downto 0) <= std_logic_vector(x);
-- compute address for top left corner for Lxy_2
compute_addr_1(13 downto 10) <= std_logic_vector(y4);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top right corner for Lxy_1
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top left corner for Lxy_0
bottom_right_0 <= unsigned(dout_0);
top_left_0 <= unsigned(dout_1);
-- compute Lyy_2
Lyy_2 <= Lyy_2_bottom_right - Lyy_2_bottom_left - Lyy_2_top_right + Lyy_2_top_left;
cycle <= "0111";
elsif cycle = "0111" then
-- compute (x, y) bottom right corner and top left corner for Lxy_3
x0 <= x-3;
x1 <= x-6;
-- compute addresses for bottom left corner and top right corner for Lxy_2
compute_addr_2(13 downto 10) <= std_logic_vector(y1);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y4);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write address to write above point to cache
addr_0 <= compute_addr_0;
din <= cache(ROW_WIDTH-2);
wen <= '1';
-- write address to read top left corner for Lxy_2
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_0
bottom_left_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
-- shift cache
for i in 1 to ROW_WIDTH loop
cache(i) <= cache(i-1);
end loop;
cache(0) <= std_logic_vector(Lyy_2_bottom_right);
-- compute Lyy
Lyy <= signed(Lyy_0 - Lyy_1 + Lyy_2);
cycle <= "1000";
elsif cycle = "1000" then
-- compute (x, y) bottom left corner and top right corner for Lxy_3
x0 <= x1;
x1 <= x0;
-- compute addresses for bottom right corner and top left corner for Lxy_3
compute_addr_0(13 downto 10) <= std_logic_vector(y1);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y4);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top right corner for Lxy_2
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- turn off write
wen <= '0';
-- data ready, bottom right corner and top left corner for Lxy_1
bottom_right_1 <= unsigned(dout_0);
top_left_1 <= unsigned(dout_1);
-- compute Lxy_0
Lxy_0 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "1001";
elsif cycle = "1001" then
-- compute (x, y) bottom right corner and top right corner for Lxx_0
x0 <= x+2;
y2 <= y-2;
y7 <= y-7;
-- compute addresses for bottom left corner and top right corner for Lxy_3
compute_addr_2(13 downto 10) <= std_logic_vector(y1);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y4);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom right corner and top left corner for Lxy_3
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_1
bottom_left_1 <= unsigned(dout_0);
top_right_1 <= unsigned(dout_1);
-- compute determinant secondary diagonal
det_1 <= Lxy * Lxy;
cycle <= "1010";
elsif cycle = "1010" then
-- compute (x, y) bottom right corner and top right corner for Lxx_1/Lxx_0
x0 <= x-1;
-- compute addresses for bottom right corner and top right corner for Lxx_0
compute_addr_0(13 downto 10) <= std_logic_vector(y2);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y7);
compute_addr_1(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom left corner and top right corner for Lxy_3
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top left corner for Lxy_2
bottom_right_0 <= unsigned(cache(ROW_WIDTH-2));
top_left_0 <= unsigned(dout_1);
-- compute Lxy_1
Lxy_1 <= bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1;
cycle <= "1011";
elsif cycle = "1011" then
-- compute (x, y) bottom right corner and top right corner for Lxx_2/Lxx_1
x0 <= x-4;
-- compute addresses for bottom right corner and top right corner for Lxx_1/Lxx_0
compute_addr_2(13 downto 10) <= std_logic_vector(y2);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y7);
compute_addr_3(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom right corner and top right corner for Lxx_0
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_2
bottom_left_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
cycle <= "1100";
elsif cycle = "1100" then
-- compute (x, y) bottom left and top left corner for Lxx_2
x0 <= x-7;
-- compute addresses for bottom right corner and top right corner for Lxx_2/Lxx_1
compute_addr_0(13 downto 10) <= std_logic_vector(y2);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y7);
compute_addr_1(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom right corner and top right corner for Lxx_1/Lxx_0
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top left corner for Lxy_3
bottom_right_1 <= unsigned(dout_0);
top_left_1 <= unsigned(dout_1);
-- compute determinant primary diagonal
det_0 <= Lxx * Lyy;
-- compute Lxy_2
Lxy_2 <= bottom_right_0 - top_right_0 - bottom_left_0 + top_left_0;
cycle <= "1101";
elsif cycle = "1101" then
-- compute (x, y) top left and top right for Lyy_0
x0 <= x-5;
x1 <= x;
y9 <= y-9;
-- compute addresses for bottom left and top left corner for Lxx_2
compute_addr_2(13 downto 10) <= std_logic_vector(y2);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y7);
compute_addr_3(9 downto 0) <= std_logic_vector(x0);
-- write addresses to read bottom right corner and top right corner for Lxx_2/Lxx_1
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom left corner and top right corner for Lxy_3
bottom_left_1 <= unsigned(dout_0);
top_right_1 <= unsigned(dout_1);
-- compute determinant
det <= det_0 - det_1;
cycle <= "1110";
elsif cycle <= "1110" then
-- compute (x, y) top left and top right for Lyy_1/Lyy_0
y6 <= y-6;
-- compute addresses for top left and top right for Lyy_0
compute_addr_0(13 downto 10) <= std_logic_vector(y9);
compute_addr_0(9 downto 0) <= std_logic_vector(x0);
compute_addr_1(13 downto 10) <= std_logic_vector(y9);
compute_addr_1(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read bottom left corner and top left corner for Lxx_2
addr_0 <= compute_addr_2;
addr_1 <= compute_addr_3;
-- data ready, bottom right corner and top right corner for Lxx_0
bottom_right_0 <= unsigned(dout_0);
top_right_0 <= unsigned(dout_1);
-- compute Lxy_3
Lxy_3 <= bottom_right_1 - top_right_1 - bottom_left_1 + top_left_1;
-- absolute value determinant
if det < 0 then
det_abs <= -det;
else
det_abs <= det;
end if;
cycle <= "1111";
elsif cycle <= "1111" then
-- compute (x, y) top left and top right for Lyy_2/Lyy_1
y3 <= y-3;
-- compute addresses for top left and top right for Lyy_1/Lyy_0
compute_addr_2(13 downto 10) <= std_logic_vector(y6);
compute_addr_2(9 downto 0) <= std_logic_vector(x0);
compute_addr_3(13 downto 10) <= std_logic_vector(y6);
compute_addr_3(9 downto 0) <= std_logic_vector(x1);
-- write addresses to read top left corner and top right corner for Lyy_0
addr_0 <= compute_addr_0;
addr_1 <= compute_addr_1;
-- data ready, bottom right corner and top right corner for Lxx_1/Lxx_0
bottom_left_0 <= unsigned(dout_0);
top_left_0 <= unsigned(dout_1);
-- compute Lxy
Lxy <= signed(Lxy_0 - Lxy_1 + Lxy_2 - Lxy_3);
-- output hessian
hessian_out <= std_logic_vector(det_abs);
cycle <= "0000";
end if;
end if;
end if;
end if;
end process;
end Structural;
| mit | df5117898868dc0f73e9c1478b244c26 | 0.381741 | 4.897225 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/system_c_addsub_0_0_sim_netlist.vhdl | 1 | 32,611 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:06:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/system_c_addsub_0_0_sim_netlist.vhdl
-- Design : system_c_addsub_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_c_addsub_0_0_c_addsub_v12_0_10 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
CLK : in STD_LOGIC;
ADD : in STD_LOGIC;
C_IN : in STD_LOGIC;
CE : in STD_LOGIC;
BYPASS : in STD_LOGIC;
SCLR : in STD_LOGIC;
SSET : in STD_LOGIC;
SINIT : in STD_LOGIC;
C_OUT : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADD_MODE : integer;
attribute C_ADD_MODE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_AINIT_VAL : string;
attribute C_AINIT_VAL of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "0";
attribute C_A_TYPE : integer;
attribute C_A_TYPE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 10;
attribute C_BORROW_LOW : integer;
attribute C_BORROW_LOW of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 1;
attribute C_BYPASS_LOW : integer;
attribute C_BYPASS_LOW of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_B_CONSTANT : integer;
attribute C_B_CONSTANT of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "0000000000";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 10;
attribute C_CE_OVERRIDES_BYPASS : integer;
attribute C_CE_OVERRIDES_BYPASS of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 1;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_BYPASS : integer;
attribute C_HAS_BYPASS of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_C_IN : integer;
attribute C_HAS_C_IN of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_C_OUT : integer;
attribute C_HAS_C_OUT of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_SINIT : integer;
attribute C_HAS_SINIT of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_SSET : integer;
attribute C_HAS_SSET of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_OUT_WIDTH : integer;
attribute C_OUT_WIDTH of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 10;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 1;
attribute C_SINIT_VAL : string;
attribute C_SINIT_VAL of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "0";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "c_addsub_v12_0_10";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "yes";
end system_c_addsub_0_0_c_addsub_v12_0_10;
architecture STRUCTURE of system_c_addsub_0_0_c_addsub_v12_0_10 is
signal \<const0>\ : STD_LOGIC;
signal NLW_xst_addsub_C_OUT_UNCONNECTED : STD_LOGIC;
attribute C_BORROW_LOW of xst_addsub : label is 1;
attribute C_CE_OVERRIDES_BYPASS of xst_addsub : label is 1;
attribute C_CE_OVERRIDES_SCLR of xst_addsub : label is 0;
attribute C_IMPLEMENTATION of xst_addsub : label is 0;
attribute C_SCLR_OVERRIDES_SSET of xst_addsub : label is 1;
attribute C_VERBOSITY of xst_addsub : label is 0;
attribute C_XDEVICEFAMILY of xst_addsub : label is "zynq";
attribute c_a_type of xst_addsub : label is 0;
attribute c_a_width of xst_addsub : label is 10;
attribute c_add_mode of xst_addsub : label is 0;
attribute c_ainit_val of xst_addsub : label is "0";
attribute c_b_constant of xst_addsub : label is 0;
attribute c_b_type of xst_addsub : label is 0;
attribute c_b_value of xst_addsub : label is "0000000000";
attribute c_b_width of xst_addsub : label is 10;
attribute c_bypass_low of xst_addsub : label is 0;
attribute c_has_bypass of xst_addsub : label is 0;
attribute c_has_c_in of xst_addsub : label is 0;
attribute c_has_c_out of xst_addsub : label is 0;
attribute c_has_ce of xst_addsub : label is 0;
attribute c_has_sclr of xst_addsub : label is 0;
attribute c_has_sinit of xst_addsub : label is 0;
attribute c_has_sset of xst_addsub : label is 0;
attribute c_latency of xst_addsub : label is 0;
attribute c_out_width of xst_addsub : label is 10;
attribute c_sinit_val of xst_addsub : label is "0";
attribute downgradeipidentifiedwarnings of xst_addsub : label is "yes";
begin
C_OUT <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
xst_addsub: entity work.system_c_addsub_0_0_c_addsub_v12_0_10_viv
port map (
A(9 downto 0) => A(9 downto 0),
ADD => '0',
B(9 downto 0) => B(9 downto 0),
BYPASS => '0',
CE => '0',
CLK => '0',
C_IN => '0',
C_OUT => NLW_xst_addsub_C_OUT_UNCONNECTED,
S(9 downto 0) => S(9 downto 0),
SCLR => '0',
SINIT => '0',
SSET => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_c_addsub_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_c_addsub_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_c_addsub_0_0 : entity is "system_c_addsub_0_0,c_addsub_v12_0_10,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_c_addsub_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_c_addsub_0_0 : entity is "c_addsub_v12_0_10,Vivado 2016.4";
end system_c_addsub_0_0;
architecture STRUCTURE of system_c_addsub_0_0 is
signal NLW_U0_C_OUT_UNCONNECTED : STD_LOGIC;
attribute C_BORROW_LOW : integer;
attribute C_BORROW_LOW of U0 : label is 1;
attribute C_CE_OVERRIDES_BYPASS : integer;
attribute C_CE_OVERRIDES_BYPASS of U0 : label is 1;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of U0 : label is 0;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute c_a_type : integer;
attribute c_a_type of U0 : label is 0;
attribute c_a_width : integer;
attribute c_a_width of U0 : label is 10;
attribute c_add_mode : integer;
attribute c_add_mode of U0 : label is 0;
attribute c_ainit_val : string;
attribute c_ainit_val of U0 : label is "0";
attribute c_b_constant : integer;
attribute c_b_constant of U0 : label is 0;
attribute c_b_type : integer;
attribute c_b_type of U0 : label is 0;
attribute c_b_value : string;
attribute c_b_value of U0 : label is "0000000000";
attribute c_b_width : integer;
attribute c_b_width of U0 : label is 10;
attribute c_bypass_low : integer;
attribute c_bypass_low of U0 : label is 0;
attribute c_has_bypass : integer;
attribute c_has_bypass of U0 : label is 0;
attribute c_has_c_in : integer;
attribute c_has_c_in of U0 : label is 0;
attribute c_has_c_out : integer;
attribute c_has_c_out of U0 : label is 0;
attribute c_has_ce : integer;
attribute c_has_ce of U0 : label is 0;
attribute c_has_sclr : integer;
attribute c_has_sclr of U0 : label is 0;
attribute c_has_sinit : integer;
attribute c_has_sinit of U0 : label is 0;
attribute c_has_sset : integer;
attribute c_has_sset of U0 : label is 0;
attribute c_latency : integer;
attribute c_latency of U0 : label is 0;
attribute c_out_width : integer;
attribute c_out_width of U0 : label is 10;
attribute c_sinit_val : string;
attribute c_sinit_val of U0 : label is "0";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_c_addsub_0_0_c_addsub_v12_0_10
port map (
A(9 downto 0) => A(9 downto 0),
ADD => '1',
B(9 downto 0) => B(9 downto 0),
BYPASS => '0',
CE => '1',
CLK => '0',
C_IN => '0',
C_OUT => NLW_U0_C_OUT_UNCONNECTED,
S(9 downto 0) => S(9 downto 0),
SCLR => '0',
SINIT => '0',
SSET => '0'
);
end STRUCTURE;
| mit | 0b98d62e4365676bc706979962f51661 | 0.85327 | 2.125326 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/synth/system_vga_sync_reset_0_0.vhd | 2 | 4,935 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 27
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "vga_sync_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_reset_0_0_arch : ARCHITECTURE IS "system_vga_sync_reset_0_0,vga_sync_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "system_vga_sync_reset_0_0,vga_sync_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync_reset,x_ipVersion=1.0,x_ipCoreRevision=27,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
| mit | 8f61d03677a1b3d6ddd302bf2aa84d9e | 0.70618 | 3.64745 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/sim/system_zed_hdmi_0_0.vhd | 6 | 4,282 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_hdmi:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_hdmi_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END system_zed_hdmi_0_0;
ARCHITECTURE system_zed_hdmi_0_0_arch OF system_zed_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
clk_100 : IN STD_LOGIC;
active : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
rgb888 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hdmi_clk : OUT STD_LOGIC;
hdmi_hsync : OUT STD_LOGIC;
hdmi_vsync : OUT STD_LOGIC;
hdmi_d : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
hdmi_de : OUT STD_LOGIC;
hdmi_scl : OUT STD_LOGIC;
hdmi_sda : INOUT STD_LOGIC
);
END COMPONENT zed_hdmi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF hdmi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 hdmi_clk CLK";
BEGIN
U0 : zed_hdmi
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
clk_100 => clk_100,
active => active,
hsync => hsync,
vsync => vsync,
rgb888 => rgb888,
hdmi_clk => hdmi_clk,
hdmi_hsync => hdmi_hsync,
hdmi_vsync => hdmi_vsync,
hdmi_d => hdmi_d,
hdmi_de => hdmi_de,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
END system_zed_hdmi_0_0_arch;
| mit | 1b7bb9e533f8f8c6caae435a1d659f19 | 0.693601 | 3.769366 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ipshared/6c11/vga_sync.vhd | 1 | 3,664 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk_25 : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture Structural of vga_sync is
-- sync counters
signal v_count_reg, v_count_next: std_logic_vector(9 downto 0);
signal h_count_reg, h_count_next: std_logic_vector(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
-- registers
process (clk_25,rst)
begin
if rst='1' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
v_sync_reg <= '1';
h_sync_reg <= '1';
elsif (rising_edge(clk_25)) then
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- status
h_end <= -- end of horizontal counter
'1' when h_count_reg=(H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1) else --799
'0';
v_end <= -- end of vertical counter
'1' when v_count_reg=(V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg,h_end)
begin
h_count_next <= h_count_reg;
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg + 1;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg,h_end,v_end)
begin
if h_end='1' then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <=
'1' when (h_count_reg >= (H_SIZE + H_FRONT_DELAY)) --656
and (h_count_reg <= (H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY - 1)) else --751
'0';
v_sync_next <=
'1' when (v_count_reg>=(V_SIZE + V_FRONT_DELAY)) --490
and (v_count_reg<=(V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY - 1)) else --491
'0';
-- video on/off
active <=
'1' when (h_count_reg < H_SIZE) and (v_count_reg < V_SIZE) else
'0';
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
xaddr <= std_logic_vector(h_count_reg);
yaddr <= std_logic_vector(v_count_reg);
end Structural;
| mit | 42722794e853325e7f21879bd25d7466 | 0.508461 | 3.405204 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zybo_vga/zybo_vga.srcs/sources_1/new/zybo_vga.vhd | 2 | 1,222 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zybo_vga is
port(
clk : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(15 downto 0);
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end zybo_vga;
architecture Structural of zybo_vga is
signal r : std_logic_vector(4 downto 0) := "00000";
signal g : std_logic_vector(5 downto 0) := "000000";
signal b : std_logic_vector(4 downto 0) := "00000";
begin
process(clk)
begin
if falling_edge(clk) then
if active = '1' then
r <= rgb(15 downto 11);
g <= rgb(10 downto 5);
b <= rgb(4 downto 0);
end if;
end if;
end process;
vga_r <= r;
vga_g <= g;
vga_b <= b;
end Structural;
| mit | c1f96cca7b4f2c78e4596f70142d819c | 0.487725 | 3.92926 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 19,043 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 17:25:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | b359acc56b20af6c5fd83f8029581b95 | 0.491519 | 2.734492 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 195,699 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:47:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
pullup_MIO_0inst: unisim.vcomponents.PULLUP
port map (
O => MIO(0)
);
pullup_MIO_9inst: unisim.vcomponents.PULLUP
port map (
O => MIO(9)
);
pullup_MIO_10inst: unisim.vcomponents.PULLUP
port map (
O => MIO(10)
);
pullup_MIO_11inst: unisim.vcomponents.PULLUP
port map (
O => MIO(11)
);
pullup_MIO_12inst: unisim.vcomponents.PULLUP
port map (
O => MIO(12)
);
pullup_MIO_13inst: unisim.vcomponents.PULLUP
port map (
O => MIO(13)
);
pullup_MIO_14inst: unisim.vcomponents.PULLUP
port map (
O => MIO(14)
);
pullup_MIO_15inst: unisim.vcomponents.PULLUP
port map (
O => MIO(15)
);
pullup_MIO_46inst: unisim.vcomponents.PULLUP
port map (
O => MIO(46)
);
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 4acbb06563f028607b4b3414a6bb4da6 | 0.633948 | 2.762004 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/ov7670_controller/ov7670_controller.srcs/sources_1/imports/new/ov7670_controller.vhd | 6 | 2,356 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural; | mit | 2880b85f262bf680503148d761093fdf | 0.517402 | 4.10453 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_0_0/sim/system_vga_nmsuppression_0_0.vhd | 2 | 4,143 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_nmsuppression:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_nmsuppression_0_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_nmsuppression_0_0;
ARCHITECTURE system_vga_nmsuppression_0_0_arch OF system_vga_nmsuppression_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_nmsuppression_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_nmsuppression IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_nmsuppression;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_nmsuppression
GENERIC MAP (
ROW_WIDTH => 5
)
PORT MAP (
clk => clk,
enable => enable,
active => active,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
hessian_in => hessian_in,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out,
hessian_out => hessian_out
);
END system_vga_nmsuppression_0_0_arch;
| mit | 3f37078cb6bc655a1dcaaa3990f2526b | 0.709631 | 3.702413 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/i2c_sender.vhd | 7 | 7,166 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: i2c_sender h- Behavioral
--
-- Description: Send register writes over an I2C-like interface
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_sender is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC
);
end i2c_sender;
architecture Behavioral of i2c_sender is
signal divider : unsigned(8 downto 0) := (others => '0');
-- this value gives nearly 200ms cycles before the first register is written
signal initial_pause : unsigned(7 downto 0) := (others => '0');
signal finished : std_logic := '0';
signal address : std_logic_vector(7 downto 0) := (others => '0');
signal clk_first_quarter : std_logic_vector(28 downto 0) := (others => '1');
signal clk_last_quarter : std_logic_vector(28 downto 0) := (others => '1');
signal busy_sr : std_logic_vector(28 downto 0) := (others => '1');
signal data_sr : std_logic_vector(28 downto 0) := (others => '1');
signal tristate_sr : std_logic_vector(28 downto 0) := (others => '0');
signal reg_value : std_logic_vector(15 downto 0) := (others => '0');
constant i2c_wr_addr : std_logic_vector(7 downto 0) := x"72";
type reg_value_pair is ARRAY(0 TO 63) OF std_logic_vector(15 DOWNTO 0);
signal reg_value_pairs : reg_value_pair := (
-------------------
-- Powerup please!
-------------------
x"4110",
---------------------------------------
-- These values must be set as follows
---------------------------------------
x"9803", x"9AE0", x"9C30", x"9D61", x"A2A4", x"A3A4", x"E0D0", x"5512", x"F900",
---------------
-- Input mode
---------------
x"1506", -- YCbCr 422, DDR, External sync
x"4810", -- Left justified data (D23 downto 8)
x"1637", -- 444 output, 8 bit style 2, 1st half on rising edge - YCrCb clipping
x"1700", -- output aspect ratio 16:9, external DE
x"D03C", -- auto sync data - must be set for DDR modes. No DDR clock delay
---------------
-- Output mode
---------------
x"AF04", -- DVI mode
x"4c04", -- Deep colour off (HDMI only?) - not needed
x"4000", -- Turn off additional data packets - not needed
--------------------------------------------------------------
-- Here is the YCrCb => RGB conversion, as per programming guide
-- This is table 57 - HDTV YCbCr (16 to 255) to RGB (0 to 255)
--------------------------------------------------------------
-- (Cr * A1 + Y * A2 + Cb * A3)/4096 + A4 = Red
x"18E7", x"1934", x"1A04", x"1BAD", x"1C00", x"1D00", x"1E1C", x"1F1B",
-- (Cr * B1 + Y * B2 + Cb * B3)/4096 + B4 = Green
x"201D", x"21DC", x"2204", x"23AD", x"241F", x"2524", x"2601", x"2735",
-- (Cr * C1 + Y * C2 + Cb * C3)/4096 + C4 = Blue
x"2800", x"2900", x"2A04", x"2BAD", x"2C08", x"2D7C", x"2E1B", x"2F77",
-- Extra space filled with FFFFs to signify end of data
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF",
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF",
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF"
);
begin
registers: process(clk)
begin
if rising_edge(clk) then
reg_value <= reg_value_pairs(to_integer(unsigned(address)));
end if;
end process;
i2c_tristate: process(data_sr, tristate_sr)
begin
if tristate_sr(tristate_sr'length-1) = '0' then
siod <= data_sr(data_sr'length-1);
else
siod <= 'Z';
end if;
end process;
with divider(divider'length-1 downto divider'length-2)
select sioc <= clk_first_quarter(clk_first_quarter'length -1) when "00",
clk_last_quarter(clk_last_quarter'length -1) when "11",
'1' when others;
i2c_send: process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
clk_first_quarter <= (others => '1');
clk_last_quarter <= (others => '1');
busy_sr <= (others => '0');
divider <= (others => '0');
initial_pause <= (others => '0');
finished <= '0';
end if;
if busy_sr(busy_sr'length-1) = '0' then
if initial_pause(initial_pause'length-1) = '0' then
initial_pause <= initial_pause+1;
elsif finished = '0' then
if divider = "11111111" then
divider <= (others =>'0');
if reg_value(15 downto 8) = "11111111" then
finished <= '1';
else
-- move the new data into the shift registers
clk_first_quarter <= (others => '0'); clk_first_quarter(clk_first_quarter'length-1) <= '1';
clk_last_quarter <= (others => '0'); clk_last_quarter(0) <= '1';
-- Start Address Ack Register Ack Value Ack Stop
tristate_sr <= "0" & "00000000" & "1" & "00000000" & "1" & "00000000" & "1" & "0";
data_sr <= "0" & i2c_wr_addr & "1" & reg_value(15 downto 8) & "1" & reg_value( 7 downto 0) & "1" & "0";
busy_sr <= (others => '1');
address <= std_logic_vector(unsigned(address)+1);
end if;
else
divider <= divider+1;
end if;
end if;
else
if divider = "11111111" then -- divide clkin by 256 for I2C
tristate_sr <= tristate_sr(tristate_sr'length-2 downto 0) & '0';
busy_sr <= busy_sr(busy_sr'length-2 downto 0) & '0';
data_sr <= data_sr(data_sr'length-2 downto 0) & '1';
clk_first_quarter <= clk_first_quarter(clk_first_quarter'length-2 downto 0) & '1';
clk_last_quarter <= clk_last_quarter(clk_first_quarter'length-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | c730e6732a899d64683c3ef085c2eff4 | 0.44753 | 3.740084 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_0/synth/affine_block_ieee754_fp_to_uint_0_0.vhd | 2 | 3,943 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_0;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_0_arch OF affine_block_ieee754_fp_to_uint_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_to_uint_0_0_arch: ARCHITECTURE IS "ieee754_fp_to_uint,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_to_uint_0_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_to_uint_0_0,ieee754_fp_to_uint,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_to_uint_0_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_to_uint_0_0,ieee754_fp_to_uint,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_to_uint,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=10}";
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_0_arch;
| mit | 5a76e0c285b058faffe17d71647ec445 | 0.739031 | 3.644177 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/sim/sqrt.vhd | 1 | 7,160 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY sqrt IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END sqrt;
ARCHITECTURE sqrt_arch OF sqrt IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sqrt_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 6,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 1,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 16,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END sqrt_arch;
| mit | 14974f7f9d17d233ecf913ac1067f5b0 | 0.668715 | 3.40466 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/div_seq-rtl.vhdl | 1 | 1,650 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of div_seq is
begin
div : entity work.div_seq_inferred(rtl)
generic map (
latency => latency,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
en => en,
unsgnd => unsgnd,
src1 => src1,
src2 => src2,
valid => valid,
dbz => dbz,
overflow => overflow,
result => result
);
end;
| apache-2.0 | 9aab5154d8e3bf26b1c2cb9fe6f4f71e | 0.473939 | 5.076923 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_sim_netlist.vhdl | 1 | 70,948 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_1_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_1_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_1_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_1_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_1_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_1_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_1_0 : entity is "system_ov7670_controller_1_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_1_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_1_0;
architecture STRUCTURE of system_ov7670_controller_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_1_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 4b3bc540870c4ed3b7ec0b680468d25b | 0.53277 | 2.812161 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_3/system_xlconstant_0_3_sim_netlist.vhdl | 1 | 1,874 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 12:45:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_xlconstant_0_3 -prefix
-- system_xlconstant_0_3_ system_xlconstant_0_3_sim_netlist.vhdl
-- Design : system_xlconstant_0_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xlconstant_0_3 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xlconstant_0_3 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_xlconstant_0_3 : entity is "yes";
end system_xlconstant_0_3;
architecture STRUCTURE of system_xlconstant_0_3 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
dout(9) <= \<const0>\;
dout(8) <= \<const0>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const1>\;
dout(3) <= \<const0>\;
dout(2) <= \<const1>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 8f383b435bfd912f94a6ca7a41936b15 | 0.602455 | 3.832311 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s8.vhd | 2 | 3,965 | library ieee;
use ieee.std_logic_1164.all;
entity s8 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s8;
architecture behaviour of s8 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
end case;
end process;
end; | mit | fbbce7f2b2bcbf8876b2e9d0756ac382 | 0.675914 | 3.019802 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70,017 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:54 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 11c38effad50d2a1164d8ae711a75b29 | 0.531728 | 2.810573 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/IIR_Biquad_II_v3.vhd | 4 | 10,813 | --/////////////////////////////////////////////////IIR_Biquad////////////////////////////////////////////////////////////
-- FileName: IIR_Biquad_II_v3.vhd
-- This is a direct Form1, 2nd Order IIR Filter. This code was created from the original version which you can find at:
-- https://eewiki.net/display/LOGIC/IIR+Filter+Design+in+VHDL+Targeted+for+18-Bit,+48+KHz+Audio+Signal+Use#IIRFilterDesigninVHDLTargetedfor18-Bit,48KHzAudioSignalUse-InstantiatingtheIIR_Biquad.vhdFilterModule
-- Credit must be given to Tony Storey of DIGI-KEY for providing the original code upon which this version has been created from.
--
-- Original Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
--
-- Current Version History
-- Version 3.0 27/05/2015 Ovie, Tsotne, Juri, and Silvester.
--
-- A lot of changes and updates have been made to this version. This version uses a single "shift add" multiplier instead of five DSP multipliers.
-- This version has a reduced area size due to the scheduling and sharing of resource, but with a trade off of time.
--
--
-- IIR_Biquad_II_v3.vhd IS PROVIDED "AS IS." WE EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL WE
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- WE ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
--/////////////////////////////////Recommendations on how to use this component.///////////////////////////////////////////
-- The current configuration has coefficient width of 32 bits and sample data width of 32 bits (24 bits but padded with zeros)
-- , it takes approximately 350 clock circles to perform a
-- single filter operation. With this configuration the approximate minimum frequency of operation of the filter should be
-- 16.8Mhz
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v3 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (23 downto 0)
);
end IIR_Biquad_II_v3;
architecture arch of IIR_Biquad_II_v3 is
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : signed( 63 downto 0) := (others => '0');
signal mul_result, pgZFF_X0_quad_0, pgZFF_X1_quad_1, pgZFF_X2_quad_2, pgZFF_Y1_quad_1, pgZFF_Y2_quad_2 : signed( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
signal counter: integer:=1;
signal rst_cnt, s_trigger, s_multiply: std_logic;
constant shiftAddMultiply: boolean:=true;
constant DSPMultiply: boolean:=false;
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out, cnt, Mul_stage_over, Mul_Ready, Mul_Ready1, Mul_Ready2, Mul_Ready3, Mul_Ready4, Mul_Ready5 : std_logic;
signal ZFF, Coef: std_logic_vector(31 downto 0) := (others => '0');
begin
-- process to shift samples
process(clk, rst, Y_out_double, sample_trig)
begin
if(rising_edge(clk)) then
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
else
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(23) & X_in(23) & X_in & B"0000_00";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, rst)
begin
if (rising_edge(clk)) then
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
else
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 2 when q_add = '1' and q_reg = 1 else q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig,Mul_Ready,Mul_stage_over)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
rst_cnt <= '1';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
rst_cnt <= '0'; -- allow counter to run so that it can count how many multiplication has been performed.
mul_coefs <= '1';
q_add <= '0';
-- seize the counter from counting until
if Mul_stage_over = '1' then -- multiplication is done.
q_add <= '1';
end if;
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
--Mul_Ready<= Mul_Ready1 and Mul_Ready2 and Mul_Ready3 and Mul_Ready4 and Mul_Ready5;
mul: entity work.multiplier
generic map(
MultiplierIsShiftAdd=> shiftAddMultiply, --DSPMultiply,--
BIT_WIDTH => 32,COUNT_WIDTH => 6)
Port map (CLK => CLK, TRIGGER => s_multiply, A => signed(Coef), B => signed(ZFF), RES => mul_result, READY => Mul_Ready);
s_multiply <= mul_coefs and s_trigger;
Count_Multiplication: process(clk,rst_cnt,mul_coefs,Mul_Ready) begin
--if rising_edge(clk) then
if rst_cnt = '1' or rst = '1' then
counter <= 0;
elsif rising_edge(Mul_Ready) then
if mul_coefs = '1' then
counter <= counter + 1;
end if;
end if;
--end if;
end process;
--Mul_stage_over <= '1' when counter = 5 else '0';
Stage_input_values_for_multiplier:process(counter,Coef_b0,Coef_b1, Coef_b2, Coef_a1, Coef_a2, ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2)
begin
case counter is
when 0 =>
Coef <= Coef_b0;
ZFF <= ZFF_X0;
when 1 =>
Coef <= Coef_b1;
ZFF <= ZFF_X1;
when 2 =>
Coef <= Coef_b2;
ZFF <= ZFF_X2;
when 3 =>
Coef <= Coef_a1;
ZFF <= ZFF_Y1;
when 4 =>
Coef <= Coef_a2;
ZFF <= ZFF_Y2;
when others =>
Coef <= (others => '0');
ZFF <= (others => '0');
end case;
end process;
Stage_Multiplication_Result: process(clk,counter,mul_result,Mul_Ready)
begin
if rising_edge(clk) then
if rst = '1' then
pgZFF_X0_quad <= (others => '0');
pgZFF_X1_quad <= (others => '0');
pgZFF_X2_quad <= (others => '0');
pgZFF_Y1_quad <= (others => '0');
pgZFF_Y2_quad <= (others => '0');
s_trigger <= '1';
else
s_trigger <= '1';
Mul_stage_over <= '0';
case counter is
when 1 =>
if Mul_Ready = '1' then
pgZFF_X0_quad <= mul_result;
s_trigger <= '0';
end if;
when 2 =>
if Mul_Ready = '1' then
pgZFF_X1_quad <= mul_result;
s_trigger <= '0';
end if;
when 3 =>
if Mul_Ready = '1' then
pgZFF_X2_quad <= mul_result;
s_trigger <= '0';
end if;
when 4 =>
if Mul_Ready = '1' then
pgZFF_Y1_quad <= mul_result;
s_trigger <= '0';
end if;
when 5 =>
if Mul_Ready = '1' then
pgZFF_Y2_quad <= mul_result;
--s_trigger <= '0';
Mul_stage_over <= '1';
end if;
when others =>
-- pgZFF_X0_quad <= (others => '0');
-- pgZFF_X1_quad <= (others => '0');
-- pgZFF_X2_quad <= (others => '0');
-- pgZFF_Y1_quad <= (others => '0');
-- pgZFF_Y2_quad <= (others => '0');
end case;
end if;
end if;
end process;
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= std_logic_vector(pgZFF_X0_quad(61 downto 30));
pgZFF_X2 <= std_logic_vector(pgZFF_X2_quad(61 downto 30));
pgZFF_X1 <= std_logic_vector(pgZFF_X1_quad(61 downto 30));
pgZFF_Y1 <= std_logic_vector(pgZFF_Y1_quad(61 downto 30));
pgZFF_Y2 <= std_logic_vector(pgZFF_Y2_quad(61 downto 30));
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 7);
end if;
end if;
end process;
end arch; | mit | aee2a8db421d4266bfe1e3deb71e4d1e | 0.577176 | 2.993632 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/rgb888_to_g8/rgb888_to_g8.srcs/sources_1/new/rgb888_to_g8.vhd | 5 | 711 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb888_to_g8 is
port (
clk : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
g8 : out std_logic_vector(7 downto 0)
);
end rgb888_to_g8;
architecture Behavioral of rgb888_to_g8 is
begin
process(clk)
variable r, g, b : integer := 0;
begin
if rising_edge(clk) then
r := to_integer(unsigned(rgb888(23 downto 16)));
g := to_integer(unsigned(rgb888(15 downto 8)));
b := to_integer(unsigned(rgb888(7 downto 0)));
g8 <= std_logic_vector(to_unsigned((r + g + b)/3, 8));
end if;
end process;
end Behavioral;
| mit | 68162a16dc8afba65615af5f64ae46e0 | 0.578059 | 3.276498 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl | 1 | 4,331 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
| mit | 4580cdfe0e836782b3ffe090395beb86 | 0.554145 | 2.924375 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/cordic_v6_0_vh_rfs.vhd | 2 | 587,436 | `protect begin_protected
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| mit | 5646bb654b225a3860bd3b677bf790be | 0.955542 | 1.807323 | false | false | false | false |
pgavin/carpe | proj/cpu_or1knd_i5_min_sim/hdl/cpu_or1knd_i5_min_sim/cpu_or1knd_i5_min_sim_top-behav.vhdl | 1 | 16,507 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- CARPE OR1KND in-order 5-stage minimal simulator
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.types_pkg.all;
use util.io_pkg.all;
use util.numeric_pkg.all;
use util.logic_pkg.all;
use util.names_pkg.all;
library isa;
use isa.or1k_pkg.all;
library sys;
use sys.sys_config_pkg.all;
use sys.sys_pkg.all;
library cpu_or1knd_i5;
use cpu_or1knd_i5.cpu_or1knd_i5_config_pkg.all;
use cpu_or1knd_i5.cpu_or1knd_i5_pkg.all;
library sim;
use sim.options_pkg.all;
use sim.monitor_pkg.all;
library tech;
use work.cpu_or1knd_i5_min_sim_config_pkg.all;
architecture behav of cpu_or1knd_i5_min_sim_top is
type request_type is record
valid : std_ulogic;
size : sys_transfer_size_type;
be : std_ulogic;
write : std_ulogic;
cacheable : std_ulogic;
priv : std_ulogic;
inst : std_ulogic;
burst : std_ulogic;
bwrap : std_ulogic;
bcycles : sys_burst_cycles_type;
paddr : sys_paddr_type;
data : sys_bus_type;
eta : std_ulogic_vector(cpu_or1knd_i5_min_sim_mem_latency-1 downto 0);
burst_status : std_ulogic_vector(sys_max_burst_cycles-1 downto 0);
end record;
constant request_init : request_type := (
valid => '0',
size => (others => 'X'),
be => 'X',
write => 'X',
cacheable => 'X',
priv => 'X',
inst => 'X',
burst => 'X',
bwrap => 'X',
bcycles => (others => 'X'),
paddr => (others => 'X'),
data => (others => 'X'),
eta => (others => 'X'),
burst_status => (others => 'X')
);
type comb_type is record
sys_master_ctrl_out : sys_master_ctrl_out_type;
sys_master_dp_out : sys_master_dp_out_type;
sys_slave_ctrl_out : sys_slave_ctrl_out_type;
sys_slave_dp_out : sys_slave_dp_out_type;
a_new_request_bcycles_dec : std_ulogic_vector(sys_max_burst_cycles-1 downto 0);
a_new_request_burst_status : std_ulogic_vector(sys_max_burst_cycles-1 downto 0);
a_mem_en : std_ulogic;
a_burst : std_ulogic;
a_request : request_type;
a_request_fast : std_ulogic;
b_request_complete : std_ulogic;
b_mem_dout : sys_bus_type;
end record;
signal c : comb_type;
type register_type is record
b_request : request_type;
b_burst : std_ulogic;
end record;
constant r_init : register_type := (
b_request => request_init,
b_burst => '0'
);
signal r, r_next : register_type;
signal clk : std_ulogic := '0';
signal rstn : std_ulogic := '1';
procedure process_monitor_events(file monitor_output_file : text;
variable monitor_exit : out boolean) is
variable l : line;
begin
while monitor_has_event loop
case monitor_event_code is
when monitor_event_code_error =>
when monitor_event_code_cycle =>
when monitor_event_code_reset =>
when monitor_event_code_exit =>
monitor_exit := true;
when monitor_event_code_watch =>
end case;
write(l,
string'("""") &
time'image(monitor_event_timestamp) &
string'(""" """) &
monitor_event_instance &
string'(""" ")
);
case monitor_event_code is
when monitor_event_code_error =>
write(l, string'("error"));
when monitor_event_code_cycle =>
write(l, string'("cycle"));
when monitor_event_code_reset =>
write(l, string'("reset"));
when monitor_event_code_exit =>
write(l, string'("exit"));
when monitor_event_code_watch =>
write(l, string'("watch"));
end case;
write(l,
string'(" """) &
monitor_event_name &
string'(""" """)
);
write(l,
monitor_event_data);
write(l,
string'("""")
);
writeline(monitor_output_file, l);
deallocate(l);
monitor_event_finish;
end loop;
end;
begin
c.b_request_complete <= (
not r.b_request.valid or
r.b_request.eta(cpu_or1knd_i5_min_sim_mem_latency-1)
);
c.a_request.valid <= (
(r.b_request.valid and not c.b_request_complete) or
c.sys_master_ctrl_out.request
);
with c.b_request_complete select
c.a_request.size <= c.sys_master_dp_out.size when '1',
r.b_request.size when '0',
(others => 'X') when others;
with c.b_request_complete select
c.a_request.be <= c.sys_master_ctrl_out.be when '1',
r.b_request.be when '0',
'X' when others;
with c.b_request_complete select
c.a_request.write <= c.sys_master_ctrl_out.write when '1',
r.b_request.write when '0',
'X' when others;
with c.b_request_complete select
c.a_request.cacheable <= c.sys_master_ctrl_out.cacheable when '1',
r.b_request.cacheable when '0',
'X' when others;
with c.b_request_complete select
c.a_request.priv <= c.sys_master_ctrl_out.priv when '1',
r.b_request.priv when '0',
'X' when others;
with c.b_request_complete select
c.a_request.inst <= c.sys_master_ctrl_out.inst when '1',
r.b_request.inst when '0',
'X' when others;
with c.b_request_complete select
c.a_request.burst <= c.sys_master_ctrl_out.burst when '1',
r.b_request.burst when '0',
'X' when others;
with c.b_request_complete select
c.a_request.bwrap <= c.sys_master_ctrl_out.bwrap when '1',
r.b_request.bwrap when '0',
'X' when others;
with c.b_request_complete select
c.a_request.bcycles <= c.sys_master_ctrl_out.bcycles when '1',
r.b_request.bcycles when '0',
(others => 'X') when others;
with c.b_request_complete select
c.a_request.paddr <= c.sys_master_dp_out.paddr when '1',
r.b_request.paddr when '0',
(others => 'X') when others;
with c.b_request_complete select
c.a_request.data <= c.sys_master_dp_out.data when '1',
r.b_request.data when '0',
(others => 'X') when others;
a_request_eta_gen_gt_1 : if cpu_or1knd_i5_min_sim_mem_latency > 1 generate
c.a_request_fast <= logic_if(c.a_request.write, c.a_request.burst, r.b_burst);
with c.b_request_complete select
c.a_request.eta <=
(cpu_or1knd_i5_min_sim_mem_latency-1 => c.a_request_fast,
0 => not c.a_request_fast,
others => '0'
) when '1',
(r.b_request.eta(cpu_or1knd_i5_min_sim_mem_latency-2 downto 0) & '0') when '0',
(others => 'X') when others;
end generate;
a_request_eta_gen_eq_1 : if cpu_or1knd_i5_min_sim_mem_latency <= 1 generate
c.a_request.eta(0) <= '1';
end generate;
c.a_burst <= logic_if(c.b_request_complete and c.a_request.valid,
c.a_request.burst,
r.b_burst);
a_new_request_bcycles_decoder : entity tech.decoder(rtl)
generic map (
output_bits => sys_max_burst_cycles
)
port map (
datain => c.sys_master_ctrl_out.bcycles,
dataout => c.a_new_request_bcycles_dec
);
with r.b_request.burst select
c.a_new_request_burst_status <= ('X' & r.b_request.burst_status(sys_max_burst_cycles-1 downto 1)) when '1',
c.a_new_request_bcycles_dec when '0',
(others => 'X') when others;
with c.b_request_complete select
c.a_request.burst_status <= c.a_new_request_burst_status when '1',
r.b_request.burst_status when '0',
(others => 'X') when others;
c.a_mem_en <= c.a_request.valid and c.a_request.eta(cpu_or1knd_i5_min_sim_mem_latency-1);
c.sys_slave_ctrl_out <= (
ready => c.b_request_complete,
error => '0'
);
c.sys_slave_dp_out <= (
data => c.b_mem_dout
);
r_next.b_request <= c.a_request;
r_next.b_burst <= c.a_burst;
core : entity cpu_or1knd_i5.cpu_or1knd_i5_core(rtl)
port map (
clk => clk,
rstn => rstn,
sys_master_ctrl_out => c.sys_master_ctrl_out,
sys_master_dp_out => c.sys_master_dp_out,
sys_slave_ctrl_out => c.sys_slave_ctrl_out,
sys_slave_dp_out => c.sys_slave_dp_out
);
a_mem_en_watch : block
signal watch_data : std_ulogic_vector(0 downto 0);
begin
watch_data <= (0 => c.a_mem_en);
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "a_mem_en",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
a_mem_write_watch : block
signal watch_data : std_ulogic_vector(0 downto 0);
begin
watch_data <= (0 => c.a_request.write);
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "a_mem_write",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
a_mem_be_watch : block
signal watch_data : std_ulogic_vector(0 downto 0);
begin
watch_data <= (0 => c.a_request.be);
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "a_mem_be",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
a_mem_size_watch : block
signal watch_data : std_ulogic_vector(c.a_request.size'length-1 downto 0);
begin
watch_data <= c.a_request.size;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "a_mem_size",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
a_mem_paddr_watch : block
signal watch_data : std_ulogic_vector(c.a_request.paddr'length-1 downto 0);
begin
watch_data <= c.a_request.paddr;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "a_mem_paddr",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
a_mem_din_watch : block
signal watch_data : std_ulogic_vector(c.a_request.data'length-1 downto 0);
begin
watch_data <= c.a_request.data;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "a_mem_din",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
mem : entity sim.mem_1rw(behav)
generic map (
addr_bits => sys_paddr_bits,
log2_bus_bytes => sys_log2_bus_bytes
)
port map (
clk => clk,
rstn => rstn,
en => c.a_mem_en,
we => c.a_request.write,
be => c.a_request.be,
size => c.a_request.size,
addr => c.a_request.paddr,
din => c.a_request.data,
dout => c.b_mem_dout
);
b_mem_dout_watch : block
signal watch_data : std_ulogic_vector(c.a_request.data'length-1 downto 0);
begin
watch_data <= c.a_request.data;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => entity_path_name(cpu_or1knd_i5_min_sim_top'path_name),
name => "b_mem_dout",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
seq : process (clk) is
begin
if rising_edge(clk) then
if rstn = '0' then
r <= r_init;
else
r <= r_next;
end if;
end if;
end process;
run : process is
variable monitor_output_filename : line;
file monitor_output : text;
variable monitor_exit : boolean;
variable cycle_source : monitor_event_source_id_type;
variable reset_source : monitor_event_source_id_type;
begin
report "options_filename: " & options_filename;
options_read(options_filename);
options_ready <= true;
wait for 0 ns;
if option(entity_path_name(cpu_or1knd_i5_min_sim_top'path_name) & ":monitor_enable") = "true" then
report "enabling monitor for " & cpu_or1knd_i5_min_sim_top'path_name;
monitor_output_filename := new string'(option(entity_path_name(cpu_or1knd_i5_min_sim_top'path_name) & ":monitor_output_filename"));
assert monitor_output_filename.all /= ""
report entity_path_name(cpu_or1knd_i5_min_sim_top'path_name) & ":monitor_output_filename is not set"
severity failure;
file_open(monitor_output, monitor_output_filename.all, write_mode);
deallocate(monitor_output_filename);
monitor_enable <= true;
cycle_source := monitor_event_source(entity_path_name(cpu_or1knd_i5_min_sim_top'path_name), monitor_event_code_cycle, "");
reset_source := monitor_event_source(entity_path_name(cpu_or1knd_i5_min_sim_top'path_name), monitor_event_code_reset, "");
end if;
clk <= '0';
rstn <= '0';
wait for 1000 ps;
clk <= '1';
wait for 250 ps;
rstn <= '1';
wait for 250 ps;
clk <= '0';
wait for 500 ps;
if monitor_enable then
monitor_event(reset_source, "");
end if;
while not monitor_exit loop
clk <= not clk;
wait for 500 ps;
if monitor_enable and clk = '0' then
monitor_event(cycle_source, "");
process_monitor_events(monitor_output, monitor_exit);
end if;
end loop;
monitor_finish;
wait;
end process;
end;
| apache-2.0 | 16b94288235aaec97454fc98fe5ad025 | 0.522445 | 3.550656 | false | false | false | false |
loa-org/loa-hdl | modules/utils/hdl/utils_pkg.vhd | 1 | 5,036 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package utils_pkg is
-- Calculates the number of bits required to encode the given number
--
-- Note that this function is not intended to synthesize directly into
-- hardware, rather it is used to generate constants for synthesized
-- hardware.
--
-- Example:
-- entity foo is
-- generic(
-- ABC : positive);
-- port(
-- xzy : out std_logic_vector(required_bits(ABC) downto 0));
-- end foo;
function required_bits (value : natural) return natural;
-- Another function which does the same, up to 32 bits
function log2 (val : integer) return natural;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer;
function minn(L : integer;
R : integer)
return integer;
----------------------------------------------------------------------------
-- replacement for std_logic_arith
-- works with unsigneds
-- see http://www.lothar-miller.de/s9y/archives/14-Numeric_Std.html
function conv_integer(
vec : std_logic_vector)
return integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector;
----------------------------------------------------------------------------
component clock_divider is
generic (
DIV : positive);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component;
-- Requires MUL <= DIV
component fractional_clock_divider is
generic (
DIV : positive;
MUL : positive;
WIDTH : positive := 16);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider;
-- Requires mul <= div
component fractional_clock_divider_variable is
generic (
WIDTH : positive);
port (
div : in std_logic_vector(WIDTH-1 downto 0);
mul : in std_logic_vector(WIDTH-1 downto 0);
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider_variable;
----------------------------------------------------------------------------
component event_hold_stage is
port (
dout_p : out std_logic;
din_p : in std_logic;
period_p : in std_logic;
clk : in std_logic);
end component event_hold_stage;
component edge_detect is
port (
async_sig : in std_logic;
clk : in std_logic;
rise : out std_logic;
fall : out std_logic);
end component edge_detect;
----------------------------------------------------------------------------
component dff is
port (
dout_p : out std_logic;
din_p : in std_logic;
set_p : in std_logic;
reset_p : in std_logic;
ce_p : in std_logic;
clk : in std_logic);
end component dff;
end package utils_pkg;
package body utils_pkg is
function required_bits (value : natural) return natural is
begin
if value <= 0 then
return 0;
elsif value = 1 then
return 1;
elsif value < 8 then
return integer(ceil(log2(real(value))));
else
-- FIXME: Why is this hack necessary?
-- Otherwise the values for 2**x (x >= 3) are calculated wrong.
-- E.g.:
-- required_bits(8) = 3 != 4
-- required_bits(16) = 4 != 5
-- see ../tb/utils_tb.vhd
return integer(ceil(log2(real(value) + 0.5)));
end if;
end function;
function log2 (val : integer) return natural is
variable res : positive;
begin -- log2
for i in 1 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop; -- i
return res;
end log2;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer is
begin -- max
if L > R then
return L;
else
return R;
end if;
end max;
function minn(L : integer;
R : integer)
return integer is
begin -- min
if L < R then
return L;
else
return R;
end if;
end minn;
----------------------------------------------------------------------------
function conv_integer(
vec : std_logic_vector)
return integer is
begin
return to_integer(unsigned(vec));
end conv_integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector is
begin -- conv_std_logic_vector
return std_logic_vector(to_unsigned(int, len));
end conv_std_logic_vector;
end package body utils_pkg;
| bsd-3-clause | 840e070931bee86c87610ad8994ef5a5 | 0.493844 | 4.304274 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_buffer_addressable/vga_buffer_addressable.srcs/sources_1/new/vga_buffer_addressable.vhd | 1 | 1,971 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_buffer_addressable - Structural
-- Description: Read and buffer vga data in an addressable queue
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_buffer_addressable is
generic(
H_SIZE : integer := 640;
H_DELAY : integer := 160;
ROWS : integer := 24
);
port(
clk_25 : in std_logic;
reset : in std_logic;
rgb_in: in std_logic_vector(23 downto 0);
xaddr_in : in std_logic_vector(9 downto 0);
yaddr_in : in std_logic_vector(9 downto 0);
rgb_out: out std_logic_vector(23 downto 0)
);
end vga_buffer_addressable;
architecture Structural of vga_buffer_addressable is
type RGB_BUFFER is array ((H_SIZE + H_DELAY) * ROWS - 1 downto 0) of std_logic_vector(23 downto 0);
begin
process(clk_25)
variable rgb_buffer_inst : RGB_BUFFER;
variable offset : integer := 0;
variable index : integer;
begin
if rising_edge(clk_25) then
index := to_integer(unsigned(yaddr_in)) * (H_SIZE + H_DELAY) + to_integer(unsigned(xaddr_in)) + offset;
rgb_out <= rgb_buffer_inst(index);
for i in (H_SIZE + H_DELAY) * ROWS - 1 downto 1 loop
rgb_buffer_inst(i) := rgb_buffer_inst(i - 1);
end loop;
rgb_buffer_inst(0) := rgb_in;
offset := offset + 1;
if reset = '1' then
offset := 0;
for i in (H_SIZE + H_DELAY) * ROWS - 1 downto 0 loop
rgb_buffer_inst(i) := x"000000";
end loop;
end if;
end if;
end process;
end Structural;
| mit | fe845e006b2dcc8431e483e5bc8765b8 | 0.511416 | 3.965795 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_laplacian_fusion/vga_laplacian_fusion.srcs/sources_1/new/vga_laplacian_fusion.vhd | 2 | 2,510 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: vga_laplacian_fusion - Structural
-- Description: Use the laplacian difference to weight two values and create a fused output
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_laplacian_fusion is
port(
clk_25 : in std_logic;
rgb_blur_0 : in std_logic_vector(23 downto 0);
rgb_pass_0 : in std_logic_vector(23 downto 0);
rgb_blur_1 : in std_logic_vector(23 downto 0);
rgb_pass_1 : in std_logic_vector(23 downto 0);
rgb_out : out std_logic_vector(23 downto 0)
);
end vga_laplacian_fusion;
architecture Structural of vga_laplacian_fusion is
begin
process(clk_25)
variable r_0, g_0, b_0, r_1, g_1, b_1 : integer;
variable r_diff_0, g_diff_0, b_diff_0, r_diff_1, g_diff_1, b_diff_1 : integer;
begin
if rising_edge(clk_25) then
r_0 := to_integer(unsigned(rgb_pass_0(23 downto 16)));
g_0 := to_integer(unsigned(rgb_pass_0(15 downto 8)));
b_0 := to_integer(unsigned(rgb_pass_0(7 downto 0)));
r_1 := to_integer(unsigned(rgb_pass_1(23 downto 16)));
g_1 := to_integer(unsigned(rgb_pass_1(15 downto 8)));
b_1 := to_integer(unsigned(rgb_pass_1(7 downto 0)));
r_diff_0 := r_0 - to_integer(unsigned(rgb_blur_0(23 downto 16)));
g_diff_0 := g_0 - to_integer(unsigned(rgb_blur_0(15 downto 8)));
b_diff_0 := b_0 - to_integer(unsigned(rgb_blur_0(7 downto 0)));
r_diff_1 := r_1 - to_integer(unsigned(rgb_blur_1(23 downto 16)));
g_diff_1 := g_1 - to_integer(unsigned(rgb_blur_1(15 downto 8)));
b_diff_1 := b_1 - to_integer(unsigned(rgb_blur_1(7 downto 0)));
rgb_out(23 downto 16) <= std_logic_vector(to_unsigned(r_0 * (r_diff_0 / (r_diff_0 + r_diff_1)) + r_1 * (r_diff_1 / (r_diff_0 + r_diff_1)), 8));
rgb_out(15 downto 8) <= std_logic_vector(to_unsigned(g_0 * (g_diff_0 / (g_diff_0 + g_diff_1)) + g_1 * (g_diff_1 / (g_diff_0 + g_diff_1)), 8));
rgb_out(7 downto 0) <= std_logic_vector(to_unsigned(b_0 * (b_diff_0 / (b_diff_0 + b_diff_1)) + b_1 * (b_diff_1 / (b_diff_0 + b_diff_1)), 8));
end if;
end process;
end Structural;
| mit | 3e58b3d829536d089ad35f32944669a4 | 0.533865 | 3.020457 | false | false | false | false |
sbourdeauducq/dspunit | sim/gen_rom.vhd | 2 | 4,104 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2006-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL ;
use work.rompkg.all;
-------------------------------------------------------------------------------
entity gen_rom is
generic (
addr_width : natural := 11;
data_width : natural := 8;
init_file : STRING
);
port (
--@inputs
address : in std_logic_vector((addr_width - 1) downto 0);
clk : in std_logic;
--@outputs;
q : out std_logic_vector((data_width - 1) downto 0)
);
end gen_rom;
--=----------------------------------------------------------------------------
architecture archi_gen_rom of gen_rom is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type memType is array((2**addr_width - 1) downto 0) of std_logic_vector((data_width - 1) downto 0);
signal s_address : std_logic_vector((addr_width - 1) downto 0);
signal s_ram_block : memType;
begin -- archs_gen_rom
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
ramProc_a : process (clk)
begin -- process ramProc
if rising_edge(clk) then -- rising clock edge
s_address <= address;
q <= s_ram_block(to_integer(unsigned(s_address)));
end if;
end process ramProc_a;
file_read : process
file data : TEXT IS init_file;
variable lineStr, msg : line;
variable i : natural := 0;
variable rom_buf : std_logic_vector((data_width - 1) downto 0);
variable ok : boolean;
begin -- process file_read
while not endfile(data) loop
readline(data, lineStr);
hread(lineStr, rom_buf, ok);
if ok then
s_ram_block(i) <= rom_buf; -- no conversion
else
write(msg, String'(" !!! FORMAT !!! : "));
-- write(msg, String'(line.all));
write(msg, String'(" @ line : "));
write(msg, i);
report msg.all;
end if;
if i < (2**addr_width - 1) then
i := i + 1;
else
report "rom full";
exit;
end if;
end loop;
wait;
end process file_read;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
end archi_gen_rom;
-------------------------------------------------------------------------------
| gpl-3.0 | f4b17b3448e64049c1b2a2ed26c5a519 | 0.434942 | 4.822562 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 1 | 7,418 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:45 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 9.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
| mit | ea4d8c13ed712ed28a49e876a6358a3d | 0.634538 | 3.30276 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_sim_netlist.vhdl | 1 | 2,402 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:18 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_1_0 is
port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_1_0 : entity is "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_1_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_1_0;
architecture STRUCTURE of system_rgb565_to_rgb888_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_565\ : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
\^rgb_565\(15 downto 0) <= rgb_565(15 downto 0);
rgb_888(23 downto 19) <= \^rgb_565\(15 downto 11);
rgb_888(18 downto 16) <= \^rgb_565\(15 downto 13);
rgb_888(15 downto 10) <= \^rgb_565\(10 downto 5);
rgb_888(9 downto 8) <= \^rgb_565\(10 downto 9);
rgb_888(7 downto 3) <= \^rgb_565\(4 downto 0);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
| mit | 5ae4b22471b290d4dfd78c48dc0f335a | 0.639051 | 3.368864 | false | false | false | false |
loa-org/loa-hdl | modules/dds/hdl/dds_module.vhd | 1 | 6,091 | -------------------------------------------------------------------------------
-- Title : Direct digital synhtesis module - 1 Channel
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2015-08-24
-------------------------------------------------------------------------------
-- Copyright (c) 2015, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg_file_pkg.all;
use work.nco_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
entity dds_module is
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- NCO 0 output
dout : out std_logic_vector(15 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity dds_module;
architecture structural of dds_module is
signal phase_increment : std_logic_vector(31 downto 0);
signal phase : std_logic_vector(9 downto 0);
signal ctrl_reg : std_logic_vector(15 downto 0);
signal accu_load0 : std_logic_vector(31 downto 0);
signal load0, en0 : std_logic;
signal bus_ram_o, bus_ctrl_reg_o, bus_phase_inc_lsb_register_o, bus_load_lsb_register_o, bus_phase_inc_msb_register_o, bus_load_msb_register_o : busdevice_out_type;
begin -- architecture structural
-----------------------------------------------------------------------------
-- NCO 0 - controls fed by bus mapped registers
-- output goes to waveform_ram below
-----------------------------------------------------------------------------
nco_0 : entity work.nco
generic map (
ACCU_WIDTH => 32,
PHASE_WIDTH => 10,
RESET_IMPL => RESET_IMPL)
port map (
en => en0,
phase_increment => phase_increment,
phase => phase,
load => load0,
accu_load => accu_load0,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Double ported BRAM
-- waveform has to be loaded from bus-side
-- output is updated every cycle
-----------------------------------------------------------------------------
waveform_ram : entity work.reg_file_bram
generic map (
BASE_ADDRESS => BASE_ADDRESS,
RESET_IMPL => RESET_IMPL)
port map (
bus_o => bus_ram_o,
bus_i => bus_i,
bram_data_i => (others => '0'),
bram_data_o => dout,
bram_addr_i => phase,
bram_we_p => '0',
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Registers:
--
-- Control register
-- Enable
-- Load
--
-- Phase Increment Reg - sets increment
--
-- Accu Preload - sets Phase accumulator directly, has to be enabled by laod
-- bit in control register (and disabled).
-----------------------------------------------------------------------------
control_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#400#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => ctrl_reg,
din_p => ctrl_reg,
bus_o => bus_ctrl_reg_o,
bus_i => bus_i,
reset => reset,
clk => clk);
phase_inc_lsb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#401#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => phase_increment(15 downto 0),
din_p => phase_increment(15 downto 0),
bus_o => bus_phase_inc_lsb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
phase_inc_msb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#402#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => phase_increment(31 downto 16),
din_p => phase_increment(31 downto 16),
bus_o => bus_phase_inc_msb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
load_lsb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#403#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => accu_load0(15 downto 0),
din_p => accu_load0(15 downto 0),
bus_o => bus_load_lsb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
load_msb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#404#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => accu_load0(31 downto 16),
din_p => accu_load0(31 downto 16),
bus_o => bus_load_msb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Control Register Mapping
-- (ctrl_reg bits to control signals)
-----------------------------------------------------------------------------
en0 <= ctrl_reg(0);
load0 <= ctrl_reg(1);
-----------------------------------------------------------------------------
-- combine bus_o signals of all components
-----------------------------------------------------------------------------
bus_o.data <= bus_load_lsb_register_o.data or
bus_load_msb_register_o.data or
bus_phase_inc_lsb_register_o.data or
bus_phase_inc_msb_register_o.data or
bus_ctrl_reg_o.data or
bus_ram_o.data;
end architecture structural;
| bsd-3-clause | 7e68d808ff6d5e60377e332f454d5fcf | 0.46659 | 4.163363 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_transform/vga_transform.srcs/sources_1/new/vga_transform.vhd | 3 | 2,127 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_transform is
port (
clk : in std_logic;
enable : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
rot_m00 : in std_logic_vector(15 downto 0);
rot_m01 : in std_logic_vector(15 downto 0);
rot_m10 : in std_logic_vector(15 downto 0);
rot_m11 : in std_logic_vector(15 downto 0);
t_x : in std_logic_vector(9 downto 0);
t_y : in std_logic_vector(9 downto 0);
x_addr_out : out std_logic_vector(9 downto 0);
y_addr_out : out std_logic_vector(9 downto 0)
);
end vga_transform;
architecture Behavioral of vga_transform is
begin
process(clk)
variable m00_op, m01_op, m10_op, m11_op, x_op, y_op, t_x_op, t_y_op, x_s, y_s : signed(31 downto 0) := (others => '0');
variable x_p, y_p : signed(63 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if enable = '1' then
m00_op := resize(signed(rot_m00), 32);
m01_op := resize(signed(rot_m01), 32);
m10_op := resize(signed(rot_m10), 32);
m11_op := resize(signed(rot_m11), 32);
x_op(23 downto 14) := signed(x_addr_in);
y_op(23 downto 14) := signed(y_addr_in);
t_x_op(23 downto 14) := signed(t_x);
t_y_op(23 downto 14) := signed(t_y);
x_p := (m00_op * x_op + m01_op * y_op) srl 14;
y_p := (m10_op * x_op + m11_op * y_op) srl 14;
x_s := x_p(31 downto 0) + t_x_op;
y_s := y_p(31 downto 0) + t_y_op;
x_addr_out <= std_logic_vector(x_s(23 downto 14));
y_addr_out <= std_logic_vector(y_s(23 downto 14));
else
x_addr_out <= x_addr_in;
x_addr_out <= x_addr_in;
end if;
end if;
end process;
end Behavioral;
| mit | 24b0a1d8696fceff3dc46af28fc3e589 | 0.48331 | 3.160475 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/synth/system_zed_vga_0_0.vhd | 1 | 4,115 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "zed_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_vga_0_0_arch : ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_vga,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : zed_vga
PORT MAP (
clk => clk,
active => active,
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
| mit | 582aef96cf02673087bca7a0723c514b | 0.723694 | 3.727355 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_generic_tristate_controller_0_uas_translator.vhd | 1 | 15,043 | -- niosii_system_generic_tristate_controller_0_uas_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_generic_tristate_controller_0_uas_translator is
generic (
AV_ADDRESS_W : integer := 22;
AV_DATA_W : integer := 8;
UAV_DATA_W : integer := 8;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 1;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 1;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 1;
AV_ADDRESS_SYMBOLS : integer := 1;
AV_BURSTCOUNT_SYMBOLS : integer := 1;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- .readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(21 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(7 downto 0); -- .writedata
av_burstcount : out std_logic_vector(0 downto 0); -- .burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- .byteenable
av_readdatavalid : in std_logic := '0'; -- .readdatavalid
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_lock : out std_logic; -- .lock
av_debugaccess : out std_logic; -- .debugaccess
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_chipselect : out std_logic;
av_clken : out std_logic;
av_outputenable : out std_logic;
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_generic_tristate_controller_0_uas_translator;
architecture rtl of niosii_system_generic_tristate_controller_0_uas_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(7 downto 0); -- writedata
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_lock : out std_logic; -- lock
av_debugaccess : out std_logic; -- debugaccess
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
generic_tristate_controller_0_uas_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_burstcount => av_burstcount, -- .burstcount
av_byteenable => av_byteenable, -- .byteenable
av_readdatavalid => av_readdatavalid, -- .readdatavalid
av_waitrequest => av_waitrequest, -- .waitrequest
av_lock => av_lock, -- .lock
av_debugaccess => av_debugaccess, -- .debugaccess
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_generic_tristate_controller_0_uas_translator
| apache-2.0 | 8c7ac32b2daa0254a4b5bc634fc91619 | 0.428372 | 4.415321 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 1 | 70,017 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | e155dd63fbb007756b3d420bcb596539 | 0.531728 | 2.810573 | false | false | false | false |
ErikAndren/SramTest-IS61LV25616AL | SramControllerTestGen.vhd | 1 | 3,241 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity SramControllerTestGen is
generic (
AddrW : positive := 18;
DataW : positive := 16
);
port (
Clk : in bit1;
RstN : in bit1;
--
Button0 : in bit1;
Button1 : in bit1;
--
Addr : out word(AddrW-1 downto 0);
Data : out word(DataW-1 downto 0);
We : out bit1;
Re : out bit1
);
end entity;
architecture rtl of SramControllerTestGen is
constant noWords : positive := 262144;
constant noWordsW : positive := bits(NoWords);
signal SeqCnt_N, SeqCnt_D : word(NoWordsW downto 0);
--
signal Btn0State_N, Btn0State_D : bit1;
signal Btn1State_N, Btn1State_D : bit1;
signal Addr_N, Addr_D : word(AddrW-1 downto 0);
signal Button0Stable : bit1;
signal Button1Stable : bit1;
constant Delay : positive := 1;
constant DelayW : positive := bits(Delay);
signal WaitCnt_N, WaitCnt_D : word(DelayW-1 downto 0);
constant NumbersPerSec : positive := 20;
constant ClkFreq : positive := 50000000;
constant ClksPerNbr : positive := ClkFreq / NumbersPerSec;
constant ClksPerNbrW : positive := bits(ClksPerNbr);
signal ToggleCnt_N, ToggleCnt_D : word(ClksPerNbrW-1 downto 0);
begin
Button0Debounce : entity work.Debounce
port map (
Clk => Clk,
x => Button0,
DBx => Button0Stable
);
Button1Debounce : entity work.Debounce
port map (
Clk => Clk,
x => Button1,
DBx => Button1Stable
);
SyncProcRst : process (Clk, RstN)
begin
if RstN = '0' then
Btn0State_D <= '1';
Btn1State_D <= '1';
Addr_D <= (others => '0');
SeqCnt_D <= (others => '0');
WaitCnt_d <= (others => '0');
ToggleCnt_D <= (others => '0');
elsif rising_edge(Clk) then
Btn0State_D <= Btn0State_N;
Btn1State_D <= Btn1State_N;
Addr_D <= Addr_N;
SeqCnt_D <= SeqCnt_N;
WaitCnt_D <= WaitCnt_N;
ToggleCnt_D <= ToggleCnt_N;
end if;
end process;
AsyncProc : process (Btn0State_D, Btn1State_D, Addr_D, Button0Stable, Button1Stable, SeqCnt_D, WaitCnt_D, ToggleCnt_D)
begin
We <= '0';
Re <= '0';
Data <= (others => '0');
Btn0State_N <= Button0Stable;
Btn1State_N <= Button1Stable;
Addr_N <= Addr_D;
SeqCnt_N <= SeqCnt_D;
ToggleCnt_N <= ToggleCnt_D + 1;
WaitCnt_N <= WaitCnt_D;
if (WaitCnt_D > 0) then
WaitCnt_N <= WaitCnt_D - 1;
-- elsif SeqCnt_D < noWords then
-- SeqCnt_N <= SeqCnt_D + 1;
-- Addr_N <= SeqCnt_D(Addr_N'range);
-- We <= '1';
-- Data <= SeqCnt_D(Data'range);
-- WaitCnt_N <= conv_word(Delay, WaitCnt_N'length);
elsif Button0Stable = '0' and Btn0State_D = '1' then
Addr_N <= Addr_D - 1;
Re <= '1';
WaitCnt_N <= conv_word(Delay, WaitCnt_N'length);
elsif Button1Stable = '0' and Btn1State_D = '1' then
Addr_N <= Addr_D + 1;
Re <= '1';
WaitCnt_N <= conv_word(Delay, WaitCnt_N'length);
elsif ToggleCnt_D = ClksPerNbr-3 then
Addr_N <= Addr_D + 2;
We <= '1';
WaitCnt_N <= conv_word(Delay, WaitCnt_N'length);
SeqCnt_N <= SeqCnt_D + 1;
Data <= SeqCnt_D(Data'range);
elsif ToggleCnt_D = ClksPerNbr-1 then
Addr_N <= Addr_D - 1;
Re <= '1';
WaitCnt_N <= conv_word(Delay, WaitCnt_N'length);
ToggleCnt_N <= (others => '0');
end if;
end process;
Addr <= Addr_N;
end architecture; | gpl-2.0 | a0c87e8ba89d3588180cb94967c0da95 | 0.634064 | 2.615819 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_3/Uart_working/HEX2ASC.vhd | 2 | 835 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HEX2ASC is
Port (VAL :IN STD_LOGIC_VECTOR(3 downto 0);
CLK :IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end HEX2ASC;
architecture Behavioral of HEX2ASC is
begin
PROCESS(CLK)
BEGIN
CASE VAL IS
when "0000" => Y <= X"30";
when "0001" => Y <= X"31";
when "0010" => Y <= X"32";
when "0011" => Y <= X"33";
when "0100" => Y <= X"34";
when "0101" => Y <= X"35";
when "0110" => Y <= X"36";
when "0111" => Y <= X"37";
when "1000" => Y <= X"38";
when "1001" => Y <= X"39";
when "1010" => Y <= X"41";
when "1011" => Y <= X"42";
when "1100" => Y <= X"43";
when "1101" => Y <= X"44";
when "1110" => Y <= X"45";
when "1111" => Y <= X"46";
when others => Y <= X"2D";
end case;
end process;
end Behavioral;
| mit | 0aec60aa6994aa596d8c5b0e27d9e4b5 | 0.568862 | 2.44152 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/decoder_inferred-rtl.vhdl | 1 | 11,728 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.numeric_pkg.all;
architecture rtl of decoder_inferred is
begin
output_bits_1 : if output_bits = 1 generate
dataout <= "1";
end generate;
output_bits_2 : if output_bits = 2 generate
mux : block
signal sel : std_ulogic_vector(0 downto 0);
begin
sel <= datain(0 downto 0);
with sel select
dataout <= "01" when "0",
"10" when "1",
(others => 'X') when others;
end block;
end generate;
output_bits_3 : if output_bits = 3 generate
mux : block
signal sel : std_ulogic_vector(1 downto 0);
begin
sel <= datain(1 downto 0);
with sel select
dataout <= "001" when "00",
"010" when "01",
"100" when "10",
(others => 'X') when others;
end block;
end generate;
output_bits_4 : if output_bits = 4 generate
mux : block
signal sel : std_ulogic_vector(1 downto 0);
begin
sel <= datain(1 downto 0);
with sel select
dataout <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
(others => 'X') when others;
end block;
end generate;
output_bits_5 : if output_bits = 5 generate
mux : block
signal sel : std_ulogic_vector(2 downto 0);
begin
sel <= datain(2 downto 0);
with sel select
dataout <= "00001" when "000",
"00010" when "001",
"00100" when "010",
"01000" when "011",
"10000" when "100",
(others => 'X') when others;
end block;
end generate;
output_bits_6 : if output_bits = 6 generate
mux : block
signal sel : std_ulogic_vector(2 downto 0);
begin
sel <= datain(2 downto 0);
with sel select
dataout <= "000001" when "000",
"000010" when "001",
"000100" when "010",
"001000" when "011",
"010000" when "100",
"100000" when "101",
(others => 'X') when others;
end block;
end generate;
output_bits_7 : if output_bits = 7 generate
mux : block
signal sel : std_ulogic_vector(2 downto 0);
begin
sel <= datain(2 downto 0);
with sel select
dataout <= "0000001" when "000",
"0000010" when "001",
"0000100" when "010",
"0001000" when "011",
"0010000" when "100",
"0100000" when "101",
"1000000" when "110",
(others => 'X') when others;
end block;
end generate;
output_bits_8 : if output_bits = 8 generate
mux : block
signal sel : std_ulogic_vector(2 downto 0);
begin
sel <= datain(2 downto 0);
with sel select
dataout <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
(others => 'X') when others;
end block;
end generate;
output_bits_9 : if output_bits = 9 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "000000001" when "0000",
"000000010" when "0001",
"000000100" when "0010",
"000001000" when "0011",
"000010000" when "0100",
"000100000" when "0101",
"001000000" when "0110",
"010000000" when "0111",
"100000000" when "1000",
(others => 'X') when others;
end block;
end generate;
output_bits_10 : if output_bits = 10 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "0000000001" when "0000",
"0000000010" when "0001",
"0000000100" when "0010",
"0000001000" when "0011",
"0000010000" when "0100",
"0000100000" when "0101",
"0001000000" when "0110",
"0010000000" when "0111",
"0100000000" when "1000",
"1000000000" when "1001",
(others => 'X') when others;
end block;
end generate;
output_bits_11 : if output_bits = 11 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "00000000001" when "0000",
"00000000010" when "0001",
"00000000100" when "0010",
"00000001000" when "0011",
"00000010000" when "0100",
"00000100000" when "0101",
"00001000000" when "0110",
"00010000000" when "0111",
"00100000000" when "1000",
"01000000000" when "1001",
"10000000000" when "1010",
(others => 'X') when others;
end block;
end generate;
output_bits_12 : if output_bits = 12 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "000000000001" when "0000",
"000000000010" when "0001",
"000000000100" when "0010",
"000000001000" when "0011",
"000000010000" when "0100",
"000000100000" when "0101",
"000001000000" when "0110",
"000010000000" when "0111",
"000100000000" when "1000",
"001000000000" when "1001",
"010000000000" when "1010",
"100000000000" when "1011",
(others => 'X') when others;
end block;
end generate;
output_bits_13 : if output_bits = 13 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "0000000000001" when "0000",
"0000000000010" when "0001",
"0000000000100" when "0010",
"0000000001000" when "0011",
"0000000010000" when "0100",
"0000000100000" when "0101",
"0000001000000" when "0110",
"0000010000000" when "0111",
"0000100000000" when "1000",
"0001000000000" when "1001",
"0010000000000" when "1010",
"0100000000000" when "1011",
"1000000000000" when "1100",
(others => 'X') when others;
end block;
end generate;
output_bits_14 : if output_bits = 14 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "00000000000001" when "0000",
"00000000000010" when "0001",
"00000000000100" when "0010",
"00000000001000" when "0011",
"00000000010000" when "0100",
"00000000100000" when "0101",
"00000001000000" when "0110",
"00000010000000" when "0111",
"00000100000000" when "1000",
"00001000000000" when "1001",
"00010000000000" when "1010",
"00100000000000" when "1011",
"01000000000000" when "1100",
"10000000000000" when "1101",
(others => 'X') when others;
end block;
end generate;
output_bits_15 : if output_bits = 15 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "000000000000001" when "0000",
"000000000000010" when "0001",
"000000000000100" when "0010",
"000000000001000" when "0011",
"000000000010000" when "0100",
"000000000100000" when "0101",
"000000001000000" when "0110",
"000000010000000" when "0111",
"000000100000000" when "1000",
"000001000000000" when "1001",
"000010000000000" when "1010",
"000100000000000" when "1011",
"001000000000000" when "1100",
"010000000000000" when "1101",
"100000000000000" when "1110",
(others => 'X') when others;
end block;
end generate;
output_bits_16 : if output_bits = 16 generate
mux : block
signal sel : std_ulogic_vector(3 downto 0);
begin
sel <= datain(3 downto 0);
with sel select
dataout <= "0000000000000001" when "0000",
"0000000000000010" when "0001",
"0000000000000100" when "0010",
"0000000000001000" when "0011",
"0000000000010000" when "0100",
"0000000000100000" when "0101",
"0000000001000000" when "0110",
"0000000010000000" when "0111",
"0000000100000000" when "1000",
"0000001000000000" when "1001",
"0000010000000000" when "1010",
"0000100000000000" when "1011",
"0001000000000000" when "1100",
"0010000000000000" when "1101",
"0100000000000000" when "1110",
"1000000000000000" when "1111",
(others => 'X') when others;
end block;
end generate;
output_bits_out_of_range : if output_bits > 16 generate
output_bits_out_of_rance_proc : process is
begin
assert output_bits > 16 report "output_bits is out of range" severity failure;
wait;
end process;
end generate;
end;
| apache-2.0 | f4e8332ee1710c6fb63c95d8edd048b1 | 0.484482 | 4.830313 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/adau1761.vhd | 1 | 3,952 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 19:23:40 01/06/2014
-- Module Name: adau1761 - Behavioral
-- Description: Implement a Line in => I2S => FPGA => I2S => Headphones
-- using the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity adau1761 is
Port ( clk_100 : in STD_LOGIC;
clk_48_o :out STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
new_sample : OUT std_logic;
AUDIO_OUT_L : out STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : out STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : in STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : in STD_LOGIC_VECTOR(23 downto 0);
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AC_SDA : inout STD_LOGIC;
sw : in STD_LOGIC_VECTOR(7 downto 0)
);
end adau1761;
architecture Behavioral of adau1761 is
COMPONENT adau1761_izedboard
PORT(
clk_48 : IN std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
hphone_l : IN std_logic_vector(23 downto 0);
hphone_r : IN std_logic_vector(23 downto 0);
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : OUT std_logic;
line_in_l : OUT std_logic_vector(23 downto 0);
line_in_r : OUT std_logic_vector(23 downto 0);
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0)
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
signal clk_48 : std_logic;
signal sw_synced : std_logic_vector(7 downto 0);
signal active : std_logic_vector(1 downto 0);
constant hi : natural := 23;
begin
process(clk_48)
begin
if rising_edge(clk_48) then
sw_synced <= sw;
end if;
end process;
--i_clocking : clocking port map (
-- CLK_100 => CLK_100,
-- CLK_48 => CLK_48,
-- RESET => '0',
-- LOCKED => open
-- );
clk_divider_2083: entity WORK.ClkDividerN(Behavioral)
generic map(divFactor => 2)
port map(reset => '0',
clkIn => CLK_100,
clkOut => CLK_48);
clk_48_o <= clk_48;
Inst_adau1761_izedboard: adau1761_izedboard PORT MAP(
clk_48 => clk_48,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
hphone_l => AUDIO_IN_L,
hphone_r => AUDIO_IN_R,
line_in_l => AUDIO_OUT_L,
line_in_r => AUDIO_OUT_R,
new_sample => new_sample,
sw => sw(1 downto 0),
active => active
);
end Behavioral;
| mit | 68d22dc3742ad8952074bb4c76fda12d | 0.51164 | 3.054096 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/mux_1hot_inferred-rtl.vhdl | 1 | 5,735 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of mux_1hot_inferred is
type mux_type is array (sel_bits-1 downto 0) of std_ulogic_vector(data_bits-1 downto 0);
type comb_type is record
m : mux_type;
end record;
signal c : comb_type;
begin
sel_bit_loop : for n in sel_bits-1 downto 0 generate
data_bit_loop : for m in data_bits-1 downto 0 generate
c.m(n)(m) <= din(n, m);
end generate;
end generate;
sel_bits_0 : if sel_bits = 0 generate
dout <= "";
end generate;
sel_bits_1 : if sel_bits = 1 generate
mux : block
signal sel_tmp : std_ulogic_vector(0 downto 0);
begin
sel_tmp <= sel(0 downto 0);
with sel_tmp select
dout <= c.m(0) when "1",
(others => 'X') when others;
end block;
end generate;
sel_bits_2 : if sel_bits = 2 generate
mux : block
signal sel_tmp : std_ulogic_vector(1 downto 0);
begin
sel_tmp <= sel(1 downto 0);
with sel_tmp select
dout <= c.m(0) when "01",
c.m(1) when "10",
(others => 'X') when others;
end block;
end generate;
sel_bits_3 : if sel_bits = 3 generate
mux : block
signal sel_tmp : std_ulogic_vector(2 downto 0);
begin
sel_tmp <= sel(2 downto 0);
with sel_tmp select
dout <= c.m(0) when "001",
c.m(1) when "010",
c.m(2) when "100",
(others => 'X') when others;
end block;
end generate;
sel_bits_4 : if sel_bits = 4 generate
mux : block
signal sel_tmp : std_ulogic_vector(3 downto 0);
begin
sel_tmp <= sel(3 downto 0);
with sel_tmp select
dout <= c.m(0) when "0001",
c.m(1) when "0010",
c.m(2) when "0100",
c.m(3) when "1000",
(others => 'X') when others;
end block;
end generate;
sel_bits_5 : if sel_bits = 5 generate
mux : block
signal sel_tmp : std_ulogic_vector(4 downto 0);
begin
sel_tmp <= sel(4 downto 0);
with sel_tmp select
dout <= c.m(0) when "00001",
c.m(1) when "00010",
c.m(2) when "00100",
c.m(3) when "01000",
c.m(4) when "10000",
(others => 'X') when others;
end block;
end generate;
sel_bits_6 : if sel_bits = 6 generate
mux : block
signal sel_tmp : std_ulogic_vector(5 downto 0);
begin
sel_tmp <= sel(5 downto 0);
with sel_tmp select
dout <= c.m(0) when "000001",
c.m(1) when "000010",
c.m(2) when "000100",
c.m(3) when "001000",
c.m(4) when "010000",
c.m(5) when "100000",
(others => 'X') when others;
end block;
end generate;
sel_bits_7 : if sel_bits = 7 generate
mux : block
signal sel_tmp : std_ulogic_vector(6 downto 0);
begin
sel_tmp <= sel(6 downto 0);
with sel_tmp select
dout <= c.m(0) when "0000001",
c.m(1) when "0000010",
c.m(2) when "0000100",
c.m(3) when "0001000",
c.m(4) when "0010000",
c.m(5) when "0100000",
c.m(6) when "1000000",
(others => 'X') when others;
end block;
end generate;
sel_bits_8 : if sel_bits = 8 generate
mux : block
signal sel_tmp : std_ulogic_vector(7 downto 0);
begin
sel_tmp <= sel(7 downto 0);
with sel_tmp select
dout <= c.m(0) when "00000001",
c.m(1) when "00000010",
c.m(2) when "00000100",
c.m(3) when "00001000",
c.m(4) when "00010000",
c.m(5) when "00100000",
c.m(6) when "01000000",
c.m(7) when "10000000",
(others => 'X') when others;
end block;
end generate;
sel_bits_out_of_range : if sel_bits > 8 generate
error_process : process is
begin
assert sel_bits <= 8 report "sel_bits out of range" severity failure;
wait;
end process;
end generate;
end;
| apache-2.0 | 8c0e0c44495494cb5d68b7e71346cb8f | 0.470968 | 3.925394 | false | false | false | false |
loa-org/loa-hdl | modules/uart/tb/uart_loopback_tb.vhd | 2 | 3,055 | -------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx" and "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_loopback_tb is
end entity uart_loopback_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_loopback_tb is
-- component ports
signal txd : std_logic;
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal rxd : std_logic := '1';
signal data_recv : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut_tx : entity work.uart_tx
port map (
txd_p => txd,
data_p => data_out,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
dut_rx : entity work.uart_rx
port map (
rxd_p => rxd,
data_p => data_recv,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
disable_p => '0',
clk => clk);
rxd <= txd;
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 60 ns;
end process bitclock;
clk_rx_en <= '1';
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data_out <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data_out <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data_out <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data_out <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data_out <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
| bsd-3-clause | 700c587219b7f93f23600a5ca8a533ee | 0.420295 | 4.248957 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/audio_buffer_v1_00_a/hdl/vhdl/user_logic.vhd | 3 | 10,518 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 13 19:59:47 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 2;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
clk_48_i : in std_logic;
sample_data_L_in : in std_logic_vector(23 downto 0);
sample_data_R_in : in std_logic_vector(23 downto 0);
sample_data_L_out : out std_logic_vector(23 downto 0);
sample_data_R_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(1 downto 0);
signal slv_reg_read_sel : std_logic_vector(1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_reg0;
when "01" => slv_ip2bus_data <= slv_reg1;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 9721a5ebcbac057c1c73852bf1a9f598 | 0.465203 | 4.348078 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_gaussian_blur/vga_gaussian_blur.srcs/sources_1/new/vga_gaussian_blur.vhd | 2 | 5,725 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_gaussian_blur - Structural
-- Description: Blur an input image stream and sync with output
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_gaussian_blur is
generic(
H_SIZE : integer := 640;
H_DELAY : integer := 160;
KERNEL : integer := 3
);
port(
clk_25 : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
rgb_in : in std_logic_vector(23 downto 0);
hsync_out : out std_logic;
vsync_out : out std_logic;
rgb_blur : out std_logic_vector(23 downto 0);
rgb_pass : out std_logic_vector(23 downto 0)
);
end vga_gaussian_blur;
architecture Structural of vga_gaussian_blur is
type PIXEL_BUFFER is array ((H_SIZE)*(KERNEL-1) + KERNEL - 1 downto 0) of std_logic_vector(23 downto 0);
type SIGNAL_BUFFER is array ((H_SIZE + H_DELAY)*(KERNEL/2) + KERNEL/2 downto 0) of std_logic_vector(1 downto 0);
type INT_ARRAY is array (integer range<>) of integer;
signal active : std_logic;
begin
active <= not (hsync_in or vsync_in);
process(clk_25)
variable rgb_buffer : PIXEL_BUFFER;
variable sync_buffer : SIGNAL_BUFFER;
variable temp_r : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable temp_g : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable temp_b : INT_ARRAY(KERNEL*KERNEL - 1 downto 0);
variable compute_r, compute_g, compute_b : integer;
begin
if rising_edge(clk_25) then
if active = '1' then
temp_r(0) := to_integer(unsigned(rgb_buffer(0)(23 downto 16)));
temp_r(1) := to_integer(unsigned(rgb_buffer(1)(23 downto 16)));
temp_r(2) := to_integer(unsigned(rgb_buffer(2)(23 downto 16)));
temp_r(3) := to_integer(unsigned(rgb_buffer(H_SIZE)(23 downto 16)));
temp_r(4) := to_integer(unsigned(rgb_buffer(H_SIZE+1)(23 downto 16)));
temp_r(5) := to_integer(unsigned(rgb_buffer(H_SIZE+2)(23 downto 16)));
temp_r(6) := to_integer(unsigned(rgb_buffer(2*(H_SIZE))(23 downto 16)));
temp_r(7) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+1)(23 downto 16)));
temp_r(8) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+2)(23 downto 16)));
compute_r := (temp_r(0) + 2*temp_r(1) + temp_r(2) + 2*temp_r(3) + 4*temp_r(4) + 2*temp_r(5) + temp_r(6) + 2*temp_r(7) + temp_r(8))/16;
temp_g(0) := to_integer(unsigned(rgb_buffer(0)(15 downto 8)));
temp_g(1) := to_integer(unsigned(rgb_buffer(1)(15 downto 8)));
temp_g(2) := to_integer(unsigned(rgb_buffer(2)(15 downto 8)));
temp_g(3) := to_integer(unsigned(rgb_buffer(H_SIZE)(15 downto 8)));
temp_g(4) := to_integer(unsigned(rgb_buffer(H_SIZE+1)(15 downto 8)));
temp_g(5) := to_integer(unsigned(rgb_buffer(H_SIZE+2)(15 downto 8)));
temp_g(6) := to_integer(unsigned(rgb_buffer(2*(H_SIZE))(15 downto 8)));
temp_g(7) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+1)(15 downto 8)));
temp_g(8) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+2)(15 downto 8)));
compute_g := (temp_g(0) + 2*temp_g(1) + temp_g(2) + 2*temp_g(3) + 4*temp_g(4) + 2*temp_g(5) + temp_g(6) + 2*temp_g(7) + temp_g(8))/16;
temp_b(0) := to_integer(unsigned(rgb_buffer(0)(7 downto 0)));
temp_b(1) := to_integer(unsigned(rgb_buffer(1)(7 downto 0)));
temp_b(2) := to_integer(unsigned(rgb_buffer(2)(7 downto 0)));
temp_b(3) := to_integer(unsigned(rgb_buffer(H_SIZE)(7 downto 0)));
temp_b(4) := to_integer(unsigned(rgb_buffer(H_SIZE+1)(7 downto 0)));
temp_b(5) := to_integer(unsigned(rgb_buffer(H_SIZE+2)(7 downto 0)));
temp_b(6) := to_integer(unsigned(rgb_buffer(2*(H_SIZE))(7 downto 0)));
temp_b(7) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+1)(7 downto 0)));
temp_b(8) := to_integer(unsigned(rgb_buffer(2*(H_SIZE)+2)(7 downto 0)));
compute_b := (temp_b(0) + 2*temp_b(1) + temp_b(2) + 2*temp_b(3) + 4*temp_b(4) + 2*temp_b(5) + temp_b(6) + 2*temp_b(7) + temp_b(8))/16;
rgb_blur(23 downto 16) <= std_logic_vector(to_unsigned(compute_r, 8));
rgb_blur(15 downto 8) <= std_logic_vector(to_unsigned(compute_g, 8));
rgb_blur(7 downto 0) <= std_logic_vector(to_unsigned(compute_b, 8));
rgb_pass <= rgb_buffer(H_SIZE+1);
for i in (H_SIZE)*(KERNEL-1) + KERNEL - 1 downto 1 loop
rgb_buffer(i) := rgb_buffer(i-1);
end loop;
rgb_buffer(0) := rgb_in;
else
rgb_blur <= (others => '0');
rgb_pass <= (others => '0');
end if;
hsync_out <= sync_buffer(H_SIZE+H_DELAY+1)(1);
vsync_out <= sync_buffer(H_SIZE+H_DELAY+1)(0);
for i in (H_SIZE + H_DELAY)*(KERNEL/2) + KERNEL/2 - 1 downto 1 loop
sync_buffer(i) := sync_buffer(i-1);
end loop;
sync_buffer(0) := (1 => hsync_in, 0 => vsync_in);
end if;
end process;
end Structural;
| mit | 967b2e9678bf4332f0ba179ea4976f61 | 0.514934 | 3.26583 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dspdiv.vhd | 2 | 15,546 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
--
-- Pipelined divider usign restoring algorithm
-- total pipe length is (sig_width + 1)
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity dspdiv is
generic (
sig_width : integer := 16);
port (
--@inputs
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
--@outputs;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end dspdiv;
--=----------------------------------------------------------------------------
architecture archi_dspdiv of dspdiv is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_div_length : integer := sig_width - 1;
constant c_work_length : integer := 2*c_div_length;
constant c_trial_length : integer := c_div_length + 2;
constant c_trial_overflow : integer := c_trial_length - 2;
constant c_trial_sign : integer := c_trial_length - 1;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type t_work_pipe is array(0 to c_div_length) of std_logic_vector((c_work_length - 1) downto 0);
type t_trial_pipe is array(0 to c_div_length) of unsigned((c_trial_length - 1) downto 0);
--type t_trial_pipe is array(0 to c_div_length) of std_logic_vector((c_trial_length - 1) downto 0);
type t_val_pipe is array(0 to c_div_length - 1) of std_logic_vector((c_div_length - 1) downto 0);
type t_bit_pipe is array(0 to c_div_length - 1) of std_logic;
signal s_r : t_work_pipe;
signal s_trial_r : t_trial_pipe;
signal s_d : t_val_pipe;
signal s_q : t_val_pipe;
signal s_sign : t_bit_pipe;
signal s_overflow : t_bit_pipe;
signal s_overflow_cur : t_bit_pipe;
signal s_num_abs : signed((2*sig_width - 1) downto 0);
signal s_num_sign : std_logic;
signal s_den_abs : signed((sig_width - 1) downto 0);
signal s_den_sign : std_logic;
signal s_sign_last : std_logic;
--
-- SIgnals for debug
--
signal s_d0 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d1 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d2 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d3 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d4 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d5 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d6 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d7 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d8 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d9 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d10 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d11 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d12 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d13 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d14 : std_logic_vector((c_div_length - 1) downto 0);
--signal s_d15 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q0 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q1 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q2 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q3 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q4 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q5 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q6 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q7 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q8 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q9 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q10 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q11 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q12 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q13 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q14 : std_logic_vector((c_div_length - 1) downto 0);
--signal s_q15 : std_logic_vector((c_div_length - 1) downto 0);
signal s_r0 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r1 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r2 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r3 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r4 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r5 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r6 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r7 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r8 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r9 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r10 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r11 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r12 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r13 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r14 : std_logic_vector((c_work_length - 1) downto 0);
--signal s_r15 : std_logic_vector((c_work_length - 1) downto 0);
signal s_trial_r0 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r1 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r2 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r3 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r4 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r5 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r6 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r7 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r8 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r9 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r10 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r11 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r12 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r13 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r14 : unsigned((c_trial_length - 1) downto 0);
--signal s_trial_r15 : unsigned((c_trial_length - 1) downto 0);
begin -- archs_dspdiv
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_div : process (clk)
begin -- process p_div
if rising_edge(clk) then -- rising clock edge
-- s_r(0)((c_div_length - 1) downto 0)<= num(2*sig_width - 2 downto (2*sig_width - c_div_length - 1));
-- s_r(0)((c_work_length - 1) downto c_div_length) <= (others => '0');
s_r(0) <= std_logic_vector(s_num_abs((c_work_length - 1) downto 0));
s_d(0) <= std_logic_vector(s_den_abs((c_div_length - 1) downto 0));
s_sign(0) <= s_num_sign xor s_den_sign;
-- fill unused lines with 0 for simulation
for i in 0 to c_div_length - 2 loop
-- propagation of quotient bits previously computed
s_q(i)((c_div_length - i - 2) downto 0) <= (others => '0');
end loop;
-- pipe
for i in 1 to c_div_length - 1 loop
s_sign(i) <= s_sign(i - 1);
s_d(i) <= s_d(i - 1);
-- propagation of quotient bits previously computed
s_q(i)((c_div_length - 1) downto (c_div_length - i)) <= s_q(i - 1)((c_div_length - 1) downto (c_div_length - i));
-- test for overflow (denominator too small)
s_overflow(i) <= s_overflow(i - 1) or s_overflow_cur(i);
end loop;
s_overflow(0) <= s_overflow_cur(0);
s_sign_last <= s_sign(c_div_length - 1);
for i in 0 to c_div_length - 1 loop
if s_trial_r(i)(c_trial_length - 1) = '0' then --if >= 0
s_r(i + 1)((c_work_length - 1) downto c_div_length) <= std_logic_vector(s_trial_r(i)(c_div_length - 1 downto 0)); -- store trial reminder
s_q(i)(c_div_length - 1 - i) <= '1';
else
-- restore s_r and shift one bit left (R <- 2R)
s_r(i + 1)((c_work_length - 1) downto c_div_length) <= s_r(i)(c_work_length - 2 downto c_div_length - 1);
s_q(i)(c_div_length - 1 - i) <= '0';
end if;
-- The lower part of the remainder is just shifted
s_r(i + 1)((c_div_length - 1) downto 0) <= s_r(i)((c_div_length - 2) downto 0) & '0';
end loop;
end if;
end process p_div;
p_sign : process (num,den)
begin -- process p_sign
if den(sig_width - 1) = '0' then
s_den_abs <= signed(den);
s_den_sign <= '0';
else
s_den_abs <= -signed(den);
s_den_sign <= '1';
end if;
if num(2*sig_width - 1) = '0' then
s_num_abs <= signed(num);
s_num_sign <= '0';
else
s_num_abs <= -signed(num);
s_num_sign <= '1';
end if;
end process p_sign;
p_out_reg : process (clk)
begin -- process p_out_reg
if rising_edge(clk) then -- rising clock edge
if s_overflow(c_div_length - 1) = '1' then
q(sig_width - 2 downto 0) <= (others => '1');
q(sig_width - 1) <= '0';
r <= (others => '0');
elsif s_sign_last = '0' then
r <= s_r(c_div_length - 1);
q <= '0' & s_q(c_div_length - 1);
else
r <= s_r(c_div_length - 1);
q <= std_logic_vector(-signed('0' & s_q(c_div_length - 1)));
end if;
end if;
end process p_out_reg;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
computtrial : for i in 0 to c_div_length - 1 generate
-- compute the trial reminder (substractions) (Rt <- 2R - D)
-- substract performed only on the left part of s_r
-- s_trial_r(i) <= std_logic_vector(
-- unsigned('0' & std_logic_vector(s_r(i)((c_work_length - 1) downto (c_work_length - c_div_length - 1))))
-- - unsigned("00" & std_logic_vector(s_d(i))));
s_trial_r(i) <=
('0' & unsigned(s_r(i)((c_work_length - 1) downto (c_work_length - c_div_length - 1))))
- ("00" & unsigned(s_d(i)));
end generate computtrial;
overflow_cur : for i in 0 to c_div_length - 1 generate
s_overflow_cur(i) <= not s_trial_r(i)(c_trial_sign) and s_trial_r(i)(c_trial_overflow);
end generate overflow_cur;
------------------------------------------------------------------------------
--
-- Details on signals shift for the computation of trial remainder
--
------------------------------------------------------------------------------
--
-- Operation performed : Rtrial(n) = 2R(n - 1) - Den << N
--
-- ----------------------------------------------------------------
-- bits 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
-- numbers: 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
-- ----------------------------------------------------------------
--|
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--| s_r (shifted) | 0| r(n-1) |
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--|
--| | - - - - - - - - - - - - - - -
--| s_d (shifted) | 0 0| denominator |0 0 0 0 0 0 0 0 0 0 0 0 0 0
--| | - - - - - - - - - - - - - - -
--|
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--| s_trial_r | |s|o| |
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--
--
-- if s = 1 (negative value) : restore previous remainder
-- if o = 1 and s = 0 : the denominator is too small : quotient is infinity
-- if o = 0 and s = 0 : the difference is the new remainder : R(n) <= Rtrial(n)
--
--
-- Signals for debug
--
s_d0 <= s_d(0);
s_d1 <= s_d(1);
s_d2 <= s_d(2);
s_d3 <= s_d(3);
s_d4 <= s_d(4);
s_d5 <= s_d(5);
s_d6 <= s_d(6);
s_d7 <= s_d(7);
s_d8 <= s_d(8);
s_d9 <= s_d(9);
s_d10 <= s_d(10);
s_d11 <= s_d(11);
s_d12 <= s_d(12);
s_d13 <= s_d(13);
s_d14 <= s_d(14);
--s_d15 <= s_d(15);
s_q0 <= s_q(0);
s_q1 <= s_q(1);
s_q2 <= s_q(2);
s_q3 <= s_q(3);
s_q4 <= s_q(4);
s_q5 <= s_q(5);
s_q6 <= s_q(6);
s_q7 <= s_q(7);
s_q8 <= s_q(8);
s_q9 <= s_q(9);
s_q10 <= s_q(10);
s_q11 <= s_q(11);
s_q12 <= s_q(12);
s_q13 <= s_q(13);
s_q14 <= s_q(14);
--s_q15 <= s_q(15);
s_r0 <= s_r(0);
s_r1 <= s_r(1);
s_r2 <= s_r(2);
s_r3 <= s_r(3);
s_r4 <= s_r(4);
s_r5 <= s_r(5);
s_r6 <= s_r(6);
s_r7 <= s_r(7);
s_r8 <= s_r(8);
s_r9 <= s_r(9);
s_r10 <= s_r(10);
s_r11 <= s_r(11);
s_r12 <= s_r(12);
s_r13 <= s_r(13);
s_r14 <= s_r(14);
--s_r15 <= s_r(15);
s_trial_r0 <= s_trial_r(0);
s_trial_r1 <= s_trial_r(1);
s_trial_r2 <= s_trial_r(2);
s_trial_r3 <= s_trial_r(3);
s_trial_r4 <= s_trial_r(4);
s_trial_r5 <= s_trial_r(5);
s_trial_r6 <= s_trial_r(6);
s_trial_r7 <= s_trial_r(7);
s_trial_r8 <= s_trial_r(8);
s_trial_r9 <= s_trial_r(9);
s_trial_r10 <= s_trial_r(10);
s_trial_r11 <= s_trial_r(11);
s_trial_r12 <= s_trial_r(12);
s_trial_r13 <= s_trial_r(13);
s_trial_r14 <= s_trial_r(14);
--s_trial_r15 <= s_trial_r(15);
end archi_dspdiv;
-------------------------------------------------------------------------------
| gpl-3.0 | 106758810420e068e5f1656ea60e9621 | 0.486041 | 2.961143 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 18,180 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Thu Mar 10 14:13:03 2016
--Host : minmi running 64-bit elementary OS Freya
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
end component system_zybo_hdmi_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
signal Net : STD_LOGIC;
signal hdmi_cec_1 : STD_LOGIC;
signal hdmi_hpd_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC;
signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
hdmi_cec_1 <= hdmi_cec;
hdmi_hpd_1 <= hdmi_hpd;
hdmi_out_en <= zybo_hdmi_0_hdmi_out_en;
tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0);
tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => Net,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => processing_system7_0_FCLK_RESET0_N,
x_not => inverter_0_x_not
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => Net,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk_25 => Net,
hsync => vga_sync_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zybo_hdmi_0: component system_zybo_hdmi_0_0
port map (
active => vga_sync_0_active,
clk_125 => processing_system7_0_FCLK_CLK0,
clk_25 => Net,
hdmi_cec => hdmi_cec_1,
hdmi_hpd => hdmi_hpd_1,
hdmi_out_en => zybo_hdmi_0_hdmi_out_en,
hsync => vga_sync_0_hsync,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0),
tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0),
vsync => vga_sync_0_vsync
);
end STRUCTURE;
| mit | 3542c0cc73f807806520946dbdca7094 | 0.662431 | 2.918138 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 1 | 7,157 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 00:51:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 44.625000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 75.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;
| mit | 6537b1e68aec8005c1cc9e79fe0a93f0 | 0.640212 | 3.290575 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/bldc_motor_module_tb.vhd | 2 | 4,318 | -------------------------------------------------------------------------------
-- Title : Testbench for design "bldc_motor_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity bldc_motor_module_tb is
end bldc_motor_module_tb;
-------------------------------------------------------------------------------
architecture tb of bldc_motor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant WIDTH : positive := 8;
constant PRESCALER : positive := 2;
-- component ports
signal driver_stage : bldc_driver_stage_type;
signal hall : hall_sensor_type := ('0', '0', '0');
signal break : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : bldc_motor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
driver_stage_p => driver_stage,
hall_p => hall,
break_p => break,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
bus_waveform : process
begin
wait for 100 ns;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 630 US;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 100 US;
-- Disable PWM via Shutdown
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"800f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process;
hall_sensor_waveform : process
begin
wait for 50 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
wait for 100 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
end process;
-- Test break signal
process
begin
wait for 220 US;
break <= '1';
wait for 50 US;
break <= '0';
end process;
end tb;
| bsd-3-clause | f91d4847da3312913a37644ef5ede669 | 0.44465 | 3.745013 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 12,239 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Sat May 27 20:54:34 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=14,numReposBlks=14,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_g8_to_rgb888_0_0 is
port (
g8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_g8_to_rgb888_0_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal g8_to_rgb888_0_rgb888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal hsync_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vsync_1 : STD_LOGIC;
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
data_1(7 downto 0) <= data(7 downto 0);
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1 <= hsync;
pclk_1 <= pclk;
ready <= ov7670_controller_0_config_finished;
reset_1 <= reset;
sioc <= ov7670_controller_0_sioc;
vsync_1 <= vsync;
xclk <= clk_wiz_0_clk_out1;
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => pclk_1,
clk_out => clock_splitter_0_clk_out,
latch_edge => vsync_1
);
debounce_0: component system_debounce_0_0
port map (
clk => vga_pll_0_clk_25,
signal_in => reset_1,
signal_out => debounce_0_o
);
g8_to_rgb888_0: component system_g8_to_rgb888_0_0
port map (
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => g8_to_rgb888_0_rgb888(23 downto 0)
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => pclk_1,
data(7 downto 0) => data_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_6,
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_6,
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => hsync_1,
rst => ov7670_controller_0_config_finished,
start => vga_sync_ref_0_start,
vsync => vsync_1,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_25,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => g8_to_rgb888_0_rgb888(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
| mit | b0b1a805172088ff79fb73ce035b261c | 0.627747 | 2.929392 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/hdl/imotor_receiver.vhd | 2 | 5,489 | -------------------------------------------------------------------------------
-- Title : iMotor Receiver
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Receives messages from the slave.
--
-- Endianess: Little (as it is the default of ARM)
-- (Transmits lower byte first)
-- -------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity imotor_receiver is
generic (
DATA_WORDS : positive := 2;
DATA_WIDTH : positive := 16;
START_BYTE : std_logic_vector(7 downto 0) := x"51"; -- expected start byte
END_BYTE : std_logic_vector(7 downto 0) := x"A1" -- expected stop byte
);
port (
-- parallel data out
data_out_p : out imotor_output_type(DATA_WORDS - 1 downto 0);
-- parallel data from UART RX
data_in_p : in std_logic_vector(7 downto 0);
parity_error_in_p : in std_logic;
ready_in_p : in std_logic;
clk : in std_logic
);
end imotor_receiver;
-------------------------------------------------------------------------------
architecture behavioural of imotor_receiver is
type imotor_receiver_state_type is (
IDLE, -- Idle state:
DATA, -- Receiving data bytes
STOP -- Expecting end byte
);
type imotor_receiver_type is record
state : imotor_receiver_state_type;
-- Store all bytes until proper end byte received
data_store : imotor_output_type(DATA_WORDS - 1 downto 0);
-- The output to the register file is only updated when proper end byte
-- received.
data_out : imotor_output_type(DATA_WORDS - 1 downto 0);
byte_count : integer range 0 to (DATA_WORDS * 2);
end record;
constant last_byte : natural := DATA_WORDS * 2 - 1; -- index of last data byte
-- before end byte
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_receiver_type := (
state => IDLE,
data_out => (others => (others => '0')),
data_store => (others => (others => '0')),
byte_count => 0
);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
data_out_p <= r.data_out;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(data_in_p, r, ready_in_p)
variable v : imotor_receiver_type;
begin
v := r;
case r.state is
when IDLE =>
if ready_in_p = '1' and data_in_p = START_BYTE then
-- It is the correct byte
v.byte_count := 0;
v.state := DATA;
end if;
when DATA =>
if ready_in_p = '1' then
-- Store byte in data_store,
if r.byte_count mod 2 = 0 then
v.data_store(r.byte_count / 2)(7 downto 0) := data_in_p;
else
v.data_store(r.byte_count / 2)(15 downto 8) := data_in_p;
end if;
-- All received?
if v.byte_count = last_byte then
v.state := STOP; -- expect END byte
end if;
-- Always count
v.byte_count := r.byte_count + 1;
end if;
when STOP =>
if ready_in_p = '1' then
-- Next state is always idle
v.state := IDLE;
if data_in_p = END_BYTE then
-- Correct end byte received. Copy data to register file
v.data_out := r.data_store;
end if;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | e0bafddcfc1694400e34f3c58ba039bf | 0.37894 | 5.318798 | false | false | false | false |
loa-org/loa-hdl | modules/utils/tb/clock_divider_tb.vhd | 2 | 429 |
library ieee;
use ieee.std_logic_1164.all;
entity clock_divider_tb is
end clock_divider_tb;
architecture behavior of clock_divider_tb is
use work.utils_pkg.all;
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
uut : clock_divider
generic map (DIV => 5)
port map(
clk => clk,
clk_out_p => output);
end;
| bsd-3-clause | f131c728df02104a8447e5e1db9fe8ea | 0.599068 | 3.377953 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/synth/system_clock_splitter_1_0.vhd | 2 | 3,769 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_1_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_1_0;
ARCHITECTURE system_clock_splitter_1_0_arch OF system_clock_splitter_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_1_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_1_0_arch : ARCHITECTURE IS "system_clock_splitter_1_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_1_0_arch: ARCHITECTURE IS "system_clock_splitter_1_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_1_0_arch;
| mit | d0e79fd1bdc9c637fa1fdf1ac147445e | 0.746086 | 3.967368 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_4_lane_link.vhd | 1 | 5,662 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--MIPI CSI-2 Rx 4 lane link layer
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This combines the clock and data PHYs; byte aligners and word aligner to
--form the lower levels of the CSI Rx link layer
entity csi_rx_4_lane_link is
generic(
fpga_series : string := "7SERIES";
dphy_term_en : boolean := true;
d0_invert : boolean := false;
d1_invert : boolean := false;
d2_invert : boolean := false;
d3_invert : boolean := false;
d0_skew : natural := 0;
d1_skew : natural := 0;
d2_skew : natural := 0;
d3_skew : natural := 0;
generate_idelayctrl : boolean := false
);
port(
dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --clock lane (1 is P, 0 is N)
dphy_d0 : in STD_LOGIC_VECTOR (1 downto 0); --data lanes (1 is P, 0 is N)
dphy_d1 : in STD_LOGIC_VECTOR (1 downto 0);
dphy_d2 : in STD_LOGIC_VECTOR (1 downto 0);
dphy_d3 : in STD_LOGIC_VECTOR (1 downto 0);
ref_clock : in STD_LOGIC; --reference clock for clock detection and IDELAYCTRLs (nominally ~200MHz)
reset : in STD_LOGIC; --active high synchronous reset in
enable : in STD_LOGIC; --active high enable out
wait_for_sync : in STD_LOGIC; --sync wait signal from packet handler
packet_done : in STD_LOGIC; --packet done signal from packet handler
reset_out : out STD_LOGIC; --reset output based on clock detection
word_clock : out STD_LOGIC; --divided word clock output
word_data : out STD_LOGIC_VECTOR (31 downto 0); --aligned word data output
word_valid : out STD_LOGIC --whether or not above data is synced and aligned
);
end csi_rx_4_lane_link;
architecture Behavioral of csi_rx_4_lane_link is
signal ddr_bit_clock : std_logic;
signal ddr_bit_clock_b : std_logic;
signal word_clock_int : std_logic;
signal serdes_reset : std_logic;
signal deser_data : std_logic_vector(31 downto 0);
signal deser_data_rev : std_logic_vector(31 downto 0);
signal byte_align_data : std_logic_vector(31 downto 0);
signal byte_valid : std_logic_vector(3 downto 0);
signal word_align_data : std_logic_vector(31 downto 0);
signal byte_packet_done : std_logic;
begin
clkphy : entity work.csi_rx_hs_clk_phy
generic map(
series => fpga_series,
term_en => dphy_term_en)
port map(
dphy_clk => dphy_clk,
reset => reset,
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int);
clkdet : entity work.csi_rx_clock_det
port map(
ref_clock => ref_clock,
ext_clock => word_clock_int,
enable => enable,
reset_in => reset,
reset_out => serdes_reset);
d0phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d0_invert,
term_en => dphy_term_en,
delay => d0_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d0,
deser_out => deser_data(7 downto 0));
d1phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d1_invert,
term_en => dphy_term_en,
delay => d1_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d1,
deser_out => deser_data(15 downto 8));
d2phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d2_invert,
term_en => dphy_term_en,
delay => d2_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d2,
deser_out => deser_data(23 downto 16));
d3phy : entity work.csi_rx_hs_lane_phy
generic map(
series => fpga_series,
invert => d3_invert,
term_en => dphy_term_en,
delay => d3_skew)
port map (
ddr_bit_clock => ddr_bit_clock,
ddr_bit_clock_b => ddr_bit_clock_b,
byte_clock => word_clock_int,
enable => enable,
reset => serdes_reset,
dphy_hs => dphy_d3,
deser_out => deser_data(31 downto 24));
gen_bytealign : for i in 0 to 3 generate
ba : entity work.csi_rx_byte_align
port map (
clock => word_clock_int,
reset => serdes_reset,
enable => enable,
deser_in => deser_data((8*i) + 7 downto 8 * i),
wait_for_sync => wait_for_sync,
packet_done => byte_packet_done,
valid_data => byte_valid(i),
data_out => byte_align_data((8*i) + 7 downto 8 * i));
end generate;
wordalign : entity work.csi_rx_word_align
port map (
word_clock => word_clock_int,
reset => serdes_reset,
enable => enable,
packet_done => packet_done,
wait_for_sync => wait_for_sync,
packet_done_out => byte_packet_done,
word_in => byte_align_data,
valid_in => byte_valid,
word_out => word_align_data,
valid_out => word_valid);
word_clock <= word_clock_int;
word_data <= word_align_data;
reset_out <= serdes_reset;
gen_idctl : if generate_idelayctrl generate
idctrl : entity work.csi_rx_idelayctrl_gen
port map(
ref_clock => ref_clock,
reset => reset);
end generate;
end Behavioral;
| mit | 2e018e2358f07b384126f5f98587afd1 | 0.606676 | 3.32277 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ltc2351/tb/adc_ltc2351_module_tb.vhd | 2 | 4,677 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc_ltc2351_module"
-- Project :
-------------------------------------------------------------------------------
-- File : adc_ltc2351_module_tb.vhd
-- Author : strongly-typed
-- Company :
-- Created : 2012-04-10
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-- Tests the ADC LTC2351 module including a simulation of the ADC.
-- It is not self checking. The expected result after an ADC cycle (when done
-- went '1' is that the register file (reg_i(0) to reg_i(5)) contains the
-- predefined ADC values from adc_ltc2351_model.vhd
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_module_tb is
end adc_ltc2351_module_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ltc2351_module_tb is
use work.adc_ltc2351_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 0;
-- component ports
signal adc_out_p : adc_ltc2351_spi_out_type;
signal adc_in_p : adc_ltc2351_spi_in_type;
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type;
signal sck_p : std_logic;
signal conv_p : std_logic;
signal sdo_p : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : adc_ltc2351_module
generic map (
BASE_ADDRESS => BASE_ADDRESS
)
port map (
adc_out_p => adc_out_p,
adc_in_p => adc_in_p,
bus_o => bus_o,
bus_i => bus_i,
adc_values_o => open,
done_p => open,
clk => clk
);
STIM : adc_ltc2351_model
port map (
sck => sck_p,
conv => conv_p,
sdo => sdo_p
);
-- --------------------------------------------------------------------------
-- clock generation
-----------------------------------------------------------------------------
clk <= not clk after 10 ns;
sck_p <= adc_out_P.sck;
conv_p <= adc_out_p.conv;
adc_in_p.sdo <= sdo_p;
-- --------------------------------------------------------------------------
-- waveform generation
-- --------------------------------------------------------------------------
-- waveform generation
bus_stimulus_proc : process
begin
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
-- write 0x01 to 0x00
wait until Clk = '1';
bus_i.addr <= (others => '0');
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
-- write 0x01 to 0x01
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.data <= "0000" & "0000" & "0000" & "0001";
bus_i.re <= '0';
bus_i.we <= '1';
wait until Clk = '1';
bus_i.data <= (others => '0');
bus_i.we <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
bus_i.addr(0) <= '0';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- do the same reads, but the DUT shouldn't react
bus_i.addr(0) <= '0';
bus_i.addr(8) <= '0'; -- another address
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
bus_i.addr(0) <= '1';
bus_i.re <= '1';
wait until Clk = '1';
bus_i.re <= '0';
wait until Clk = '1';
wait for 10000 ns;
end process bus_stimulus_proc;
end tb;
-------------------------------------------------------------------------------
configuration adc_ltc2351_module_tb_tb_cfg of adc_ltc2351_module_tb is
for tb
end for;
end adc_ltc2351_module_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | 86231ce3e8143f318a30b776e0674c9d | 0.413513 | 3.694313 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/add-rtl.vhdl | 1 | 1,531 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of add is
begin
add : entity work.add_inferred(rtl)
generic map (
src_bits => src_bits
)
port map (
carryin => carryin,
src1 => src1,
src2 => src2,
result => result,
carryout => carryout,
overflow => overflow
);
end;
| apache-2.0 | 0efd99954f80be1d21fe78869018eb58 | 0.475506 | 5.37193 | false | false | false | false |
pgavin/carpe | hdl/sim/monitor_sync_watch-behav.vhdl | 1 | 2,205 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library sim;
use sim.options_pkg.all;
use sim.monitor_pkg.all;
architecture behav of monitor_sync_watch is
begin
process is
variable old_data : std_ulogic_vector(data_bits-1 downto 0);
variable source : monitor_event_source_id_type;
begin
wait until options_ready and monitor_enable;
if option(instance & ":" & name & ":monitor") = "true" then
source := monitor_event_source(instance, monitor_event_code_watch, name);
if option("verbose") = "true" then
report "monitor " & instance & " " & name & " enabled";
end if;
monitor_event(source, data);
loop
wait until rising_edge(clk);
if old_data /= data then
monitor_event(source, data);
old_data := data;
end if;
end loop;
else
if option("verbose") = "true" then
report "monitor " & instance & " " & name & " disabled";
end if;
wait;
end if;
end process;
end;
| apache-2.0 | e0f064f229aa66cbce593e1f62c33ac9 | 0.517007 | 4.762419 | false | false | false | false |
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