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SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/globalmixer_v1_00_a/hdl/vhdl/globalmixer.vhd | 1 | 17,936 | ------------------------------------------------------------------------------
-- globalmixer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: globalmixer.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 29 17:58:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library globalmixer_v1_00_a;
use globalmixer_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity globalmixer is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
GM_Left_in_0 : in std_logic_vector(23 downto 0);
GM_Right_in_0 : in std_logic_vector(23 downto 0);
GM_Left_in_1 : in std_logic_vector(23 downto 0);
GM_Right_in_1 : in std_logic_vector(23 downto 0);
GM_Left_in_2 : in std_logic_vector(23 downto 0);
GM_Right_in_2 : in std_logic_vector(23 downto 0);
GM_Left_in_3 : in std_logic_vector(23 downto 0);
GM_Right_in_3 : in std_logic_vector(23 downto 0);
GM_Left_out : out std_logic_vector(23 downto 0);
GM_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity globalmixer;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of globalmixer is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity globalmixer_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
GM_Left_in_0 => GM_Left_in_0,
GM_Right_in_0 => GM_Right_in_0,
GM_Left_in_1 => GM_Left_in_1,
GM_Right_in_1 => GM_Right_in_1,
GM_Left_in_2 => GM_Left_in_2,
GM_Right_in_2 => GM_Right_in_2,
GM_Left_in_3 => GM_Left_in_3,
GM_Right_in_3 => GM_Right_in_3,
GM_Left_out => GM_Left_out,
GM_Right_out => GM_Right_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | e6e441f92e32463841534c4dec581678 | 0.459244 | 4.031468 | false | false | false | false |
loa-org/loa-hdl | modules/ws2812/hdl/ws2812.vhd | 1 | 5,172 | -------------------------------------------------------------------------------
-- Title : WS2812 Controller
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description: This is an WS2812 Master, it must be commanded to put out
-- single pixels and finished with a reset sequence.
--
-- Timing constants are defined in ws2812_cfg_pkg.vhd
--
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ws2812_pkg.all;
use work.ws2812_cfg_pkg.all;
use work.reset_pkg.all;
entity ws2812 is
generic (
RESET_IMPL : reset_type := none);
port (
ws2812_in : in ws2812_in_type;
ws2812_out : out ws2812_out_type;
ws2812_chain_out : out ws2812_chain_out_type;
reset : in std_logic;
clk : in std_logic);
end ws2812;
architecture rtl of ws2812 is
type ws2812_states is (idle, rst, write1, write2, write3);
type ws2812_state_type is record
timer : integer range 0 to 3000;
chain_out : ws2812_chain_out_type;
o : ws2812_out_type;
sr : std_logic_vector(23 downto 0);
bit_cnt : integer range 0 to 23;
state : ws2812_states;
end record;
constant ws2812_state_type_initial : ws2812_state_type := (timer => 0,
chain_out => (d => '0'),
o => (busy => '1'),
sr => (others => '0'),
bit_cnt => 0,
state => idle);
signal r, rin : ws2812_state_type := ws2812_state_type_initial;
begin -- ws2812
ws2812_chain_out <= r.chain_out;
ws2812_out <= r.o;
comb : process(r, ws2812_in, reset)
variable v : ws2812_state_type;
begin
v := r;
case v.state is
when idle =>
v.o.busy := '0';
if ws2812_in.send_reset = '1' then
v.state := rst;
v.timer := reset_cycles;
v.o.busy := '1';
end if;
if ws2812_in.we = '1' then
v.sr := ws2812_in.d;
v.bit_cnt := 0;
v.state := write1;
v.o.busy := '1';
end if;
-----------------------------------------------------------------------
-- Reset
-----------------------------------------------------------------------
when rst =>
v.chain_out.d := '0';
if v.timer = 0 then
v.state := idle;
else
v.timer := v.timer - 1;
end if;
-------------------------------------------------------------------------
-- Write loop sequence
-------------------------------------------------------------------------
when write1 =>
v.chain_out.d := '1';
if v.sr(23) = '0' then
v.timer := zero_th_cycles;
else
v.timer := one_th_cycles;
end if;
v.state := write2;
when write2 =>
if v.timer = 0 then
if v.sr(23) = '0' then
v.timer := zero_tl_cycles;
else
v.timer := one_tl_cycles;
end if;
v.state := write3;
else
v.timer := v.timer - 1;
end if;
when write3 =>
v.chain_out.d := '0';
v.timer := v.timer - 1;
if v.timer = 0 then
v.sr := v.sr(22 downto 0) & '0';
if v.bit_cnt = 23 then
v.state := idle;
else
v.state := write1;
v.bit_cnt := v.bit_cnt + 1;
end if;
end if;
when others => null;
end case;
-- sync reset
if RESET_IMPL = sync and reset = '1' then
v := ws2812_state_type_initial;
end if;
rin <= v;
end process comb;
async_reset : if RESET_IMPL = async generate
seq : process (clk, reset) is
begin -- process seq
if reset = '0' then -- asynchronous reset (active low)
r <= ws2812_state_type_initial;
elsif clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
sync_reset : if RESET_IMPL /= async generate
seq : process (clk) is
begin -- process seq
if clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
end rtl;
| bsd-3-clause | ca0c9c54ed86a7fa267c79298fd7f03c | 0.412993 | 4.187854 | false | false | false | false |
loa-org/loa-hdl | modules/adc_mcp3008/tb/adc_mcp3008_tb.vhd | 2 | 4,012 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc_mcp3008"
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simulates a single cycle measurement. Is not self-checking.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity adc_mcp3008_tb is
end adc_mcp3008_tb;
-------------------------------------------------------------------------------
architecture tb of adc_mcp3008_tb is
use work.adc_mcp3008_pkg.all;
-- Component generics
constant DELAY : natural := 5;
-- component ports
signal miso_p : std_logic;
signal mosi_p : std_logic;
signal cs_np : std_logic;
signal sck_p : std_logic;
signal start_p : std_logic;
signal adc_mode_p : std_logic;
signal channel_p : std_logic_vector(2 downto 0);
signal value_p : std_logic_vector(9 downto 0);
signal done_p : std_logic;
signal adc_i : adc_mcp3008_spi_in_type;
signal adc_o : adc_mcp3008_spi_out_type;
--signal clk : std_logic;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : adc_mcp3008
generic map (
DELAY => 5)
port map (
adc_out => adc_o,
adc_in => adc_i,
start_p => start_p,
adc_mode_p => adc_mode_p,
channel_p => channel_p,
value_p => value_p,
done_p => done_p,
clk => clk);
adc_i.miso <= miso_p;
mosi_p <= adc_o.mosi;
cs_np <= adc_o.cs_n;
sck_p <= adc_o.sck;
-----------------------------------------------------------------------------
-- clock generation
-----------------------------------------------------------------------------
Clk <= not Clk after 10 ns;
-----------------------------------------------------------------------------
-- this is the bus/command side of the ADC I/F
-----------------------------------------------------------------------------
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
start_p <= '0';
adc_mode_p <= '1';
channel_p <= "011";
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
start_p <= '1';
wait until Clk = '1';
start_p <= '0';
wait until Clk = '1';
wait for 1 ms;
end process WaveGen_Proc;
-----------------------------------------------------------------------------
-- ADC side stimulus
-----------------------------------------------------------------------------
process
begin
miso_p <= 'Z';
wait until cs_np = '0';
wait until sck_p = '1';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
wait until sck_p = '0';
-- leading zero of mcp3008
miso_p <= '0';
wait until sck_p = '0';
-- actual MSB of conversion
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= '0';
wait until sck_p = '0';
miso_p <= '1';
wait until sck_p = '0';
miso_p <= 'Z';
wait for 1 ms;
end process;
end tb;
-------------------------------------------------------------------------------
configuration adc_mcp3008_tb_tb_cfg of adc_mcp3008_tb is
for tb
end for;
end adc_mcp3008_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | f82737c62625d41ba49088fc8912773c | 0.392074 | 4.040282 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl | 1 | 69,926 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_sync_ref_0_0 -prefix
-- system_vga_sync_ref_0_0_ system_vga_sync_ref_1_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
end system_vga_sync_ref_0_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_0_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_0_0 : entity is "system_vga_sync_ref_1_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_0_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_0_0;
architecture STRUCTURE of system_vga_sync_ref_0_0 is
begin
U0: entity work.system_vga_sync_ref_0_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | fa4d183a4300039ad916e1fa0e79787b | 0.48547 | 2.524131 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_buffer_register_1_0/synth/system_buffer_register_1_0.vhd | 2 | 4,059 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:buffer_register:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_buffer_register_1_0 IS
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_buffer_register_1_0;
ARCHITECTURE system_buffer_register_1_0_arch OF system_buffer_register_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_buffer_register_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT buffer_register IS
GENERIC (
WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT buffer_register;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_buffer_register_1_0_arch: ARCHITECTURE IS "buffer_register,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_buffer_register_1_0_arch : ARCHITECTURE IS "system_buffer_register_1_0,buffer_register,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_buffer_register_1_0_arch: ARCHITECTURE IS "system_buffer_register_1_0,buffer_register,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=buffer_register,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : buffer_register
GENERIC MAP (
WIDTH => 32
)
PORT MAP (
clk => clk,
val_in => val_in,
val_out => val_out
);
END system_buffer_register_1_0_arch;
| mit | f58504b8241671d58c84f3858b204502 | 0.739837 | 3.948444 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_nmsuppression/vga_nmsuppression.srcs/sources_1/new/vga_nmsuppression.vhd | 3 | 2,178 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_nmsuppression is
generic (
ROW_WIDTH : integer := 5
);
port (
clk : in std_logic;
enable : in std_logic;
active : in std_logic;
x_addr_in : in std_logic_vector(9 downto 0);
y_addr_in : in std_logic_vector(9 downto 0);
hessian_in : in std_logic_vector(31 downto 0);
x_addr_out : out std_logic_vector(9 downto 0);
y_addr_out : out std_logic_vector(9 downto 0);
hessian_out : out std_logic_vector(31 downto 0)
);
end vga_nmsuppression;
architecture Behavioral of vga_nmsuppression is
type HESSIAN_BUFFER is array (ROW_WIDTH * 2 + 2 downto 0) of std_logic_vector(31 downto 0);
signal hessian : HESSIAN_BUFFER;
begin
process(clk)
variable center : unsigned(31 downto 0) := x"00000000";
begin
if rising_edge(clk) then
if active = '1' then
-- compare
center := unsigned(hessian(ROW_WIDTH + 1));
if enable = '1' and (unsigned(hessian_in) > center or
unsigned(hessian(0)) > center or
unsigned(hessian(1)) > center or
unsigned(hessian(ROW_WIDTH)) > center or
unsigned(hessian(ROW_WIDTH + 2)) > center or
unsigned(hessian(ROW_WIDTH * 2 - 1)) > center or
unsigned(hessian(ROW_WIDTH * 2)) > center or
unsigned(hessian(ROW_WIDTH * 2 + 1)) > center) then
hessian_out <= x"00000000";
else
hessian_out <= std_logic_vector(center);
end if;
x_addr_out <= std_logic_vector(unsigned(x_addr_in) - 1);
y_addr_out <= std_logic_vector(unsigned(y_addr_in) - 1);
-- shift
for i in 0 to ROW_WIDTH * 2 loop
hessian(i+1) <= hessian(i);
end loop;
hessian(0) <= hessian_in;
end if;
end if;
end process;
end Behavioral;
| mit | 308895cf4c7ef5de53af8a81677e9afc | 0.51056 | 3.801047 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_axi_buffer/vga_axi_buffer_1.0/hdl/vga_axi_buffer_v1_0_SAXI.vhd | 1 | 16,566 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_axi_buffer_v1_0_SAXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
clk : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end vga_axi_buffer_v1_0_SAXI;
architecture arch_imp of vga_axi_buffer_v1_0_SAXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 5
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
--slv_reg0 <= (others => '0');
--slv_reg1 <= (others => '0');
--slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
--slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
--slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
--slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
--slv_reg0 <= slv_reg0;
--slv_reg1 <= slv_reg1;
--slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
when b"011" =>
reg_data_out <= slv_reg3;
when b"100" =>
reg_data_out <= slv_reg4;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
process(clk) is
begin
if rising_edge(clk) then
if slv_reg3(24) = '0' then
slv_reg0(9 downto 0) <= x_addr_w;
slv_reg0(19 downto 10) <= y_addr_w;
slv_reg0(20) <= wen;
slv_reg1(9 downto 0) <= x_addr_r;
slv_reg1(19 downto 10) <= y_addr_r;
slv_reg2(23 downto 0) <= data_w;
data_r <= slv_reg3(23 downto 0);
end if;
end if;
end process;
-- User logic ends
end arch_imp;
| mit | f2e4fcb76429f9b40fb0613c6826d08e | 0.604431 | 3.441213 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 195,639 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
pullup_MIO_0inst: unisim.vcomponents.PULLUP
port map (
O => MIO(0)
);
pullup_MIO_9inst: unisim.vcomponents.PULLUP
port map (
O => MIO(9)
);
pullup_MIO_10inst: unisim.vcomponents.PULLUP
port map (
O => MIO(10)
);
pullup_MIO_11inst: unisim.vcomponents.PULLUP
port map (
O => MIO(11)
);
pullup_MIO_12inst: unisim.vcomponents.PULLUP
port map (
O => MIO(12)
);
pullup_MIO_13inst: unisim.vcomponents.PULLUP
port map (
O => MIO(13)
);
pullup_MIO_14inst: unisim.vcomponents.PULLUP
port map (
O => MIO(14)
);
pullup_MIO_15inst: unisim.vcomponents.PULLUP
port map (
O => MIO(15)
);
pullup_MIO_46inst: unisim.vcomponents.PULLUP
port map (
O => MIO(46)
);
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 9663431f7757db27802003753a3cf6a7 | 0.633882 | 2.761858 | false | false | false | false |
loa-org/loa-hdl | modules/utils/tb/edge_detect_tb.vhd | 2 | 1,875 | -------------------------------------------------------------------------------
-- Title : Testbench for design "edge_detect"
-------------------------------------------------------------------------------
-- File : edge_detect_tb.vhd
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.utils_pkg.all;
-------------------------------------------------------------------------------
entity edge_detect_tb is
end entity edge_detect_tb;
-------------------------------------------------------------------------------
architecture tb of edge_detect_tb is
--Inputs
signal async_sig : std_logic := '0';
--Outputs
signal rise : std_logic;
signal fall : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
uut : edge_detect
port map (
async_sig => async_sig,
clk => clk,
rise => rise,
fall => fall);
-- clock generation
clk <= not clk after 5 ns;
-- Create an asynchronous, random signal
stim : process
variable seed1, seed2 : positive;
variable Rand : real;
variable IRand : integer;
begin
-- Zufallszahl ziwschen 0 und 1
uniform(seed1, seed2, rand);
-- daraus ein Integer zwischen 50 und 150
irand := integer((rand*100.0 - 0.5) + 50.0);
-- und dann diese Zeit abwarten
wait for irand * 1 ns;
async_sig <= not async_sig;
end process;
end architecture tb;
-------------------------------------------------------------------------------
| bsd-3-clause | c01c626f6361a73048163bb0d9662bc2 | 0.416 | 4.795396 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_1/synth/affine_block_ieee754_fp_multiplier_1_1.vhd | 2 | 4,008 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_1;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_1_arch OF affine_block_ieee754_fp_multiplier_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_multiplier_1_1_arch: ARCHITECTURE IS "ieee754_fp_multiplier,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_multiplier_1_1_arch : ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_1,ieee754_fp_multiplier,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_multiplier_1_1_arch: ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_1,ieee754_fp_multiplier,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_multiplier,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_1_arch;
| mit | c9c61cc07c0613b115f26054a6230ef9 | 0.749251 | 3.802657 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_affine_transform_0_1/synth/system_affine_transform_0_1.vhd | 1 | 4,453 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:affine_transform:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_affine_transform_0_1 IS
PORT (
a00 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_affine_transform_0_1;
ARCHITECTURE system_affine_transform_0_1_arch OF system_affine_transform_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_affine_transform_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT affine_block_wrapper IS
PORT (
a00 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a01 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT affine_block_wrapper;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_affine_transform_0_1_arch: ARCHITECTURE IS "affine_block_wrapper,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_affine_transform_0_1_arch : ARCHITECTURE IS "system_affine_transform_0_1,affine_block_wrapper,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_affine_transform_0_1_arch: ARCHITECTURE IS "system_affine_transform_0_1,affine_block_wrapper,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=affine_transform,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : affine_block_wrapper
PORT MAP (
a00 => a00,
a01 => a01,
a10 => a10,
a11 => a11,
x_in => x_in,
x_out => x_out,
y_in => y_in,
y_out => y_out
);
END system_affine_transform_0_1_arch;
| mit | ca92c00e4a853ac62b75565e85aee792 | 0.724455 | 3.686258 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_rst_controller_001.vhd | 1 | 3,687 | -- niosii_system_rst_controller_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 2;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
reset_in1 : in std_logic := '0'; -- reset_in1.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic
);
end entity niosii_system_rst_controller_001;
architecture rtl of niosii_system_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_in3 : in std_logic := 'X'; -- reset
reset_in4 : in std_logic := 'X'; -- reset
reset_in5 : in std_logic := 'X'; -- reset
reset_in6 : in std_logic := 'X'; -- reset
reset_in7 : in std_logic := 'X'; -- reset
reset_in8 : in std_logic := 'X'; -- reset
reset_in9 : in std_logic := 'X'; -- reset
reset_in10 : in std_logic := 'X'; -- reset
reset_in11 : in std_logic := 'X'; -- reset
reset_in12 : in std_logic := 'X'; -- reset
reset_in13 : in std_logic := 'X'; -- reset
reset_in14 : in std_logic := 'X'; -- reset
reset_in15 : in std_logic := 'X' -- reset
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
reset_in1 => reset_in1, -- reset_in1.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_rst_controller_001
| apache-2.0 | de5b275cd52dd4678be9235460d3d8b8 | 0.553024 | 2.735163 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s4.vhd | 2 | 3,979 | library ieee;
use ieee.std_logic_1164.all;
entity s4 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s4;
architecture behaviour of s4 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
end case;
end process;
end; | mit | d0eb0329aa2ddaa35fce5fe00c0e8b1e | 0.673536 | 3.030465 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_1/synth/affine_block_ieee754_fp_to_uint_0_1.vhd | 2 | 3,943 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_1;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_1_arch OF affine_block_ieee754_fp_to_uint_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_to_uint_0_1_arch: ARCHITECTURE IS "ieee754_fp_to_uint,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_to_uint_0_1_arch : ARCHITECTURE IS "affine_block_ieee754_fp_to_uint_0_1,ieee754_fp_to_uint,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_to_uint_0_1_arch: ARCHITECTURE IS "affine_block_ieee754_fp_to_uint_0_1,ieee754_fp_to_uint,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_to_uint,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=10}";
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_1_arch;
| mit | 65ce13b01214a1fd8f7b545b81b4cf0a | 0.739031 | 3.644177 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl | 1 | 10,119 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:46 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
active : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_0_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal \data_pair[15]_i_1_n_0\ : STD_LOGIC;
signal \data_pair[7]_i_1_n_0\ : STD_LOGIC;
signal \data_pair_reg_n_0_[0]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[10]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[11]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[12]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[13]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[14]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[15]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[1]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[2]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[3]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[4]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[5]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[6]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[7]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[8]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[9]\ : STD_LOGIC;
signal rgb_regn_0_0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => \data_pair[7]_i_1_n_0\,
Q => cycle,
R => '0'
);
\data_pair[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle,
I1 => active,
O => \data_pair[15]_i_1_n_0\
);
\data_pair[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => active,
I1 => cycle,
O => \data_pair[7]_i_1_n_0\
);
\data_pair_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[0]\,
R => '0'
);
\data_pair_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[10]\,
R => '0'
);
\data_pair_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[11]\,
R => '0'
);
\data_pair_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[12]\,
R => '0'
);
\data_pair_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[13]\,
R => '0'
);
\data_pair_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[14]\,
R => '0'
);
\data_pair_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[15]\,
R => '0'
);
\data_pair_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[1]\,
R => '0'
);
\data_pair_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[2]\,
R => '0'
);
\data_pair_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[3]\,
R => '0'
);
\data_pair_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[4]\,
R => '0'
);
\data_pair_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[5]\,
R => '0'
);
\data_pair_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[6]\,
R => '0'
);
\data_pair_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[7]\,
R => '0'
);
\data_pair_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[8]\,
R => '0'
);
\data_pair_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[9]\,
R => '0'
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[0]\,
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[10]\,
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[11]\,
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[12]\,
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[13]\,
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[14]\,
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[15]\,
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[1]\,
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[2]\,
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[3]\,
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[4]\,
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[5]\,
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[6]\,
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[7]\,
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[8]\,
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[9]\,
Q => rgb(9),
R => '0'
);
rgb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_x2,
O => rgb_regn_0_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_0_0;
architecture STRUCTURE of system_ov7670_vga_0_0 is
begin
U0: entity work.system_ov7670_vga_0_0_ov7670_vga
port map (
active => active,
clk_x2 => clk_x2,
data(7 downto 0) => data(7 downto 0),
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | 2767168cc016e4e26b1e102609280cec | 0.506572 | 2.787603 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/DE2Component.vhd | 1 | 9,775 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port (
KEY : in std_logic_vector (3 downto 0); --Buttons
SW : in std_logic_vector (7 downto 0); -- Switches
CLOCK_50 : in std_logic; -- 50 MHz Clock
LEDG : out DE2_LED_GREEN; -- Green LEDs
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
--UART Connection
UART_TXD : out std_logic; --Transmitter
UART_RXD : in std_logic; --Receiver
-- USB controller
OTG_INT0 : in std_logic;
OTG_INT1 : in std_logic;
OTG_DREQ0 : in std_logic;
OTG_DREQ1 : in std_logic;
OTG_DACK0_N : out std_logic;
OTG_DACK1_N : out std_logic;
OTG_FSPEED : out std_logic;
OTG_LSPEED : out std_logic;
OTG_ADDR : out std_logic_vector(1 downto 0);
OTG_DATA : inout std_logic_vector(15 downto 0);
OTG_CS_N : out std_logic;
OTG_RD_N : out std_logic;
OTG_WR_N : out std_logic;
OTG_RST_N : out std_logic;
--Flash
FL_ADDR : out std_logic_vector (21 downto 0);
FL_CE_N : out std_logic_vector (0 downto 0);
FL_OE_N : out std_logic_vector (0 downto 0);
FL_DQ : inout std_logic_vector (7 downto 0);
FL_RST_N : out std_logic_vector (0 downto 0) := "1";
FL_WE_N : out std_logic_vector (0 downto 0)
);
end DE2Component;
architecture structure of DE2Component is
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
altpll_0_c0_clk : out std_logic; -- clk
usb_0_external_interface_INT1 : in std_logic := 'X'; -- Interrupt1
usb_0_external_interface_INT0 : in std_logic := 'X'; -- Interrupt2
usb_0_external_interface_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
usb_0_external_interface_RST_N : out std_logic; -- reset_n
usb_0_external_interface_ADDR : out std_logic_vector(1 downto 0); -- ADDR
usb_0_external_interface_CS_N : out std_logic; -- CS_N
usb_0_external_interface_RD_N : out std_logic; -- RD_N
usb_0_external_interface_WR_N : out std_logic; -- WR_N
rs232_0_external_interface_RXD : in std_logic; --:= 'X'; -- RXD
rs232_0_external_interface_TXD : out std_logic; -- TXD
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
-- DACK not used
OTG_DACK0_N <= 'Z';
OTG_DACK1_N <= 'Z';
-- Speed set to Full-speed
OTG_FSPEED <= 'Z';
OTG_LSPEED <= '0';
--Memory related signal settings. Appears to be used for combining two signals into a singal interface.
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
usb_0_external_interface_INT1 => OTG_INT1,
usb_0_external_interface_INT0 => OTG_INT0,
usb_0_external_interface_DATA => OTG_DATA,
usb_0_external_interface_RST_N => OTG_RST_N,
usb_0_external_interface_ADDR => OTG_ADDR,
usb_0_external_interface_CS_N => OTG_CS_N,
usb_0_external_interface_RD_N => OTG_RD_N,
usb_0_external_interface_WR_N => OTG_WR_N,
rs232_0_external_interface_RXD => UART_RXD,
rs232_0_external_interface_TXD => UART_TXD,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out => FL_ADDR,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out => FL_CE_N,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out => FL_OE_N,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out => FL_DQ,
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out => FL_WE_N
);
end structure;
library ieee;
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| apache-2.0 | 450545d5ad5423f5cc1da541c7d7f1aa | 0.526343 | 3.10712 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0_1/system_clk_wiz_0_0_sim_netlist.vhdl | 1 | 7,622 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:45 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0_1/system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz : entity is "system_clk_wiz_0_0_clk_wiz";
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 9.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
| mit | a4f0886de4808e11a9edcfda08841d60 | 0.63789 | 3.274055 | false | false | false | false |
loa-org/loa-hdl | modules/utils/tb/fractional_clock_divider_variable_tb.vhd | 2 | 569 |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity fractional_clock_divider_variable_tb is
end fractional_clock_divider_variable_tb;
architecture tb of fractional_clock_divider_variable_tb is
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
uut : fractional_clock_divider_variable
generic map (
WIDTH => 16)
port map (
div => x"05f4",
mul => x"0001",
clk_out_p => output,
clk => clk);
end tb;
| bsd-3-clause | 0ed0e249669ebdf9bd09b8f329179c9d | 0.604569 | 3.534161 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/hdl/imotor_uart_tx.vhd | 2 | 6,630 | -------------------------------------------------------------------------------
-- Title : iMotor UART send
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Simple UART that sends parallel data serially.
--
-- This implementation does not have an baud rate generator. As the intention
-- of this entity is to be used in parallel a global baud rate generator is
-- used. When new data is to be send the entity needs to wait for the first
-- clock enable of the baud rate generator. Otherwise the length of the start
-- bit would be different.
--
-- The parity bit is always present. If parity is set to None it is set '1'
-- which is interpreted as the stop bit. In this case there is one more
-- stop bit then requested.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_uart_tx is
generic (
START_BITS : positive := 1;
DATA_BITS : positive := 8;
STOP_BITS : positive := 1;
PARITY : parity_type := None
);
port (
data_in_p : in std_logic_vector(DATA_BITS - 1 downto 0); -- parallel
-- data in
start_in_p : in std_logic; -- start a transmission of data_in_p
busy_out_p : out std_logic; -- high when busy
txd_out_p : out std_logic; -- output to transceiver
clock_tx_in_p : in std_logic; -- Bit clock for transmitter
clk : in std_logic
);
end imotor_uart_tx;
-------------------------------------------------------------------------------
architecture behavioural of imotor_uart_tx is
type imotor_uart_tx_state_type is (
IDLE, -- Idle state:
STATE1, -- State 1: Request to send received, wait for first bit time.
STATE2 -- State 2: Sending of bis in progress
);
type imotor_uart_tx_type is record
-- shift register
-- Omitting -1 because of the parity bit
sr : std_logic_vector (START_BITS + DATA_BITS + STOP_BITS downto 0);
-- Number of bits
-- One more for parity bit
bitcnt : integer range 0 to START_BITS + DATA_BITS + 1 + STOP_BITS;
state : imotor_uart_tx_state_type;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : imotor_uart_tx_type := (state => IDLE,
sr => (others => '1'),
bitcnt => START_BITS + DATA_BITS + 1 + STOP_BITS);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
busy_out_p <= '1' when (start_in_p = '1' or r.state /= IDLE) else '0';
txd_out_p <= r.sr(0) when (r.state = STATE2) else '1';
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clock_tx_in_p, data_in_p, r, start_in_p)
variable v : imotor_uart_tx_type;
variable parity_bit : std_logic := '1'; -- Computed parity, default '1'
-- for parity = None
begin
-- Parity bit:
parity_bit := '1';
for i in data_in_p'range loop
parity_bit := parity_bit xor data_in_p(i);
end loop;
v := r;
case r.state is
when IDLE =>
if start_in_p = '1' then
-- Set the shift register:
-- STOP_BITS PARITY_BIT DATA_BITS START_BITS
-- Upper bits: STOP_BITS set to '1':
v.sr(START_BITS + DATA_BITS + STOP_BITS downto START_BITS + DATA_BITS + 1) := (others => '1');
-- Set parity bit in shift register
case PARITY is
when None => v.sr(START_BITS + DATA_BITS) := '1';
when Even => v.sr(START_BITS + DATA_BITS) := parity_bit;
when Odd => v.sr(START_BITS + DATA_BITS) := not parity_bit;
end case;
-- Lower bits: START_BITS set to '0':
v.sr(START_BITS - 1 downto 0) := (others => '0');
-- Middle bits: DATA_BITS
v.sr(START_BITS + DATA_BITS - 1 downto START_BITS) := data_in_p;
v.bitcnt := 0;
v.state := STATE1;
end if;
when STATE1 =>
-- Bit clock enable arrived, send start bit now.
if clock_tx_in_p = '1' then
v.state := STATE2;
end if;
when STATE2 =>
if clock_tx_in_p = '1' then
if v.bitcnt < (START_BITS + DATA_BITS + STOP_BITS) then
-- Next bit
v.bitcnt := r.bitcnt + 1;
v.sr := '1' & r.sr(v.sr'left downto 1);
else
v.state := IDLE;
end if;
end if;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | 0576d5855418da7cc2b9df41dcef46d7 | 0.406184 | 4.907476 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/synth/system_vga_buffer_0_0.vhd | 4 | 4,630 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "vga_buffer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_buffer_0_0_arch : ARCHITECTURE IS "system_vga_buffer_0_0,vga_buffer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "system_vga_buffer_0_0,vga_buffer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_buffer,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE_POW2=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
| mit | 3c2a9489ace1fa01c47f54948fb71bda | 0.707127 | 3.58082 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl | 2 | 70,017 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 21 18:13:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 09d59283239e88f16c76f6c44034ee62 | 0.531728 | 2.810573 | false | false | false | false |
loa-org/loa-hdl | modules/uss_tx/hdl/serialiser.vhd | 2 | 3,016 | -------------------------------------------------------------------------------
-- Title : Modulator
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser is
generic (
BITPATTERN_WIDTH : positive := 32
);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic
);
end serialiser;
-------------------------------------------------------------------------------
architecture behavioural of serialiser is
type serialiser_type is record
counter : integer range 0 to BITPATTERN_WIDTH;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : serialiser_type := (counter => 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
bitstream_out_p <= pattern_in_p(r.counter);
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clk_bit, r)
variable v : serialiser_type;
begin
v := r;
if clk_bit = '1' then
v.counter := v.counter + 1;
if v.counter = BITPATTERN_WIDTH then
v.counter := 0;
end if;
end if;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | b1244d3eb34d58b9a6ee3546a2d274c4 | 0.301393 | 7.079812 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_sim_netlist.vhdl | 1 | 263,741 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_adder_subtractor_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor is
port (
z : out STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
x : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor : entity is "ieee754_fp_adder_subtractor";
end affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor;
architecture STRUCTURE of affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor is
signal A : STD_LOGIC_VECTOR ( 19 downto 0 );
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal large_exp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal large_mant1_carry_i_1_n_0 : STD_LOGIC;
signal large_mant1_carry_i_2_n_0 : STD_LOGIC;
signal large_mant1_carry_i_3_n_0 : STD_LOGIC;
signal large_mant1_carry_i_4_n_0 : STD_LOGIC;
signal large_mant1_carry_i_5_n_0 : STD_LOGIC;
signal large_mant1_carry_i_6_n_0 : STD_LOGIC;
signal large_mant1_carry_i_7_n_0 : STD_LOGIC;
signal large_mant1_carry_i_8_n_0 : STD_LOGIC;
signal large_mant1_carry_n_0 : STD_LOGIC;
signal large_mant1_carry_n_1 : STD_LOGIC;
signal large_mant1_carry_n_2 : STD_LOGIC;
signal large_mant1_carry_n_3 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
signal sel0 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \sign00__0_carry__0_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_19_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_20_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_40_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_41_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_n_0\ : STD_LOGIC;
signal \sign00__0_carry__0_n_1\ : STD_LOGIC;
signal \sign00__0_carry__0_n_2\ : STD_LOGIC;
signal \sign00__0_carry__0_n_3\ : STD_LOGIC;
signal \sign00__0_carry__1_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_17_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_19_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_41_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_42_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_44_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_46_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_47_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__1_n_1\ : STD_LOGIC;
signal \sign00__0_carry__1_n_2\ : STD_LOGIC;
signal \sign00__0_carry__1_n_3\ : STD_LOGIC;
signal \sign00__0_carry__2_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_40_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__2_n_1\ : STD_LOGIC;
signal \sign00__0_carry__2_n_2\ : STD_LOGIC;
signal \sign00__0_carry__2_n_3\ : STD_LOGIC;
signal \sign00__0_carry__3_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_40_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_47_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_48_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_51_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_52_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__3_n_1\ : STD_LOGIC;
signal \sign00__0_carry__3_n_2\ : STD_LOGIC;
signal \sign00__0_carry__3_n_3\ : STD_LOGIC;
signal \sign00__0_carry__4_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_17_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_18_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_19_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_20_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_27_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_28_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_29_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_30_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_31_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_n_0\ : STD_LOGIC;
signal \sign00__0_carry__4_n_1\ : STD_LOGIC;
signal \sign00__0_carry__4_n_2\ : STD_LOGIC;
signal \sign00__0_carry__4_n_3\ : STD_LOGIC;
signal \sign00__0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \sign00__0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_100_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_101_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_102_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_103_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_104_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_105_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_10_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_11_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_12_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_13_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_14_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_15_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_16_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_17_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_21_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_22_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_23_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_24_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_25_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_26_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_2_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_32_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_33_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_34_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_35_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_36_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_37_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_38_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_39_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_3_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_41_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_42_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_43_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_44_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_45_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_46_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_47_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_48_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_49_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_4_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_51_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_53_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_54_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_55_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_56_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_57_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_58_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_59_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_5_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_60_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_61_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_62_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_63_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_64_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_65_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_66_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_67_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_68_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_69_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_6_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_70_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_71_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_72_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_73_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_74_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_75_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_76_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_77_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_77_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_77_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_78_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_1\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_2\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_3\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_4\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_5\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_6\ : STD_LOGIC;
signal \sign00__0_carry_i_79_n_7\ : STD_LOGIC;
signal \sign00__0_carry_i_7_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_80_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_81_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_82_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_83_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_84_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_85_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_86_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_87_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_88_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_89_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_8_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_90_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_91_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_92_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_93_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_94_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_95_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_96_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_97_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_98_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_99_n_0\ : STD_LOGIC;
signal \sign00__0_carry_i_9_n_0\ : STD_LOGIC;
signal \sign00__0_carry_n_0\ : STD_LOGIC;
signal \sign00__0_carry_n_1\ : STD_LOGIC;
signal \sign00__0_carry_n_2\ : STD_LOGIC;
signal \sign00__0_carry_n_3\ : STD_LOGIC;
signal \sign00__0_carry_n_7\ : STD_LOGIC;
signal small_mant : STD_LOGIC_VECTOR ( 22 downto 0 );
signal sum2 : STD_LOGIC_VECTOR ( 19 downto 18 );
signal sum3 : STD_LOGIC;
signal \sum3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_5_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_6_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_7_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_8_n_0\ : STD_LOGIC;
signal \sum3_carry__0_i_9_n_3\ : STD_LOGIC;
signal \sum3_carry__0_n_0\ : STD_LOGIC;
signal \sum3_carry__0_n_1\ : STD_LOGIC;
signal \sum3_carry__0_n_2\ : STD_LOGIC;
signal \sum3_carry__0_n_3\ : STD_LOGIC;
signal \sum3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_2_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_3_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_4_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_5_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_6_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_7_n_0\ : STD_LOGIC;
signal \sum3_carry__1_i_8_n_0\ : STD_LOGIC;
signal \sum3_carry__1_n_0\ : STD_LOGIC;
signal \sum3_carry__1_n_1\ : STD_LOGIC;
signal \sum3_carry__1_n_2\ : STD_LOGIC;
signal \sum3_carry__1_n_3\ : STD_LOGIC;
signal \sum3_carry__2_i_2_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_3_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_4_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_5_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_6_n_0\ : STD_LOGIC;
signal \sum3_carry__2_i_7_n_0\ : STD_LOGIC;
signal \sum3_carry__2_n_1\ : STD_LOGIC;
signal \sum3_carry__2_n_2\ : STD_LOGIC;
signal \sum3_carry__2_n_3\ : STD_LOGIC;
signal sum3_carry_i_1_n_0 : STD_LOGIC;
signal sum3_carry_i_2_n_0 : STD_LOGIC;
signal sum3_carry_i_3_n_0 : STD_LOGIC;
signal sum3_carry_i_4_n_0 : STD_LOGIC;
signal sum3_carry_i_5_n_0 : STD_LOGIC;
signal sum3_carry_i_6_n_0 : STD_LOGIC;
signal sum3_carry_i_7_n_0 : STD_LOGIC;
signal sum3_carry_i_8_n_0 : STD_LOGIC;
signal sum3_carry_n_0 : STD_LOGIC;
signal sum3_carry_n_1 : STD_LOGIC;
signal sum3_carry_n_2 : STD_LOGIC;
signal sum3_carry_n_3 : STD_LOGIC;
signal sum4 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \sum4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \sum4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \sum4_carry__0_n_0\ : STD_LOGIC;
signal \sum4_carry__0_n_1\ : STD_LOGIC;
signal \sum4_carry__0_n_2\ : STD_LOGIC;
signal \sum4_carry__0_n_3\ : STD_LOGIC;
signal sum4_carry_i_1_n_0 : STD_LOGIC;
signal sum4_carry_i_2_n_0 : STD_LOGIC;
signal sum4_carry_i_3_n_0 : STD_LOGIC;
signal sum4_carry_i_4_n_0 : STD_LOGIC;
signal sum4_carry_i_5_n_0 : STD_LOGIC;
signal sum4_carry_i_6_n_0 : STD_LOGIC;
signal sum4_carry_i_7_n_0 : STD_LOGIC;
signal sum4_carry_i_8_n_0 : STD_LOGIC;
signal sum4_carry_n_0 : STD_LOGIC;
signal sum4_carry_n_1 : STD_LOGIC;
signal sum4_carry_n_2 : STD_LOGIC;
signal sum4_carry_n_3 : STD_LOGIC;
signal \z0_carry__0_n_1\ : STD_LOGIC;
signal \z0_carry__0_n_2\ : STD_LOGIC;
signal \z0_carry__0_n_3\ : STD_LOGIC;
signal z0_carry_i_10_n_0 : STD_LOGIC;
signal z0_carry_i_11_n_0 : STD_LOGIC;
signal z0_carry_i_12_n_0 : STD_LOGIC;
signal z0_carry_i_4_n_0 : STD_LOGIC;
signal \z0_carry_i_5__0_n_0\ : STD_LOGIC;
signal z0_carry_i_5_n_0 : STD_LOGIC;
signal \z0_carry_i_6__0_n_0\ : STD_LOGIC;
signal z0_carry_i_6_n_0 : STD_LOGIC;
signal \z0_carry_i_7__0_n_0\ : STD_LOGIC;
signal z0_carry_i_7_n_0 : STD_LOGIC;
signal \z0_carry_i_8__0_n_0\ : STD_LOGIC;
signal z0_carry_i_8_n_0 : STD_LOGIC;
signal z0_carry_i_9_n_0 : STD_LOGIC;
signal z0_carry_n_0 : STD_LOGIC;
signal z0_carry_n_1 : STD_LOGIC;
signal z0_carry_n_2 : STD_LOGIC;
signal z0_carry_n_3 : STD_LOGIC;
signal z1 : STD_LOGIC_VECTOR ( 7 to 7 );
signal z10_in : STD_LOGIC_VECTOR ( 22 downto 4 );
signal z2 : STD_LOGIC;
signal \z2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z2_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z2_carry__0_n_0\ : STD_LOGIC;
signal \z2_carry__0_n_1\ : STD_LOGIC;
signal \z2_carry__0_n_2\ : STD_LOGIC;
signal \z2_carry__0_n_3\ : STD_LOGIC;
signal \z2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_5_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_6_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_7_n_0\ : STD_LOGIC;
signal \z2_carry__1_i_8_n_0\ : STD_LOGIC;
signal \z2_carry__1_n_0\ : STD_LOGIC;
signal \z2_carry__1_n_1\ : STD_LOGIC;
signal \z2_carry__1_n_2\ : STD_LOGIC;
signal \z2_carry__1_n_3\ : STD_LOGIC;
signal \z2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_5_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_6_n_0\ : STD_LOGIC;
signal \z2_carry__2_i_7_n_0\ : STD_LOGIC;
signal \z2_carry__2_n_1\ : STD_LOGIC;
signal \z2_carry__2_n_2\ : STD_LOGIC;
signal \z2_carry__2_n_3\ : STD_LOGIC;
signal z2_carry_i_1_n_0 : STD_LOGIC;
signal z2_carry_i_2_n_0 : STD_LOGIC;
signal z2_carry_i_3_n_0 : STD_LOGIC;
signal z2_carry_i_4_n_0 : STD_LOGIC;
signal z2_carry_i_5_n_0 : STD_LOGIC;
signal z2_carry_i_6_n_0 : STD_LOGIC;
signal z2_carry_i_7_n_0 : STD_LOGIC;
signal z2_carry_i_8_n_0 : STD_LOGIC;
signal z2_carry_n_0 : STD_LOGIC;
signal z2_carry_n_1 : STD_LOGIC;
signal z2_carry_n_2 : STD_LOGIC;
signal z2_carry_n_3 : STD_LOGIC;
signal z3 : STD_LOGIC_VECTOR ( 30 downto 1 );
signal \z[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[10]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[12]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[13]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[14]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[16]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[17]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[18]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[20]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[21]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[31]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[8]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_large_mant1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sign00__0_carry__5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sign00__0_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_sign00__0_carry_i_77_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_sign00__0_carry_i_77_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_sum3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__0_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_sum3_carry__0_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sum3_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_z2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_z2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \_carry\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_carry_i_15\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \_carry_i_16\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \_carry_i_5\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \_carry_i_7\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \_carry_i_9\ : label is "soft_lutpair14";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_17\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_18\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_36\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \sign00__0_carry__0_i_37\ : label is "soft_lutpair39";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_18\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_20\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_22\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_23\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_24\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_36\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_38\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_39\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_40\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_43\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \sign00__0_carry__1_i_45\ : label is "soft_lutpair33";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_17\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_18\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_19\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_20\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_22\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_24\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_26\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_33\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_34\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_36\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_38\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \sign00__0_carry__2_i_41\ : label is "soft_lutpair39";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_18\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_20\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_41\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_42\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_43\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_44\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_45\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_46\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_49\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \sign00__0_carry__3_i_50\ : label is "soft_lutpair40";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry__4_i_22\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \sign00__0_carry__4_i_25\ : label is "soft_lutpair13";
attribute METHODOLOGY_DRC_VIOS of \sign00__0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \sign00__0_carry_i_18\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \sign00__0_carry_i_19\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \sign00__0_carry_i_20\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \sign00__0_carry_i_40\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \sign00__0_carry_i_50\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \sign00__0_carry_i_52\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \sign00__0_carry_i_54\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \sign00__0_carry_i_56\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \sign00__0_carry_i_67\ : label is "soft_lutpair20";
attribute METHODOLOGY_DRC_VIOS of z0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of z0_carry_i_12 : label is "soft_lutpair15";
attribute METHODOLOGY_DRC_VIOS of z2_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z2_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z2_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \z2_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[0]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[10]_INST_0_i_10\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \z[10]_INST_0_i_8\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[10]_INST_0_i_9\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[13]_INST_0_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[13]_INST_0_i_5\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[14]_INST_0_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_5\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[16]_INST_0_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \z[16]_INST_0_i_7\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[17]_INST_0_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \z[18]_INST_0_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[19]_INST_0_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[1]_INST_0_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[20]_INST_0_i_5\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \z[21]_INST_0_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_11\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_12\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_20\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_23\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_25\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_26\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_27\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_28\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_29\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_30\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_31\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_32\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_33\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_40\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \z[22]_INST_0_i_9\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_4\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_6\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \z[31]_INST_0_i_7\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[4]_INST_0_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[5]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_6\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[8]_INST_0_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[8]_INST_0_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[9]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[9]_INST_0_i_7\ : label is "soft_lutpair46";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \z[22]_INST_0_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(4 downto 1),
S(3) => \_carry_i_1_n_0\,
S(2) => \_carry_i_2_n_0\,
S(1) => \_carry_i_3_n_0\,
S(0) => \_carry_i_4_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(12 downto 9),
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(16 downto 13),
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(20 downto 17),
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(24 downto 21),
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z3(28 downto 25),
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => z3(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFAFAE"
)
port map (
I0 => sel0(17),
I1 => sel0(13),
I2 => \_carry_i_15_n_0\,
I3 => sel0(14),
I4 => sel0(18),
I5 => \_carry_i_16_n_0\,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEF000000000000"
)
port map (
I0 => sel0(9),
I1 => sel0(10),
I2 => sel0(8),
I3 => sel0(7),
I4 => \_carry_i_17_n_0\,
I5 => \_carry_i_18_n_0\,
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(18),
I1 => sel0(17),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \_carry_i_19_n_0\,
I1 => sel0(14),
I2 => sel0(13),
I3 => sel0(2),
I4 => \_carry_i_16_n_0\,
I5 => \z[31]_INST_0_i_6_n_0\,
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(8),
I1 => sel0(7),
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(16),
I1 => sel0(15),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(21),
I1 => sel0(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEEEF"
)
port map (
I0 => sel0(10),
I1 => sel0(9),
I2 => sel0(3),
I3 => sel0(4),
I4 => sel0(5),
I5 => sel0(6),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(12),
I1 => sel0(11),
I2 => sel0(16),
I3 => sel0(15),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(10),
I1 => sel0(9),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => z0_carry_i_9_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554444400000000"
)
port map (
I0 => sel0(23),
I1 => \_carry_i_5_n_0\,
I2 => sel0(14),
I3 => \_carry_i_6_n_0\,
I4 => \_carry_i_7_n_0\,
I5 => \_carry_i_8_n_0\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8A8A8A800"
)
port map (
I0 => \_carry_i_9_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \_carry_i_11_n_0\,
I3 => \_carry_i_12_n_0\,
I4 => sel0(1),
I5 => \_carry_i_13_n_0\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(22),
I1 => sel0(21),
I2 => sel0(19),
I3 => sel0(20),
O => \_carry_i_5_n_0\
);
\_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEEEEEF"
)
port map (
I0 => sel0(12),
I1 => sel0(13),
I2 => sel0(10),
I3 => sel0(9),
I4 => \_carry_i_14_n_0\,
I5 => sel0(11),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(18),
I1 => sel0(17),
I2 => sel0(15),
I3 => sel0(16),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sel0(3),
I1 => sel0(5),
I2 => sel0(6),
I3 => \_carry_i_5_n_0\,
I4 => sel0(4),
I5 => \z[31]_INST_0_i_4_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"54545455"
)
port map (
I0 => sel0(23),
I1 => sel0(22),
I2 => sel0(21),
I3 => sel0(19),
I4 => sel0(20),
O => \_carry_i_9_n_0\
);
large_mant1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => large_mant1_carry_n_0,
CO(2) => large_mant1_carry_n_1,
CO(1) => large_mant1_carry_n_2,
CO(0) => large_mant1_carry_n_3,
CYINIT => '0',
DI(3) => large_mant1_carry_i_1_n_0,
DI(2) => large_mant1_carry_i_2_n_0,
DI(1) => large_mant1_carry_i_3_n_0,
DI(0) => large_mant1_carry_i_4_n_0,
O(3 downto 0) => NLW_large_mant1_carry_O_UNCONNECTED(3 downto 0),
S(3) => large_mant1_carry_i_5_n_0,
S(2) => large_mant1_carry_i_6_n_0,
S(1) => large_mant1_carry_i_7_n_0,
S(0) => large_mant1_carry_i_8_n_0
);
large_mant1_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => y(30),
I3 => x(30),
O => large_mant1_carry_i_1_n_0
);
large_mant1_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => y(28),
I3 => x(28),
O => large_mant1_carry_i_2_n_0
);
large_mant1_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => y(26),
I3 => x(26),
O => large_mant1_carry_i_3_n_0
);
large_mant1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"2F02"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => y(24),
I3 => x(24),
O => large_mant1_carry_i_4_n_0
);
large_mant1_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => x(30),
I3 => y(30),
O => large_mant1_carry_i_5_n_0
);
large_mant1_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => x(28),
I3 => y(28),
O => large_mant1_carry_i_6_n_0
);
large_mant1_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => x(26),
I3 => y(26),
O => large_mant1_carry_i_7_n_0
);
large_mant1_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => x(24),
I3 => y(24),
O => large_mant1_carry_i_8_n_0
);
\sign00__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \sign00__0_carry_n_0\,
CO(2) => \sign00__0_carry_n_1\,
CO(1) => \sign00__0_carry_n_2\,
CO(0) => \sign00__0_carry_n_3\,
CYINIT => A(0),
DI(3) => \sign00__0_carry_i_2_n_0\,
DI(2) => \sign00__0_carry_i_3_n_0\,
DI(1) => \sign00__0_carry_i_4_n_0\,
DI(0) => \sign00__0_carry_i_5_n_0\,
O(3 downto 1) => sel0(2 downto 0),
O(0) => \sign00__0_carry_n_7\,
S(3) => \sign00__0_carry_i_6_n_0\,
S(2) => \sign00__0_carry_i_7_n_0\,
S(1) => \sign00__0_carry_i_8_n_0\,
S(0) => \sign00__0_carry_i_9_n_0\
);
\sign00__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_n_0\,
CO(3) => \sign00__0_carry__0_n_0\,
CO(2) => \sign00__0_carry__0_n_1\,
CO(1) => \sign00__0_carry__0_n_2\,
CO(0) => \sign00__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__0_i_1_n_0\,
DI(2) => \sign00__0_carry__0_i_2_n_0\,
DI(1) => \sign00__0_carry__0_i_3_n_0\,
DI(0) => \sign00__0_carry__0_i_4_n_0\,
O(3 downto 0) => sel0(6 downto 3),
S(3) => \sign00__0_carry__0_i_5_n_0\,
S(2) => \sign00__0_carry__0_i_6_n_0\,
S(1) => \sign00__0_carry__0_i_7_n_0\,
S(0) => \sign00__0_carry__0_i_8_n_0\
);
\sign00__0_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sign00__0_carry__0_i_9_n_0\,
O => \sign00__0_carry__0_i_1_n_0\
);
\sign00__0_carry__0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__0_i_21_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__0_i_22_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_10_n_0\
);
\sign00__0_carry__0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__0_i_23_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_33_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__0_i_11_n_0\
);
\sign00__0_carry__0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__0_i_22_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__0_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_12_n_0\
);
\sign00__0_carry__0_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__0_i_25_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_35_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__0_i_13_n_0\
);
\sign00__0_carry__0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__0_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_23_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_14_n_0\
);
\sign00__0_carry__0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__0_i_26_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry__0_i_27_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__0_i_15_n_0\
);
\sign00__0_carry__0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555655AAAAAAAA"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__0_i_28_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__0_i_10_n_0\,
O => \sign00__0_carry__0_i_16_n_0\
);
\sign00__0_carry__0_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(5),
I1 => y(5),
I2 => large_mant1_carry_n_0,
O => A(5)
);
\sign00__0_carry__0_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(4),
I1 => y(4),
I2 => large_mant1_carry_n_0,
O => A(4)
);
\sign00__0_carry__0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_29_n_0\,
I1 => \sign00__0_carry_i_51_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_30_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_31_n_0\,
O => \sign00__0_carry__0_i_19_n_0\
);
\sign00__0_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_10_n_0\,
I1 => \sign00__0_carry__0_i_11_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__0_i_2_n_0\
);
\sign00__0_carry__0_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_32_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__0_i_21_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__0_i_20_n_0\
);
\sign00__0_carry__0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_32_n_0\,
I1 => \sign00__0_carry_i_47_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry__0_i_33_n_0\,
I4 => sum4(2),
I5 => \sign00__0_carry__0_i_34_n_0\,
O => \sign00__0_carry__0_i_21_n_0\
);
\sign00__0_carry__0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_35_n_0\,
I1 => \sign00__0_carry_i_45_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry_i_43_n_0\,
I4 => sum4(2),
I5 => \sign00__0_carry_i_44_n_0\,
O => \sign00__0_carry__0_i_22_n_0\
);
\sign00__0_carry__0_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(3),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(4),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_38_n_0\,
O => \sign00__0_carry__0_i_23_n_0\
);
\sign00__0_carry__0_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8FF33CC00"
)
port map (
I0 => \sign00__0_carry__0_i_33_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry__0_i_34_n_0\,
I3 => \sign00__0_carry_i_47_n_0\,
I4 => \sign00__0_carry_i_48_n_0\,
I5 => sum4(1),
O => \sign00__0_carry__0_i_24_n_0\
);
\sign00__0_carry__0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(2),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(3),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_30_n_0\,
O => \sign00__0_carry__0_i_25_n_0\
);
\sign00__0_carry__0_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(1),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(2),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_39_n_0\,
O => \sign00__0_carry__0_i_26_n_0\
);
\sign00__0_carry__0_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000044400400"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry_i_39_n_0\,
I2 => large_mant1_carry_n_0,
I3 => x(0),
I4 => y(0),
I5 => \sign00__0_carry_i_41_n_0\,
O => \sign00__0_carry__0_i_27_n_0\
);
\sign00__0_carry__0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_40_n_0\,
I1 => \sign00__0_carry__0_i_41_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_39_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_38_n_0\,
O => \sign00__0_carry__0_i_28_n_0\
);
\sign00__0_carry__0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(0),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(1),
O => \sign00__0_carry__0_i_29_n_0\
);
\sign00__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_12_n_0\,
I1 => \sign00__0_carry__0_i_13_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__0_i_3_n_0\
);
\sign00__0_carry__0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(4),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(5),
O => \sign00__0_carry__0_i_30_n_0\
);
\sign00__0_carry__0_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(6),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(7),
O => \sign00__0_carry__0_i_31_n_0\
);
\sign00__0_carry__0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(21),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(13),
I4 => y(13),
I5 => sum4(4),
O => \sign00__0_carry__0_i_32_n_0\
);
\sign00__0_carry__0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(19),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(11),
I4 => y(11),
I5 => sum4(4),
O => \sign00__0_carry__0_i_33_n_0\
);
\sign00__0_carry__0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00FFE4FFE400"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(15),
I2 => y(15),
I3 => sum4(3),
I4 => small_mant(7),
I5 => sum4(4),
O => \sign00__0_carry__0_i_34_n_0\
);
\sign00__0_carry__0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(20),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(12),
I4 => y(12),
I5 => sum4(4),
O => \sign00__0_carry__0_i_35_n_0\
);
\sign00__0_carry__0_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(3),
I1 => x(3),
I2 => large_mant1_carry_n_0,
O => small_mant(3)
);
\sign00__0_carry__0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(4),
I1 => x(4),
I2 => large_mant1_carry_n_0,
O => small_mant(4)
);
\sign00__0_carry__0_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(5),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(6),
O => \sign00__0_carry__0_i_38_n_0\
);
\sign00__0_carry__0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(3),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(4),
O => \sign00__0_carry__0_i_39_n_0\
);
\sign00__0_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_14_n_0\,
I1 => \sign00__0_carry__0_i_15_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__0_i_4_n_0\
);
\sign00__0_carry__0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => small_mant(0),
I1 => \sign00__0_carry_i_58_n_0\,
I2 => \sign00__0_carry_i_59_n_0\,
I3 => \sign00__0_carry_i_69_n_0\,
I4 => sum4(0),
O => \sign00__0_carry__0_i_40_n_0\
);
\sign00__0_carry__0_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(1),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(2),
O => \sign00__0_carry__0_i_41_n_0\
);
\sign00__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"A965"
)
port map (
I0 => \sign00__0_carry__0_i_9_n_0\,
I1 => large_mant1_carry_n_0,
I2 => y(7),
I3 => x(7),
O => \sign00__0_carry__0_i_5_n_0\
);
\sign00__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A965"
)
port map (
I0 => \sign00__0_carry__0_i_16_n_0\,
I1 => large_mant1_carry_n_0,
I2 => y(6),
I3 => x(6),
O => \sign00__0_carry__0_i_6_n_0\
);
\sign00__0_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_12_n_0\,
I1 => \sign00__0_carry__0_i_13_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(5),
O => \sign00__0_carry__0_i_7_n_0\
);
\sign00__0_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__0_i_14_n_0\,
I1 => \sign00__0_carry__0_i_15_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(4),
O => \sign00__0_carry__0_i_8_n_0\
);
\sign00__0_carry__0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555655AAAAAAAA"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__0_i_19_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__0_i_20_n_0\,
O => \sign00__0_carry__0_i_9_n_0\
);
\sign00__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__0_n_0\,
CO(3) => \sign00__0_carry__1_n_0\,
CO(2) => \sign00__0_carry__1_n_1\,
CO(1) => \sign00__0_carry__1_n_2\,
CO(0) => \sign00__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__1_i_1_n_0\,
DI(2) => \sign00__0_carry__1_i_2_n_0\,
DI(1) => \sign00__0_carry__1_i_3_n_0\,
DI(0) => \sign00__0_carry__1_i_4_n_0\,
O(3 downto 0) => sel0(10 downto 7),
S(3) => \sign00__0_carry__1_i_5_n_0\,
S(2) => \sign00__0_carry__1_i_6_n_0\,
S(1) => \sign00__0_carry__1_i_7_n_0\,
S(0) => \sign00__0_carry__1_i_8_n_0\
);
\sign00__0_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_9_n_0\,
I1 => \sign00__0_carry__1_i_10_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_1_n_0\
);
\sign00__0_carry__1_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry_i_26_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__1_i_26_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_27_n_0\,
O => \sign00__0_carry__1_i_10_n_0\
);
\sign00__0_carry__1_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_25_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_28_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_11_n_0\
);
\sign00__0_carry__1_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry_i_33_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__0_i_23_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_29_n_0\,
O => \sign00__0_carry__1_i_12_n_0\
);
\sign00__0_carry__1_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_28_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_30_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_13_n_0\
);
\sign00__0_carry__1_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry_i_35_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__0_i_25_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_31_n_0\,
O => \sign00__0_carry__1_i_14_n_0\
);
\sign00__0_carry__1_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_30_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_32_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_15_n_0\
);
\sign00__0_carry__1_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry__0_i_27_n_0\,
I1 => \sign00__0_carry_i_42_n_0\,
I2 => \sign00__0_carry__0_i_26_n_0\,
I3 => \sign00__0_carry_i_38_n_0\,
I4 => \sign00__0_carry__1_i_33_n_0\,
O => \sign00__0_carry__1_i_16_n_0\
);
\sign00__0_carry__1_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => \sign00__0_carry__1_i_27_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry__1_i_26_n_0\,
I3 => \sign00__0_carry_i_42_n_0\,
I4 => \sign00__0_carry_i_26_n_0\,
I5 => \sign00__0_carry_i_17_n_0\,
O => \sign00__0_carry__1_i_17_n_0\
);
\sign00__0_carry__1_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(11),
I1 => y(11),
I2 => large_mant1_carry_n_0,
O => A(11)
);
\sign00__0_carry__1_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => \sign00__0_carry__1_i_29_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry__0_i_23_n_0\,
I3 => \sign00__0_carry_i_42_n_0\,
I4 => \sign00__0_carry_i_33_n_0\,
I5 => \sign00__0_carry_i_17_n_0\,
O => \sign00__0_carry__1_i_19_n_0\
);
\sign00__0_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_11_n_0\,
I1 => \sign00__0_carry__1_i_12_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_2_n_0\
);
\sign00__0_carry__1_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(10),
I1 => y(10),
I2 => large_mant1_carry_n_0,
O => A(10)
);
\sign00__0_carry__1_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033E200E2"
)
port map (
I0 => \sign00__0_carry__1_i_31_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry__0_i_25_n_0\,
I3 => \sign00__0_carry_i_42_n_0\,
I4 => \sign00__0_carry_i_35_n_0\,
I5 => \sign00__0_carry_i_17_n_0\,
O => \sign00__0_carry__1_i_21_n_0\
);
\sign00__0_carry__1_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(9),
I1 => y(9),
I2 => large_mant1_carry_n_0,
O => A(9)
);
\sign00__0_carry__1_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(8),
I1 => y(8),
I2 => large_mant1_carry_n_0,
O => A(8)
);
\sign00__0_carry__1_i_24\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__1_i_34_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__1_i_35_n_0\,
O => \sign00__0_carry__1_i_24_n_0\
);
\sign00__0_carry__1_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B8B8"
)
port map (
I0 => \sign00__0_carry__1_i_36_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry__0_i_33_n_0\,
I3 => \sign00__0_carry__1_i_37_n_0\,
I4 => sum4(1),
O => \sign00__0_carry__1_i_25_n_0\
);
\sign00__0_carry__1_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(4),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(5),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_31_n_0\,
O => \sign00__0_carry__1_i_26_n_0\
);
\sign00__0_carry__1_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(8),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(9),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_41_n_0\,
O => \sign00__0_carry__1_i_27_n_0\
);
\sign00__0_carry__1_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B8B8"
)
port map (
I0 => \sign00__0_carry__1_i_42_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_43_n_0\,
I3 => \sign00__0_carry__1_i_35_n_0\,
I4 => sum4(1),
O => \sign00__0_carry__1_i_28_n_0\
);
\sign00__0_carry__1_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(7),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(8),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_44_n_0\,
O => \sign00__0_carry__1_i_29_n_0\
);
\sign00__0_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_13_n_0\,
I1 => \sign00__0_carry__1_i_14_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_3_n_0\
);
\sign00__0_carry__1_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF33CC00B8B8B8B8"
)
port map (
I0 => \sign00__0_carry__0_i_32_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_47_n_0\,
I3 => \sign00__0_carry__1_i_36_n_0\,
I4 => \sign00__0_carry__0_i_33_n_0\,
I5 => sum4(1),
O => \sign00__0_carry__1_i_30_n_0\
);
\sign00__0_carry__1_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(6),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(7),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_46_n_0\,
O => \sign00__0_carry__1_i_31_n_0\
);
\sign00__0_carry__1_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_42_n_0\,
I1 => \sign00__0_carry_i_43_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry__0_i_35_n_0\,
I4 => sum4(2),
I5 => \sign00__0_carry_i_45_n_0\,
O => \sign00__0_carry__1_i_32_n_0\
);
\sign00__0_carry__1_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(5),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(6),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_47_n_0\,
O => \sign00__0_carry__1_i_33_n_0\
);
\sign00__0_carry__1_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(18),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__1_i_42_n_0\,
O => \sign00__0_carry__1_i_34_n_0\
);
\sign00__0_carry__1_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(16),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__0_i_35_n_0\,
O => \sign00__0_carry__1_i_35_n_0\
);
\sign00__0_carry__1_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FEBA"
)
port map (
I0 => sum4(3),
I1 => large_mant1_carry_n_0,
I2 => x(15),
I3 => y(15),
I4 => sum4(4),
O => \sign00__0_carry__1_i_36_n_0\
);
\sign00__0_carry__1_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(17),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__0_i_32_n_0\,
O => \sign00__0_carry__1_i_37_n_0\
);
\sign00__0_carry__1_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(5),
I1 => x(5),
I2 => large_mant1_carry_n_0,
O => small_mant(5)
);
\sign00__0_carry__1_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(8),
I1 => x(8),
I2 => large_mant1_carry_n_0,
O => small_mant(8)
);
\sign00__0_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_15_n_0\,
I1 => \sign00__0_carry__1_i_16_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__1_i_4_n_0\
);
\sign00__0_carry__1_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(9),
I1 => x(9),
I2 => large_mant1_carry_n_0,
O => small_mant(9)
);
\sign00__0_carry__1_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(10),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(11),
O => \sign00__0_carry__1_i_41_n_0\
);
\sign00__0_carry__1_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(22),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(14),
I4 => y(14),
I5 => sum4(4),
O => \sign00__0_carry__1_i_42_n_0\
);
\sign00__0_carry__1_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(7),
I1 => x(7),
I2 => large_mant1_carry_n_0,
O => small_mant(7)
);
\sign00__0_carry__1_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(9),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(10),
O => \sign00__0_carry__1_i_44_n_0\
);
\sign00__0_carry__1_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(6),
I1 => x(6),
I2 => large_mant1_carry_n_0,
O => small_mant(6)
);
\sign00__0_carry__1_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(8),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(9),
O => \sign00__0_carry__1_i_46_n_0\
);
\sign00__0_carry__1_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(7),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(8),
O => \sign00__0_carry__1_i_47_n_0\
);
\sign00__0_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__1_i_9_n_0\,
I1 => \sign00__0_carry__1_i_17_n_0\,
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(11),
O => \sign00__0_carry__1_i_5_n_0\
);
\sign00__0_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__1_i_11_n_0\,
I1 => \sign00__0_carry__1_i_19_n_0\,
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(10),
O => \sign00__0_carry__1_i_6_n_0\
);
\sign00__0_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__1_i_13_n_0\,
I1 => \sign00__0_carry__1_i_21_n_0\,
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(9),
O => \sign00__0_carry__1_i_7_n_0\
);
\sign00__0_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__1_i_15_n_0\,
I1 => \sign00__0_carry__1_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(8),
O => \sign00__0_carry__1_i_8_n_0\
);
\sign00__0_carry__1_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__1_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_25_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__1_i_9_n_0\
);
\sign00__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__1_n_0\,
CO(3) => \sign00__0_carry__2_n_0\,
CO(2) => \sign00__0_carry__2_n_1\,
CO(1) => \sign00__0_carry__2_n_2\,
CO(0) => \sign00__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__2_i_1_n_0\,
DI(2) => \sign00__0_carry__2_i_2_n_0\,
DI(1) => \sign00__0_carry__2_i_3_n_0\,
DI(0) => \sign00__0_carry__2_i_4_n_0\,
O(3 downto 0) => sel0(14 downto 11),
S(3) => \sign00__0_carry__2_i_5_n_0\,
S(2) => \sign00__0_carry__2_i_6_n_0\,
S(1) => \sign00__0_carry__2_i_7_n_0\,
S(0) => \sign00__0_carry__2_i_8_n_0\
);
\sign00__0_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_9_n_0\,
I1 => \sign00__0_carry__2_i_10_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_1_n_0\
);
\sign00__0_carry__2_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_26_n_0\,
I1 => \sign00__0_carry__1_i_26_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_23_n_0\,
O => \sign00__0_carry__2_i_10_n_0\
);
\sign00__0_carry__2_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_22_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_11_n_0\
);
\sign00__0_carry__2_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_33_n_0\,
I1 => \sign00__0_carry__0_i_23_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_29_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_25_n_0\,
O => \sign00__0_carry__2_i_12_n_0\
);
\sign00__0_carry__2_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_26_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_13_n_0\
);
\sign00__0_carry__2_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_35_n_0\,
I1 => \sign00__0_carry__0_i_25_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_31_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_27_n_0\,
O => \sign00__0_carry__2_i_14_n_0\
);
\sign00__0_carry__2_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_26_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__1_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_15_n_0\
);
\sign00__0_carry__2_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_27_n_0\,
I1 => \sign00__0_carry__0_i_26_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__1_i_33_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__2_i_28_n_0\,
O => \sign00__0_carry__2_i_16_n_0\
);
\sign00__0_carry__2_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(15),
I1 => y(15),
I2 => large_mant1_carry_n_0,
O => A(15)
);
\sign00__0_carry__2_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(14),
I1 => y(14),
I2 => large_mant1_carry_n_0,
O => A(14)
);
\sign00__0_carry__2_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(13),
I1 => y(13),
I2 => large_mant1_carry_n_0,
O => A(13)
);
\sign00__0_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_11_n_0\,
I1 => \sign00__0_carry__2_i_12_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_2_n_0\
);
\sign00__0_carry__2_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(12),
I1 => y(12),
I2 => large_mant1_carry_n_0,
O => A(12)
);
\sign00__0_carry__2_i_21\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_29_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__2_i_30_n_0\,
O => \sign00__0_carry__2_i_21_n_0\
);
\sign00__0_carry__2_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_31_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__2_i_32_n_0\,
O => \sign00__0_carry__2_i_22_n_0\
);
\sign00__0_carry__2_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(12),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(13),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_35_n_0\,
O => \sign00__0_carry__2_i_23_n_0\
);
\sign00__0_carry__2_i_24\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_30_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__1_i_34_n_0\,
O => \sign00__0_carry__2_i_24_n_0\
);
\sign00__0_carry__2_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(11),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(12),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_37_n_0\,
O => \sign00__0_carry__2_i_25_n_0\
);
\sign00__0_carry__2_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \sign00__0_carry__2_i_32_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry__1_i_37_n_0\,
O => \sign00__0_carry__2_i_26_n_0\
);
\sign00__0_carry__2_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(10),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(11),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_39_n_0\,
O => \sign00__0_carry__2_i_27_n_0\
);
\sign00__0_carry__2_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(9),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(10),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_40_n_0\,
O => \sign00__0_carry__2_i_28_n_0\
);
\sign00__0_carry__2_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => small_mant(22),
I1 => sum4(2),
I2 => sum4(4),
I3 => small_mant(18),
I4 => sum4(3),
O => \sign00__0_carry__2_i_29_n_0\
);
\sign00__0_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_13_n_0\,
I1 => \sign00__0_carry__2_i_14_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_3_n_0\
);
\sign00__0_carry__2_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => small_mant(20),
I1 => sum4(2),
I2 => sum4(4),
I3 => small_mant(16),
I4 => sum4(3),
O => \sign00__0_carry__2_i_30_n_0\
);
\sign00__0_carry__2_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => small_mant(21),
I1 => sum4(2),
I2 => sum4(4),
I3 => small_mant(17),
I4 => sum4(3),
O => \sign00__0_carry__2_i_31_n_0\
);
\sign00__0_carry__2_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sum4(4),
I1 => small_mant(19),
I2 => sum4(3),
I3 => sum4(2),
I4 => \sign00__0_carry__1_i_36_n_0\,
O => \sign00__0_carry__2_i_32_n_0\
);
\sign00__0_carry__2_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(12),
I1 => x(12),
I2 => large_mant1_carry_n_0,
O => small_mant(12)
);
\sign00__0_carry__2_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(13),
I1 => x(13),
I2 => large_mant1_carry_n_0,
O => small_mant(13)
);
\sign00__0_carry__2_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(14),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(15),
O => \sign00__0_carry__2_i_35_n_0\
);
\sign00__0_carry__2_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(11),
I1 => x(11),
I2 => large_mant1_carry_n_0,
O => small_mant(11)
);
\sign00__0_carry__2_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(13),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(14),
O => \sign00__0_carry__2_i_37_n_0\
);
\sign00__0_carry__2_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(10),
I1 => x(10),
I2 => large_mant1_carry_n_0,
O => small_mant(10)
);
\sign00__0_carry__2_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(12),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(13),
O => \sign00__0_carry__2_i_39_n_0\
);
\sign00__0_carry__2_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_15_n_0\,
I1 => \sign00__0_carry__2_i_16_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__2_i_4_n_0\
);
\sign00__0_carry__2_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(11),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(12),
O => \sign00__0_carry__2_i_40_n_0\
);
\sign00__0_carry__2_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(14),
I1 => x(14),
I2 => large_mant1_carry_n_0,
O => small_mant(14)
);
\sign00__0_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_9_n_0\,
I1 => \sign00__0_carry__2_i_10_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(15),
O => \sign00__0_carry__2_i_5_n_0\
);
\sign00__0_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_11_n_0\,
I1 => \sign00__0_carry__2_i_12_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(14),
O => \sign00__0_carry__2_i_6_n_0\
);
\sign00__0_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_13_n_0\,
I1 => \sign00__0_carry__2_i_14_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(13),
O => \sign00__0_carry__2_i_7_n_0\
);
\sign00__0_carry__2_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry__2_i_15_n_0\,
I1 => \sign00__0_carry__2_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(12),
O => \sign00__0_carry__2_i_8_n_0\
);
\sign00__0_carry__2_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__2_i_21_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_22_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__2_i_9_n_0\
);
\sign00__0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__2_n_0\,
CO(3) => \sign00__0_carry__3_n_0\,
CO(2) => \sign00__0_carry__3_n_1\,
CO(1) => \sign00__0_carry__3_n_2\,
CO(0) => \sign00__0_carry__3_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__3_i_1_n_0\,
DI(2) => \sign00__0_carry__3_i_2_n_0\,
DI(1) => \sign00__0_carry__3_i_3_n_0\,
DI(0) => \sign00__0_carry__3_i_4_n_0\,
O(3 downto 0) => sel0(18 downto 15),
S(3) => \sign00__0_carry__3_i_5_n_0\,
S(2) => \sign00__0_carry__3_i_6_n_0\,
S(1) => \sign00__0_carry__3_i_7_n_0\,
S(0) => \sign00__0_carry__3_i_8_n_0\
);
\sign00__0_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_9_n_0\,
I1 => \sign00__0_carry_i_11_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_10_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_1_n_0\
);
\sign00__0_carry__3_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_26_n_0\,
I1 => \sign00__0_carry__1_i_27_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_23_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_25_n_0\,
O => \sign00__0_carry__3_i_10_n_0\
);
\sign00__0_carry__3_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_26_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_11_n_0\
);
\sign00__0_carry__3_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_23_n_0\,
I1 => \sign00__0_carry__1_i_29_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_25_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_27_n_0\,
O => \sign00__0_carry__3_i_12_n_0\
);
\sign00__0_carry__3_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_26_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_28_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_13_n_0\
);
\sign00__0_carry__3_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_25_n_0\,
I1 => \sign00__0_carry__1_i_31_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_29_n_0\,
O => \sign00__0_carry__3_i_14_n_0\
);
\sign00__0_carry__3_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_28_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__2_i_21_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_15_n_0\
);
\sign00__0_carry__3_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_26_n_0\,
I1 => \sign00__0_carry__1_i_33_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__2_i_28_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__3_i_30_n_0\,
O => \sign00__0_carry__3_i_16_n_0\
);
\sign00__0_carry__3_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => \sign00__0_carry_i_38_n_0\,
I1 => \sign00__0_carry_i_26_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_31_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__3_i_32_n_0\,
O => sum2(19)
);
\sign00__0_carry__3_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(19),
I1 => y(19),
I2 => large_mant1_carry_n_0,
O => A(19)
);
\sign00__0_carry__3_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => \sign00__0_carry_i_38_n_0\,
I1 => \sign00__0_carry_i_33_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_33_n_0\,
I4 => \sign00__0_carry_i_42_n_0\,
I5 => \sign00__0_carry__3_i_34_n_0\,
O => sum2(18)
);
\sign00__0_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_11_n_0\,
I1 => \sign00__0_carry_i_14_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_12_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_2_n_0\
);
\sign00__0_carry__3_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(18),
I1 => y(18),
I2 => large_mant1_carry_n_0,
O => A(18)
);
\sign00__0_carry__3_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__3_i_35_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_36_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__3_i_37_n_0\,
O => \sign00__0_carry__3_i_21_n_0\
);
\sign00__0_carry__3_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__3_i_38_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_39_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__3_i_40_n_0\,
O => \sign00__0_carry__3_i_22_n_0\
);
\sign00__0_carry__3_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000B08"
)
port map (
I0 => small_mant(22),
I1 => sum4(1),
I2 => sum4(3),
I3 => small_mant(20),
I4 => sum4(4),
I5 => sum4(2),
O => \sign00__0_carry__3_i_23_n_0\
);
\sign00__0_carry__3_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000003B0038"
)
port map (
I0 => small_mant(21),
I1 => sum4(1),
I2 => sum4(2),
I3 => sum4(4),
I4 => small_mant(19),
I5 => sum4(3),
O => \sign00__0_carry__3_i_24_n_0\
);
\sign00__0_carry__3_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(16),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(17),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_47_n_0\,
O => \sign00__0_carry__3_i_25_n_0\
);
\sign00__0_carry__3_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => sum4(3),
I1 => small_mant(20),
I2 => sum4(4),
I3 => sum4(2),
I4 => sum4(1),
I5 => \sign00__0_carry__2_i_29_n_0\,
O => \sign00__0_carry__3_i_26_n_0\
);
\sign00__0_carry__3_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC5C0C0CAC0C0C0"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__3_i_48_n_0\,
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(17),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(18),
O => \sign00__0_carry__3_i_27_n_0\
);
\sign00__0_carry__3_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0032FFFF00320000"
)
port map (
I0 => sum4(2),
I1 => sum4(4),
I2 => small_mant(19),
I3 => sum4(3),
I4 => sum4(1),
I5 => \sign00__0_carry__2_i_31_n_0\,
O => \sign00__0_carry__3_i_28_n_0\
);
\sign00__0_carry__3_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC5C0C0CAC0C0C0"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__2_i_35_n_0\,
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(16),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(17),
O => \sign00__0_carry__3_i_29_n_0\
);
\sign00__0_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_13_n_0\,
I1 => \sign00__0_carry_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_14_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_3_n_0\
);
\sign00__0_carry__3_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC5C0C0CAC0C0C0"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__2_i_37_n_0\,
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(15),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(16),
O => \sign00__0_carry__3_i_30_n_0\
);
\sign00__0_carry__3_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_30_n_0\,
I1 => \sign00__0_carry__0_i_31_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_46_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_41_n_0\,
O => \sign00__0_carry__3_i_31_n_0\
);
\sign00__0_carry__3_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_39_n_0\,
I1 => \sign00__0_carry__2_i_35_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_51_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_47_n_0\,
O => \sign00__0_carry__3_i_32_n_0\
);
\sign00__0_carry__3_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_39_n_0\,
I1 => \sign00__0_carry__0_i_38_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_47_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_44_n_0\,
O => \sign00__0_carry__3_i_33_n_0\
);
\sign00__0_carry__3_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_40_n_0\,
I1 => \sign00__0_carry__2_i_37_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_48_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_52_n_0\,
O => \sign00__0_carry__3_i_34_n_0\
);
\sign00__0_carry__3_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_41_n_0\,
I1 => \sign00__0_carry__2_i_39_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__2_i_35_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_51_n_0\,
O => \sign00__0_carry__3_i_35_n_0\
);
\sign00__0_carry__3_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry_i_51_n_0\,
I1 => \sign00__0_carry__0_i_30_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_31_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_46_n_0\,
O => \sign00__0_carry__3_i_36_n_0\
);
\sign00__0_carry__3_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000031002000"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry_i_41_n_0\,
I2 => small_mant(0),
I3 => \sign00__0_carry_i_39_n_0\,
I4 => small_mant(1),
I5 => \sign00__0_carry_i_38_n_0\,
O => \sign00__0_carry__3_i_37_n_0\
);
\sign00__0_carry__3_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_44_n_0\,
I1 => \sign00__0_carry__2_i_40_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__2_i_37_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__3_i_48_n_0\,
O => \sign00__0_carry__3_i_38_n_0\
);
\sign00__0_carry__3_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_41_n_0\,
I1 => \sign00__0_carry__0_i_39_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_38_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__1_i_47_n_0\,
O => \sign00__0_carry__3_i_39_n_0\
);
\sign00__0_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__3_i_15_n_0\,
I1 => \sign00__0_carry_i_22_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__3_i_16_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__3_i_4_n_0\
);
\sign00__0_carry__3_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => \sign00__0_carry_i_41_n_0\,
I1 => small_mant(0),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => sum4(0),
I4 => \sign00__0_carry_i_38_n_0\,
O => \sign00__0_carry__3_i_40_n_0\
);
\sign00__0_carry__3_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => large_mant1_carry_n_0,
O => small_mant(22)
);
\sign00__0_carry__3_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => large_mant1_carry_n_0,
O => small_mant(20)
);
\sign00__0_carry__3_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(21),
I1 => x(21),
I2 => large_mant1_carry_n_0,
O => small_mant(21)
);
\sign00__0_carry__3_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(19),
I1 => x(19),
I2 => large_mant1_carry_n_0,
O => small_mant(19)
);
\sign00__0_carry__3_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => large_mant1_carry_n_0,
O => small_mant(16)
);
\sign00__0_carry__3_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(17),
I1 => x(17),
I2 => large_mant1_carry_n_0,
O => small_mant(17)
);
\sign00__0_carry__3_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(18),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(19),
O => \sign00__0_carry__3_i_47_n_0\
);
\sign00__0_carry__3_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(15),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(16),
O => \sign00__0_carry__3_i_48_n_0\
);
\sign00__0_carry__3_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => large_mant1_carry_n_0,
O => small_mant(18)
);
\sign00__0_carry__3_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__3_i_9_n_0\,
I1 => sum2(19),
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(19),
O => \sign00__0_carry__3_i_5_n_0\
);
\sign00__0_carry__3_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(15),
I1 => x(15),
I2 => large_mant1_carry_n_0,
O => small_mant(15)
);
\sign00__0_carry__3_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(16),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(17),
O => \sign00__0_carry__3_i_51_n_0\
);
\sign00__0_carry__3_i_52\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(17),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(18),
O => \sign00__0_carry__3_i_52_n_0\
);
\sign00__0_carry__3_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A25D5DA25DA2A25D"
)
port map (
I0 => \sign00__0_carry__3_i_11_n_0\,
I1 => sum2(18),
I2 => sum3,
I3 => x(31),
I4 => y(31),
I5 => A(18),
O => \sign00__0_carry__3_i_6_n_0\
);
\sign00__0_carry__3_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__3_i_13_n_0\,
I1 => \sign00__0_carry__3_i_21_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(17),
I5 => x(17),
O => \sign00__0_carry__3_i_7_n_0\
);
\sign00__0_carry__3_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__3_i_15_n_0\,
I1 => \sign00__0_carry__3_i_22_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(16),
I5 => x(16),
O => \sign00__0_carry__3_i_8_n_0\
);
\sign00__0_carry__3_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__3_i_23_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__3_i_9_n_0\
);
\sign00__0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__3_n_0\,
CO(3) => \sign00__0_carry__4_n_0\,
CO(2) => \sign00__0_carry__4_n_1\,
CO(1) => \sign00__0_carry__4_n_2\,
CO(0) => \sign00__0_carry__4_n_3\,
CYINIT => '0',
DI(3) => \sign00__0_carry__4_i_1_n_0\,
DI(2) => \sign00__0_carry__4_i_2_n_0\,
DI(1) => \sign00__0_carry__4_i_3_n_0\,
DI(0) => \sign00__0_carry__4_i_4_n_0\,
O(3 downto 0) => sel0(22 downto 19),
S(3) => \sign00__0_carry__4_i_5_n_0\,
S(2) => \sign00__0_carry__4_i_6_n_0\,
S(1) => \sign00__0_carry__4_i_7_n_0\,
S(0) => \sign00__0_carry__4_i_8_n_0\
);
\sign00__0_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555303FAAAACFC0"
)
port map (
I0 => \sign00__0_carry__4_i_9_n_0\,
I1 => \sign00__0_carry__4_i_10_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_11_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_1_n_0\
);
\sign00__0_carry__4_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEBA028A"
)
port map (
I0 => \sign00__0_carry__1_i_26_n_0\,
I1 => sum3,
I2 => \sign00__0_carry_i_12_n_6\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_26_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry__4_i_10_n_0\
);
\sign00__0_carry__4_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_27_n_0\,
I1 => \sign00__0_carry__2_i_23_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_25_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_21_n_0\,
O => \sign00__0_carry__4_i_11_n_0\
);
\sign00__0_carry__4_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"7747FFFFFFFFFFFF"
)
port map (
I0 => \sign00__0_carry__4_i_22_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__4_i_23_n_0\,
I3 => sum4(1),
I4 => \sign00__0_carry_i_25_n_0\,
I5 => sum3,
O => \sign00__0_carry__4_i_12_n_0\
);
\sign00__0_carry__4_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_29_n_0\,
I1 => \sign00__0_carry__2_i_25_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_24_n_0\,
O => \sign00__0_carry__4_i_13_n_0\
);
\sign00__0_carry__4_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0DFFFFFFFFFFFFF"
)
port map (
I0 => \sign00__0_carry__4_i_23_n_0\,
I1 => sum4(1),
I2 => sum4(0),
I3 => \sign00__0_carry__4_i_25_n_0\,
I4 => \sign00__0_carry_i_25_n_0\,
I5 => sum3,
O => \sign00__0_carry__4_i_14_n_0\
);
\sign00__0_carry__4_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_31_n_0\,
I1 => \sign00__0_carry__2_i_27_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_29_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_26_n_0\,
O => \sign00__0_carry__4_i_15_n_0\
);
\sign00__0_carry__4_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry__4_i_25_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry__3_i_23_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry__4_i_16_n_0\
);
\sign00__0_carry__4_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_33_n_0\,
I1 => \sign00__0_carry__2_i_28_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__3_i_30_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__4_i_27_n_0\,
O => \sign00__0_carry__4_i_17_n_0\
);
\sign00__0_carry__4_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__4_i_28_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_29_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__0_i_28_n_0\,
O => \sign00__0_carry__4_i_18_n_0\
);
\sign00__0_carry__4_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__4_i_30_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_31_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__4_i_32_n_0\,
O => \sign00__0_carry__4_i_19_n_0\
);
\sign00__0_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__4_i_12_n_0\,
I1 => \sign00__0_carry__0_i_11_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_13_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_2_n_0\
);
\sign00__0_carry__4_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => sum3,
I1 => \sign00__0_carry__4_i_33_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_34_n_0\,
I4 => \sign00__0_carry_i_17_n_0\,
I5 => \sign00__0_carry__4_i_35_n_0\,
O => \sign00__0_carry__4_i_20_n_0\
);
\sign00__0_carry__4_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"D8FFD85500000000"
)
port map (
I0 => sum4(0),
I1 => small_mant(20),
I2 => small_mant(21),
I3 => \sign00__0_carry_i_41_n_0\,
I4 => small_mant(22),
I5 => \sign00__0_carry_i_39_n_0\,
O => \sign00__0_carry__4_i_21_n_0\
);
\sign00__0_carry__4_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sum4(2),
I1 => sum4(4),
I2 => sum4(3),
I3 => sum4(1),
O => \sign00__0_carry__4_i_22_n_0\
);
\sign00__0_carry__4_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000005410"
)
port map (
I0 => sum4(3),
I1 => large_mant1_carry_n_0,
I2 => x(22),
I3 => y(22),
I4 => sum4(4),
I5 => sum4(2),
O => \sign00__0_carry__4_i_23_n_0\
);
\sign00__0_carry__4_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(19),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(20),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_36_n_0\,
O => \sign00__0_carry__4_i_24_n_0\
);
\sign00__0_carry__4_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000032"
)
port map (
I0 => sum4(1),
I1 => sum4(3),
I2 => small_mant(21),
I3 => sum4(4),
I4 => sum4(2),
O => \sign00__0_carry__4_i_25_n_0\
);
\sign00__0_carry__4_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(18),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(19),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_37_n_0\,
O => \sign00__0_carry__4_i_26_n_0\
);
\sign00__0_carry__4_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(17),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(18),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_38_n_0\,
O => \sign00__0_carry__4_i_27_n_0\
);
\sign00__0_carry__4_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__3_i_48_n_0\,
I1 => \sign00__0_carry__3_i_52_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__4_i_38_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_36_n_0\,
O => \sign00__0_carry__4_i_28_n_0\
);
\sign00__0_carry__4_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__1_i_47_n_0\,
I1 => \sign00__0_carry__1_i_44_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__2_i_40_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_37_n_0\,
O => \sign00__0_carry__4_i_29_n_0\
);
\sign00__0_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__4_i_14_n_0\,
I1 => \sign00__0_carry__0_i_13_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_15_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_3_n_0\
);
\sign00__0_carry__4_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_35_n_0\,
I1 => \sign00__0_carry__3_i_51_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_47_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_37_n_0\,
O => \sign00__0_carry__4_i_30_n_0\
);
\sign00__0_carry__4_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_31_n_0\,
I1 => \sign00__0_carry__1_i_46_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_41_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_39_n_0\,
O => \sign00__0_carry__4_i_31_n_0\
);
\sign00__0_carry__4_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \sign00__0_carry__0_i_29_n_0\,
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry_i_51_n_0\,
I3 => \sign00__0_carry_i_41_n_0\,
I4 => \sign00__0_carry__0_i_30_n_0\,
O => \sign00__0_carry__4_i_32_n_0\
);
\sign00__0_carry__4_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_37_n_0\,
I1 => \sign00__0_carry__3_i_48_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__3_i_52_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__4_i_38_n_0\,
O => \sign00__0_carry__4_i_33_n_0\
);
\sign00__0_carry__4_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__0_i_38_n_0\,
I1 => \sign00__0_carry__1_i_47_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__1_i_44_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__2_i_40_n_0\,
O => \sign00__0_carry__4_i_34_n_0\
);
\sign00__0_carry__4_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry__4_i_39_n_0\,
I2 => \sign00__0_carry_i_38_n_0\,
I3 => \sign00__0_carry__0_i_41_n_0\,
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry__0_i_39_n_0\,
O => \sign00__0_carry__4_i_35_n_0\
);
\sign00__0_carry__4_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(21),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(22),
O => \sign00__0_carry__4_i_36_n_0\
);
\sign00__0_carry__4_i_37\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(20),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(21),
O => \sign00__0_carry__4_i_37_n_0\
);
\sign00__0_carry__4_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(19),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(20),
O => \sign00__0_carry__4_i_38_n_0\
);
\sign00__0_carry__4_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101010000010000"
)
port map (
I0 => \sign00__0_carry_i_69_n_0\,
I1 => \sign00__0_carry_i_59_n_0\,
I2 => \sign00__0_carry_i_58_n_0\,
I3 => large_mant1_carry_n_0,
I4 => x(0),
I5 => y(0),
O => \sign00__0_carry__4_i_39_n_0\
);
\sign00__0_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA202A5555DFD5"
)
port map (
I0 => \sign00__0_carry__4_i_16_n_0\,
I1 => \sign00__0_carry__0_i_15_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => \sign00__0_carry__4_i_17_n_0\,
I4 => sum3,
I5 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry__4_i_4_n_0\
);
\sign00__0_carry__4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA999A966655565"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry__4_i_11_n_0\,
I3 => \sign00__0_carry_i_17_n_0\,
I4 => \sign00__0_carry__4_i_10_n_0\,
I5 => \sign00__0_carry__4_i_9_n_0\,
O => \sign00__0_carry__4_i_5_n_0\
);
\sign00__0_carry__4_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__4_i_12_n_0\,
I1 => \sign00__0_carry__4_i_18_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(22),
I5 => x(22),
O => \sign00__0_carry__4_i_6_n_0\
);
\sign00__0_carry__4_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__4_i_14_n_0\,
I1 => \sign00__0_carry__4_i_19_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(21),
I5 => x(21),
O => \sign00__0_carry__4_i_7_n_0\
);
\sign00__0_carry__4_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878788787788787"
)
port map (
I0 => \sign00__0_carry__4_i_16_n_0\,
I1 => \sign00__0_carry__4_i_20_n_0\,
I2 => \sign00__0_carry_i_5_n_0\,
I3 => large_mant1_carry_n_0,
I4 => y(20),
I5 => x(20),
O => \sign00__0_carry__4_i_8_n_0\
);
\sign00__0_carry__4_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \sign00__0_carry_i_25_n_0\,
I1 => sum4(0),
I2 => sum4(2),
I3 => sum4(4),
I4 => sum4(3),
I5 => sum4(1),
O => \sign00__0_carry__4_i_9_n_0\
);
\sign00__0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry__4_n_0\,
CO(3 downto 0) => \NLW_sign00__0_carry__5_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_sign00__0_carry__5_O_UNCONNECTED\(3 downto 1),
O(0) => sel0(23),
S(3 downto 1) => B"000",
S(0) => \sign00__0_carry__5_i_1_n_0\
);
\sign00__0_carry__5_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9A999AAA"
)
port map (
I0 => \sign00__0_carry_i_5_n_0\,
I1 => sum3,
I2 => \sign00__0_carry__1_i_16_n_0\,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry__5_i_2_n_0\,
O => \sign00__0_carry__5_i_1_n_0\
);
\sign00__0_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \sign00__0_carry__2_i_28_n_0\,
I1 => \sign00__0_carry__3_i_30_n_0\,
I2 => \sign00__0_carry_i_42_n_0\,
I3 => \sign00__0_carry__4_i_27_n_0\,
I4 => \sign00__0_carry_i_38_n_0\,
I5 => \sign00__0_carry__5_i_3_n_0\,
O => \sign00__0_carry__5_i_2_n_0\
);
\sign00__0_carry__5_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFC00000"
)
port map (
I0 => small_mant(21),
I1 => small_mant(22),
I2 => \sign00__0_carry_i_41_n_0\,
I3 => sum4(0),
I4 => \sign00__0_carry_i_39_n_0\,
O => \sign00__0_carry__5_i_3_n_0\
);
\sign00__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(0),
I1 => y(0),
I2 => large_mant1_carry_n_0,
O => A(0)
);
\sign00__0_carry_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry_i_23_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_24_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry_i_10_n_0\
);
\sign00__0_carry_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_100_n_0\
);
\sign00__0_carry_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_101_n_0\
);
\sign00__0_carry_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_102_n_0\
);
\sign00__0_carry_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_103_n_0\
);
\sign00__0_carry_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_104_n_0\
);
\sign00__0_carry_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_105_n_0\
);
\sign00__0_carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050005030"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => \sign00__0_carry_i_26_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_12_n_5\,
I5 => sum4(3),
O => \sign00__0_carry_i_11_n_0\
);
\sign00__0_carry_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \sign00__0_carry_i_12_n_0\,
CO(2) => \sign00__0_carry_i_12_n_1\,
CO(1) => \sign00__0_carry_i_12_n_2\,
CO(0) => \sign00__0_carry_i_12_n_3\,
CYINIT => p_0_in(0),
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_12_n_4\,
O(2) => \sign00__0_carry_i_12_n_5\,
O(1) => \sign00__0_carry_i_12_n_6\,
O(0) => \sign00__0_carry_i_12_n_7\,
S(3 downto 0) => p_0_in(4 downto 1)
);
\sign00__0_carry_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry_i_24_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_32_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry_i_13_n_0\
);
\sign00__0_carry_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050005030"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => \sign00__0_carry_i_33_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_12_n_5\,
I5 => sum4(3),
O => \sign00__0_carry_i_14_n_0\
);
\sign00__0_carry_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \sign00__0_carry_i_32_n_0\,
I1 => sum4(0),
I2 => \sign00__0_carry_i_34_n_0\,
I3 => \sign00__0_carry_i_25_n_0\,
I4 => sum3,
O => \sign00__0_carry_i_15_n_0\
);
\sign00__0_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000003050005030"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => \sign00__0_carry_i_35_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_12_n_5\,
I5 => sum4(3),
O => \sign00__0_carry_i_16_n_0\
);
\sign00__0_carry_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(4),
I1 => \sign00__0_carry_i_12_n_4\,
I2 => sum3,
O => \sign00__0_carry_i_17_n_0\
);
\sign00__0_carry_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(3),
I1 => y(3),
I2 => large_mant1_carry_n_0,
O => A(3)
);
\sign00__0_carry_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(2),
I1 => y(2),
I2 => large_mant1_carry_n_0,
O => A(2)
);
\sign00__0_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_10_n_0\,
I1 => \sign00__0_carry_i_11_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry_i_2_n_0\
);
\sign00__0_carry_i_20\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(1),
I1 => y(1),
I2 => large_mant1_carry_n_0,
O => A(1)
);
\sign00__0_carry_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \sign00__0_carry_i_25_n_0\,
I1 => \sign00__0_carry_i_36_n_0\,
I2 => sum4(1),
I3 => \sign00__0_carry_i_37_n_0\,
I4 => sum4(0),
I5 => \sign00__0_carry_i_34_n_0\,
O => \sign00__0_carry_i_21_n_0\
);
\sign00__0_carry_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => sum4(0),
I1 => \sign00__0_carry_i_38_n_0\,
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(0),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry_i_42_n_0\,
O => \sign00__0_carry_i_22_n_0\
);
\sign00__0_carry_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8FF33CC00"
)
port map (
I0 => \sign00__0_carry_i_43_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_44_n_0\,
I3 => \sign00__0_carry_i_45_n_0\,
I4 => \sign00__0_carry_i_46_n_0\,
I5 => sum4(1),
O => \sign00__0_carry_i_23_n_0\
);
\sign00__0_carry_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \sign00__0_carry_i_47_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_48_n_0\,
I3 => sum4(1),
I4 => \sign00__0_carry_i_49_n_0\,
O => \sign00__0_carry_i_24_n_0\
);
\sign00__0_carry_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
I1 => sum4(6),
I2 => sum4(5),
I3 => sum4(7),
O => \sign00__0_carry_i_25_n_0\
);
\sign00__0_carry_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"D080FFFFD0800000"
)
port map (
I0 => sum4(0),
I1 => small_mant(0),
I2 => \sign00__0_carry_i_39_n_0\,
I3 => small_mant(1),
I4 => \sign00__0_carry_i_41_n_0\,
I5 => \sign00__0_carry_i_51_n_0\,
O => \sign00__0_carry_i_26_n_0\
);
\sign00__0_carry_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(0),
O => p_0_in(0)
);
\sign00__0_carry_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(4),
O => p_0_in(4)
);
\sign00__0_carry_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(3),
O => p_0_in(3)
);
\sign00__0_carry_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_13_n_0\,
I1 => \sign00__0_carry_i_14_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry_i_3_n_0\
);
\sign00__0_carry_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(2),
O => p_0_in(2)
);
\sign00__0_carry_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(1),
O => p_0_in(1)
);
\sign00__0_carry_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \sign00__0_carry_i_45_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_46_n_0\,
I3 => sum4(1),
I4 => \sign00__0_carry_i_37_n_0\,
O => \sign00__0_carry_i_32_n_0\
);
\sign00__0_carry_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F4500004A400000"
)
port map (
I0 => sum4(0),
I1 => small_mant(0),
I2 => \sign00__0_carry_i_41_n_0\,
I3 => small_mant(1),
I4 => \sign00__0_carry_i_39_n_0\,
I5 => small_mant(2),
O => \sign00__0_carry_i_33_n_0\
);
\sign00__0_carry_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry_i_49_n_0\,
I1 => sum4(1),
I2 => \sign00__0_carry_i_48_n_0\,
I3 => sum4(2),
I4 => \sign00__0_carry_i_53_n_0\,
O => \sign00__0_carry_i_34_n_0\
);
\sign00__0_carry_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C808"
)
port map (
I0 => small_mant(1),
I1 => \sign00__0_carry_i_39_n_0\,
I2 => sum4(0),
I3 => small_mant(0),
I4 => \sign00__0_carry_i_41_n_0\,
O => \sign00__0_carry_i_35_n_0\
);
\sign00__0_carry_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry_i_46_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_54_n_0\,
I3 => sum4(3),
I4 => \sign00__0_carry_i_55_n_0\,
O => \sign00__0_carry_i_36_n_0\
);
\sign00__0_carry_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry_i_44_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_56_n_0\,
I3 => sum4(3),
I4 => \sign00__0_carry_i_57_n_0\,
O => \sign00__0_carry_i_37_n_0\
);
\sign00__0_carry_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(2),
I1 => \sign00__0_carry_i_12_n_6\,
I2 => sum3,
O => \sign00__0_carry_i_38_n_0\
);
\sign00__0_carry_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \sign00__0_carry_i_58_n_0\,
I1 => \sign00__0_carry_i_59_n_0\,
I2 => \sign00__0_carry_i_60_n_0\,
I3 => \sign00__0_carry_i_61_n_0\,
I4 => \sign00__0_carry_i_62_n_0\,
I5 => \sign00__0_carry_i_63_n_0\,
O => \sign00__0_carry_i_39_n_0\
);
\sign00__0_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_15_n_0\,
I1 => \sign00__0_carry_i_16_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
I4 => \sign00__0_carry_i_5_n_0\,
O => \sign00__0_carry_i_4_n_0\
);
\sign00__0_carry_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(0),
I1 => x(0),
I2 => large_mant1_carry_n_0,
O => small_mant(0)
);
\sign00__0_carry_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(1),
I1 => \sign00__0_carry_i_12_n_7\,
I2 => sum3,
O => \sign00__0_carry_i_41_n_0\
);
\sign00__0_carry_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => sum4(3),
I1 => \sign00__0_carry_i_12_n_5\,
I2 => sum3,
O => \sign00__0_carry_i_42_n_0\
);
\sign00__0_carry_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(18),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(10),
I4 => y(10),
I5 => sum4(4),
O => \sign00__0_carry_i_43_n_0\
);
\sign00__0_carry_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(14),
I2 => y(14),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_64_n_0\,
O => \sign00__0_carry_i_44_n_0\
);
\sign00__0_carry_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(16),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(8),
I4 => y(8),
I5 => sum4(4),
O => \sign00__0_carry_i_45_n_0\
);
\sign00__0_carry_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(12),
I2 => y(12),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_65_n_0\,
O => \sign00__0_carry_i_46_n_0\
);
\sign00__0_carry_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBB88B88"
)
port map (
I0 => small_mant(17),
I1 => sum4(3),
I2 => large_mant1_carry_n_0,
I3 => x(9),
I4 => y(9),
I5 => sum4(4),
O => \sign00__0_carry_i_47_n_0\
);
\sign00__0_carry_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(13),
I2 => y(13),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_66_n_0\,
O => \sign00__0_carry_i_48_n_0\
);
\sign00__0_carry_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \sign00__0_carry__0_i_34_n_0\,
I1 => sum4(2),
I2 => \sign00__0_carry_i_67_n_0\,
I3 => sum4(3),
I4 => \sign00__0_carry_i_68_n_0\,
O => \sign00__0_carry_i_49_n_0\
);
\sign00__0_carry_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => x(31),
I1 => y(31),
O => \sign00__0_carry_i_5_n_0\
);
\sign00__0_carry_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(1),
I1 => x(1),
I2 => large_mant1_carry_n_0,
O => small_mant(1)
);
\sign00__0_carry_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D00000008"
)
port map (
I0 => sum4(0),
I1 => small_mant(2),
I2 => \sign00__0_carry_i_69_n_0\,
I3 => \sign00__0_carry_i_59_n_0\,
I4 => \sign00__0_carry_i_58_n_0\,
I5 => small_mant(3),
O => \sign00__0_carry_i_51_n_0\
);
\sign00__0_carry_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y(2),
I1 => x(2),
I2 => large_mant1_carry_n_0,
O => small_mant(2)
);
\sign00__0_carry_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E4FFFF00E40000"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(9),
I2 => y(9),
I3 => sum4(4),
I4 => sum4(3),
I5 => \sign00__0_carry_i_70_n_0\,
O => \sign00__0_carry_i_53_n_0\
);
\sign00__0_carry_i_54\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(8),
I2 => y(8),
I3 => sum4(4),
O => \sign00__0_carry_i_54_n_0\
);
\sign00__0_carry_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(16),
I1 => x(16),
I2 => sum4(4),
I3 => y(0),
I4 => x(0),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_55_n_0\
);
\sign00__0_carry_i_56\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(10),
I2 => y(10),
I3 => sum4(4),
O => \sign00__0_carry_i_56_n_0\
);
\sign00__0_carry_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(18),
I1 => x(18),
I2 => sum4(4),
I3 => y(2),
I4 => x(2),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_57_n_0\
);
\sign00__0_carry_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF32FE"
)
port map (
I0 => \sign00__0_carry_i_71_n_7\,
I1 => sum3,
I2 => \sign00__0_carry_i_71_n_6\,
I3 => \sum3_carry__0_i_9_n_3\,
I4 => \sign00__0_carry_i_72_n_0\,
I5 => \sign00__0_carry_i_73_n_0\,
O => \sign00__0_carry_i_58_n_0\
);
\sign00__0_carry_i_59\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACFCA"
)
port map (
I0 => \sign00__0_carry_i_74_n_7\,
I1 => sum4(5),
I2 => sum3,
I3 => \sign00__0_carry_i_74_n_6\,
I4 => sum4(6),
O => \sign00__0_carry_i_59_n_0\
);
\sign00__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_10_n_0\,
I1 => \sign00__0_carry_i_11_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(3),
O => \sign00__0_carry_i_6_n_0\
);
\sign00__0_carry_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_75_n_4\,
I1 => \sign00__0_carry_i_75_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_76_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_76_n_7\,
O => \sign00__0_carry_i_60_n_0\
);
\sign00__0_carry_i_61\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_76_n_4\,
I1 => \sign00__0_carry_i_76_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_77_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_77_n_7\,
O => \sign00__0_carry_i_61_n_0\
);
\sign00__0_carry_i_62\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_78_n_4\,
I1 => \sign00__0_carry_i_78_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_79_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_79_n_7\,
O => \sign00__0_carry_i_62_n_0\
);
\sign00__0_carry_i_63\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_79_n_4\,
I1 => \sign00__0_carry_i_79_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_75_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_75_n_7\,
O => \sign00__0_carry_i_63_n_0\
);
\sign00__0_carry_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(22),
I1 => x(22),
I2 => sum4(4),
I3 => y(6),
I4 => x(6),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_64_n_0\
);
\sign00__0_carry_i_65\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(20),
I1 => x(20),
I2 => sum4(4),
I3 => y(4),
I4 => x(4),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_65_n_0\
);
\sign00__0_carry_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(21),
I1 => x(21),
I2 => sum4(4),
I3 => y(5),
I4 => x(5),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_66_n_0\
);
\sign00__0_carry_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => x(11),
I2 => y(11),
I3 => sum4(4),
O => \sign00__0_carry_i_67_n_0\
);
\sign00__0_carry_i_68\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(19),
I1 => x(19),
I2 => sum4(4),
I3 => y(3),
I4 => x(3),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_68_n_0\
);
\sign00__0_carry_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \sign00__0_carry_i_63_n_0\,
I1 => \sign00__0_carry_i_62_n_0\,
I2 => \sign00__0_carry_i_61_n_0\,
I3 => \sign00__0_carry_i_60_n_0\,
O => \sign00__0_carry_i_69_n_0\
);
\sign00__0_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_13_n_0\,
I1 => \sign00__0_carry_i_14_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(2),
O => \sign00__0_carry_i_7_n_0\
);
\sign00__0_carry_i_70\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0AFA0CFCFC0C0"
)
port map (
I0 => y(17),
I1 => x(17),
I2 => sum4(4),
I3 => y(1),
I4 => x(1),
I5 => large_mant1_carry_n_0,
O => \sign00__0_carry_i_70_n_0\
);
\sign00__0_carry_i_71\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_74_n_0\,
CO(3) => \sign00__0_carry_i_71_n_0\,
CO(2) => \sign00__0_carry_i_71_n_1\,
CO(1) => \sign00__0_carry_i_71_n_2\,
CO(0) => \sign00__0_carry_i_71_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_71_n_4\,
O(2) => \sign00__0_carry_i_71_n_5\,
O(1) => \sign00__0_carry_i_71_n_6\,
O(0) => \sign00__0_carry_i_71_n_7\,
S(3) => \sign00__0_carry_i_80_n_0\,
S(2) => \sign00__0_carry_i_81_n_0\,
S(1) => \sign00__0_carry_i_82_n_0\,
S(0) => \sign00__0_carry_i_83_n_0\
);
\sign00__0_carry_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"CFCAFFFA"
)
port map (
I0 => \sign00__0_carry_i_74_n_5\,
I1 => sum4(7),
I2 => sum3,
I3 => \sign00__0_carry_i_74_n_4\,
I4 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_72_n_0\
);
\sign00__0_carry_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => \sign00__0_carry_i_71_n_4\,
I1 => \sign00__0_carry_i_71_n_5\,
I2 => \sum3_carry__0_i_9_n_3\,
I3 => \sign00__0_carry_i_78_n_6\,
I4 => sum3,
I5 => \sign00__0_carry_i_78_n_7\,
O => \sign00__0_carry_i_73_n_0\
);
\sign00__0_carry_i_74\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_12_n_0\,
CO(3) => \sign00__0_carry_i_74_n_0\,
CO(2) => \sign00__0_carry_i_74_n_1\,
CO(1) => \sign00__0_carry_i_74_n_2\,
CO(0) => \sign00__0_carry_i_74_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_74_n_4\,
O(2) => \sign00__0_carry_i_74_n_5\,
O(1) => \sign00__0_carry_i_74_n_6\,
O(0) => \sign00__0_carry_i_74_n_7\,
S(3) => \sign00__0_carry_i_84_n_0\,
S(2) => \sign00__0_carry_i_85_n_0\,
S(1) => \sign00__0_carry_i_86_n_0\,
S(0) => \sign00__0_carry_i_87_n_0\
);
\sign00__0_carry_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_79_n_0\,
CO(3) => \sign00__0_carry_i_75_n_0\,
CO(2) => \sign00__0_carry_i_75_n_1\,
CO(1) => \sign00__0_carry_i_75_n_2\,
CO(0) => \sign00__0_carry_i_75_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_75_n_4\,
O(2) => \sign00__0_carry_i_75_n_5\,
O(1) => \sign00__0_carry_i_75_n_6\,
O(0) => \sign00__0_carry_i_75_n_7\,
S(3) => \sign00__0_carry_i_88_n_0\,
S(2) => \sign00__0_carry_i_89_n_0\,
S(1) => \sign00__0_carry_i_90_n_0\,
S(0) => \sign00__0_carry_i_91_n_0\
);
\sign00__0_carry_i_76\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_75_n_0\,
CO(3) => \sign00__0_carry_i_76_n_0\,
CO(2) => \sign00__0_carry_i_76_n_1\,
CO(1) => \sign00__0_carry_i_76_n_2\,
CO(0) => \sign00__0_carry_i_76_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_76_n_4\,
O(2) => \sign00__0_carry_i_76_n_5\,
O(1) => \sign00__0_carry_i_76_n_6\,
O(0) => \sign00__0_carry_i_76_n_7\,
S(3) => \sign00__0_carry_i_92_n_0\,
S(2) => \sign00__0_carry_i_93_n_0\,
S(1) => \sign00__0_carry_i_94_n_0\,
S(0) => \sign00__0_carry_i_95_n_0\
);
\sign00__0_carry_i_77\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_76_n_0\,
CO(3 downto 1) => \NLW_sign00__0_carry_i_77_CO_UNCONNECTED\(3 downto 1),
CO(0) => \sign00__0_carry_i_77_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_sign00__0_carry_i_77_O_UNCONNECTED\(3 downto 2),
O(1) => \sign00__0_carry_i_77_n_6\,
O(0) => \sign00__0_carry_i_77_n_7\,
S(3 downto 2) => B"00",
S(1) => \sign00__0_carry_i_96_n_0\,
S(0) => \sign00__0_carry_i_97_n_0\
);
\sign00__0_carry_i_78\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_71_n_0\,
CO(3) => \sign00__0_carry_i_78_n_0\,
CO(2) => \sign00__0_carry_i_78_n_1\,
CO(1) => \sign00__0_carry_i_78_n_2\,
CO(0) => \sign00__0_carry_i_78_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_78_n_4\,
O(2) => \sign00__0_carry_i_78_n_5\,
O(1) => \sign00__0_carry_i_78_n_6\,
O(0) => \sign00__0_carry_i_78_n_7\,
S(3) => \sign00__0_carry_i_98_n_0\,
S(2) => \sign00__0_carry_i_99_n_0\,
S(1) => \sign00__0_carry_i_100_n_0\,
S(0) => \sign00__0_carry_i_101_n_0\
);
\sign00__0_carry_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \sign00__0_carry_i_78_n_0\,
CO(3) => \sign00__0_carry_i_79_n_0\,
CO(2) => \sign00__0_carry_i_79_n_1\,
CO(1) => \sign00__0_carry_i_79_n_2\,
CO(0) => \sign00__0_carry_i_79_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \sign00__0_carry_i_79_n_4\,
O(2) => \sign00__0_carry_i_79_n_5\,
O(1) => \sign00__0_carry_i_79_n_6\,
O(0) => \sign00__0_carry_i_79_n_7\,
S(3) => \sign00__0_carry_i_102_n_0\,
S(2) => \sign00__0_carry_i_103_n_0\,
S(1) => \sign00__0_carry_i_104_n_0\,
S(0) => \sign00__0_carry_i_105_n_0\
);
\sign00__0_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555DAAA2AAA2555D"
)
port map (
I0 => \sign00__0_carry_i_15_n_0\,
I1 => \sign00__0_carry_i_16_n_0\,
I2 => \sign00__0_carry_i_17_n_0\,
I3 => sum3,
I4 => \sign00__0_carry_i_5_n_0\,
I5 => A(1),
O => \sign00__0_carry_i_8_n_0\
);
\sign00__0_carry_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_80_n_0\
);
\sign00__0_carry_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_81_n_0\
);
\sign00__0_carry_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_82_n_0\
);
\sign00__0_carry_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_83_n_0\
);
\sign00__0_carry_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_84_n_0\
);
\sign00__0_carry_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(7),
O => \sign00__0_carry_i_85_n_0\
);
\sign00__0_carry_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(6),
O => \sign00__0_carry_i_86_n_0\
);
\sign00__0_carry_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => sum4(5),
O => \sign00__0_carry_i_87_n_0\
);
\sign00__0_carry_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_88_n_0\
);
\sign00__0_carry_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_89_n_0\
);
\sign00__0_carry_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"A0AC"
)
port map (
I0 => \sign00__0_carry_i_21_n_0\,
I1 => \sign00__0_carry_i_22_n_0\,
I2 => sum3,
I3 => \sign00__0_carry_i_12_n_4\,
O => \sign00__0_carry_i_9_n_0\
);
\sign00__0_carry_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_90_n_0\
);
\sign00__0_carry_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_91_n_0\
);
\sign00__0_carry_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_92_n_0\
);
\sign00__0_carry_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_93_n_0\
);
\sign00__0_carry_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_94_n_0\
);
\sign00__0_carry_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_95_n_0\
);
\sign00__0_carry_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_96_n_0\
);
\sign00__0_carry_i_97\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_97_n_0\
);
\sign00__0_carry_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_98_n_0\
);
\sign00__0_carry_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sign00__0_carry_i_99_n_0\
);
sum3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sum3_carry_n_0,
CO(2) => sum3_carry_n_1,
CO(1) => sum3_carry_n_2,
CO(0) => sum3_carry_n_3,
CYINIT => '1',
DI(3) => sum3_carry_i_1_n_0,
DI(2) => sum3_carry_i_2_n_0,
DI(1) => sum3_carry_i_3_n_0,
DI(0) => sum3_carry_i_4_n_0,
O(3 downto 0) => NLW_sum3_carry_O_UNCONNECTED(3 downto 0),
S(3) => sum3_carry_i_5_n_0,
S(2) => sum3_carry_i_6_n_0,
S(1) => sum3_carry_i_7_n_0,
S(0) => sum3_carry_i_8_n_0
);
\sum3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sum3_carry_n_0,
CO(3) => \sum3_carry__0_n_0\,
CO(2) => \sum3_carry__0_n_1\,
CO(1) => \sum3_carry__0_n_2\,
CO(0) => \sum3_carry__0_n_3\,
CYINIT => '0',
DI(3) => \sum3_carry__0_i_1_n_0\,
DI(2) => \sum3_carry__0_i_2_n_0\,
DI(1) => \sum3_carry__0_i_3_n_0\,
DI(0) => \sum3_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_sum3_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \sum3_carry__0_i_5_n_0\,
S(2) => \sum3_carry__0_i_6_n_0\,
S(1) => \sum3_carry__0_i_7_n_0\,
S(0) => \sum3_carry__0_i_8_n_0\
);
\sum3_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_1_n_0\
);
\sum3_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_2_n_0\
);
\sum3_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_3_n_0\
);
\sum3_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_4_n_0\
);
\sum3_carry__0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_5_n_0\
);
\sum3_carry__0_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_6_n_0\
);
\sum3_carry__0_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_7_n_0\
);
\sum3_carry__0_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__0_i_8_n_0\
);
\sum3_carry__0_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \sum4_carry__0_n_0\,
CO(3 downto 1) => \NLW_sum3_carry__0_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \sum3_carry__0_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_sum3_carry__0_i_9_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => B"0001"
);
\sum3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sum3_carry__0_n_0\,
CO(3) => \sum3_carry__1_n_0\,
CO(2) => \sum3_carry__1_n_1\,
CO(1) => \sum3_carry__1_n_2\,
CO(0) => \sum3_carry__1_n_3\,
CYINIT => '0',
DI(3) => \sum3_carry__1_i_1_n_0\,
DI(2) => \sum3_carry__1_i_2_n_0\,
DI(1) => \sum3_carry__1_i_3_n_0\,
DI(0) => \sum3_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_sum3_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \sum3_carry__1_i_5_n_0\,
S(2) => \sum3_carry__1_i_6_n_0\,
S(1) => \sum3_carry__1_i_7_n_0\,
S(0) => \sum3_carry__1_i_8_n_0\
);
\sum3_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_1_n_0\
);
\sum3_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_2_n_0\
);
\sum3_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_3_n_0\
);
\sum3_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_4_n_0\
);
\sum3_carry__1_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_5_n_0\
);
\sum3_carry__1_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_6_n_0\
);
\sum3_carry__1_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_7_n_0\
);
\sum3_carry__1_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__1_i_8_n_0\
);
\sum3_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sum3_carry__1_n_0\,
CO(3) => sum3,
CO(2) => \sum3_carry__2_n_1\,
CO(1) => \sum3_carry__2_n_2\,
CO(0) => \sum3_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => sum4(31),
DI(1) => \sum3_carry__2_i_2_n_0\,
DI(0) => \sum3_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_sum3_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \sum3_carry__2_i_4_n_0\,
S(2) => \sum3_carry__2_i_5_n_0\,
S(1) => \sum3_carry__2_i_6_n_0\,
S(0) => \sum3_carry__2_i_7_n_0\
);
\sum3_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => sum4(31)
);
\sum3_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_2_n_0\
);
\sum3_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_3_n_0\
);
\sum3_carry__2_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_4_n_0\
);
\sum3_carry__2_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_5_n_0\
);
\sum3_carry__2_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_6_n_0\
);
\sum3_carry__2_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \sum3_carry__0_i_9_n_3\,
O => \sum3_carry__2_i_7_n_0\
);
sum3_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(6),
I1 => sum4(7),
O => sum3_carry_i_1_n_0
);
sum3_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(4),
I1 => sum4(5),
O => sum3_carry_i_2_n_0
);
sum3_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(2),
I1 => sum4(3),
O => sum3_carry_i_3_n_0
);
sum3_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sum4(0),
I1 => sum4(1),
O => sum3_carry_i_4_n_0
);
sum3_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(6),
I1 => sum4(7),
O => sum3_carry_i_5_n_0
);
sum3_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(4),
I1 => sum4(5),
O => sum3_carry_i_6_n_0
);
sum3_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(2),
I1 => sum4(3),
O => sum3_carry_i_7_n_0
);
sum3_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sum4(0),
I1 => sum4(1),
O => sum3_carry_i_8_n_0
);
sum4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sum4_carry_n_0,
CO(2) => sum4_carry_n_1,
CO(1) => sum4_carry_n_2,
CO(0) => sum4_carry_n_3,
CYINIT => '1',
DI(3) => sum4_carry_i_1_n_0,
DI(2) => sum4_carry_i_2_n_0,
DI(1) => sum4_carry_i_3_n_0,
DI(0) => sum4_carry_i_4_n_0,
O(3 downto 0) => sum4(3 downto 0),
S(3) => sum4_carry_i_5_n_0,
S(2) => sum4_carry_i_6_n_0,
S(1) => sum4_carry_i_7_n_0,
S(0) => sum4_carry_i_8_n_0
);
\sum4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sum4_carry_n_0,
CO(3) => \sum4_carry__0_n_0\,
CO(2) => \sum4_carry__0_n_1\,
CO(1) => \sum4_carry__0_n_2\,
CO(0) => \sum4_carry__0_n_3\,
CYINIT => '0',
DI(3) => large_exp(7),
DI(2) => \sum4_carry__0_i_2_n_0\,
DI(1) => \sum4_carry__0_i_3_n_0\,
DI(0) => \sum4_carry__0_i_4_n_0\,
O(3 downto 0) => sum4(7 downto 4),
S(3) => \sum4_carry__0_i_5_n_0\,
S(2) => \sum4_carry__0_i_6_n_0\,
S(1) => \sum4_carry__0_i_7_n_0\,
S(0) => \sum4_carry__0_i_8_n_0\
);
\sum4_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => large_mant1_carry_n_0,
O => large_exp(7)
);
\sum4_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => large_mant1_carry_n_0,
O => \sum4_carry__0_i_2_n_0\
);
\sum4_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(28),
I1 => y(28),
I2 => large_mant1_carry_n_0,
O => \sum4_carry__0_i_3_n_0\
);
\sum4_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => large_mant1_carry_n_0,
O => \sum4_carry__0_i_4_n_0\
);
\sum4_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(30),
I1 => y(30),
O => \sum4_carry__0_i_5_n_0\
);
\sum4_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(29),
I1 => y(29),
O => \sum4_carry__0_i_6_n_0\
);
\sum4_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(28),
I1 => y(28),
O => \sum4_carry__0_i_7_n_0\
);
\sum4_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(27),
I1 => y(27),
O => \sum4_carry__0_i_8_n_0\
);
sum4_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(26),
I1 => y(26),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_1_n_0
);
sum4_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_2_n_0
);
sum4_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(24),
I1 => y(24),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_3_n_0
);
sum4_carry_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => large_mant1_carry_n_0,
O => sum4_carry_i_4_n_0
);
sum4_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(26),
I1 => y(26),
O => sum4_carry_i_5_n_0
);
sum4_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(25),
I1 => y(25),
O => sum4_carry_i_6_n_0
);
sum4_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(24),
I1 => y(24),
O => sum4_carry_i_7_n_0
);
sum4_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x(23),
I1 => y(23),
O => sum4_carry_i_8_n_0
);
z0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z0_carry_n_0,
CO(2) => z0_carry_n_1,
CO(1) => z0_carry_n_2,
CO(0) => z0_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => large_exp(3 downto 0),
O(3 downto 0) => z(26 downto 23),
S(3) => \z0_carry_i_5__0_n_0\,
S(2) => z0_carry_i_6_n_0,
S(1) => z0_carry_i_7_n_0,
S(0) => z0_carry_i_8_n_0
);
\z0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z0_carry_n_0,
CO(3) => \NLW_z0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z0_carry__0_n_1\,
CO(1) => \z0_carry__0_n_2\,
CO(0) => \z0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => large_exp(6 downto 4),
O(3 downto 0) => z(30 downto 27),
S(3) => z0_carry_i_4_n_0,
S(2) => z0_carry_i_5_n_0,
S(1) => \z0_carry_i_6__0_n_0\,
S(0) => \z0_carry_i_7__0_n_0\
);
z0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(26),
I1 => y(26),
I2 => large_mant1_carry_n_0,
O => large_exp(3)
);
z0_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"5554444400000000"
)
port map (
I0 => sel0(23),
I1 => \_carry_i_5_n_0\,
I2 => sel0(14),
I3 => \_carry_i_6_n_0\,
I4 => \_carry_i_7_n_0\,
I5 => \_carry_i_8_n_0\,
O => z0_carry_i_10_n_0
);
z0_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8A8A8A800"
)
port map (
I0 => \_carry_i_9_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \_carry_i_11_n_0\,
I3 => \_carry_i_12_n_0\,
I4 => sel0(1),
I5 => \_carry_i_13_n_0\,
O => z0_carry_i_11_n_0
);
z0_carry_i_12: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(13),
I1 => sel0(23),
I2 => sel0(11),
I3 => sel0(12),
O => z0_carry_i_12_n_0
);
\z0_carry_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(29),
I1 => y(29),
I2 => large_mant1_carry_n_0,
O => large_exp(6)
);
z0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(25),
I1 => y(25),
I2 => large_mant1_carry_n_0,
O => large_exp(2)
);
\z0_carry_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(28),
I1 => y(28),
I2 => large_mant1_carry_n_0,
O => large_exp(5)
);
z0_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(24),
I1 => y(24),
I2 => large_mant1_carry_n_0,
O => large_exp(1)
);
\z0_carry_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(27),
I1 => y(27),
I2 => large_mant1_carry_n_0,
O => large_exp(4)
);
z0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(30),
I2 => x(30),
I3 => \z[18]_INST_0_i_1_n_0\,
O => z0_carry_i_4_n_0
);
\z0_carry_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => large_mant1_carry_n_0,
O => large_exp(0)
);
z0_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(29),
I2 => x(29),
I3 => \z[18]_INST_0_i_1_n_0\,
O => z0_carry_i_5_n_0
);
\z0_carry_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E41B"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(26),
I2 => x(26),
I3 => z0_carry_i_9_n_0,
O => \z0_carry_i_5__0_n_0\
);
z0_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(25),
I2 => x(25),
I3 => z0_carry_i_10_n_0,
O => z0_carry_i_6_n_0
);
\z0_carry_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(28),
I2 => x(28),
I3 => \z[18]_INST_0_i_1_n_0\,
O => \z0_carry_i_6__0_n_0\
);
z0_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(24),
I2 => x(24),
I3 => z0_carry_i_11_n_0,
O => z0_carry_i_7_n_0
);
\z0_carry_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(27),
I2 => x(27),
I3 => \z0_carry_i_8__0_n_0\,
O => \z0_carry_i_7__0_n_0\
);
z0_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"1BE4"
)
port map (
I0 => large_mant1_carry_n_0,
I1 => y(23),
I2 => x(23),
I3 => \z[22]_INST_0_i_1_n_0\,
O => z0_carry_i_8_n_0
);
\z0_carry_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z0_carry_i_8__0_n_0\
);
z0_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"F1F1F1F1F1F1F100"
)
port map (
I0 => \_carry_i_5_n_0\,
I1 => \z[31]_INST_0_i_7_n_0\,
I2 => sel0(23),
I3 => z0_carry_i_12_n_0,
I4 => \z[31]_INST_0_i_3_n_0\,
I5 => sel0(14),
O => z0_carry_i_9_n_0
);
z2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z2_carry_n_0,
CO(2) => z2_carry_n_1,
CO(1) => z2_carry_n_2,
CO(0) => z2_carry_n_3,
CYINIT => '1',
DI(3) => z2_carry_i_1_n_0,
DI(2) => z2_carry_i_2_n_0,
DI(1) => z2_carry_i_3_n_0,
DI(0) => z2_carry_i_4_n_0,
O(3 downto 0) => NLW_z2_carry_O_UNCONNECTED(3 downto 0),
S(3) => z2_carry_i_5_n_0,
S(2) => z2_carry_i_6_n_0,
S(1) => z2_carry_i_7_n_0,
S(0) => z2_carry_i_8_n_0
);
\z2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z2_carry_n_0,
CO(3) => \z2_carry__0_n_0\,
CO(2) => \z2_carry__0_n_1\,
CO(1) => \z2_carry__0_n_2\,
CO(0) => \z2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \z2_carry__0_i_1_n_0\,
DI(2) => \z2_carry__0_i_2_n_0\,
DI(1) => \z2_carry__0_i_3_n_0\,
DI(0) => \z2_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_z2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \z2_carry__0_i_5_n_0\,
S(2) => \z2_carry__0_i_6_n_0\,
S(1) => \z2_carry__0_i_7_n_0\,
S(0) => \z2_carry__0_i_8_n_0\
);
\z2_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_1_n_0\
);
\z2_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_2_n_0\
);
\z2_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_3_n_0\
);
\z2_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__0_i_4_n_0\
);
\z2_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_5_n_0\
);
\z2_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_6_n_0\
);
\z2_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_7_n_0\
);
\z2_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__0_i_8_n_0\
);
\z2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \z2_carry__0_n_0\,
CO(3) => \z2_carry__1_n_0\,
CO(2) => \z2_carry__1_n_1\,
CO(1) => \z2_carry__1_n_2\,
CO(0) => \z2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \z2_carry__1_i_1_n_0\,
DI(2) => \z2_carry__1_i_2_n_0\,
DI(1) => \z2_carry__1_i_3_n_0\,
DI(0) => \z2_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_z2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \z2_carry__1_i_5_n_0\,
S(2) => \z2_carry__1_i_6_n_0\,
S(1) => \z2_carry__1_i_7_n_0\,
S(0) => \z2_carry__1_i_8_n_0\
);
\z2_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_1_n_0\
);
\z2_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_2_n_0\
);
\z2_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_3_n_0\
);
\z2_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__1_i_4_n_0\
);
\z2_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_5_n_0\
);
\z2_carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_6_n_0\
);
\z2_carry__1_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_7_n_0\
);
\z2_carry__1_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__1_i_8_n_0\
);
\z2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \z2_carry__1_n_0\,
CO(3) => z2,
CO(2) => \z2_carry__2_n_1\,
CO(1) => \z2_carry__2_n_2\,
CO(0) => \z2_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => z1(7),
DI(1) => \z2_carry__2_i_2_n_0\,
DI(0) => \z2_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_z2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \z2_carry__2_i_4_n_0\,
S(2) => \z2_carry__2_i_5_n_0\,
S(1) => \z2_carry__2_i_6_n_0\,
S(0) => \z2_carry__2_i_7_n_0\
);
\z2_carry__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => z1(7)
);
\z2_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__2_i_2_n_0\
);
\z2_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => \z2_carry__2_i_3_n_0\
);
\z2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_4_n_0\
);
\z2_carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_5_n_0\
);
\z2_carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_6_n_0\
);
\z2_carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z2_carry__2_i_7_n_0\
);
z2_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
O => z2_carry_i_1_n_0
);
z2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \z0_carry_i_8__0_n_0\,
I1 => \z[18]_INST_0_i_1_n_0\,
O => z2_carry_i_2_n_0
);
z2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => z0_carry_i_9_n_0,
O => z2_carry_i_3_n_0
);
z2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z0_carry_i_11_n_0,
O => z2_carry_i_4_n_0
);
z2_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => z2_carry_i_5_n_0
);
z2_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \z0_carry_i_8__0_n_0\,
I1 => \z[18]_INST_0_i_1_n_0\,
O => z2_carry_i_6_n_0
);
z2_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => z0_carry_i_9_n_0,
O => z2_carry_i_7_n_0
);
z2_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z0_carry_i_11_n_0,
O => z2_carry_i_8_n_0
);
\z[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[0]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[0]_INST_0_i_2_n_0\,
I4 => \z[1]_INST_0_i_2_n_0\,
I5 => z2,
O => z(0)
);
\z[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \z[1]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z2,
O => \z[0]_INST_0_i_1_n_0\
);
\z[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[6]_INST_0_i_5_n_0\,
I1 => \z[2]_INST_0_i_4_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[4]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[0]_INST_0_i_3_n_0\,
O => \z[0]_INST_0_i_2_n_0\
);
\z[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => sel0(23),
I1 => sel0(7),
I2 => \z[22]_INST_0_i_19_n_0\,
I3 => sel0(15),
I4 => \z[22]_INST_0_i_20_n_0\,
I5 => \sign00__0_carry_n_7\,
O => \z[0]_INST_0_i_3_n_0\
);
\z[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(10),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[10]_INST_0_i_2_n_0\,
I4 => \z[11]_INST_0_i_2_n_0\,
I5 => z2,
O => z(10)
);
\z[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[10]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[10]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[10]_INST_0_i_5_n_0\,
O => z10_in(10)
);
\z[10]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(2),
I2 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_10_n_0\
);
\z[10]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[12]_INST_0_i_4_n_0\,
I1 => \z[12]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[10]_INST_0_i_6_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[10]_INST_0_i_7_n_0\,
O => \z[10]_INST_0_i_2_n_0\
);
\z[10]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[16]_INST_0_i_7_n_0\,
I1 => \z[10]_INST_0_i_8_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[10]_INST_0_i_9_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[10]_INST_0_i_10_n_0\,
O => \z[10]_INST_0_i_3_n_0\
);
\z[10]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => \sign00__0_carry_n_7\,
I1 => sel0(7),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(3),
I5 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_4_n_0\
);
\z[10]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => sel0(1),
I1 => sel0(9),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(5),
I5 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_5_n_0\
);
\z[10]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(21),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(13),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[10]_INST_0_i_6_n_0\
);
\z[10]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(17),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(9),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[10]_INST_0_i_7_n_0\
);
\z[10]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(4),
I2 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_8_n_0\
);
\z[10]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(6),
I2 => z0_carry_i_9_n_0,
O => \z[10]_INST_0_i_9_n_0\
);
\z[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(11),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[11]_INST_0_i_2_n_0\,
I4 => \z[12]_INST_0_i_2_n_0\,
I5 => z2,
O => z(11)
);
\z[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[11]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[12]_INST_0_i_3_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[14]_INST_0_i_3_n_0\,
O => z10_in(11)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[13]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[11]_INST_0_i_4_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[11]_INST_0_i_5_n_0\,
O => \z[11]_INST_0_i_2_n_0\
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[17]_INST_0_i_5_n_0\,
I1 => \z[13]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[15]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[11]_INST_0_i_6_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(22),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(14),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[11]_INST_0_i_4_n_0\
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(18),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(10),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[11]_INST_0_i_5_n_0\
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(3),
I2 => z0_carry_i_9_n_0,
O => \z[11]_INST_0_i_6_n_0\
);
\z[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(12),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[12]_INST_0_i_2_n_0\,
I4 => \z[13]_INST_0_i_2_n_0\,
I5 => z2,
O => z(12)
);
\z[12]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[12]_INST_0_i_3_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[14]_INST_0_i_3_n_0\,
I4 => \z[22]_INST_0_i_1_n_0\,
I5 => \z[13]_INST_0_i_3_n_0\,
O => z10_in(12)
);
\z[12]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[14]_INST_0_i_5_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[12]_INST_0_i_4_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[12]_INST_0_i_5_n_0\,
O => \z[12]_INST_0_i_2_n_0\
);
\z[12]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => sel0(0),
I1 => sel0(8),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(4),
I5 => z0_carry_i_9_n_0,
O => \z[12]_INST_0_i_3_n_0\
);
\z[12]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(15),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[12]_INST_0_i_4_n_0\
);
\z[12]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(19),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(11),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[12]_INST_0_i_5_n_0\
);
\z[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(13),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[13]_INST_0_i_2_n_0\,
I4 => \z[14]_INST_0_i_2_n_0\,
I5 => z2,
O => z(13)
);
\z[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[13]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[14]_INST_0_i_3_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[14]_INST_0_i_4_n_0\,
O => z10_in(13)
);
\z[13]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[15]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[13]_INST_0_i_4_n_0\,
O => \z[13]_INST_0_i_2_n_0\
);
\z[13]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[19]_INST_0_i_5_n_0\,
I1 => \z[15]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[17]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[13]_INST_0_i_5_n_0\,
O => \z[13]_INST_0_i_3_n_0\
);
\z[13]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(16),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(20),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(12),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[13]_INST_0_i_4_n_0\
);
\z[13]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(5),
I2 => z0_carry_i_9_n_0,
O => \z[13]_INST_0_i_5_n_0\
);
\z[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(14),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[14]_INST_0_i_2_n_0\,
I4 => \z[15]_INST_0_i_2_n_0\,
I5 => z2,
O => z(14)
);
\z[14]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[14]_INST_0_i_3_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[14]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_1_n_0\,
I5 => \z[15]_INST_0_i_3_n_0\,
O => z10_in(14)
);
\z[14]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[16]_INST_0_i_6_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[14]_INST_0_i_5_n_0\,
O => \z[14]_INST_0_i_2_n_0\
);
\z[14]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000A000CF00C000"
)
port map (
I0 => sel0(2),
I1 => sel0(10),
I2 => z0_carry_i_10_n_0,
I3 => \z0_carry_i_8__0_n_0\,
I4 => sel0(6),
I5 => z0_carry_i_9_n_0,
O => \z[14]_INST_0_i_3_n_0\
);
\z[14]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800FFFFB8000000"
)
port map (
I0 => sel0(4),
I1 => z0_carry_i_9_n_0,
I2 => sel0(12),
I3 => \z0_carry_i_8__0_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[16]_INST_0_i_7_n_0\,
O => \z[14]_INST_0_i_4_n_0\
);
\z[14]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(17),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(21),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(13),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[14]_INST_0_i_5_n_0\
);
\z[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[15]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[15]_INST_0_i_2_n_0\,
I4 => \z[16]_INST_0_i_2_n_0\,
I5 => z2,
O => z(15)
);
\z[15]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[16]_INST_0_i_5_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[15]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[15]_INST_0_i_1_n_0\
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[17]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[15]_INST_0_i_4_n_0\,
O => \z[15]_INST_0_i_2_n_0\
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[21]_INST_0_i_4_n_0\,
I1 => \z[17]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[19]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[15]_INST_0_i_5_n_0\,
O => \z[15]_INST_0_i_3_n_0\
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(18),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(22),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(14),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[15]_INST_0_i_4_n_0\
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => \sign00__0_carry_n_7\,
I1 => z0_carry_i_9_n_0,
I2 => sel0(7),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[15]_INST_0_i_5_n_0\
);
\z[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[16]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[16]_INST_0_i_2_n_0\,
I4 => \z[16]_INST_0_i_3_n_0\,
I5 => z2,
O => z(16)
);
\z[16]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[16]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[16]_INST_0_i_5_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[16]_INST_0_i_1_n_0\
);
\z[16]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[18]_INST_0_i_9_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[16]_INST_0_i_6_n_0\,
O => \z[16]_INST_0_i_2_n_0\
);
\z[16]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[19]_INST_0_i_4_n_0\,
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[17]_INST_0_i_4_n_0\,
O => \z[16]_INST_0_i_3_n_0\
);
\z[16]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_31_n_0\,
I1 => \z[19]_INST_0_i_5_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[21]_INST_0_i_4_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[17]_INST_0_i_5_n_0\,
O => \z[16]_INST_0_i_4_n_0\
);
\z[16]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_29_n_0\,
I1 => \z[18]_INST_0_i_10_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[20]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[16]_INST_0_i_7_n_0\,
O => \z[16]_INST_0_i_5_n_0\
);
\z[16]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030BB3088"
)
port map (
I0 => sel0(19),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => sel0(23),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => sel0(15),
I5 => \z[22]_INST_0_i_20_n_0\,
O => \z[16]_INST_0_i_6_n_0\
);
\z[16]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(0),
I1 => z0_carry_i_9_n_0,
I2 => sel0(8),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[16]_INST_0_i_7_n_0\
);
\z[17]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888F000"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[17]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[17]_INST_0_i_2_n_0\,
I4 => z2,
O => z(17)
);
\z[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[18]_INST_0_i_6_n_0\,
I1 => \z[18]_INST_0_i_7_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[18]_INST_0_i_5_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[17]_INST_0_i_3_n_0\,
O => \z[17]_INST_0_i_1_n_0\
);
\z[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE44FAFAEE445050"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[20]_INST_0_i_4_n_0\,
I2 => \z[18]_INST_0_i_9_n_0\,
I3 => \z[19]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[17]_INST_0_i_4_n_0\,
O => \z[17]_INST_0_i_2_n_0\
);
\z[17]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800FFFFB8000000"
)
port map (
I0 => sel0(5),
I1 => z0_carry_i_9_n_0,
I2 => sel0(13),
I3 => \z0_carry_i_8__0_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[17]_INST_0_i_5_n_0\,
O => \z[17]_INST_0_i_3_n_0\
);
\z[17]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(20),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(16),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[17]_INST_0_i_4_n_0\
);
\z[17]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(1),
I1 => z0_carry_i_9_n_0,
I2 => sel0(9),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[17]_INST_0_i_5_n_0\
);
\z[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888F000"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[18]_INST_0_i_2_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_3_n_0\,
I4 => z2,
O => z(18)
);
\z[18]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
O => \z[18]_INST_0_i_1_n_0\
);
\z[18]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(2),
I1 => z0_carry_i_9_n_0,
I2 => sel0(10),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[18]_INST_0_i_10_n_0\
);
\z[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[18]_INST_0_i_4_n_0\,
I1 => \z[18]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[18]_INST_0_i_6_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[18]_INST_0_i_7_n_0\,
O => \z[18]_INST_0_i_2_n_0\
);
\z[18]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE44FAFAEE445050"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[18]_INST_0_i_8_n_0\,
I2 => \z[19]_INST_0_i_4_n_0\,
I3 => \z[20]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[18]_INST_0_i_9_n_0\,
O => \z[18]_INST_0_i_3_n_0\
);
\z[18]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB88888888888"
)
port map (
I0 => \z[22]_INST_0_i_33_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => sel0(5),
I3 => z0_carry_i_9_n_0,
I4 => sel0(13),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[18]_INST_0_i_4_n_0\
);
\z[18]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB88888888888"
)
port map (
I0 => \z[22]_INST_0_i_31_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => sel0(3),
I3 => z0_carry_i_9_n_0,
I4 => sel0(11),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[18]_INST_0_i_5_n_0\
);
\z[18]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BBB88888888888"
)
port map (
I0 => \z[22]_INST_0_i_27_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => sel0(4),
I3 => z0_carry_i_9_n_0,
I4 => sel0(12),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[18]_INST_0_i_6_n_0\
);
\z[18]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800FFFFB8000000"
)
port map (
I0 => sel0(6),
I1 => z0_carry_i_9_n_0,
I2 => sel0(14),
I3 => \z0_carry_i_8__0_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[18]_INST_0_i_10_n_0\,
O => \z[18]_INST_0_i_7_n_0\
);
\z[18]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400040400000004"
)
port map (
I0 => \z[22]_INST_0_i_19_n_0\,
I1 => sel0(20),
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => z2,
I4 => z3(2),
I5 => z0_carry_i_10_n_0,
O => \z[18]_INST_0_i_8_n_0\
);
\z[18]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(21),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(17),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[18]_INST_0_i_9_n_0\
);
\z[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[19]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[19]_INST_0_i_2_n_0\,
I4 => \z[20]_INST_0_i_2_n_0\,
I5 => z2,
O => z(19)
);
\z[19]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[20]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[19]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[19]_INST_0_i_1_n_0\
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => \z[22]_INST_0_i_19_n_0\,
I1 => sel0(20),
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[19]_INST_0_i_4_n_0\,
O => \z[19]_INST_0_i_2_n_0\
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_33_n_0\,
I1 => \z[21]_INST_0_i_4_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_31_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[19]_INST_0_i_5_n_0\,
O => \z[19]_INST_0_i_3_n_0\
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(22),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(18),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[19]_INST_0_i_4_n_0\
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(3),
I1 => z0_carry_i_9_n_0,
I2 => sel0(11),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[19]_INST_0_i_5_n_0\
);
\z[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[1]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[1]_INST_0_i_2_n_0\,
I4 => \z[2]_INST_0_i_2_n_0\,
I5 => z2,
O => z(1)
);
\z[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[2]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[1]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[1]_INST_0_i_1_n_0\
);
\z[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[7]_INST_0_i_5_n_0\,
I1 => \z[3]_INST_0_i_4_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[5]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[1]_INST_0_i_4_n_0\,
O => \z[1]_INST_0_i_2_n_0\
);
\z[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => \z0_carry_i_8__0_n_0\,
I2 => \sign00__0_carry_n_7\,
I3 => z0_carry_i_9_n_0,
I4 => z0_carry_i_11_n_0,
O => \z[1]_INST_0_i_3_n_0\
);
\z[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(8),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(16),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(0),
O => \z[1]_INST_0_i_4_n_0\
);
\z[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[20]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[20]_INST_0_i_2_n_0\,
I4 => \z[21]_INST_0_i_2_n_0\,
I5 => z2,
O => z(20)
);
\z[20]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[21]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[20]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[20]_INST_0_i_1_n_0\
);
\z[20]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => \z[22]_INST_0_i_19_n_0\,
I1 => sel0(21),
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => \z[22]_INST_0_i_21_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
I5 => \z[20]_INST_0_i_4_n_0\,
O => \z[20]_INST_0_i_2_n_0\
);
\z[20]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_28_n_0\,
I1 => \z[22]_INST_0_i_29_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_27_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[20]_INST_0_i_5_n_0\,
O => \z[20]_INST_0_i_3_n_0\
);
\z[20]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000B08"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_21_n_0\,
I2 => \z[22]_INST_0_i_20_n_0\,
I3 => sel0(19),
I4 => \z[22]_INST_0_i_19_n_0\,
O => \z[20]_INST_0_i_4_n_0\
);
\z[20]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(4),
I1 => z0_carry_i_9_n_0,
I2 => sel0(12),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[20]_INST_0_i_5_n_0\
);
\z[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[21]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[21]_INST_0_i_2_n_0\,
I4 => \z[22]_INST_0_i_4_n_0\,
I5 => z2,
O => z(21)
);
\z[21]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[22]_INST_0_i_10_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[21]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[21]_INST_0_i_1_n_0\
);
\z[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000B08"
)
port map (
I0 => sel0(22),
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[22]_INST_0_i_19_n_0\,
I3 => sel0(20),
I4 => \z[22]_INST_0_i_20_n_0\,
I5 => \z[22]_INST_0_i_21_n_0\,
O => \z[21]_INST_0_i_2_n_0\
);
\z[21]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_30_n_0\,
I1 => \z[22]_INST_0_i_31_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_33_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[21]_INST_0_i_4_n_0\,
O => \z[21]_INST_0_i_3_n_0\
);
\z[21]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(5),
I1 => z0_carry_i_9_n_0,
I2 => sel0(13),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[21]_INST_0_i_4_n_0\
);
\z[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(22),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[22]_INST_0_i_4_n_0\,
I4 => \z[22]_INST_0_i_5_n_0\,
I5 => z2,
O => z(22)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555544444440"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_6_n_0\,
I2 => sel0(14),
I3 => \z[22]_INST_0_i_7_n_0\,
I4 => \z[22]_INST_0_i_8_n_0\,
I5 => \z[22]_INST_0_i_9_n_0\,
O => \z[22]_INST_0_i_1_n_0\
);
\z[22]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[22]_INST_0_i_26_n_0\,
I1 => \z[22]_INST_0_i_27_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[22]_INST_0_i_28_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[22]_INST_0_i_29_n_0\,
O => \z[22]_INST_0_i_10_n_0\
);
\z[22]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[22]_INST_0_i_30_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => \z[22]_INST_0_i_31_n_0\,
O => \z[22]_INST_0_i_11_n_0\
);
\z[22]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[22]_INST_0_i_32_n_0\,
I1 => z0_carry_i_10_n_0,
I2 => \z[22]_INST_0_i_33_n_0\,
O => \z[22]_INST_0_i_12_n_0\
);
\z[22]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \z[22]_INST_0_i_34_n_0\,
I1 => \z[22]_INST_0_i_35_n_0\,
I2 => \z[22]_INST_0_i_36_n_0\,
I3 => \z[22]_INST_0_i_37_n_0\,
I4 => \z[22]_INST_0_i_38_n_0\,
O => \z[22]_INST_0_i_13_n_0\
);
\z[22]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(11),
I1 => z3(12),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(9),
I4 => z2,
I5 => z3(10),
O => \z[22]_INST_0_i_14_n_0\
);
\z[22]_INST_0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(7),
I1 => z3(8),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(5),
I4 => z2,
I5 => z3(6),
O => \z[22]_INST_0_i_15_n_0\
);
\z[22]_INST_0_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(19),
I1 => z3(20),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(17),
I4 => z2,
I5 => z3(18),
O => \z[22]_INST_0_i_16_n_0\
);
\z[22]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF0F0FFFEE"
)
port map (
I0 => z3(15),
I1 => z3(16),
I2 => \z[18]_INST_0_i_1_n_0\,
I3 => z3(13),
I4 => z2,
I5 => z3(14),
O => \z[22]_INST_0_i_17_n_0\
);
\z[22]_INST_0_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"5C"
)
port map (
I0 => z0_carry_i_11_n_0,
I1 => z3(1),
I2 => z2,
O => \z[22]_INST_0_i_18_n_0\
);
\z[22]_INST_0_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => z3(3),
I2 => z2,
O => \z[22]_INST_0_i_19_n_0\
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[22]_INST_0_i_10_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[22]_INST_0_i_11_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[22]_INST_0_i_12_n_0\,
O => z10_in(22)
);
\z[22]_INST_0_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"99F0"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => \z[31]_INST_0_i_2_n_0\,
I2 => z3(4),
I3 => z2,
O => \z[22]_INST_0_i_20_n_0\
);
\z[22]_INST_0_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBFFF00"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_39_n_0\,
I2 => \_carry_i_8_n_0\,
I3 => z3(2),
I4 => z2,
O => \z[22]_INST_0_i_21_n_0\
);
\z[22]_INST_0_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(19),
I1 => sel0(21),
O => \z[22]_INST_0_i_22_n_0\
);
\z[22]_INST_0_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sel0(9),
I1 => sel0(11),
O => \z[22]_INST_0_i_23_n_0\
);
\z[22]_INST_0_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFEEEFEFFFFEEFE"
)
port map (
I0 => sel0(6),
I1 => sel0(2),
I2 => sel0(4),
I3 => sel0(5),
I4 => sel0(0),
I5 => sel0(1),
O => \z[22]_INST_0_i_24_n_0\
);
\z[22]_INST_0_i_25\: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => sel0(6),
I1 => sel0(5),
I2 => sel0(4),
O => \z[22]_INST_0_i_25_n_0\
);
\z[22]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(12),
I1 => z0_carry_i_9_n_0,
I2 => sel0(20),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(4),
O => \z[22]_INST_0_i_26_n_0\
);
\z[22]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(8),
I1 => z0_carry_i_9_n_0,
I2 => sel0(16),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(0),
O => \z[22]_INST_0_i_27_n_0\
);
\z[22]_INST_0_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(10),
I1 => z0_carry_i_9_n_0,
I2 => sel0(18),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(2),
O => \z[22]_INST_0_i_28_n_0\
);
\z[22]_INST_0_i_29\: unisim.vcomponents.LUT4
generic map(
INIT => X"3088"
)
port map (
I0 => sel0(6),
I1 => z0_carry_i_9_n_0,
I2 => sel0(14),
I3 => \z[31]_INST_0_i_2_n_0\,
O => \z[22]_INST_0_i_29_n_0\
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \z[22]_INST_0_i_13_n_0\,
I1 => \z[22]_INST_0_i_14_n_0\,
I2 => \z[22]_INST_0_i_15_n_0\,
I3 => \z[22]_INST_0_i_16_n_0\,
I4 => \z[22]_INST_0_i_17_n_0\,
O => \z[22]_INST_0_i_3_n_0\
);
\z[22]_INST_0_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(11),
I1 => z0_carry_i_9_n_0,
I2 => sel0(19),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(3),
O => \z[22]_INST_0_i_30_n_0\
);
\z[22]_INST_0_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(7),
I1 => z0_carry_i_9_n_0,
I2 => sel0(15),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => \sign00__0_carry_n_7\,
O => \z[22]_INST_0_i_31_n_0\
);
\z[22]_INST_0_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(13),
I1 => z0_carry_i_9_n_0,
I2 => sel0(21),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(5),
O => \z[22]_INST_0_i_32_n_0\
);
\z[22]_INST_0_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(9),
I1 => z0_carry_i_9_n_0,
I2 => sel0(17),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => sel0(1),
O => \z[22]_INST_0_i_33_n_0\
);
\z[22]_INST_0_i_34\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(30),
I1 => z2,
I2 => z3(29),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_34_n_0\
);
\z[22]_INST_0_i_35\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(24),
I1 => z2,
I2 => z3(23),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_35_n_0\
);
\z[22]_INST_0_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(22),
I1 => z2,
I2 => z3(21),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_36_n_0\
);
\z[22]_INST_0_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(28),
I1 => z2,
I2 => z3(27),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_37_n_0\
);
\z[22]_INST_0_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE323232"
)
port map (
I0 => z3(26),
I1 => z2,
I2 => z3(25),
I3 => \z[31]_INST_0_i_2_n_0\,
I4 => z0_carry_i_9_n_0,
O => \z[22]_INST_0_i_38_n_0\
);
\z[22]_INST_0_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAA"
)
port map (
I0 => \_carry_i_5_n_0\,
I1 => sel0(14),
I2 => \z[22]_INST_0_i_40_n_0\,
I3 => sel0(13),
I4 => sel0(12),
I5 => \_carry_i_7_n_0\,
O => \z[22]_INST_0_i_39_n_0\
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000B08"
)
port map (
I0 => sel0(23),
I1 => \z[22]_INST_0_i_18_n_0\,
I2 => \z[22]_INST_0_i_19_n_0\,
I3 => sel0(21),
I4 => \z[22]_INST_0_i_20_n_0\,
I5 => \z[22]_INST_0_i_21_n_0\,
O => \z[22]_INST_0_i_4_n_0\
);
\z[22]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => sel0(11),
I1 => sel0(8),
I2 => sel0(7),
I3 => sel0(9),
I4 => sel0(10),
O => \z[22]_INST_0_i_40_n_0\
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \z[22]_INST_0_i_21_n_0\,
I1 => \z[22]_INST_0_i_20_n_0\,
I2 => sel0(22),
I3 => \z[22]_INST_0_i_19_n_0\,
I4 => \z[22]_INST_0_i_18_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000F000F0B"
)
port map (
I0 => sel0(14),
I1 => sel0(13),
I2 => sel0(17),
I3 => sel0(16),
I4 => sel0(15),
I5 => \z[22]_INST_0_i_22_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[22]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFFEEFFEEEEEEFE"
)
port map (
I0 => sel0(12),
I1 => sel0(16),
I2 => sel0(8),
I3 => sel0(11),
I4 => sel0(9),
I5 => sel0(10),
O => \z[22]_INST_0_i_7_n_0\
);
\z[22]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000004000C000C00"
)
port map (
I0 => sel0(5),
I1 => \z[22]_INST_0_i_23_n_0\,
I2 => sel0(7),
I3 => \z[22]_INST_0_i_24_n_0\,
I4 => sel0(3),
I5 => \z[22]_INST_0_i_25_n_0\,
O => \z[22]_INST_0_i_8_n_0\
);
\z[22]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFAFAAAE"
)
port map (
I0 => sel0(22),
I1 => sel0(18),
I2 => sel0(21),
I3 => sel0(19),
I4 => sel0(20),
O => \z[22]_INST_0_i_9_n_0\
);
\z[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[2]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[2]_INST_0_i_2_n_0\,
I4 => \z[3]_INST_0_i_2_n_0\,
I5 => z2,
O => z(2)
);
\z[2]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[3]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[2]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[2]_INST_0_i_1_n_0\
);
\z[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[8]_INST_0_i_5_n_0\,
I1 => \z[4]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[6]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[2]_INST_0_i_4_n_0\,
O => \z[2]_INST_0_i_2_n_0\
);
\z[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => z0_carry_i_10_n_0,
I1 => \z0_carry_i_8__0_n_0\,
I2 => sel0(0),
I3 => z0_carry_i_9_n_0,
I4 => z0_carry_i_11_n_0,
O => \z[2]_INST_0_i_3_n_0\
);
\z[2]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(9),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(17),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(1),
O => \z[2]_INST_0_i_4_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"E2E2E200"
)
port map (
I0 => y(31),
I1 => large_mant1_carry_n_0,
I2 => x(31),
I3 => \z[31]_INST_0_i_1_n_0\,
I4 => \z[31]_INST_0_i_2_n_0\,
O => z(31)
);
\z[31]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[31]_INST_0_i_3_n_0\,
I1 => \z[31]_INST_0_i_4_n_0\,
I2 => \z[31]_INST_0_i_5_n_0\,
I3 => \z[31]_INST_0_i_6_n_0\,
I4 => sel0(3),
I5 => sel0(4),
O => \z[31]_INST_0_i_1_n_0\
);
\z[31]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => sel0(22),
I1 => \z[31]_INST_0_i_7_n_0\,
I2 => sel0(21),
I3 => sel0(23),
I4 => sel0(19),
I5 => sel0(20),
O => \z[31]_INST_0_i_2_n_0\
);
\z[31]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(9),
I1 => sel0(10),
I2 => sel0(7),
I3 => sel0(8),
O => \z[31]_INST_0_i_3_n_0\
);
\z[31]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(13),
I1 => sel0(14),
I2 => sel0(11),
I3 => sel0(12),
O => \z[31]_INST_0_i_4_n_0\
);
\z[31]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(1),
I1 => sel0(2),
I2 => \sign00__0_carry_n_7\,
I3 => sel0(0),
O => \z[31]_INST_0_i_5_n_0\
);
\z[31]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sel0(6),
I1 => sel0(5),
O => \z[31]_INST_0_i_6_n_0\
);
\z[31]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sel0(17),
I1 => sel0(18),
I2 => sel0(15),
I3 => sel0(16),
O => \z[31]_INST_0_i_7_n_0\
);
\z[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333F373B333"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => \z[3]_INST_0_i_1_n_0\,
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[3]_INST_0_i_2_n_0\,
I4 => \z[4]_INST_0_i_2_n_0\,
I5 => z2,
O => z(3)
);
\z[3]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"47FFFFFF"
)
port map (
I0 => \z[4]_INST_0_i_3_n_0\,
I1 => \z[22]_INST_0_i_1_n_0\,
I2 => \z[3]_INST_0_i_3_n_0\,
I3 => \z[18]_INST_0_i_1_n_0\,
I4 => z2,
O => \z[3]_INST_0_i_1_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[9]_INST_0_i_6_n_0\,
I1 => \z[5]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[7]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[3]_INST_0_i_4_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0B08000000000000"
)
port map (
I0 => sel0(1),
I1 => z0_carry_i_11_n_0,
I2 => z0_carry_i_9_n_0,
I3 => \sign00__0_carry_n_7\,
I4 => \z0_carry_i_8__0_n_0\,
I5 => z0_carry_i_10_n_0,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(10),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(18),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(2),
O => \z[3]_INST_0_i_4_n_0\
);
\z[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(4),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[4]_INST_0_i_2_n_0\,
I4 => \z[5]_INST_0_i_2_n_0\,
I5 => z2,
O => z(4)
);
\z[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[4]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[4]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[6]_INST_0_i_4_n_0\,
O => z10_in(4)
);
\z[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_7_n_0\,
I1 => \z[6]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[8]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[4]_INST_0_i_5_n_0\,
O => \z[4]_INST_0_i_2_n_0\
);
\z[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0B08000000000000"
)
port map (
I0 => sel0(2),
I1 => z0_carry_i_11_n_0,
I2 => z0_carry_i_9_n_0,
I3 => sel0(0),
I4 => \z0_carry_i_8__0_n_0\,
I5 => z0_carry_i_10_n_0,
O => \z[4]_INST_0_i_3_n_0\
);
\z[4]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => sel0(1),
I2 => \z0_carry_i_8__0_n_0\,
I3 => z0_carry_i_10_n_0,
O => \z[4]_INST_0_i_4_n_0\
);
\z[4]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(11),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(19),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(3),
O => \z[4]_INST_0_i_5_n_0\
);
\z[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(5),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[5]_INST_0_i_2_n_0\,
I4 => \z[6]_INST_0_i_2_n_0\,
I5 => z2,
O => z(5)
);
\z[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[5]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[5]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[7]_INST_0_i_4_n_0\,
O => z10_in(5)
);
\z[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[11]_INST_0_i_5_n_0\,
I1 => \z[7]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[9]_INST_0_i_6_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[5]_INST_0_i_5_n_0\,
O => \z[5]_INST_0_i_2_n_0\
);
\z[5]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFA0C0C0"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
I1 => \z[7]_INST_0_i_6_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[9]_INST_0_i_7_n_0\,
I4 => z0_carry_i_10_n_0,
O => \z[5]_INST_0_i_3_n_0\
);
\z[5]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => z0_carry_i_9_n_0,
I1 => sel0(2),
I2 => \z0_carry_i_8__0_n_0\,
I3 => z0_carry_i_10_n_0,
O => \z[5]_INST_0_i_4_n_0\
);
\z[5]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(12),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(20),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(4),
O => \z[5]_INST_0_i_5_n_0\
);
\z[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(6),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[6]_INST_0_i_2_n_0\,
I4 => \z[7]_INST_0_i_2_n_0\,
I5 => z2,
O => z(6)
);
\z[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[6]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[6]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[8]_INST_0_i_4_n_0\,
O => z10_in(6)
);
\z[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[12]_INST_0_i_5_n_0\,
I1 => \z[8]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[10]_INST_0_i_7_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[6]_INST_0_i_5_n_0\,
O => \z[6]_INST_0_i_2_n_0\
);
\z[6]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_8_n_0\,
I1 => \z[8]_INST_0_i_6_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[10]_INST_0_i_10_n_0\,
I4 => z0_carry_i_10_n_0,
O => \z[6]_INST_0_i_3_n_0\
);
\z[6]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(3),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => \sign00__0_carry_n_7\,
I4 => z0_carry_i_9_n_0,
O => \z[6]_INST_0_i_4_n_0\
);
\z[6]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(13),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(21),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(5),
O => \z[6]_INST_0_i_5_n_0\
);
\z[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(7),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[7]_INST_0_i_2_n_0\,
I4 => \z[8]_INST_0_i_2_n_0\,
I5 => z2,
O => z(7)
);
\z[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[7]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[7]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[9]_INST_0_i_4_n_0\,
O => z10_in(7)
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[9]_INST_0_i_5_n_0\,
I1 => \z[9]_INST_0_i_6_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[11]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[7]_INST_0_i_5_n_0\,
O => \z[7]_INST_0_i_2_n_0\
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[13]_INST_0_i_5_n_0\,
I1 => \z[9]_INST_0_i_7_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[11]_INST_0_i_6_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[7]_INST_0_i_6_n_0\,
O => \z[7]_INST_0_i_3_n_0\
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(4),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => sel0(0),
I4 => z0_carry_i_9_n_0,
O => \z[7]_INST_0_i_4_n_0\
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(14),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(22),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(6),
O => \z[7]_INST_0_i_5_n_0\
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => \sign00__0_carry_n_7\,
I2 => z0_carry_i_9_n_0,
O => \z[7]_INST_0_i_6_n_0\
);
\z[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(8),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[8]_INST_0_i_2_n_0\,
I4 => \z[9]_INST_0_i_2_n_0\,
I5 => z2,
O => z(8)
);
\z[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[8]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[8]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[10]_INST_0_i_4_n_0\,
O => z10_in(8)
);
\z[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_6_n_0\,
I1 => \z[10]_INST_0_i_7_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[12]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[8]_INST_0_i_5_n_0\,
O => \z[8]_INST_0_i_2_n_0\
);
\z[8]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[10]_INST_0_i_9_n_0\,
I1 => \z[10]_INST_0_i_10_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[10]_INST_0_i_8_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[8]_INST_0_i_6_n_0\,
O => \z[8]_INST_0_i_3_n_0\
);
\z[8]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(5),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => sel0(1),
I4 => z0_carry_i_9_n_0,
O => \z[8]_INST_0_i_4_n_0\
);
\z[8]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => sel0(15),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(23),
I3 => \z[22]_INST_0_i_20_n_0\,
I4 => sel0(7),
O => \z[8]_INST_0_i_5_n_0\
);
\z[8]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(0),
I2 => z0_carry_i_9_n_0,
O => \z[8]_INST_0_i_6_n_0\
);
\z[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCF050A000"
)
port map (
I0 => \z[22]_INST_0_i_1_n_0\,
I1 => z10_in(9),
I2 => \z[22]_INST_0_i_3_n_0\,
I3 => \z[9]_INST_0_i_2_n_0\,
I4 => \z[10]_INST_0_i_2_n_0\,
I5 => z2,
O => z(9)
);
\z[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8080808A808"
)
port map (
I0 => \z[18]_INST_0_i_1_n_0\,
I1 => \z[9]_INST_0_i_3_n_0\,
I2 => \z[22]_INST_0_i_1_n_0\,
I3 => \z[9]_INST_0_i_4_n_0\,
I4 => z0_carry_i_11_n_0,
I5 => \z[12]_INST_0_i_3_n_0\,
O => z10_in(9)
);
\z[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[11]_INST_0_i_4_n_0\,
I1 => \z[11]_INST_0_i_5_n_0\,
I2 => \z[22]_INST_0_i_18_n_0\,
I3 => \z[9]_INST_0_i_5_n_0\,
I4 => \z[22]_INST_0_i_21_n_0\,
I5 => \z[9]_INST_0_i_6_n_0\,
O => \z[9]_INST_0_i_2_n_0\
);
\z[9]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[15]_INST_0_i_5_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => z0_carry_i_11_n_0,
I3 => \z[13]_INST_0_i_5_n_0\,
I4 => z0_carry_i_10_n_0,
I5 => \z[9]_INST_0_i_7_n_0\,
O => \z[9]_INST_0_i_3_n_0\
);
\z[9]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000B080"
)
port map (
I0 => sel0(6),
I1 => z0_carry_i_10_n_0,
I2 => \z0_carry_i_8__0_n_0\,
I3 => sel0(2),
I4 => z0_carry_i_9_n_0,
O => \z[9]_INST_0_i_4_n_0\
);
\z[9]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(20),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(12),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[9]_INST_0_i_5_n_0\
);
\z[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8B8000000B8"
)
port map (
I0 => sel0(16),
I1 => \z[22]_INST_0_i_19_n_0\,
I2 => sel0(8),
I3 => z2,
I4 => z3(4),
I5 => \z0_carry_i_8__0_n_0\,
O => \z[9]_INST_0_i_6_n_0\
);
\z[9]_INST_0_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \z[31]_INST_0_i_2_n_0\,
I1 => sel0(1),
I2 => z0_carry_i_9_n_0,
O => \z[9]_INST_0_i_7_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_adder_subtractor_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_adder_subtractor_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_adder_subtractor_0_1 : entity is "affine_block_ieee754_fp_adder_subtractor_0_1,ieee754_fp_adder_subtractor,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_adder_subtractor_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_adder_subtractor_0_1 : entity is "ieee754_fp_adder_subtractor,Vivado 2016.4";
end affine_block_ieee754_fp_adder_subtractor_0_1;
architecture STRUCTURE of affine_block_ieee754_fp_adder_subtractor_0_1 is
begin
U0: entity work.affine_block_ieee754_fp_adder_subtractor_0_1_ieee754_fp_adder_subtractor
port map (
x(31 downto 0) => x(31 downto 0),
y(31 downto 0) => y(31 downto 0),
z(31 downto 0) => z(31 downto 0)
);
end STRUCTURE;
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`protect end_protected
| mit | 007f28bab0439439557ca40b35589773 | 0.946862 | 1.833145 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough_vga/video_passthrough_vga.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 18,144 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue May 09 00:09:42 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
hsync : out STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vsync : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_rgb888_to_rgb565_0_0;
component system_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_zybo_vga_0_0 is
port (
clk : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component system_zybo_vga_0_0;
signal Net : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal rgb888_to_rgb565_0_rgb_565 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zybo_vga_0_vga_b : STD_LOGIC_VECTOR ( 4 downto 0 );
signal zybo_vga_0_vga_g : STD_LOGIC_VECTOR ( 5 downto 0 );
signal zybo_vga_0_vga_r : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
hsync <= vga_sync_0_hsync;
vga_b(4 downto 0) <= zybo_vga_0_vga_b(4 downto 0);
vga_g(5 downto 0) <= zybo_vga_0_vga_g(5 downto 0);
vga_r(4 downto 0) <= zybo_vga_0_vga_r(4 downto 0);
vsync <= vga_sync_0_vsync;
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => Net,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
rgb888_to_rgb565_0: component system_rgb888_to_rgb565_0_0
port map (
rgb_565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
rgb_888(23 downto 0) => vga_color_test_0_rgb(23 downto 0)
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => Net,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk => Net,
hsync => vga_sync_0_hsync,
rst => processing_system7_0_FCLK_RESET0_N,
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zybo_vga_0: component system_zybo_vga_0_0
port map (
active => vga_sync_0_active,
clk => Net,
rgb(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
vga_b(4 downto 0) => zybo_vga_0_vga_b(4 downto 0),
vga_g(5 downto 0) => zybo_vga_0_vga_g(5 downto 0),
vga_r(4 downto 0) => zybo_vga_0_vga_r(4 downto 0)
);
end STRUCTURE;
| mit | 159d806567dff35c1dac95ce96b1c41f | 0.664297 | 2.908625 | false | false | false | false |
phil91stud/pwm_hdl | pwm/hdl/pwm_wrapper.vhd | 1 | 1,524 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_wrapper is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(1 downto 0);
pwm0 : out std_logic;
pwm0_n : out std_logic;
pwm1 : out std_logic;
pwm1_n : out std_logic
);
end entity pwm_wrapper;
architecture structure of pwm_wrapper is
component pwm is
generic(
pwm_bits : natural := 31
);
port(
clk : in std_logic;
resetn : in std_logic;
enable : in std_logic;
duty_cycle : in std_logic_vector(pwm_bits - 1 downto 0);
phase : in std_logic_vector(pwm_bits - 1 downto 0);
highimp : in std_logic;
pwm_out : out std_logic;
pwm_out_n: out std_logic
);
end component;
constant duty_cycle_1 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(1048576, 32));
constant phase_1 : std_logic_vector(31 downto 0) := (others => '0');
constant duty_cycle_0 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(1048576, 32));
constant phase_0 : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(1048576, 32));
begin
i_pwm_0: pwm
generic map(pwm_bits => 32)
port map(
clk => CLOCK_50,
resetn => KEY(0),
enable => '1',
duty_cycle => duty_cycle_0,
phase => phase_0,
highimp => KEY(1),
pwm_out => pwm0,
pwm_out_n => pwm0_n
);
i_pwm_1: pwm
generic map(pwm_bits => 32)
port map(
clk => CLOCK_50,
resetn => KEY(0),
enable => '1',
duty_cycle => duty_cycle_1,
phase => phase_1,
highimp => KEY(1),
pwm_out => pwm1,
pwm_out_n => pwm1_n
);
end architecture structure;
| mit | de410691b96d2cf502dd6b52f7f061a9 | 0.656168 | 2.486134 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_2/system_auto_us_2_sim_netlist.vhdl | 1 | 330,418 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:17:20 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_2/system_auto_us_2_sim_netlist.vhdl
-- Design : system_auto_us_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_axi_dwidth_converter_v2_1_11_w_upsizer is
port (
first_word_q : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]_0\ : out STD_LOGIC;
wstrb_wrap_buffer_1 : out STD_LOGIC;
wstrb_wrap_buffer_2 : out STD_LOGIC;
wstrb_wrap_buffer_3 : out STD_LOGIC;
wstrb_wrap_buffer_4 : out STD_LOGIC;
wstrb_wrap_buffer_5 : out STD_LOGIC;
wstrb_wrap_buffer_6 : out STD_LOGIC;
wstrb_wrap_buffer_7 : out STD_LOGIC;
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_buffer_available : out STD_LOGIC;
first_mi_word_q : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]_0\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]_0\ : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
pop_si_data : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_25_out26_out : in STD_LOGIC;
p_22_out : in STD_LOGIC;
p_17_out18_out : in STD_LOGIC;
p_14_out : in STD_LOGIC;
p_11_out : in STD_LOGIC;
p_8_out : in STD_LOGIC;
p_3_out4_out : in STD_LOGIC;
p_0_out : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : in STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_251_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\p_31_out__2\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\p_61_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\ : in STD_LOGIC;
\p_91_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\ : in STD_LOGIC;
\p_122_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\ : in STD_LOGIC;
\p_151_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\ : in STD_LOGIC;
\p_180_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\ : in STD_LOGIC;
\p_209_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\ : in STD_LOGIC;
\p_245_out__2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wr_cmd_valid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_axi_dwidth_converter_v2_1_11_w_upsizer : entity is "axi_dwidth_converter_v2_1_11_w_upsizer";
end system_auto_us_2_axi_dwidth_converter_v2_1_11_w_upsizer;
architecture STRUCTURE of system_auto_us_2_axi_dwidth_converter_v2_1_11_w_upsizer is
signal \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \^use_rtl_length.length_counter_q_reg[0]_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^use_rtl_length.length_counter_q_reg[2]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\ : STD_LOGIC;
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wstrb_wrap_buffer_q_reg[0]_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\ : STD_LOGIC;
signal \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word_q\ : STD_LOGIC;
signal \^m_axi_wlast\ : STD_LOGIC;
signal \^m_axi_wstrb\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_19_out : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_out : STD_LOGIC;
signal p_23_out : STD_LOGIC;
signal p_27_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \pop_mi_data__0\ : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_1\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_2\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_3\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_4\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_5\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_6\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_7\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WLAST_q_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2\ : label is "soft_lutpair3";
begin
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ <= \^use_rtl_length.length_counter_q_reg[0]_0\;
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0) <= \^use_rtl_length.length_counter_q_reg[1]_0\(1 downto 0);
\USE_RTL_LENGTH.length_counter_q_reg[2]_0\ <= \^use_rtl_length.length_counter_q_reg[2]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]_0\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wstrb_wrap_buffer_q_reg[0]_0\;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]_0\ <= \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\;
first_mi_word_q <= \^first_mi_word_q\;
first_word_q <= \^first_word_q\;
m_axi_wlast <= \^m_axi_wlast\;
m_axi_wstrb(7 downto 0) <= \^m_axi_wstrb\(7 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
wrap_buffer_available <= \^wrap_buffer_available\;
wstrb_wrap_buffer_1 <= \^wstrb_wrap_buffer_1\;
wstrb_wrap_buffer_2 <= \^wstrb_wrap_buffer_2\;
wstrb_wrap_buffer_3 <= \^wstrb_wrap_buffer_3\;
wstrb_wrap_buffer_4 <= \^wstrb_wrap_buffer_4\;
wstrb_wrap_buffer_5 <= \^wstrb_wrap_buffer_5\;
wstrb_wrap_buffer_6 <= \^wstrb_wrap_buffer_6\;
wstrb_wrap_buffer_7 <= \^wstrb_wrap_buffer_7\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0000000B0B00000"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
I2 => s_axi_wvalid,
I3 => \^wrap_buffer_available\,
I4 => wr_cmd_valid,
I5 => Q(8),
O => \USE_RTL_LENGTH.length_counter_q_reg[1]_1\
);
\USE_REGISTER.M_AXI_WLAST_q_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wlast,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \^m_axi_wlast\,
O => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\
);
\USE_REGISTER.M_AXI_WLAST_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\,
Q => \^m_axi_wlast\,
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_REGISTER.M_AXI_WVALID_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\,
Q => \^m_axi_wvalid\,
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.current_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.first_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => s_axi_wlast,
Q => \^first_word_q\,
S => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^first_word_q\,
I1 => Q(9),
O => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => D(0),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => D(1),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => pop_si_data,
D => D(2),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.first_mi_word_q_reg_0\,
Q => \^first_mi_word_q\,
S => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F70"
)
port map (
I0 => \^first_mi_word_q\,
I1 => Q(0),
I2 => p_251_in,
I3 => \^use_rtl_length.length_counter_q_reg[1]_0\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACCC5C3C"
)
port map (
I0 => Q(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => p_251_in,
I3 => \^first_mi_word_q\,
I4 => \^use_rtl_length.length_counter_q_reg[2]_0\,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[1]_0\(0),
I1 => Q(0),
I2 => \^use_rtl_length.length_counter_q_reg[1]_0\(1),
I3 => \^first_mi_word_q\,
I4 => Q(1),
O => \^use_rtl_length.length_counter_q_reg[2]_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D272D2"
)
port map (
I0 => p_251_in,
I1 => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => \^first_mi_word_q\,
I4 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => \^first_mi_word_q\,
I2 => Q(2),
I3 => \^use_rtl_length.length_counter_q_reg[2]_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACCC5C3C"
)
port map (
I0 => Q(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => p_251_in,
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFAEEEEFFFA"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[2]_0\,
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D272D2"
)
port map (
I0 => p_251_in,
I1 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I3 => \^first_mi_word_q\,
I4 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => \^first_mi_word_q\,
I2 => Q(4),
I3 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D272D2"
)
port map (
I0 => p_251_in,
I1 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I3 => \^first_mi_word_q\,
I4 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFAEEEEFFFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I1 => Q(4),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC5CCC3C"
)
port map (
I0 => Q(7),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I2 => p_251_in,
I3 => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\,
I4 => \^first_mi_word_q\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I2 => \^first_mi_word_q\,
I3 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \^use_rtl_length.length_counter_q_reg[1]_0\(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q_reg[0]_1\,
Q => \^use_rtl_length.length_counter_q_reg[1]_0\(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(1),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(1)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(2),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(2)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(3),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(3)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(4),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(4)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(5),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(5)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(6),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(6)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_245_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(7),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I3 => \p_245_out__2\,
O => p_1_in(7)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wstrb_wrap_buffer_q_reg[0]_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(0),
Q => m_axi_wdata(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(1),
Q => m_axi_wdata(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(2),
Q => m_axi_wdata(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(3),
Q => m_axi_wdata(3),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(4),
Q => m_axi_wdata(4),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(5),
Q => m_axi_wdata(5),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(6),
Q => m_axi_wdata(6),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0\,
D => p_1_in(7),
Q => m_axi_wdata(7),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(0),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\,
O => p_27_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_27_out,
Q => \^m_axi_wstrb\(0),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_25_out26_out,
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.wstrb_wrap_buffer_q_reg[0]_0\,
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(10),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(11),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(12),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(14),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_209_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(15),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_1\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(8),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(9),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I3 => \p_209_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\,
Q => m_axi_wdata(10),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\,
Q => m_axi_wdata(11),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\,
Q => m_axi_wdata(12),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\,
Q => m_axi_wdata(13),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\,
Q => m_axi_wdata(14),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\,
Q => m_axi_wdata(15),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\,
Q => m_axi_wdata(8),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\,
Q => m_axi_wdata(9),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(1),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\,
O => p_23_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_23_out,
Q => \^m_axi_wstrb\(1),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_22_out,
Q => \^wstrb_wrap_buffer_1\,
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(16),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(17),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(18),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(19),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(20),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(21),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(22),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_180_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(23),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I3 => \p_180_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\,
Q => m_axi_wdata(16),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\,
Q => m_axi_wdata(17),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\,
Q => m_axi_wdata(18),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\,
Q => m_axi_wdata(19),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\,
Q => m_axi_wdata(20),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\,
Q => m_axi_wdata(21),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\,
Q => m_axi_wdata(22),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\,
Q => m_axi_wdata(23),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(2),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\,
O => p_19_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_19_out,
Q => \^m_axi_wstrb\(2),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_17_out18_out,
Q => \^wstrb_wrap_buffer_2\,
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(24),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(25),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(26),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(27),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(28),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(29),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(30),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_151_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(31),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I3 => \p_151_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_3\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\,
Q => m_axi_wdata(24),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\,
Q => m_axi_wdata(25),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\,
Q => m_axi_wdata(26),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\,
Q => m_axi_wdata(27),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\,
Q => m_axi_wdata(28),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\,
Q => m_axi_wdata(29),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\,
Q => m_axi_wdata(30),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0\,
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\,
Q => m_axi_wdata(31),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(3),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\,
O => p_15_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_15_out,
Q => \^m_axi_wstrb\(3),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_14_out,
Q => \^wstrb_wrap_buffer_3\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(0),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(1),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(2),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(3),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(4),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(5),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(6),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_122_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(7),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I3 => \p_122_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_4\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\,
Q => m_axi_wdata(32),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\,
Q => m_axi_wdata(33),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\,
Q => m_axi_wdata(34),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\,
Q => m_axi_wdata(35),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\,
Q => m_axi_wdata(36),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\,
Q => m_axi_wdata(37),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\,
Q => m_axi_wdata(38),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\,
Q => m_axi_wdata(39),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(4),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\,
O => p_12_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_12_out,
Q => \^m_axi_wstrb\(4),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_11_out,
Q => \^wstrb_wrap_buffer_4\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(8),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(9),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(10),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(11),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(12),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(13),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(14),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_91_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(15),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I3 => \p_91_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_5\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\,
Q => m_axi_wdata(40),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\,
Q => m_axi_wdata(41),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\,
Q => m_axi_wdata(42),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\,
Q => m_axi_wdata(43),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\,
Q => m_axi_wdata(44),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\,
Q => m_axi_wdata(45),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\,
Q => m_axi_wdata(46),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\,
Q => m_axi_wdata(47),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(5),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\,
O => p_9_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_9_out,
Q => \^m_axi_wstrb\(5),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_8_out,
Q => \^wstrb_wrap_buffer_5\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(16),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(17),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(18),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(19),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(20),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(21),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(22),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_61_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(23),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I3 => \p_61_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_6\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\,
Q => m_axi_wdata(48),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\,
Q => m_axi_wdata(49),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\,
Q => m_axi_wdata(50),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\,
Q => m_axi_wdata(51),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\,
Q => m_axi_wdata(52),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\,
Q => m_axi_wdata(53),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\,
Q => m_axi_wdata(54),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\,
Q => m_axi_wdata(55),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_4_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(6),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\,
O => p_5_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_5_out,
Q => \^m_axi_wstrb\(6),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[53]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_3_out4_out,
Q => \^wstrb_wrap_buffer_6\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(24),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(25),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(26),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(27),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(28),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(29),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(30),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \out\,
O => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => \^first_mi_word_q\,
I4 => Q(3),
O => \USE_REGISTER.M_AXI_WVALID_q_reg_1\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => Q(4),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I3 => \^first_mi_word_q\,
I4 => Q(5),
O => \USE_REGISTER.M_AXI_WVALID_q_reg_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \p_31_out__2\,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAC0"
)
port map (
I0 => s_axi_wdata(31),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I3 => \p_31_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => pop_si_data,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\,
I2 => \^wrap_buffer_available\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\,
I4 => \^wstrb_wrap_buffer_7\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"1010101F"
)
port map (
I0 => Q(6),
I1 => Q(7),
I2 => \^first_mi_word_q\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\,
Q => m_axi_wdata(56),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\,
Q => m_axi_wdata(57),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\,
Q => m_axi_wdata(58),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\,
Q => m_axi_wdata(59),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\,
Q => m_axi_wdata(60),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\,
Q => m_axi_wdata(61),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\,
Q => m_axi_wdata(62),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0\,
Q => m_axi_wdata(63),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000BABA0000"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0\,
I1 => \pop_mi_data__0\,
I2 => \^m_axi_wstrb\(7),
I3 => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\,
I4 => \out\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\,
O => p_1_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
O => \pop_mi_data__0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D0000000D00000"
)
port map (
I0 => \^m_axi_wvalid\,
I1 => m_axi_wready,
I2 => s_axi_wvalid,
I3 => Q(8),
I4 => wr_cmd_valid,
I5 => \^wrap_buffer_available\,
O => \^word_lane[1].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wstrb_i_reg[7]_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_out,
Q => \^m_axi_wstrb\(7),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(0),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(1),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(2),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(3),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(4),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(5),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[62]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(6),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg\(7),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out,
Q => \^wstrb_wrap_buffer_7\,
R => '0'
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
Q => \^wrap_buffer_available\,
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_axi_register_slice_v2_1_11_axic_register_slice is
port (
sr_awvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 24 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\out\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_2_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_2_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 41 downto 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\ : STD_LOGIC;
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\ : STD_LOGIC;
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 24 downto 0 );
signal \m_axi_awaddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awlen[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[3]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[4]\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[5]\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_awlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal sr_awaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sr_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_awvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_axi_awaddr[0]_INST_0_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_awaddr[1]_INST_0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_axi_awaddr[1]_INST_0_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_3\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0_i_4\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_4\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_8\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_awburst[0]_INST_0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_axi_awburst[1]_INST_0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_axi_awlen[1]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_axi_awlen[2]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_axi_awlen[5]_INST_0_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_3\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_4\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_10\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_13\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_14\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_2\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_4\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0_i_6\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_axi_awsize[0]_INST_0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_axi_awsize[1]_INST_0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_axi_awsize[2]_INST_0\ : label is "soft_lutpair37";
begin
Q(41 downto 0) <= \^q\(41 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\;
\in\(24 downto 0) <= \^in\(24 downto 0);
s_axi_awready <= \^s_axi_awready\;
sr_awvalid <= \^sr_awvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAE"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => sr_awsize(2),
I4 => sr_awsize(1),
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAFEBA"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => sr_awsize(1),
I5 => sr_awsize(2),
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => sr_awaddr(2),
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"380038003800C800"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I1 => sr_awaddr(0),
I2 => s_axi_awlen_ii(0),
I3 => \^in\(8),
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414141141414144"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I2 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I3 => sr_awburst(1),
I4 => sr_awburst(0),
I5 => sr_awaddr(1),
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00100000FFFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_4_n_0\,
I2 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I3 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
I4 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I5 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000E00000000000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => sr_awaddr(0),
I3 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"03EFFC00FC0003EF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\,
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => sr_awaddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001010100"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(0),
I4 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
I5 => sr_awaddr(0),
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4441444144414444"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I1 => sr_awaddr(1),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => sr_awaddr(0),
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4015151515404040"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\,
I2 => sr_awaddr(1),
I3 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I4 => sr_awsize(1),
I5 => sr_awaddr(2),
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"000E"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000200020000"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(0),
I5 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awaddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awaddr(2),
I1 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
O => \^in\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(9)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '1',
Q => \aresetn_d_reg_n_0_[0]\,
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \aresetn_d_reg_n_0_[0]\,
Q => \aresetn_d_reg_n_0_[1]\,
R => SR(0)
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A2AAAAAA"
)
port map (
I0 => sr_awaddr(0),
I1 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(0),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(0)
);
\m_axi_awaddr[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
O => \m_axi_awaddr[0]_INST_0_i_1_n_0\
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"008A"
)
port map (
I0 => sr_awaddr(1),
I1 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF1B"
)
port map (
I0 => sr_awsize(0),
I1 => s_axi_awlen_ii(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[1]_INST_0_i_1_n_0\
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88008F00"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I3 => sr_awaddr(2),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awaddr(2)
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I3 => \m_axi_awaddr[2]_INST_0_i_4_n_0\,
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
O => \m_axi_awaddr[2]_INST_0_i_1_n_0\
);
\m_axi_awaddr[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I1 => \m_axi_awaddr[2]_INST_0_i_6_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\
);
\m_axi_awaddr[2]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0033557F"
)
port map (
I0 => sr_awsize(1),
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[2]_INST_0_i_3_n_0\
);
\m_axi_awaddr[2]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \m_axi_awaddr[2]_INST_0_i_4_n_0\
);
\m_axi_awaddr[2]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0A0C00000A0C"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => s_axi_awlen_ii(2),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[2]_INST_0_i_5_n_0\
);
\m_axi_awaddr[2]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAEFFFFFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(2),
I2 => \^in\(8),
I3 => \m_axi_awaddr[2]_INST_0_i_3_n_0\,
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \m_axi_awaddr[2]_INST_0_i_6_n_0\
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9AAAAAA999AAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[3]\,
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I5 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
O => m_axi_awaddr(3)
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(3),
O => \m_axi_awaddr[3]_INST_0_i_1_n_0\
);
\m_axi_awaddr[3]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"53"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(0),
O => \m_axi_awaddr[3]_INST_0_i_2_n_0\
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[4]\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_payload_i_reg_n_0_[3]\,
I3 => \m_axi_awaddr[4]_INST_0_i_1_n_0\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
O => m_axi_awaddr(4)
);
\m_axi_awaddr[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAA2A28AAAAAAA"
)
port map (
I0 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[4]_INST_0_i_1_n_0\
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA6AAAAAAA"
)
port map (
I0 => \m_payload_i_reg_n_0_[5]\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => \m_payload_i_reg_n_0_[3]\,
I4 => \m_payload_i_reg_n_0_[4]\,
I5 => \m_axi_awaddr[5]_INST_0_i_3_n_0\,
O => m_axi_awaddr(5)
);
\m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010101000"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I2 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I3 => sr_awaddr(2),
I4 => sr_awaddr(1),
I5 => sr_awaddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[26]\
);
\m_axi_awaddr[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => \^q\(30),
I1 => s_axi_awlen_ii(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \^in\(24),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\
);
\m_axi_awaddr[5]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"30233323"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => sr_awsize(2),
I3 => sr_awsize(1),
I4 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_3_n_0\
);
\m_axi_awaddr[5]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \m_axi_awaddr[5]_INST_0_i_4_n_0\
);
\m_axi_awaddr[5]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(2),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => \^q\(30),
O => \m_axi_awaddr[5]_INST_0_i_5_n_0\
);
\m_axi_awaddr[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => s_axi_awlen_ii(5),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(4),
I4 => s_axi_awlen_ii(7),
I5 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_6_n_0\
);
\m_axi_awaddr[5]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => s_axi_awlen_ii(7),
I2 => s_axi_awlen_ii(6),
I3 => s_axi_awlen_ii(4),
I4 => s_axi_awlen_ii(5),
O => \m_axi_awaddr[5]_INST_0_i_7_n_0\
);
\m_axi_awaddr[5]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000A000C"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
O => \m_axi_awaddr[5]_INST_0_i_8_n_0\
);
\m_axi_awaddr[5]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFAFAEECCEA88"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(1),
I5 => sr_awsize(2),
O => \m_axi_awaddr[5]_INST_0_i_9_n_0\
);
\m_axi_awburst[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awburst(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awburst(0)
);
\m_axi_awburst[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awburst(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[27]\,
O => m_axi_awburst(1)
);
\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9599"
)
port map (
I0 => \m_axi_awlen[0]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[0]_INST_0_i_2_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => s_axi_awlen_ii(0),
O => \^in\(0)
);
\m_axi_awlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF0000E000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I3 => sr_awaddr(2),
I4 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
O => \m_axi_awlen[0]_INST_0_i_1_n_0\
);
\m_axi_awlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"575F5757575F5F5F"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I1 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I2 => \m_axi_awlen[0]_INST_0_i_3_n_0\,
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[0]_INST_0_i_2_n_0\
);
\m_axi_awlen[0]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
O => \m_axi_awlen[0]_INST_0_i_3_n_0\
);
\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"959A"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => s_axi_awlen_ii(1),
O => \^in\(1)
);
\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1FF2E00"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I4 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
O => \^in\(2)
);
\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08880800F777F7FF"
)
port map (
I0 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I4 => s_axi_awlen_ii(1),
I5 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
O => \^in\(3)
);
\m_axi_awlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCDFCFDFFCDFFFD"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => sr_awsize(1),
I4 => s_axi_awlen_ii(3),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[3]_INST_0_i_1_n_0\
);
\m_axi_awlen[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I1 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
O => \^in\(4)
);
\m_axi_awlen[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFF00008000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
O => \^in\(5)
);
\m_axi_awlen[5]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003222"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I2 => sr_awaddr(2),
I3 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
O => \m_axi_awlen[5]_INST_0_i_1_n_0\
);
\m_axi_awlen[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"2E"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
O => \m_axi_awlen[5]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000DFFFFFFF"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I2 => \m_axi_awlen[6]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_1_n_0\,
O => \^in\(6)
);
\m_axi_awlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055004000000000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I2 => sr_awaddr(2),
I3 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I5 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
O => \m_axi_awlen[6]_INST_0_i_1_n_0\
);
\m_axi_awlen[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACACACACACACACA"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I3 => sr_awsize(1),
I4 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[6]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I1 => sr_awburst(1),
I2 => sr_awburst(0),
O => \m_axi_awlen[6]_INST_0_i_3_n_0\
);
\m_axi_awlen[6]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(0),
O => \m_axi_awlen[6]_INST_0_i_4_n_0\
);
\m_axi_awlen[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[7]_INST_0_i_3_n_0\,
I3 => \m_axi_awlen[7]_INST_0_i_4_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_5_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_6_n_0\,
O => \^in\(7)
);
\m_axi_awlen[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF3FFFF55555555"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(7),
I5 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => \m_axi_awlen[7]_INST_0_i_1_n_0\
);
\m_axi_awlen[7]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I3 => sr_awaddr(2),
O => \m_axi_awlen[7]_INST_0_i_10_n_0\
);
\m_axi_awlen[7]_INST_0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDD1111D1DD"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[7]_INST_0_i_13_n_0\,
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awlen[6]_INST_0_i_4_n_0\,
I5 => \m_axi_awlen[7]_INST_0_i_15_n_0\,
O => \m_axi_awlen[7]_INST_0_i_11_n_0\
);
\m_axi_awlen[7]_INST_0_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF3F3F5F5F0FF"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
I2 => sr_awsize(2),
I3 => s_axi_awlen_ii(6),
I4 => sr_awsize(1),
I5 => sr_awsize(0),
O => \m_axi_awlen[7]_INST_0_i_12_n_0\
);
\m_axi_awlen[7]_INST_0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
O => \m_axi_awlen[7]_INST_0_i_13_n_0\
);
\m_axi_awlen[7]_INST_0_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"03080008"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(6),
O => \m_axi_awlen[7]_INST_0_i_14_n_0\
);
\m_axi_awlen[7]_INST_0_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"3530353535353535"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[7]_INST_0_i_15_n_0\
);
\m_axi_awlen[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \m_axi_awlen[7]_INST_0_i_7_n_0\,
O => \m_axi_awlen[7]_INST_0_i_2_n_0\
);
\m_axi_awlen[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF5F7FFFFFFFF"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_2_n_0\,
I1 => \m_axi_awlen[7]_INST_0_i_8_n_0\,
I2 => \m_axi_awlen[7]_INST_0_i_9_n_0\,
I3 => \m_axi_awlen[7]_INST_0_i_10_n_0\,
I4 => \m_axi_awlen[7]_INST_0_i_11_n_0\,
I5 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
O => \m_axi_awlen[7]_INST_0_i_3_n_0\
);
\m_axi_awlen[7]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_12_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => s_axi_awlen_ii(3),
O => \m_axi_awlen[7]_INST_0_i_4_n_0\
);
\m_axi_awlen[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E222EEEEE222E222"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => \^in\(10),
I3 => s_axi_awlen_ii(6),
I4 => \m_axi_awlen[7]_INST_0_i_13_n_0\,
I5 => s_axi_awlen_ii(7),
O => \m_axi_awlen[7]_INST_0_i_5_n_0\
);
\m_axi_awlen[7]_INST_0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => \m_axi_awlen[7]_INST_0_i_6_n_0\
);
\m_axi_awlen[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBFBB"
)
port map (
I0 => \m_axi_awlen[7]_INST_0_i_14_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
I2 => sr_awsize(1),
I3 => s_axi_awlen_ii(7),
I4 => sr_awsize(0),
I5 => sr_awsize(2),
O => \m_axi_awlen[7]_INST_0_i_7_n_0\
);
\m_axi_awlen[7]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"08AE08AE08AE0808"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0\,
I1 => sr_awaddr(1),
I2 => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0\,
I3 => \m_axi_awaddr[1]_INST_0_i_1_n_0\,
I4 => sr_awburst(1),
I5 => sr_awburst(0),
O => \m_axi_awlen[7]_INST_0_i_8_n_0\
);
\m_axi_awlen[7]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFAFFFBFFFBFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_5_n_0\,
I2 => sr_awburst(1),
I3 => sr_awburst(0),
I4 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I5 => sr_awaddr(2),
O => \m_axi_awlen[7]_INST_0_i_9_n_0\
);
\m_axi_awsize[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(0),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(0)
);
\m_axi_awsize[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(1),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(1)
);
\m_axi_awsize[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => sr_awsize(2),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[28]\,
O => m_axi_awsize(2)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_awvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_awaddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_awaddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_awaddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_awsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_awsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_awsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_awburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_awburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => \m_payload_i_reg_n_0_[3]\,
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_awlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_awlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_awlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_awlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_awlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_awlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \m_payload_i_reg_n_0_[4]\,
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_awlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_awlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \m_payload_i_reg_n_0_[5]\,
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^q\(3),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2AAA00002AAA"
)
port map (
I0 => \aresetn_d_reg_n_0_[1]\,
I1 => cmd_push_block_reg,
I2 => m_axi_awready,
I3 => \out\,
I4 => \^s_axi_awready\,
I5 => s_axi_awvalid,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_awvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => \aresetn_d_reg_n_0_[1]\,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_reg\,
I3 => \^sr_awvalid\,
I4 => s_axi_awvalid,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_awready\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_generic_baseblocks_v2_1_0_command_fifo is
port (
\USE_RTL_CURR_WORD.first_word_q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
p_3_out4_out : out STD_LOGIC;
p_8_out : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_14_out : out STD_LOGIC;
p_17_out18_out : out STD_LOGIC;
p_22_out : out STD_LOGIC;
p_25_out26_out : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\p_31_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\p_61_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ : out STD_LOGIC;
\p_91_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ : out STD_LOGIC;
\p_122_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ : out STD_LOGIC;
\p_151_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\p_180_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\p_209_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\p_245_out__2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
pop_si_data : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_awvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wstrb_wrap_buffer_7 : in STD_LOGIC;
wstrb_wrap_buffer_6 : in STD_LOGIC;
wstrb_wrap_buffer_5 : in STD_LOGIC;
wstrb_wrap_buffer_4 : in STD_LOGIC;
wstrb_wrap_buffer_3 : in STD_LOGIC;
wstrb_wrap_buffer_2 : in STD_LOGIC;
wstrb_wrap_buffer_1 : in STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
first_mi_word_q : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : in STD_LOGIC;
first_word_q : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.first_word_q_reg_0\ : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_3\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_2_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_2_generic_baseblocks_v2_1_0_command_fifo is
signal M_READY_I : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\ : STD_LOGIC;
signal \^use_register.m_axi_wvalid_q_reg\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^use_rtl_curr_word.first_word_q_reg\ : STD_LOGIC;
signal \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[1]\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer_enabled__1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__6\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal wr_cmd_complete_wrap : STD_LOGIC;
signal wr_cmd_first_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_cmd_mask : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_cmd_modified : STD_LOGIC;
signal wr_cmd_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_cmd_offset : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_7\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.current_word_q[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.current_word_q[1]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.current_word_q[2]_i_1\ : label is "soft_lutpair8";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][16]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of s_ready_i_i_2 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of wrap_buffer_available_i_2 : label is "soft_lutpair10";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\USE_REGISTER.M_AXI_WVALID_q_reg\ <= \^use_register.m_axi_wvalid_q_reg\;
\USE_RTL_CURR_WORD.first_word_q_reg\ <= \^use_rtl_curr_word.first_word_q_reg\;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ <= \^use_rtl_length.length_counter_q_reg[1]\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => s_axi_wlast,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => \^use_rtl_curr_word.first_word_q_reg\,
O => M_READY_I
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAAAAAA8AAA8A"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I1 => \^q\(9),
I2 => wr_cmd_modified,
I3 => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\,
I4 => \^use_register.m_axi_wvalid_q_reg\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\,
O => \^use_rtl_length.length_counter_q_reg[1]\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => wr_cmd_mask(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => wr_cmd_mask(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => wr_cmd_mask(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q => wr_cmd_offset(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => cmd_last_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => cmd_last_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => wr_cmd_next_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => wr_cmd_next_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => wr_cmd_next_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => wr_cmd_first_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => wr_cmd_first_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => wr_cmd_first_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(8),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => wr_cmd_complete_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => wr_cmd_modified,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(9),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => M_READY_I,
D => data_Exists_I,
Q => \^use_rtl_curr_word.first_word_q_reg\,
R => SR(0)
);
\USE_REGISTER.M_AXI_WVALID_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer_enabled__1\,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => s_axi_wvalid,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__6\,
I4 => m_axi_wready,
I5 => \USE_REGISTER.M_AXI_WVALID_q_reg_3\,
O => \USE_REGISTER.M_AXI_WVALID_q_reg_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(8),
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => wrap_buffer_available,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer_enabled__1\
);
\USE_REGISTER.M_AXI_WVALID_q_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF2FF"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\,
I1 => \^use_register.m_axi_wvalid_q_reg\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\,
I3 => wr_cmd_modified,
I4 => \^q\(9),
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__6\
);
\USE_REGISTER.M_AXI_WVALID_q_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\,
I2 => wr_cmd_complete_wrap,
I3 => \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\,
O => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFFFF"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(2),
I4 => wr_cmd_mask(2),
O => \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFFFF"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(0),
I4 => wr_cmd_mask(0),
O => \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFFFF"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(1),
I4 => wr_cmd_mask(1),
O => \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB00040004FFFB"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => buffer_Full_q,
I3 => M_READY_I,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9A96AA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => valid_Write,
I4 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9AAA96AAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => valid_Write,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888838800000000"
)
port map (
I0 => data_Exists_I_i_2_n_0,
I1 => M_READY_I,
I2 => buffer_Full_q,
I3 => sr_awvalid,
I4 => cmd_push_block,
I5 => data_Exists_I,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I5 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFD5FFFF"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => s_axi_wlast,
I3 => buffer_Full_q,
I4 => sr_awvalid,
I5 => cmd_push_block,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => SR(0)
);
\USE_RTL_CURR_WORD.current_word_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(0),
I1 => wr_cmd_next_word(0),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
O => \USE_RTL_CURR_WORD.current_word_q_reg[2]\(0)
);
\USE_RTL_CURR_WORD.current_word_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(1),
I1 => wr_cmd_next_word(1),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
O => \USE_RTL_CURR_WORD.current_word_q_reg[2]\(1)
);
\USE_RTL_CURR_WORD.current_word_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(2),
I1 => wr_cmd_next_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2),
O => \USE_RTL_CURR_WORD.current_word_q_reg[2]\(2)
);
\USE_RTL_CURR_WORD.first_word_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A00080A0A0A0A0"
)
port map (
I0 => s_axi_wvalid,
I1 => \^q\(8),
I2 => \^use_rtl_curr_word.first_word_q_reg\,
I3 => wrap_buffer_available,
I4 => m_axi_wready,
I5 => \USE_REGISTER.M_AXI_WVALID_q_reg_3\,
O => pop_si_data
);
\USE_RTL_CURR_WORD.pre_next_word_q[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5556AAA600000000"
)
port map (
I0 => cmd_step(0),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_next_word(0),
I5 => wr_cmd_mask(0),
O => D(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A60000A9590000"
)
port map (
I0 => cmd_step(1),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
I2 => \USE_RTL_CURR_WORD.first_word_q_reg_0\,
I3 => wr_cmd_next_word(1),
I4 => wr_cmd_mask(1),
I5 => \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\,
O => D(1)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5557FFF7"
)
port map (
I0 => cmd_step(0),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(0),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_next_word(0),
O => \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9060909090606060"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2_n_0\,
I1 => cmd_step(2),
I2 => wr_cmd_mask(2),
I3 => wr_cmd_next_word(2),
I4 => \USE_RTL_CURR_WORD.first_word_q_reg_0\,
I5 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2),
O => D(2)
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDFDDD544454440"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\,
I1 => wr_cmd_next_word(1),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(1),
I5 => cmd_step(1),
O => \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => buffer_Full_q,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => s_axi_aclk,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wlast,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => first_mi_word_q,
O => \USE_RTL_LENGTH.first_mi_word_q_reg\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5A0DD225F0ADD22"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[1]\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg[1]_1\(0),
I2 => \^q\(0),
I3 => \USE_RTL_LENGTH.length_counter_q_reg[1]_1\(1),
I4 => first_mi_word_q,
I5 => \^q\(1),
O => \USE_RTL_LENGTH.length_counter_q_reg[1]_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00200000"
)
port map (
I0 => sr_awvalid,
I1 => cmd_push_block,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I3 => M_READY_I,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"2020F020"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_245_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002220222A"
)
port map (
I0 => s_axi_wstrb(0),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(0),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => E(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF080000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(0),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\,
I4 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
O => p_25_out26_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => wrap_buffer_available,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^q\(8),
I3 => s_axi_wvalid,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEAAAE"
)
port map (
I0 => wr_cmd_offset(2),
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_first_word(2),
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F00"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => s_axi_wlast,
I3 => \out\,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"2020F020"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_209_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002220222A"
)
port map (
I0 => s_axi_wstrb(1),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(1),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF000800"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(1),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_1,
O => p_22_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"2020F020"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_180_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002220222A"
)
port map (
I0 => s_axi_wstrb(2),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(2),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF000800"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(2),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_2,
O => p_17_out18_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"2020F020"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_151_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002220222A"
)
port map (
I0 => s_axi_wstrb(3),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(3),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF000800"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(3),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_3,
O => p_14_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_122_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA888A8880"
)
port map (
I0 => s_axi_wstrb(0),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[39]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(0),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(0),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_4,
O => p_11_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_91_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA888A8880"
)
port map (
I0 => s_axi_wstrb(1),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[47]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(1),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(1),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_5,
O => p_8_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_61_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA888A8880"
)
port map (
I0 => s_axi_wstrb(2),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[55]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(2),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(2),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_6,
O => p_3_out4_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"5556AAA6"
)
port map (
I0 => cmd_last_word(1),
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(1),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_first_word(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \p_31_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\,
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9_n_0\,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
I5 => \USE_RTL_LENGTH.length_counter_q_reg[4]\,
O => \^use_register.m_axi_wvalid_q_reg\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"7D7D7D777D7D7DDD"
)
port map (
I0 => wr_cmd_modified,
I1 => cmd_last_word(0),
I2 => wr_cmd_first_word(0),
I3 => first_word_q,
I4 => \^q\(9),
I5 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"5556AAA6"
)
port map (
I0 => cmd_last_word(2),
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_first_word(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA888A8880"
)
port map (
I0 => s_axi_wstrb(3),
I1 => wr_cmd_first_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2),
I5 => wr_cmd_offset(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[63]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I1 => s_axi_wstrb(3),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(3),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_1_in\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_215_in\,
I4 => wstrb_wrap_buffer_7,
O => p_0_out
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => m_axi_awready,
I1 => sr_awvalid,
I2 => buffer_Full_q,
I3 => cmd_push_block,
O => cmd_push_block0
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000055750030"
)
port map (
I0 => M_READY_I,
I1 => buffer_Full_q,
I2 => sr_awvalid,
I3 => cmd_push_block,
I4 => data_Exists_I,
I5 => data_Exists_I_i_2_n_0,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => SR(0)
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_awvalid,
O => m_axi_awvalid
);
m_valid_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
O => m_valid_i_reg
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F2FF0000"
)
port map (
I0 => \^q\(8),
I1 => wrap_buffer_available,
I2 => m_axi_wready,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_3\,
I4 => \^use_rtl_curr_word.first_word_q_reg\,
O => s_axi_wready
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"77F7"
)
port map (
I0 => \out\,
I1 => m_axi_awready,
I2 => buffer_Full_q,
I3 => cmd_push_block,
O => s_ready_i_reg
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFAAAA"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^use_rtl_length.length_counter_q_reg[1]\,
I3 => s_axi_wlast,
I4 => wrap_buffer_available,
O => wrap_buffer_available_reg
);
wrap_buffer_available_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_axi_wvalid,
I1 => \^q\(8),
I2 => \^use_rtl_curr_word.first_word_q_reg\,
I3 => wrap_buffer_available,
I4 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__6\,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
wr_cmd_valid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_251_in : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
p_3_out4_out : out STD_LOGIC;
p_8_out : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_14_out : out STD_LOGIC;
p_17_out18_out : out STD_LOGIC;
p_22_out : out STD_LOGIC;
p_25_out26_out : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\p_31_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\p_61_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ : out STD_LOGIC;
\p_91_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ : out STD_LOGIC;
\p_122_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ : out STD_LOGIC;
\p_151_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\p_180_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\p_209_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\p_245_out__2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
pop_si_data : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
sr_awvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wstrb_wrap_buffer_7 : in STD_LOGIC;
wstrb_wrap_buffer_6 : in STD_LOGIC;
wstrb_wrap_buffer_5 : in STD_LOGIC;
wstrb_wrap_buffer_4 : in STD_LOGIC;
wstrb_wrap_buffer_3 : in STD_LOGIC;
wstrb_wrap_buffer_2 : in STD_LOGIC;
wstrb_wrap_buffer_1 : in STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
first_mi_word_q : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : in STD_LOGIC;
first_word_q : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_RTL_CURR_WORD.first_word_q_reg\ : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_3\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_2_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_2_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_2_generic_baseblocks_v2_1_0_command_fifo
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_REGISTER.M_AXI_WVALID_q_reg\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
\USE_REGISTER.M_AXI_WVALID_q_reg_3\ => \USE_REGISTER.M_AXI_WVALID_q_reg_3\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0),
\USE_RTL_CURR_WORD.first_word_q_reg\ => wr_cmd_valid,
\USE_RTL_CURR_WORD.first_word_q_reg_0\ => \USE_RTL_CURR_WORD.first_word_q_reg\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0) => \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => p_251_in,
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\(1 downto 0) => \USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0),
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_RTL_LENGTH.length_counter_q_reg[4]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0),
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
first_mi_word_q => first_mi_word_q,
first_word_q => first_word_q,
\in\(27 downto 0) => \in\(27 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
m_valid_i_reg => m_valid_i_reg,
\out\ => \out\,
p_0_out => p_0_out,
p_11_out => p_11_out,
\p_122_out__2\ => \p_122_out__2\,
p_14_out => p_14_out,
\p_151_out__2\ => \p_151_out__2\,
p_17_out18_out => p_17_out18_out,
\p_180_out__2\ => \p_180_out__2\,
\p_209_out__2\ => \p_209_out__2\,
p_22_out => p_22_out,
\p_245_out__2\ => \p_245_out__2\,
p_25_out26_out => p_25_out26_out,
\p_31_out__2\ => \p_31_out__2\,
p_3_out4_out => p_3_out4_out,
\p_61_out__2\ => \p_61_out__2\,
p_8_out => p_8_out,
\p_91_out__2\ => \p_91_out__2\,
pop_si_data => pop_si_data,
s_axi_aclk => s_axi_aclk,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => s_ready_i_reg,
sr_awvalid => sr_awvalid,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg,
wstrb_wrap_buffer_1 => wstrb_wrap_buffer_1,
wstrb_wrap_buffer_2 => wstrb_wrap_buffer_2,
wstrb_wrap_buffer_3 => wstrb_wrap_buffer_3,
wstrb_wrap_buffer_4 => wstrb_wrap_buffer_4,
wstrb_wrap_buffer_5 => wstrb_wrap_buffer_5,
wstrb_wrap_buffer_6 => wstrb_wrap_buffer_6,
wstrb_wrap_buffer_7 => wstrb_wrap_buffer_7
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_axi_register_slice_v2_1_11_axi_register_slice is
port (
sr_awvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\out\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_2_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_2_axi_register_slice_v2_1_11_axi_register_slice is
begin
aw_pipe: entity work.system_auto_us_2_axi_register_slice_v2_1_11_axic_register_slice
port map (
D(60 downto 0) => D(60 downto 0),
Q(41 downto 0) => Q(41 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\ => \in\(24),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\ => \in\(25),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \in\(26),
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ => \USE_RTL_VALID_WRITE.buffer_Full_q_reg\,
cmd_push_block_reg => cmd_push_block_reg,
\in\(24) => \in\(27),
\in\(23 downto 0) => \in\(23 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
\out\ => \out\,
s_axi_aclk => s_axi_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_wvalid : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wlast : out STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_2_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_2_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_2\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_24\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_27\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_28\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_29\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_30\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_10\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_21\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_22\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_3\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_30\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_31\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_34\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_37\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_4\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_40\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_43\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_46\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_49\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_5\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_52\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_55\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_57\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_58\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_59\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_6\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_60\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_7\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_8\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_9\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_modified_i : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal current_word_q : STD_LOGIC_VECTOR ( 2 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word_q : STD_LOGIC;
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal \p_122_out__2\ : STD_LOGIC;
signal p_131_out : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal \p_151_out__2\ : STD_LOGIC;
signal p_160_out : STD_LOGIC;
signal p_17_out18_out : STD_LOGIC;
signal \p_180_out__2\ : STD_LOGIC;
signal p_189_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 22 downto 16 );
signal \p_209_out__2\ : STD_LOGIC;
signal p_222_out : STD_LOGIC;
signal p_22_out : STD_LOGIC;
signal \p_245_out__2\ : STD_LOGIC;
signal p_251_in : STD_LOGIC;
signal p_25_out26_out : STD_LOGIC;
signal \p_31_out__2\ : STD_LOGIC;
signal p_3_out4_out : STD_LOGIC;
signal p_41_out : STD_LOGIC;
signal \p_61_out__2\ : STD_LOGIC;
signal p_71_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal \p_91_out__2\ : STD_LOGIC;
signal pop_si_data : STD_LOGIC;
signal pre_next_word : STD_LOGIC_VECTOR ( 2 downto 0 );
signal pre_next_word_q : STD_LOGIC_VECTOR ( 2 downto 0 );
signal si_register_slice_inst_n_60 : STD_LOGIC;
signal si_register_slice_inst_n_61 : STD_LOGIC;
signal si_register_slice_inst_n_62 : STD_LOGIC;
signal si_register_slice_inst_n_63 : STD_LOGIC;
signal si_register_slice_inst_n_64 : STD_LOGIC;
signal si_register_slice_inst_n_65 : STD_LOGIC;
signal sr_awvalid : STD_LOGIC;
signal wdata_wrap_buffer_q : STD_LOGIC;
signal wr_cmd_fix : STD_LOGIC;
signal wr_cmd_packed_wrap : STD_LOGIC;
signal wr_cmd_valid : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
signal wstrb_wrap_buffer_1 : STD_LOGIC;
signal wstrb_wrap_buffer_2 : STD_LOGIC;
signal wstrb_wrap_buffer_3 : STD_LOGIC;
signal wstrb_wrap_buffer_4 : STD_LOGIC;
signal wstrb_wrap_buffer_5 : STD_LOGIC;
signal wstrb_wrap_buffer_6 : STD_LOGIC;
signal wstrb_wrap_buffer_7 : STD_LOGIC;
begin
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(7 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst\: entity work.system_auto_us_2_axi_dwidth_converter_v2_1_11_w_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => p_222_out,
Q(9) => wr_cmd_fix,
Q(8) => wr_cmd_packed_wrap,
Q(7) => \USE_WRITE.write_addr_inst_n_3\,
Q(6) => \USE_WRITE.write_addr_inst_n_4\,
Q(5) => \USE_WRITE.write_addr_inst_n_5\,
Q(4) => \USE_WRITE.write_addr_inst_n_6\,
Q(3) => \USE_WRITE.write_addr_inst_n_7\,
Q(2) => \USE_WRITE.write_addr_inst_n_8\,
Q(1) => \USE_WRITE.write_addr_inst_n_9\,
Q(0) => \USE_WRITE.write_addr_inst_n_10\,
SR(0) => wdata_wrap_buffer_q,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(2 downto 0) => next_word(2 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\ => \USE_WRITE.write_addr_inst_n_31\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0\ => \USE_WRITE.write_addr_inst_n_34\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1\ => \USE_WRITE.write_addr_inst_n_37\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2\ => \USE_WRITE.write_addr_inst_n_40\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3\ => \USE_WRITE.write_addr_inst_n_43\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4\ => \USE_WRITE.write_addr_inst_n_46\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5\ => \USE_WRITE.write_addr_inst_n_49\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6\ => \USE_WRITE.write_addr_inst_n_52\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\(0) => p_189_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_0\(0) => p_160_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_1\(0) => p_131_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_2\(0) => p_102_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_3\(0) => p_71_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_4\(0) => p_41_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]_5\(0) => \USE_WRITE.write_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\ => \USE_WRITE.write_addr_inst_n_22\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_WRITE.write_addr_inst_n_58\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_WRITE.write_addr_inst_n_59\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_27\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_28\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => pre_next_word_q(2 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_29\,
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_WRITE.write_addr_inst_n_60\,
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\USE_RTL_LENGTH.length_counter_q_reg[0]_1\ => \USE_WRITE.write_addr_inst_n_21\,
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0) => \USE_RTL_LENGTH.length_counter_q_reg\(1 downto 0),
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_30\,
\USE_RTL_LENGTH.length_counter_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_24\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(2 downto 0) => current_word_q(2 downto 0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_2\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\,
first_mi_word_q => first_mi_word_q,
first_word_q => first_word_q,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => \^m_axi_wvalid\,
\out\ => \out\,
p_0_out => p_0_out,
p_11_out => p_11_out,
\p_122_out__2\ => \p_122_out__2\,
p_14_out => p_14_out,
\p_151_out__2\ => \p_151_out__2\,
p_17_out18_out => p_17_out18_out,
\p_180_out__2\ => \p_180_out__2\,
\p_209_out__2\ => \p_209_out__2\,
p_22_out => p_22_out,
\p_245_out__2\ => \p_245_out__2\,
p_251_in => p_251_in,
p_25_out26_out => p_25_out26_out,
\p_31_out__2\ => \p_31_out__2\,
p_3_out4_out => p_3_out4_out,
\p_61_out__2\ => \p_61_out__2\,
p_8_out => p_8_out,
\p_91_out__2\ => \p_91_out__2\,
pop_si_data => pop_si_data,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available,
wstrb_wrap_buffer_1 => wstrb_wrap_buffer_1,
wstrb_wrap_buffer_2 => wstrb_wrap_buffer_2,
wstrb_wrap_buffer_3 => wstrb_wrap_buffer_3,
wstrb_wrap_buffer_4 => wstrb_wrap_buffer_4,
wstrb_wrap_buffer_5 => wstrb_wrap_buffer_5,
wstrb_wrap_buffer_6 => wstrb_wrap_buffer_6,
wstrb_wrap_buffer_7 => wstrb_wrap_buffer_7
);
\USE_WRITE.write_addr_inst\: entity work.system_auto_us_2_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
D(2 downto 0) => pre_next_word(2 downto 0),
E(0) => p_222_out,
Q(9) => wr_cmd_fix,
Q(8) => wr_cmd_packed_wrap,
Q(7) => \USE_WRITE.write_addr_inst_n_3\,
Q(6) => \USE_WRITE.write_addr_inst_n_4\,
Q(5) => \USE_WRITE.write_addr_inst_n_5\,
Q(4) => \USE_WRITE.write_addr_inst_n_6\,
Q(3) => \USE_WRITE.write_addr_inst_n_7\,
Q(2) => \USE_WRITE.write_addr_inst_n_8\,
Q(1) => \USE_WRITE.write_addr_inst_n_9\,
Q(0) => \USE_WRITE.write_addr_inst_n_10\,
SR(0) => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_24\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_WRITE.write_addr_inst_n_22\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_WRITE.write_addr_inst_n_59\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_30\,
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26\,
\USE_REGISTER.M_AXI_WVALID_q_reg_3\ => \^m_axi_wvalid\,
\USE_RTL_CURR_WORD.current_word_q_reg[2]\(2 downto 0) => next_word(2 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0\(2 downto 0) => current_word_q(2 downto 0),
\USE_RTL_CURR_WORD.first_word_q_reg\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_29\,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\(2 downto 0) => pre_next_word_q(2 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_WRITE.write_addr_inst_n_60\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25\,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_WRITE.write_addr_inst_n_21\,
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0) => \USE_RTL_LENGTH.length_counter_q_reg\(1 downto 0),
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_28\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_27\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \USE_WRITE.write_addr_inst_n_52\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => wdata_wrap_buffer_q,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_2\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \USE_WRITE.write_addr_inst_n_49\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => p_189_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \USE_WRITE.write_addr_inst_n_46\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => p_160_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \USE_WRITE.write_addr_inst_n_43\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => p_131_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\ => \USE_WRITE.write_addr_inst_n_40\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => p_102_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\ => \USE_WRITE.write_addr_inst_n_37\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => p_71_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\ => \USE_WRITE.write_addr_inst_n_34\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => p_41_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \USE_WRITE.write_addr_inst_n_31\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \USE_WRITE.write_addr_inst_n_30\,
first_mi_word_q => first_mi_word_q,
first_word_q => first_word_q,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_60,
\in\(12) => si_register_slice_inst_n_61,
\in\(11) => si_register_slice_inst_n_62,
\in\(10) => si_register_slice_inst_n_63,
\in\(9) => si_register_slice_inst_n_64,
\in\(8) => si_register_slice_inst_n_65,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
m_valid_i_reg => \USE_WRITE.write_addr_inst_n_57\,
\out\ => \out\,
p_0_out => p_0_out,
p_11_out => p_11_out,
\p_122_out__2\ => \p_122_out__2\,
p_14_out => p_14_out,
\p_151_out__2\ => \p_151_out__2\,
p_17_out18_out => p_17_out18_out,
\p_180_out__2\ => \p_180_out__2\,
\p_209_out__2\ => \p_209_out__2\,
p_22_out => p_22_out,
\p_245_out__2\ => \p_245_out__2\,
p_251_in => p_251_in,
p_25_out26_out => p_25_out26_out,
\p_31_out__2\ => \p_31_out__2\,
p_3_out4_out => p_3_out4_out,
\p_61_out__2\ => \p_61_out__2\,
p_8_out => p_8_out,
\p_91_out__2\ => \p_91_out__2\,
pop_si_data => pop_si_data,
s_axi_aclk => s_axi_aclk,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => \USE_WRITE.write_addr_inst_n_55\,
sr_awvalid => sr_awvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => \USE_WRITE.write_addr_inst_n_58\,
wstrb_wrap_buffer_1 => wstrb_wrap_buffer_1,
wstrb_wrap_buffer_2 => wstrb_wrap_buffer_2,
wstrb_wrap_buffer_3 => wstrb_wrap_buffer_3,
wstrb_wrap_buffer_4 => wstrb_wrap_buffer_4,
wstrb_wrap_buffer_5 => wstrb_wrap_buffer_5,
wstrb_wrap_buffer_6 => wstrb_wrap_buffer_6,
wstrb_wrap_buffer_7 => wstrb_wrap_buffer_7
);
si_register_slice_inst: entity work.system_auto_us_2_axi_register_slice_v2_1_11_axi_register_slice
port map (
D(60 downto 0) => D(60 downto 0),
Q(41 downto 0) => Q(41 downto 0),
SR(0) => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ => \USE_WRITE.write_addr_inst_n_55\,
cmd_push_block_reg => \USE_WRITE.write_addr_inst_n_57\,
\in\(27) => cmd_fix_i,
\in\(26) => cmd_modified_i,
\in\(25) => cmd_complete_wrap_i,
\in\(24) => cmd_packed_wrap_i,
\in\(23 downto 21) => cmd_first_word_i(2 downto 0),
\in\(20 downto 14) => p_1_out(22 downto 16),
\in\(13) => si_register_slice_inst_n_60,
\in\(12) => si_register_slice_inst_n_61,
\in\(11) => si_register_slice_inst_n_62,
\in\(10) => si_register_slice_inst_n_63,
\in\(9) => si_register_slice_inst_n_64,
\in\(8) => si_register_slice_inst_n_65,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
\out\ => \out\,
s_axi_aclk => s_axi_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_2_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_2_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_2_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
begin
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^s_axi_bready\ <= s_axi_bready;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_2_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_awregion(3 downto 0),
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52) => s_axi_awlock(0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 40) => s_axi_awcache(3 downto 0),
D(39 downto 38) => s_axi_awburst(1 downto 0),
D(37 downto 35) => s_axi_awsize(2 downto 0),
D(34 downto 32) => s_axi_awprot(2 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
Q(41 downto 38) => m_axi_awregion(3 downto 0),
Q(37 downto 34) => m_axi_awqos(3 downto 0),
Q(33) => m_axi_awlock(0),
Q(32 downto 29) => m_axi_awcache(3 downto 0),
Q(28 downto 26) => m_axi_awprot(2 downto 0),
Q(25 downto 0) => m_axi_awaddr(31 downto 6),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => m_axi_wvalid,
\out\ => s_axi_aresetn,
s_axi_aclk => s_axi_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_2 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_2 : entity is "system_auto_us_2,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_2 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_2 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_2;
architecture STRUCTURE of system_auto_us_2 is
signal NLW_inst_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 3;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 64;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_2_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => NLW_inst_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_inst_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_arvalid => NLW_inst_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rlast => '1',
m_axi_rready => NLW_inst_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"01",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_inst_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => NLW_inst_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_inst_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_inst_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 4bbe9311c0e8e24478c21878b2564495 | 0.597794 | 2.498378 | false | false | false | false |
loa-org/loa-hdl | modules/utils/tb/fractional_clock_divider_tb.vhd | 1 | 523 |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity fractional_clock_divider_tb is
end fractional_clock_divider_tb;
architecture tb of fractional_clock_divider_tb is
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : fractional_clock_divider
generic map (
MUL => 41,
DIV => 31250,
WIDTH => 16 )
port map(
clk_out_p => output,
clk => clk);
end tb;
| bsd-3-clause | 8c9fec02c66efbd7350158afeba14d72 | 0.590822 | 3.533784 | false | false | false | false |
pgavin/carpe | hdl/sys/sys_pkg.vhdl | 1 | 3,590 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use util.numeric_pkg.all;
use work.sys_config_pkg.all;
package sys_pkg is
constant sys_bus_bytes : natural := 2**sys_log2_bus_bytes;
constant sys_bus_bits : natural := sys_bus_bytes*byte_bits;
constant sys_transfer_size_bits : natural := bitsize(sys_log2_bus_bytes);
constant sys_max_burst_cycles : natural := 2**sys_log2_max_burst_cycles;
constant sys_burst_cycles_bits : natural := bitsize(sys_log2_max_burst_cycles);
subtype sys_paddr_type is std_ulogic_vector(sys_paddr_bits-1 downto 0);
subtype sys_bus_bytes_type is std_ulogic_vector2(sys_bus_bytes-1 downto 0, byte_bits-1 downto 0);
subtype sys_bus_type is std_ulogic_vector(sys_bus_bits-1 downto 0);
subtype sys_transfer_size_type is std_ulogic_vector(sys_transfer_size_bits-1 downto 0);
subtype sys_burst_cycles_type is std_ulogic_vector(sys_burst_cycles_bits-1 downto 0);
type sys_master_ctrl_out_type is record
-- a request is being made
request : std_ulogic;
-- big endian if true, otherwise little endian
be : std_ulogic;
-- this request is a write
write : std_ulogic;
-- this request is cacheable
cacheable : std_ulogic;
-- this request is privileged
priv : std_ulogic;
-- this request is for an instruction
inst : std_ulogic;
-- this request is part of a burst, but not the last request
burst : std_ulogic;
-- wrapping burst
bwrap : std_ulogic;
-- size of burst
bcycles : sys_burst_cycles_type;
end record;
type sys_master_dp_out_type is record
size : sys_transfer_size_type;
paddr : sys_paddr_type;
data : sys_bus_type;
end record;
type sys_slave_ctrl_out_type is record
ready : std_ulogic;
error : std_ulogic;
end record;
type sys_slave_dp_out_type is record
data : sys_bus_type;
end record;
type sys_master_ctrl_out_vector_type is array(natural range <>) of sys_master_ctrl_out_type;
type sys_master_dp_out_vector_type is array(natural range <>) of sys_master_dp_out_type;
type sys_slave_ctrl_out_vector_type is array(natural range <>) of sys_slave_ctrl_out_type;
type sys_slave_dp_out_vector_type is array(natural range <>) of sys_slave_dp_out_type;
end package;
| apache-2.0 | a004e2a286678e8b8f945669774e370c | 0.6 | 3.885281 | false | false | false | false |
loa-org/loa-hdl | modules/utils/hdl/fractional_clock_divider.vhd | 1 | 1,852 | -------------------------------------------------------------------------------
-- Title : Generic clock divider
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-- Generates a clock enable signal.
--
-- MUL must be smaller than DIV.
--
-- Example:
-- @code
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- ... do something with the period of the divided frequency ...
-- end if;
-- end if;
-- end process;
-- @endcode
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fractional_clock_divider is
generic (
DIV : positive := 1;
MUL : positive := 1;
WIDTH : positive
);
port (
clk_out_p : out std_logic;
clk : in std_logic
);
end fractional_clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of fractional_clock_divider is
signal cnt : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
-- report "div: " & integer'image(DIV);
if unsigned(cnt) >= to_unsigned(DIV, WIDTH) then
clk_out_p <= '1';
cnt <= std_logic_vector(unsigned(cnt) - DIV);
else
clk_out_p <= '0';
cnt <= std_logic_vector(unsigned(cnt) + MUL);
end if;
end if;
end process;
end behavior;
| bsd-3-clause | 2deeb07ee21e64fbc910376284b517eb | 0.428726 | 4.190045 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ad7266/tb/adc_ad7266_single_ended_tb.vhd | 2 | 5,508 | -------------------------------------------------------------------------------
-- Title : Testbench for design "adc_ad7266_single_ended"
-- Project :
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.adc_ad7266_pkg.all;
-------------------------------------------------------------------------------
entity adc_ad7266_single_ended_tb is
end adc_ad7266_single_ended_tb;
-------------------------------------------------------------------------------
architecture tb of adc_ad7266_single_ended_tb is
component adc_ad7266_single_ended
generic (
DELAY : natural);
port (
adc_out : out adc_ad7266_spi_out_type;
adc_in : in adc_ad7266_spi_in_type;
start_p : in std_logic;
adc_mode_p : in std_logic;
channel_p : in std_logic_vector(2 downto 0);
value_a_p : out std_logic_vector(11 downto 0);
value_b_p : out std_logic_vector(11 downto 0);
done_p : out std_logic;
clk : in std_logic);
end component;
-- component generics
constant DELAY : natural := 1;
-- component ports
signal adc_out : adc_ad7266_spi_out_type;
signal adc_in : adc_ad7266_spi_in_type;
signal start_p : std_logic := '0';
signal adc_mode_p : std_logic := '0';
signal channel_p : std_logic_vector(2 downto 0) := "000";
signal value_a_p : std_logic_vector(11 downto 0) := (others => '0');
signal value_b_p : std_logic_vector(11 downto 0) := (others => '0');
signal done_p : std_logic := '0';
-- clock
signal Clk : std_logic := '1';
-- adc_stimulus parametres (vectors are mirrored)
constant bitstream_a : std_logic_vector(11 downto 0) := "111000111001"; -- result 0x9C7
constant bitstream_b : std_logic_vector(11 downto 0) := "010111100110"; -- result 0x67A
signal bitcounter : integer range 0 to 16;
begin -- tb
-- component instantiation
DUT : adc_ad7266_single_ended
generic map (
DELAY => DELAY)
port map (
adc_out => adc_out,
adc_in => adc_in,
start_p => start_p,
adc_mode_p => adc_mode_p,
channel_p => channel_p,
value_a_p => value_a_p,
value_b_p => value_b_p,
done_p => done_p,
clk => clk);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- clock generation
Clk <= not Clk after 20 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
start_p <= '0';
adc_mode_p <= '1';
channel_p <= "011";
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
start_p <= '1';
wait until Clk = '1';
start_p <= '0';
wait until Clk = '1';
wait until done_p = '1';
wait until done_p = '0';
wait for 1 us;
start_p <= '1';
wait until Clk = '1';
start_p <= '0';
wait until Clk = '1';
wait for 1 ms;
end process WaveGen_Proc;
-------------------------------------------------------------------------------
-- ADC stimulus
----------------------------------------------------------------------------
-- change input Data
Input_stimulus : process
begin
wait for 200 us;
-- bitstream_a <= "111000111010";
-- bitstream_b <= "111000111011";
wait for 300 us;
-- bitstream_a <= "111000111100";
-- bitstream_b <= "111000111101";
end process Input_stimulus;
ADC_stimulus : process(adc_out.sck, adc_out.cs_n)
-- bitstream with second leading and two trailing zeros
-- DUT should set cs_n HIGH bevor trailing zeros are read in
variable v_bitstream_a : std_logic_vector(14 downto 0) := '0' & bitstream_a(11 downto 0) & "00";
variable v_bitstream_b : std_logic_vector(14 downto 0) := '0' & bitstream_b(11 downto 0) & "00";
variable vbitcounter : integer range 0 to 16 := bitcounter;
begin
if falling_edge(adc_out.cs_n) then
-- first leading zero
adc_in.d_a <= '0';
adc_in.d_b <= '0';
-- reset bitcounter
vbitcounter := 0;
elsif adc_out.cs_n = '0' then
if vbitcounter < 15 then
if falling_edge(adc_out.sck) then
vbitcounter := vbitcounter + 1;
adc_in.d_a <= v_bitstream_a(vbitcounter);
adc_in.d_b <= v_bitstream_b(vbitcounter);
end if;
end if;
else
adc_in.d_a <= 'Z';
adc_in.d_b <= 'Z';
end if;
bitcounter <= vbitcounter;
end process ADC_stimulus;
end tb;
-------------------------------------------------------------------------------
configuration adc_ad7266_single_ended_tb_tb_cfg of adc_ad7266_single_ended_tb is
for tb
end for;
end adc_ad7266_single_ended_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | 3fd2af152d8f14d25040680d1f8d35be | 0.448439 | 4.047024 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 23,352 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Tue Jun 06 02:30:20 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
apply : in STD_LOGIC;
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
state : out STD_LOGIC_VECTOR ( 1 downto 0 );
transform : in STD_LOGIC;
transform_led : out STD_LOGIC;
trigger : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=27,numReposBlks=27,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_vga_buffer_1_1 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_1_1;
component system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_overlay_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_xlconstant_0_3 is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_xlconstant_0_3;
component system_vga_transform_0_1 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_transform_0_1;
component system_rgb888_to_g8_1_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_1_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_c_addsub_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_c_addsub_0_0;
component system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_0_0;
component system_vga_hessian_1_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_1_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_feature_transform_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
vsync : in STD_LOGIC;
x_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_0 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_1 : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
rot_m00 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : out STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : out STD_LOGIC_VECTOR ( 9 downto 0 );
state : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_vga_feature_transform_0_0;
component system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_0_0;
component system_buffer_register_1_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_1_0;
component system_util_ds_buf_0_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_ds_buf_0_0;
component system_util_ds_buf_1_0 is
port (
BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_ds_buf_1_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal buffer_register_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffer_register_1_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal c_addsub_0_S : STD_LOGIC_VECTOR ( 9 downto 0 );
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_1_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal hsync_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb888_to_g8_1_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal transform_1 : STD_LOGIC;
signal trigger_1 : STD_LOGIC;
signal twenty_u_dout : STD_LOGIC_VECTOR ( 9 downto 0 );
signal util_ds_buf_0_BUFG_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_buffer_1_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_feature_transform_0_rot_m00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m01 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m10 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_rot_m11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_feature_transform_0_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vga_feature_transform_0_t_x : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_feature_transform_0_t_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_hessian_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_hessian_1_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_overlay_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_12_5 : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_x_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_transform_0_y_addr_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vsync_1 : STD_LOGIC;
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
data_1(7 downto 0) <= data(7 downto 0);
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1 <= hsync;
pclk_1 <= pclk;
ready <= ov7670_controller_0_config_finished;
reset_1 <= reset;
sioc <= ov7670_controller_0_sioc;
state(1 downto 0) <= vga_feature_transform_0_state(1 downto 0);
transform_1 <= transform;
transform_led <= transform_1;
trigger_1 <= trigger;
vsync_1 <= vsync;
xclk <= clk_wiz_0_clk_out1;
buffer_register_0: component system_buffer_register_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
val_in(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_0_val_out(31 downto 0)
);
buffer_register_1: component system_buffer_register_1_0
port map (
clk => vga_pll_0_clk_12_5(0),
val_in(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_1_val_out(31 downto 0)
);
c_addsub_0: component system_c_addsub_0_0
port map (
A(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
B(9 downto 0) => twenty_u_dout(9 downto 0),
S(9 downto 0) => c_addsub_0_S(9 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_1_clk_out1
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => pclk_1,
clk_out => clock_splitter_0_clk_out,
latch_edge => vsync_1
);
debounce_0: component system_debounce_0_0
port map (
clk => util_ds_buf_0_BUFG_O(0),
signal_in => reset_1,
signal_out => debounce_0_o
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => util_ds_buf_0_BUFG_O(0),
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => pclk_1,
data(7 downto 0) => data_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
rgb888_to_g8_1: component system_rgb888_to_g8_1_0
port map (
clk => vga_pll_0_clk_12_5(0),
g8(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
twenty_u: component system_xlconstant_0_3
port map (
dout(9 downto 0) => twenty_u_dout(9 downto 0)
);
util_ds_buf_0: component system_util_ds_buf_0_0
port map (
BUFG_I(0) => vga_pll_0_clk_25,
BUFG_O(0) => util_ds_buf_0_BUFG_O(0)
);
util_ds_buf_1: component system_util_ds_buf_1_0
port map (
BUFG_I(0) => vga_pll_0_clk_12_6,
BUFG_O(0) => vga_pll_0_clk_12_5(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_5(0),
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_buffer_1: component system_vga_buffer_1_1
port map (
clk_r => vga_pll_0_clk_12_5(0),
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_1_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
x_addr_w(9 downto 0) => c_addsub_0_S(9 downto 0),
y_addr_r(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_feature_transform_0: component system_vga_feature_transform_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
clk_x2 => util_ds_buf_0_BUFG_O(0),
hessian_0(31 downto 0) => buffer_register_0_val_out(31 downto 0),
hessian_1(31 downto 0) => buffer_register_1_val_out(31 downto 0),
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
rst => ov7670_controller_0_config_finished,
state(1 downto 0) => vga_feature_transform_0_state(1 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
vsync => vsync_1,
x_addr_0(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_1(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr_0(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_1(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_0: component system_vga_hessian_0_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_hessian_1: component system_vga_hessian_1_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_1_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_1_hessian_out(31 downto 0),
rst => vga_sync_reset_0_vsync,
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_overlay_0: component system_vga_overlay_0_0
port map (
clk => vga_pll_0_clk_12_5(0),
rgb(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
rgb_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb_1(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => hsync_1,
rst => ov7670_controller_0_config_finished,
start => vga_sync_ref_0_start,
vsync => vsync_1,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_transform_0: component system_vga_transform_0_1
port map (
clk => vga_pll_0_clk_12_5(0),
enable => transform_1,
rot_m00(15 downto 0) => vga_feature_transform_0_rot_m00(15 downto 0),
rot_m01(15 downto 0) => vga_feature_transform_0_rot_m01(15 downto 0),
rot_m10(15 downto 0) => vga_feature_transform_0_rot_m10(15 downto 0),
rot_m11(15 downto 0) => vga_feature_transform_0_rot_m11(15 downto 0),
t_x(9 downto 0) => vga_feature_transform_0_t_x(9 downto 0),
t_y(9 downto 0) => vga_feature_transform_0_t_y(9 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => vga_transform_0_x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => vga_transform_0_y_addr_out(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_5(0),
clk_100 => clk_100_1,
clk_x2 => util_ds_buf_0_BUFG_O(0),
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
| mit | b2f97e466d5678ea442ffacc589e7030 | 0.6253 | 2.860012 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s3.vhd | 2 | 3,979 | library ieee;
use ieee.std_logic_1164.all;
entity s3 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s3;
architecture behaviour of s3 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
end case;
end process;
end; | mit | 3a8d6f5ecbf0a80db7bbb90ebe4e0f59 | 0.673536 | 3.030465 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_1_0/sim/system_vga_gaussian_blur_1_0.vhd | 1 | 3,890 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_1_0 IS
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_1_0;
ARCHITECTURE system_vga_gaussian_blur_1_0_arch OF system_vga_gaussian_blur_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
clk_25 => clk_25,
hsync_in => hsync_in,
vsync_in => vsync_in,
rgb_in => rgb_in,
hsync_out => hsync_out,
vsync_out => vsync_out,
rgb_blur => rgb_blur,
rgb_pass => rgb_pass
);
END system_vga_gaussian_blur_1_0_arch;
| mit | 532e8118f1d52261f783323feb32c5ac | 0.703085 | 3.736792 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/synth/arctan.vhd | 1 | 8,375 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY arctan IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END arctan;
ARCHITECTURE arctan_arch OF arctan IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF arctan_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF arctan_arch: ARCHITECTURE IS "cordic_v6_0_11,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF arctan_arch : ARCHITECTURE IS "arctan,cordic_v6_0_11,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF arctan_arch: ARCHITECTURE IS "arctan,cordic_v6_0_11,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cordic,x_ipVersion=6.0,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_ARCHITECTURE=2,C_CORDIC_FUNCTION=3,C_COARSE_ROTATE=0,C_DATA_FORMAT=0,C_XDEVICEFAMILY=zynq,C_HAS_ACLKEN=0,C_HAS_ACLK=1,C_HAS_S_AXIS_CARTESIAN=1,C_HAS_S_AXIS_PHASE=0,C_HAS_ARESETN=0,C_INPUT_WIDTH=16,C_ITERATIONS=0,C_OUTPUT_WIDTH=16,C_PHASE_FORMAT=0,C_PIPELINE_MODE=-2,C_PRECISION=0,C_ROUND_MODE=0,C_SCALE_COMP=0,C_THROTTLE" &
"_SCHEME=3,C_TLAST_RESOLUTION=0,C_HAS_S_AXIS_PHASE_TUSER=0,C_HAS_S_AXIS_PHASE_TLAST=0,C_S_AXIS_PHASE_TDATA_WIDTH=16,C_S_AXIS_PHASE_TUSER_WIDTH=1,C_HAS_S_AXIS_CARTESIAN_TUSER=0,C_HAS_S_AXIS_CARTESIAN_TLAST=0,C_S_AXIS_CARTESIAN_TDATA_WIDTH=32,C_S_AXIS_CARTESIAN_TUSER_WIDTH=1,C_M_AXIS_DOUT_TDATA_WIDTH=16,C_M_AXIS_DOUT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 3,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 0,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END arctan_arch;
| mit | ca49de196c376d1158c7ce0cedb696b2 | 0.682985 | 3.239845 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/synth/system_clock_splitter_0_0.vhd | 5 | 3,769 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
| mit | cc25239f7c11c5a66d36063c1f243004 | 0.746086 | 3.967368 | false | false | false | false |
loa-org/loa-hdl | modules/adc_ltc2351/hdl/adc_ltc2351_model.vhd | 2 | 3,399 | -------------------------------------------------------------------------------
-- Description:
-- Behaviourial model of LTC2351 ADC converter.
-- Very simple, does not support standby and nap.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_model is
generic (
-- TODO find how to init a 14-bit vector with a hexadecimal
DATA_CH1 : std_logic_vector(13 downto 0) := "01" & x"f55";
DATA_CH2 : std_logic_vector(13 downto 0) := "11" & x"7f3";
DATA_CH3 : std_logic_vector(13 downto 0) := "10" & x"492";
DATA_CH4 : std_logic_vector(13 downto 0) := "11" & x"af1";
DATA_CH5 : std_logic_vector(13 downto 0) := "01" & x"b34";
DATA_CH6 : std_logic_vector(13 downto 0) := "00" & x"59f");
port (
sck : in std_logic;
conv : in std_logic;
sdo : out std_logic := 'Z');
end adc_ltc2351_model;
architecture behavioral of adc_ltc2351_model is
type adc_ltc2351_state_type is (IDLE, SAMPLING);
type adc_ltc2351_model_type is record
state : adc_ltc2351_state_type;
count_bit : integer range 1 to 98;
adc_data : std_logic_vector(1 to 98);
sdo : std_logic;
end record;
----------------------------------------------------------------------------
-- Internal signal declarations
----------------------------------------------------------------------------
signal r, rin : adc_ltc2351_model_type;
begin -- behavioral
-- rin.adc_data <=
----------------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------------
-- none
-------------------------------------------------------------------------------
-- Connect internal signals to out
-------------------------------------------------------------------------------
sdo <= r.sdo;
----------------------------------------------------------------------------
-- Sequential process of FSM
----------------------------------------------------------------------------
-- purpose: sequential process of FSM
-- type : sequential
-- inputs : sck, conv
-- outputs: sdo
seq_proc : process (sck)
begin -- process seq_proc
if rising_edge(sck) then -- rising clock edge
r <= rin;
end if;
end process seq_proc;
-- purpose: transitions and actions of FSM
-- type : sequential
-- inputs : sck, conv
-- outputs:
comb_proc : process (conv, r)
variable v : adc_ltc2351_model_type;
begin -- process comb_proc
v := r;
case v.state is
when IDLE =>
if conv = '1' then
v.state := SAMPLING;
v.count_bit := 1;
v.adc_data := "Z" & DATA_CH1 & "ZZ" & DATA_CH2 & "ZZ" & DATA_CH3 & "ZZ" & DATA_CH4 & "ZZ" & DATA_CH5 & "ZZ" & DATA_CH6 & "ZZZ";
v.sdo := 'Z'; -- first bit
end if;
when SAMPLING =>
v.adc_data := r.adc_data(2 to 98) & 'U';
if r.count_bit = 98 then
v.state := IDLE;
v.sdo := 'Z';
else
v.count_bit := r.count_bit + 1;
v.sdo := r.adc_data(1);
end if;
end case;
rin <= v;
end process comb_proc;
end behavioral;
| bsd-3-clause | bae8f7085ece632e9e994f7cd50d3494 | 0.425713 | 4.125 | false | false | false | false |
loa-org/loa-hdl | modules/ws2812/hdl/ws2812_8x1.vhd | 1 | 3,982 | -------------------------------------------------------------------------------
-- Title : 8x1 Pixel Controller
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-15
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ws2812_pkg.all;
use work.ws2812_cfg_pkg.all;
use work.reset_pkg.all;
entity ws2812_8x1 is
generic (
RESET_IMPL : reset_type := none);
port (
pixels : in ws2812_8x1_in_type;
ws2812_in : out ws2812_in_type;
ws2812_out : in ws2812_out_type;
reset : in std_logic;
clk : in std_logic);
end ws2812_8x1;
architecture rtl of ws2812_8x1 is
type ws2812_8x1_states is (idle, write1, write2, write3, finish1, finish2);
type ws2812_8x1_state_type is record
o : ws2812_in_type;
pixel_cnt : integer range 0 to 7;
state : ws2812_8x1_states;
end record;
constant ws2812_8x1_state_type_initial : ws2812_8x1_state_type := (
o => (d => (others => '0'), we => '0', send_reset => '0'),
pixel_cnt => 0,
state => idle);
signal r, rin : ws2812_8x1_state_type := ws2812_8x1_state_type_initial;
begin -- ws2812_8x1
ws2812_in <= r.o;
comb : process(pixels, r, ws2812_out, reset)
variable v : ws2812_8x1_state_type;
begin
v := r;
case v.state is
when idle =>
-- busy := '0';
if pixels.refresh = '1' then
v.state := write1;
v.pixel_cnt := 7;
--busy := '1';
end if;
-------------------------------------------------------------------------
-- Write loop sequence
-------------------------------------------------------------------------
when write1 =>
v.o.d := pixels.pixel(v.pixel_cnt);
v.o.we := '1';
v.state := write2;
when write2 =>
v.o.we := '0';
v.state := write3;
when write3 =>
if ws2812_out.busy = '0' then
if v.pixel_cnt = 0 then
v.state := finish1;
v.o.send_reset := '1';
else
v.pixel_cnt := v.pixel_cnt - 1;
v.state := write1;
end if;
end if;
-----------------------------------------------------------------------
-- Send a reset seqence to update transfered data to output registers
-- of the LEDs
-----------------------------------------------------------------------
when finish1 =>
v.o.send_reset := '0';
v.state := finish2;
when finish2 =>
if ws2812_out.busy = '0' then
v.state := idle;
end if;
when others => null;
end case;
-- sync reset
if RESET_IMPL = sync and reset = '1' then
v := ws2812_8x1_state_type_initial;
end if;
rin <= v;
end process comb;
async_reset : if RESET_IMPL = async generate
seq : process (clk, reset) is
begin -- process seq
if reset = '0' then -- asynchronous reset (active low)
r <= ws2812_8x1_state_type_initial;
elsif clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
sync_reset : if RESET_IMPL /= async generate
seq : process (clk) is
begin -- process seq
if clk'event and clk = '1' then -- rising clock edge
r <= rin;
end if;
end process seq;
end generate;
end rtl;
| bsd-3-clause | 71cccf8ade3574205fcaa54b261d80a3 | 0.454294 | 3.869776 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_onchip_memory2_0_s1_translator.vhd | 1 | 14,686 | -- niosii_system_onchip_memory2_0_s1_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 12;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 1;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(11 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_clken : out std_logic; -- .clken
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_onchip_memory2_0_s1_translator;
architecture rtl of niosii_system_onchip_memory2_0_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
onchip_memory2_0_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_clken => av_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_onchip_memory2_0_s1_translator
| apache-2.0 | 5e6d34727090f4617608a388cd1d29a6 | 0.429252 | 4.343685 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_width_adapter_004.vhd | 1 | 10,497 | -- niosii_system_width_adapter_004.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter_004 is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 69;
IN_PKT_BYTE_CNT_L : integer := 67;
IN_PKT_TRANS_COMPRESSED_READ : integer := 61;
IN_PKT_BURSTWRAP_H : integer := 72;
IN_PKT_BURSTWRAP_L : integer := 70;
IN_PKT_BURST_SIZE_H : integer := 75;
IN_PKT_BURST_SIZE_L : integer := 73;
IN_PKT_RESPONSE_STATUS_H : integer := 99;
IN_PKT_RESPONSE_STATUS_L : integer := 98;
IN_PKT_TRANS_EXCLUSIVE : integer := 66;
IN_PKT_BURST_TYPE_H : integer := 77;
IN_PKT_BURST_TYPE_L : integer := 76;
IN_ST_DATA_W : integer := 100;
OUT_PKT_ADDR_H : integer := 33;
OUT_PKT_ADDR_L : integer := 9;
OUT_PKT_DATA_H : integer := 7;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 8;
OUT_PKT_BYTEEN_L : integer := 8;
OUT_PKT_BYTE_CNT_H : integer := 42;
OUT_PKT_BYTE_CNT_L : integer := 40;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 34;
OUT_PKT_BURST_SIZE_H : integer := 48;
OUT_PKT_BURST_SIZE_L : integer := 46;
OUT_PKT_RESPONSE_STATUS_H : integer := 72;
OUT_PKT_RESPONSE_STATUS_L : integer := 71;
OUT_PKT_TRANS_EXCLUSIVE : integer := 39;
OUT_PKT_BURST_TYPE_H : integer := 50;
OUT_PKT_BURST_TYPE_L : integer := 49;
OUT_ST_DATA_W : integer := 73;
ST_CHANNEL_W : integer := 13;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(99 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(72 downto 0); -- .data
out_channel : out std_logic_vector(12 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity niosii_system_width_adapter_004;
architecture rtl of niosii_system_width_adapter_004 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(72 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_004 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of niosii_system_width_adapter_004
| apache-2.0 | 8e438c87a52c25c78652d871073d78cd | 0.46137 | 3.371988 | false | false | false | false |
loa-org/loa-hdl | modules/hdlc/hdl/hdlc_enc.vhd | 2 | 4,529 | -------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Encode 8-Bit input + frame boundary marker to 8 bit HDLC Async framing
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x000 to 0x007C -> 0x00 to 0x7C
-- 0x07f to 0x0ff -> 0x7f to 0xff
-- 0x1XX -> 0x7e (Frame boundary marker)
-- 0x07E -> 0x7D, 0x5E
-- 0x07D -> 0x7D, 0x5D
--
-- Input port can't take in data while it outputs an escape sequence!
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_enc is
port(
din_p : in hdlc_enc_in_type;
dout_p : out hdlc_enc_out_type;
busy_p : out std_logic;
clk : in std_logic
);
end hdlc_enc;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_enc is
type hdlc_enc_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_enc_type is record
state : hdlc_enc_state_type;
strobe : std_logic;
next_char : std_logic_vector(7 downto 0);
dout : std_logic_vector(7 downto 0);
busy : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_enc_type := (state => NOM, strobe => '0', next_char => (others => '0'), dout => (others => '0'), busy => '0');
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
busy_p <= r.busy;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_enc_type;
begin
v := r;
v.strobe := '0';
v.busy := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data(8) = '1' then
v.dout := x"7e";
v.strobe := '1';
elsif (din_p.data(7 downto 0) = x"7e") or (din_p.data(7 downto 0) = x"7d") then
v.dout := x"7d";
v.next_char := din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := ESC;
v.busy := '1';
else
v.dout := din_p.data(7 downto 0);
v.strobe := '1';
end if;
end if;
when ESC =>
v.strobe := '1';
v.dout := v.next_char;
v.state := NOM;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | caebede874f01804fd5258638e5826b8 | 0.372488 | 4.607325 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_1rw.vhdl | 1 | 2,186 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Cache Core (SRAMs), 1 read/write port
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity cache_core_1rw is
generic (
log2_assoc : natural := 0;
word_bits : natural := 1;
index_bits : natural := 1;
offset_bits : natural := 0;
tag_bits : natural := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
en : in std_ulogic;
we : in std_ulogic;
way : in std_ulogic_vector(2**log2_assoc-1 downto 0);
tagen : in std_ulogic;
dataen : in std_ulogic;
index : in std_ulogic_vector(index_bits-1 downto 0);
offset : in std_ulogic_vector(offset_bits-1 downto 0);
wtag : in std_ulogic_vector(tag_bits-1 downto 0);
wdata : in std_ulogic_vector(word_bits-1 downto 0);
rtag : out std_ulogic_vector2(2**log2_assoc-1 downto 0, tag_bits-1 downto 0);
rdata : out std_ulogic_vector2(2**log2_assoc-1 downto 0, word_bits-1 downto 0)
);
end;
| apache-2.0 | 287e7747be552a1403b53458da6d8f9a | 0.533852 | 4.179732 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_1r1w_inferred-rtl-sim.vhdl | 1 | 4,194 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.numeric_pkg.all;
use util.logic_pkg.all;
use util.names_pkg.all;
use std.textio.all;
architecture rtl of syncram_1r1w_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
-- fill the memory with pseudo-random (but reproduceable) data
pure function memory_init return memory_type is
constant lfsr_bits : natural := addr_bits + log2ceil(data_bits) + 1;
variable lfsr : std_ulogic_vector(lfsr_bits-1 downto 0);
constant taps : std_ulogic_vector(lfsr_bits-1 downto 0) := lfsr_taps(lfsr_bits);
variable ret : memory_type;
variable initial_bit : integer;
variable name : line;
begin
name := new string'(entity_path_name(syncram_1r1w_inferred'path_name));
for n in name.all'range loop
initial_bit := (initial_bit + character'pos(name.all(n))) mod lfsr_bits;
end loop;
deallocate(name);
lfsr := (others => '0');
lfsr(0) := '1';
lfsr(initial_bit) := '1';
for n in 0 to memory_size-1 loop
for m in data_bits-1 downto 0 loop
ret(n)(m) := lfsr(0);
lfsr(lfsr_bits-1 downto 0) := lfsr(0) & (lfsr(lfsr_bits-1 downto 1) xor ((lfsr_bits-2 downto 0 => lfsr(0)) and taps(lfsr_bits-2 downto 0)));
end loop;
end loop;
return ret;
end;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
signal memory : memory_type := memory_init;
type reg_type is record
raddr : std_ulogic_vector(addr_bits-1 downto 0);
end record;
signal r : reg_type;
begin
write_process : process(clk)
begin
if rising_edge(clk) then
assert not is_x(we) report "we is invalid" severity warning;
if we = '1' then
assert not is_x(waddr) report "waddr is invalid" severity warning;
if not is_x(waddr) then
memory(conv_addr(waddr)) <= wdata;
end if;
end if;
end if;
end process;
write_first_true_gen: if write_first generate
rdata <= memory(conv_addr(r.raddr)) when not is_x(r.raddr) else (others => 'X');
read_process : process(clk)
begin
if rising_edge(clk) then
assert not is_x(re) report "re is invalid" severity warning;
if re = '1' then
r.raddr <= raddr;
end if;
end if;
end process;
end generate;
write_first_false_gen: if not write_first generate
main : process(clk)
begin
if rising_edge(clk) then
assert not is_x(re) report "re is invalid" severity warning;
if re = '1' then
rdata <= memory(conv_addr(raddr));
end if;
end if;
end process;
end generate;
end;
| apache-2.0 | f50b746da7becec3b35dcb42b73860d9 | 0.573677 | 3.915966 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/keysched.vhd | 2 | 5,134 | --******************************************************************************
-- Copyright (c) 2017 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
--------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 20:45:11 02/14/2010
-- Design Name:
-- Project Name: DES_Fully_Pipelined
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies: DES_Fully_Pipelined
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity keysched is port
(
key : in std_logic_vector(1 to 64);EN,CLK: in std_logic;
k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x
: out std_logic_vector(1 to 48)
);
end keysched;
architecture behaviour of keysched is
signal k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16: std_logic_vector(1 to 48);
signal
c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16 :std_logic_vector(28 downto 1);
signal
d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16 :std_logic_vector(28 downto 1);
component pc1
port (
key : in std_logic_vector(1 TO 64);
c0x,d0x : out std_logic_vector(1 TO 28)
);
end component;
component pc2
port (
c,d : in std_logic_vector(1 TO 28);
k : out std_logic_vector(1 TO 48)
);
end component;
begin
pc_1: pc1 port map ( key=>key, c0x=>c0, d0x=>d0);
C1 <= C0(27 DOWNTO 1) & C0(28);
D1 <= D0(27 DOWNTO 1) & D0(28);
C2 <= C1(27 DOWNTO 1) & C1(28);
D2 <= D1(27 DOWNTO 1) & D1(28);
C3 <= C2(26 DOWNTO 1) & C2(28 DOWNTO 27);
D3 <= D2(26 DOWNTO 1) & D2(28 DOWNTO 27);
C4 <= C3(26 DOWNTO 1) & C3(28 DOWNTO 27);
D4 <= D3(26 DOWNTO 1) & D3(28 DOWNTO 27);
C5 <= C4(26 DOWNTO 1) & C4(28 DOWNTO 27);
D5 <= D4(26 DOWNTO 1) & D4(28 DOWNTO 27);
C6 <= C5(26 DOWNTO 1) & C5(28 DOWNTO 27);
D6 <= D5(26 DOWNTO 1) & D5(28 DOWNTO 27);
C7 <= C6(26 DOWNTO 1) & C6(28 DOWNTO 27);
D7 <= D6(26 DOWNTO 1) & D6(28 DOWNTO 27);
C8 <= C7(26 DOWNTO 1) & C7(28 DOWNTO 27);
D8 <= D7(26 DOWNTO 1) & D7(28 DOWNTO 27);
C9 <= C8(27 DOWNTO 1) & C8(28);
D9 <= D8(27 DOWNTO 1) & D8(28);
C10 <= C9(26 DOWNTO 1) & C9(28 DOWNTO 27);
D10 <= D9(26 DOWNTO 1) & D9(28 DOWNTO 27);
C11 <= C10(26 DOWNTO 1) & C10(28 DOWNTO 27);
D11 <= D10(26 DOWNTO 1) & D10(28 DOWNTO 27);
C12 <= C11(26 DOWNTO 1) & C11(28 DOWNTO 27);
D12 <= D11(26 DOWNTO 1) & D11(28 DOWNTO 27);
C13 <= C12(26 DOWNTO 1) & C12(28 DOWNTO 27);
D13 <= D12(26 DOWNTO 1) & D12(28 DOWNTO 27);
C14 <= C13(26 DOWNTO 1) & C13(28 DOWNTO 27);
D14 <= D13(26 DOWNTO 1) & D13(28 DOWNTO 27);
C15 <= C14(26 DOWNTO 1) & C14(28 DOWNTO 27);
D15 <= D14(26 DOWNTO 1) & D14(28 DOWNTO 27);
C16 <= C15(27 DOWNTO 1) & C15(28);
D16 <= D15(27 DOWNTO 1) & D15(28);
pc2x1: pc2 port map ( c=>c1, d=>d1, k=>k1 );
pc2x2: pc2 port map ( c=>c2, d=>d2, k=>k2 );
pc2x3: pc2 port map ( c=>c3, d=>d3, k=>k3 );
pc2x4: pc2 port map ( c=>c4, d=>d4, k=>k4 );
pc2x5: pc2 port map ( c=>c5, d=>d5, k=>k5 );
pc2x6: pc2 port map ( c=>c6, d=>d6, k=>k6 );
pc2x7: pc2 port map ( c=>c7, d=>d7, k=>k7 );
pc2x8: pc2 port map ( c=>c8, d=>d8, k=>k8 );
pc2x9: pc2 port map ( c=>c9, d=>d9, k=>k9 );
pc2x10: pc2 port map ( c=>c10, d=>d10, k=>k10 );
pc2x11: pc2 port map ( c=>c11, d=>d11, k=>k11 );
pc2x12: pc2 port map ( c=>c12, d=>d12, k=>k12 );
pc2x13: pc2 port map ( c=>c13, d=>d13, k=>k13 );
pc2x14: pc2 port map ( c=>c14, d=>d14, k=>k14 );
pc2x15: pc2 port map ( c=>c15, d=>d15, k=>k15 );
pc2x16: pc2 port map ( c=>c16, d=>d16, k=>k16 );
process(EN,KEY,CLK)
begin
if EN='0' then
k1x<=k16;k2x<=k15;k3x<=k14;k4x<=k13;k5x<=k12;k6x<=k11;k7x<=k10;k8x<=k9;
k9x<=k8;k10x<=k7;k11x<=k6;k12x<=k5;k13x<=k4;k14x<=k3;k15x<=k2;k16x<=k1;
else
k1x<=k1;k2x<=k2;k3x<=k3;k4x<=k4;k5x<=k5;k6x<=k6;k7x<=k7;k8x<=k8;
k9x<=k9;k10x<=k10;k11x<=k11;k12x<=k12;k13x<=k13;k14x<=k14;k15x<=k15;k16x<=k16;
end if;
end process;
end behaviour; | mit | 87b0dd526d2933c9ff2b7460802613c4 | 0.609661 | 2.362632 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_0_0/system_vga_nmsuppression_0_0_sim_netlist.vhdl | 1 | 215,472 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 20:23:12 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_nmsuppression_0_0 -prefix
-- system_vga_nmsuppression_0_0_ system_vga_nmsuppression_0_0_sim_netlist.vhdl
-- Design : system_vga_nmsuppression_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_0_0_vga_nmsuppression is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
active : in STD_LOGIC;
clk : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
enable : in STD_LOGIC
);
end system_vga_nmsuppression_0_0_vga_nmsuppression;
architecture STRUCTURE of system_vga_nmsuppression_0_0_vga_nmsuppression is
signal \hessian_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_3\ : STD_LOGIC;
signal hessian_out2_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_1 : STD_LOGIC;
signal hessian_out2_carry_n_2 : STD_LOGIC;
signal hessian_out2_carry_n_3 : STD_LOGIC;
signal \hessian_out3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_3\ : STD_LOGIC;
signal hessian_out3_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_1 : STD_LOGIC;
signal hessian_out3_carry_n_2 : STD_LOGIC;
signal hessian_out3_carry_n_3 : STD_LOGIC;
signal \hessian_out4_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_3\ : STD_LOGIC;
signal hessian_out4_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_1 : STD_LOGIC;
signal hessian_out4_carry_n_2 : STD_LOGIC;
signal hessian_out4_carry_n_3 : STD_LOGIC;
signal \hessian_out5_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_3\ : STD_LOGIC;
signal hessian_out5_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_1 : STD_LOGIC;
signal hessian_out5_carry_n_2 : STD_LOGIC;
signal hessian_out5_carry_n_3 : STD_LOGIC;
signal \hessian_out6_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_3\ : STD_LOGIC;
signal hessian_out6_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_1 : STD_LOGIC;
signal hessian_out6_carry_n_2 : STD_LOGIC;
signal hessian_out6_carry_n_3 : STD_LOGIC;
signal \hessian_out7_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_3\ : STD_LOGIC;
signal hessian_out7_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_1 : STD_LOGIC;
signal hessian_out7_carry_n_2 : STD_LOGIC;
signal hessian_out7_carry_n_3 : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_3\ : STD_LOGIC;
signal hessian_out8_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_1 : STD_LOGIC;
signal hessian_out8_carry_n_2 : STD_LOGIC;
signal hessian_out8_carry_n_3 : STD_LOGIC;
signal \hessian_out[31]_i_1_n_0\ : STD_LOGIC;
signal \hessian_out[31]_i_2_n_0\ : STD_LOGIC;
signal \hessian_reg[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[10]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[11]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[1]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[4][0]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][10]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][11]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][12]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][13]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][14]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][15]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][16]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][17]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][18]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][19]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][1]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][20]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][21]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][22]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][23]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][24]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][25]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][26]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][27]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][28]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][29]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][2]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][30]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][31]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][3]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][4]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][5]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][6]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][7]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][8]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][9]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[5]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[6]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[7]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[8]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[9]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 0 to 0 );
signal \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal NLW_hessian_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out4_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out5_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out6_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out7_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out8_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute srl_bus_name : string;
attribute srl_bus_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name : string;
attribute srl_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4][0]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4][10]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4][11]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4][12]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4][13]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4][14]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4][15]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4][16]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4][17]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4][18]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4][19]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4][1]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4][20]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4][21]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4][22]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4][23]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4][24]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4][25]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4][26]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4][27]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4][28]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4][29]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4][2]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4][30]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4][31]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4][3]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4][4]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4][5]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4][6]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4][7]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4][8]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4][9]_srl3 ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[9]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y_addr_out[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y_addr_out[9]_i_1\ : label is "soft_lutpair3";
begin
hessian_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out2_carry_n_0,
CO(2) => hessian_out2_carry_n_1,
CO(1) => hessian_out2_carry_n_2,
CO(0) => hessian_out2_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out2_carry_i_1_n_0,
DI(2) => hessian_out2_carry_i_2_n_0,
DI(1) => hessian_out2_carry_i_3_n_0,
DI(0) => hessian_out2_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out2_carry_i_5_n_0,
S(2) => hessian_out2_carry_i_6_n_0,
S(1) => hessian_out2_carry_i_7_n_0,
S(0) => hessian_out2_carry_i_8_n_0
);
\hessian_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out2_carry_n_0,
CO(3) => \hessian_out2_carry__0_n_0\,
CO(2) => \hessian_out2_carry__0_n_1\,
CO(1) => \hessian_out2_carry__0_n_2\,
CO(0) => \hessian_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__0_i_1_n_0\,
DI(2) => \hessian_out2_carry__0_i_2_n_0\,
DI(1) => \hessian_out2_carry__0_i_3_n_0\,
DI(0) => \hessian_out2_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__0_i_5_n_0\,
S(2) => \hessian_out2_carry__0_i_6_n_0\,
S(1) => \hessian_out2_carry__0_i_7_n_0\,
S(0) => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_1_n_0\
);
\hessian_out2_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_2_n_0\
);
\hessian_out2_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_3_n_0\
);
\hessian_out2_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_4_n_0\
);
\hessian_out2_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_5_n_0\
);
\hessian_out2_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_6_n_0\
);
\hessian_out2_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_7_n_0\
);
\hessian_out2_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__0_n_0\,
CO(3) => \hessian_out2_carry__1_n_0\,
CO(2) => \hessian_out2_carry__1_n_1\,
CO(1) => \hessian_out2_carry__1_n_2\,
CO(0) => \hessian_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__1_i_1_n_0\,
DI(2) => \hessian_out2_carry__1_i_2_n_0\,
DI(1) => \hessian_out2_carry__1_i_3_n_0\,
DI(0) => \hessian_out2_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__1_i_5_n_0\,
S(2) => \hessian_out2_carry__1_i_6_n_0\,
S(1) => \hessian_out2_carry__1_i_7_n_0\,
S(0) => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_1_n_0\
);
\hessian_out2_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_2_n_0\
);
\hessian_out2_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_3_n_0\
);
\hessian_out2_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_4_n_0\
);
\hessian_out2_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_5_n_0\
);
\hessian_out2_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_6_n_0\
);
\hessian_out2_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_7_n_0\
);
\hessian_out2_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__1_n_0\,
CO(3) => \hessian_out2_carry__2_n_0\,
CO(2) => \hessian_out2_carry__2_n_1\,
CO(1) => \hessian_out2_carry__2_n_2\,
CO(0) => \hessian_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__2_i_1_n_0\,
DI(2) => \hessian_out2_carry__2_i_2_n_0\,
DI(1) => \hessian_out2_carry__2_i_3_n_0\,
DI(0) => \hessian_out2_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__2_i_5_n_0\,
S(2) => \hessian_out2_carry__2_i_6_n_0\,
S(1) => \hessian_out2_carry__2_i_7_n_0\,
S(0) => \hessian_out2_carry__2_i_8_n_0\
);
\hessian_out2_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_1_n_0\
);
\hessian_out2_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_2_n_0\
);
\hessian_out2_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_3_n_0\
);
\hessian_out2_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_4_n_0\
);
\hessian_out2_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_5_n_0\
);
\hessian_out2_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_6_n_0\
);
\hessian_out2_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_7_n_0\
);
\hessian_out2_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_8_n_0\
);
hessian_out2_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_1_n_0
);
hessian_out2_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_2_n_0
);
hessian_out2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_3_n_0
);
hessian_out2_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_4_n_0
);
hessian_out2_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_5_n_0
);
hessian_out2_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_6_n_0
);
hessian_out2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_7_n_0
);
hessian_out2_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_8_n_0
);
hessian_out3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out3_carry_n_0,
CO(2) => hessian_out3_carry_n_1,
CO(1) => hessian_out3_carry_n_2,
CO(0) => hessian_out3_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out3_carry_i_1_n_0,
DI(2) => hessian_out3_carry_i_2_n_0,
DI(1) => hessian_out3_carry_i_3_n_0,
DI(0) => hessian_out3_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out3_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out3_carry_i_5_n_0,
S(2) => hessian_out3_carry_i_6_n_0,
S(1) => hessian_out3_carry_i_7_n_0,
S(0) => hessian_out3_carry_i_8_n_0
);
\hessian_out3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out3_carry_n_0,
CO(3) => \hessian_out3_carry__0_n_0\,
CO(2) => \hessian_out3_carry__0_n_1\,
CO(1) => \hessian_out3_carry__0_n_2\,
CO(0) => \hessian_out3_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__0_i_1_n_0\,
DI(2) => \hessian_out3_carry__0_i_2_n_0\,
DI(1) => \hessian_out3_carry__0_i_3_n_0\,
DI(0) => \hessian_out3_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__0_i_5_n_0\,
S(2) => \hessian_out3_carry__0_i_6_n_0\,
S(1) => \hessian_out3_carry__0_i_7_n_0\,
S(0) => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_1_n_0\
);
\hessian_out3_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_2_n_0\
);
\hessian_out3_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_3_n_0\
);
\hessian_out3_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_4_n_0\
);
\hessian_out3_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_5_n_0\
);
\hessian_out3_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_6_n_0\
);
\hessian_out3_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_7_n_0\
);
\hessian_out3_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__0_n_0\,
CO(3) => \hessian_out3_carry__1_n_0\,
CO(2) => \hessian_out3_carry__1_n_1\,
CO(1) => \hessian_out3_carry__1_n_2\,
CO(0) => \hessian_out3_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__1_i_1_n_0\,
DI(2) => \hessian_out3_carry__1_i_2_n_0\,
DI(1) => \hessian_out3_carry__1_i_3_n_0\,
DI(0) => \hessian_out3_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__1_i_5_n_0\,
S(2) => \hessian_out3_carry__1_i_6_n_0\,
S(1) => \hessian_out3_carry__1_i_7_n_0\,
S(0) => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_1_n_0\
);
\hessian_out3_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_2_n_0\
);
\hessian_out3_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_3_n_0\
);
\hessian_out3_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_4_n_0\
);
\hessian_out3_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_5_n_0\
);
\hessian_out3_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_6_n_0\
);
\hessian_out3_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_7_n_0\
);
\hessian_out3_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__1_n_0\,
CO(3) => \hessian_out3_carry__2_n_0\,
CO(2) => \hessian_out3_carry__2_n_1\,
CO(1) => \hessian_out3_carry__2_n_2\,
CO(0) => \hessian_out3_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__2_i_1_n_0\,
DI(2) => \hessian_out3_carry__2_i_2_n_0\,
DI(1) => \hessian_out3_carry__2_i_3_n_0\,
DI(0) => \hessian_out3_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__2_i_5_n_0\,
S(2) => \hessian_out3_carry__2_i_6_n_0\,
S(1) => \hessian_out3_carry__2_i_7_n_0\,
S(0) => \hessian_out3_carry__2_i_8_n_0\
);
\hessian_out3_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_1_n_0\
);
\hessian_out3_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_2_n_0\
);
\hessian_out3_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_3_n_0\
);
\hessian_out3_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_4_n_0\
);
\hessian_out3_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_5_n_0\
);
\hessian_out3_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_6_n_0\
);
\hessian_out3_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_7_n_0\
);
\hessian_out3_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_8_n_0\
);
hessian_out3_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_1_n_0
);
hessian_out3_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_2_n_0
);
hessian_out3_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_3_n_0
);
hessian_out3_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_4_n_0
);
hessian_out3_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_5_n_0
);
hessian_out3_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_6_n_0
);
hessian_out3_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_7_n_0
);
hessian_out3_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_8_n_0
);
hessian_out4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out4_carry_n_0,
CO(2) => hessian_out4_carry_n_1,
CO(1) => hessian_out4_carry_n_2,
CO(0) => hessian_out4_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out4_carry_i_1_n_0,
DI(2) => hessian_out4_carry_i_2_n_0,
DI(1) => hessian_out4_carry_i_3_n_0,
DI(0) => hessian_out4_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out4_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out4_carry_i_5_n_0,
S(2) => hessian_out4_carry_i_6_n_0,
S(1) => hessian_out4_carry_i_7_n_0,
S(0) => hessian_out4_carry_i_8_n_0
);
\hessian_out4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out4_carry_n_0,
CO(3) => \hessian_out4_carry__0_n_0\,
CO(2) => \hessian_out4_carry__0_n_1\,
CO(1) => \hessian_out4_carry__0_n_2\,
CO(0) => \hessian_out4_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__0_i_1_n_0\,
DI(2) => \hessian_out4_carry__0_i_2_n_0\,
DI(1) => \hessian_out4_carry__0_i_3_n_0\,
DI(0) => \hessian_out4_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__0_i_5_n_0\,
S(2) => \hessian_out4_carry__0_i_6_n_0\,
S(1) => \hessian_out4_carry__0_i_7_n_0\,
S(0) => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_1_n_0\
);
\hessian_out4_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_2_n_0\
);
\hessian_out4_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_3_n_0\
);
\hessian_out4_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_4_n_0\
);
\hessian_out4_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_5_n_0\
);
\hessian_out4_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_6_n_0\
);
\hessian_out4_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_7_n_0\
);
\hessian_out4_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__0_n_0\,
CO(3) => \hessian_out4_carry__1_n_0\,
CO(2) => \hessian_out4_carry__1_n_1\,
CO(1) => \hessian_out4_carry__1_n_2\,
CO(0) => \hessian_out4_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__1_i_1_n_0\,
DI(2) => \hessian_out4_carry__1_i_2_n_0\,
DI(1) => \hessian_out4_carry__1_i_3_n_0\,
DI(0) => \hessian_out4_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__1_i_5_n_0\,
S(2) => \hessian_out4_carry__1_i_6_n_0\,
S(1) => \hessian_out4_carry__1_i_7_n_0\,
S(0) => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_1_n_0\
);
\hessian_out4_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_2_n_0\
);
\hessian_out4_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_3_n_0\
);
\hessian_out4_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_4_n_0\
);
\hessian_out4_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_5_n_0\
);
\hessian_out4_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_6_n_0\
);
\hessian_out4_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_7_n_0\
);
\hessian_out4_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__1_n_0\,
CO(3) => \hessian_out4_carry__2_n_0\,
CO(2) => \hessian_out4_carry__2_n_1\,
CO(1) => \hessian_out4_carry__2_n_2\,
CO(0) => \hessian_out4_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__2_i_1_n_0\,
DI(2) => \hessian_out4_carry__2_i_2_n_0\,
DI(1) => \hessian_out4_carry__2_i_3_n_0\,
DI(0) => \hessian_out4_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__2_i_5_n_0\,
S(2) => \hessian_out4_carry__2_i_6_n_0\,
S(1) => \hessian_out4_carry__2_i_7_n_0\,
S(0) => \hessian_out4_carry__2_i_8_n_0\
);
\hessian_out4_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_1_n_0\
);
\hessian_out4_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_2_n_0\
);
\hessian_out4_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_3_n_0\
);
\hessian_out4_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_4_n_0\
);
\hessian_out4_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_5_n_0\
);
\hessian_out4_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_6_n_0\
);
\hessian_out4_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_7_n_0\
);
\hessian_out4_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_8_n_0\
);
hessian_out4_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_1_n_0
);
hessian_out4_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_2_n_0
);
hessian_out4_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_3_n_0
);
hessian_out4_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_4_n_0
);
hessian_out4_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_5_n_0
);
hessian_out4_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_6_n_0
);
hessian_out4_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_7_n_0
);
hessian_out4_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_8_n_0
);
hessian_out5_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out5_carry_n_0,
CO(2) => hessian_out5_carry_n_1,
CO(1) => hessian_out5_carry_n_2,
CO(0) => hessian_out5_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out5_carry_i_1_n_0,
DI(2) => hessian_out5_carry_i_2_n_0,
DI(1) => hessian_out5_carry_i_3_n_0,
DI(0) => hessian_out5_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out5_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out5_carry_i_5_n_0,
S(2) => hessian_out5_carry_i_6_n_0,
S(1) => hessian_out5_carry_i_7_n_0,
S(0) => hessian_out5_carry_i_8_n_0
);
\hessian_out5_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out5_carry_n_0,
CO(3) => \hessian_out5_carry__0_n_0\,
CO(2) => \hessian_out5_carry__0_n_1\,
CO(1) => \hessian_out5_carry__0_n_2\,
CO(0) => \hessian_out5_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__0_i_1_n_0\,
DI(2) => \hessian_out5_carry__0_i_2_n_0\,
DI(1) => \hessian_out5_carry__0_i_3_n_0\,
DI(0) => \hessian_out5_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__0_i_5_n_0\,
S(2) => \hessian_out5_carry__0_i_6_n_0\,
S(1) => \hessian_out5_carry__0_i_7_n_0\,
S(0) => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_1_n_0\
);
\hessian_out5_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_2_n_0\
);
\hessian_out5_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_3_n_0\
);
\hessian_out5_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_4_n_0\
);
\hessian_out5_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_5_n_0\
);
\hessian_out5_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_6_n_0\
);
\hessian_out5_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_7_n_0\
);
\hessian_out5_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__0_n_0\,
CO(3) => \hessian_out5_carry__1_n_0\,
CO(2) => \hessian_out5_carry__1_n_1\,
CO(1) => \hessian_out5_carry__1_n_2\,
CO(0) => \hessian_out5_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__1_i_1_n_0\,
DI(2) => \hessian_out5_carry__1_i_2_n_0\,
DI(1) => \hessian_out5_carry__1_i_3_n_0\,
DI(0) => \hessian_out5_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__1_i_5_n_0\,
S(2) => \hessian_out5_carry__1_i_6_n_0\,
S(1) => \hessian_out5_carry__1_i_7_n_0\,
S(0) => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_1_n_0\
);
\hessian_out5_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_2_n_0\
);
\hessian_out5_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_3_n_0\
);
\hessian_out5_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_4_n_0\
);
\hessian_out5_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_5_n_0\
);
\hessian_out5_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_6_n_0\
);
\hessian_out5_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_7_n_0\
);
\hessian_out5_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__1_n_0\,
CO(3) => \hessian_out5_carry__2_n_0\,
CO(2) => \hessian_out5_carry__2_n_1\,
CO(1) => \hessian_out5_carry__2_n_2\,
CO(0) => \hessian_out5_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__2_i_1_n_0\,
DI(2) => \hessian_out5_carry__2_i_2_n_0\,
DI(1) => \hessian_out5_carry__2_i_3_n_0\,
DI(0) => \hessian_out5_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__2_i_5_n_0\,
S(2) => \hessian_out5_carry__2_i_6_n_0\,
S(1) => \hessian_out5_carry__2_i_7_n_0\,
S(0) => \hessian_out5_carry__2_i_8_n_0\
);
\hessian_out5_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_1_n_0\
);
\hessian_out5_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_2_n_0\
);
\hessian_out5_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_3_n_0\
);
\hessian_out5_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_4_n_0\
);
\hessian_out5_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_5_n_0\
);
\hessian_out5_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_6_n_0\
);
\hessian_out5_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_7_n_0\
);
\hessian_out5_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_8_n_0\
);
hessian_out5_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_1_n_0
);
hessian_out5_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_2_n_0
);
hessian_out5_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_3_n_0
);
hessian_out5_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_4_n_0
);
hessian_out5_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_5_n_0
);
hessian_out5_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_6_n_0
);
hessian_out5_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_7_n_0
);
hessian_out5_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_8_n_0
);
hessian_out6_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out6_carry_n_0,
CO(2) => hessian_out6_carry_n_1,
CO(1) => hessian_out6_carry_n_2,
CO(0) => hessian_out6_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out6_carry_i_1_n_0,
DI(2) => hessian_out6_carry_i_2_n_0,
DI(1) => hessian_out6_carry_i_3_n_0,
DI(0) => hessian_out6_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out6_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out6_carry_i_5_n_0,
S(2) => hessian_out6_carry_i_6_n_0,
S(1) => hessian_out6_carry_i_7_n_0,
S(0) => hessian_out6_carry_i_8_n_0
);
\hessian_out6_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out6_carry_n_0,
CO(3) => \hessian_out6_carry__0_n_0\,
CO(2) => \hessian_out6_carry__0_n_1\,
CO(1) => \hessian_out6_carry__0_n_2\,
CO(0) => \hessian_out6_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__0_i_1_n_0\,
DI(2) => \hessian_out6_carry__0_i_2_n_0\,
DI(1) => \hessian_out6_carry__0_i_3_n_0\,
DI(0) => \hessian_out6_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__0_i_5_n_0\,
S(2) => \hessian_out6_carry__0_i_6_n_0\,
S(1) => \hessian_out6_carry__0_i_7_n_0\,
S(0) => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_1_n_0\
);
\hessian_out6_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_2_n_0\
);
\hessian_out6_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_3_n_0\
);
\hessian_out6_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_4_n_0\
);
\hessian_out6_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_5_n_0\
);
\hessian_out6_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_6_n_0\
);
\hessian_out6_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_7_n_0\
);
\hessian_out6_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__0_n_0\,
CO(3) => \hessian_out6_carry__1_n_0\,
CO(2) => \hessian_out6_carry__1_n_1\,
CO(1) => \hessian_out6_carry__1_n_2\,
CO(0) => \hessian_out6_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__1_i_1_n_0\,
DI(2) => \hessian_out6_carry__1_i_2_n_0\,
DI(1) => \hessian_out6_carry__1_i_3_n_0\,
DI(0) => \hessian_out6_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__1_i_5_n_0\,
S(2) => \hessian_out6_carry__1_i_6_n_0\,
S(1) => \hessian_out6_carry__1_i_7_n_0\,
S(0) => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_1_n_0\
);
\hessian_out6_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_2_n_0\
);
\hessian_out6_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_3_n_0\
);
\hessian_out6_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_4_n_0\
);
\hessian_out6_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_5_n_0\
);
\hessian_out6_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_6_n_0\
);
\hessian_out6_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_7_n_0\
);
\hessian_out6_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__1_n_0\,
CO(3) => \hessian_out6_carry__2_n_0\,
CO(2) => \hessian_out6_carry__2_n_1\,
CO(1) => \hessian_out6_carry__2_n_2\,
CO(0) => \hessian_out6_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__2_i_1_n_0\,
DI(2) => \hessian_out6_carry__2_i_2_n_0\,
DI(1) => \hessian_out6_carry__2_i_3_n_0\,
DI(0) => \hessian_out6_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__2_i_5_n_0\,
S(2) => \hessian_out6_carry__2_i_6_n_0\,
S(1) => \hessian_out6_carry__2_i_7_n_0\,
S(0) => \hessian_out6_carry__2_i_8_n_0\
);
\hessian_out6_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_1_n_0\
);
\hessian_out6_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_2_n_0\
);
\hessian_out6_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_3_n_0\
);
\hessian_out6_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_4_n_0\
);
\hessian_out6_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_5_n_0\
);
\hessian_out6_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_6_n_0\
);
\hessian_out6_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_7_n_0\
);
\hessian_out6_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_8_n_0\
);
hessian_out6_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_1_n_0
);
hessian_out6_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_2_n_0
);
hessian_out6_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_3_n_0
);
hessian_out6_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_4_n_0
);
hessian_out6_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_5_n_0
);
hessian_out6_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_6_n_0
);
hessian_out6_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_7_n_0
);
hessian_out6_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_8_n_0
);
hessian_out7_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out7_carry_n_0,
CO(2) => hessian_out7_carry_n_1,
CO(1) => hessian_out7_carry_n_2,
CO(0) => hessian_out7_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out7_carry_i_1_n_0,
DI(2) => hessian_out7_carry_i_2_n_0,
DI(1) => hessian_out7_carry_i_3_n_0,
DI(0) => hessian_out7_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out7_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out7_carry_i_5_n_0,
S(2) => hessian_out7_carry_i_6_n_0,
S(1) => hessian_out7_carry_i_7_n_0,
S(0) => hessian_out7_carry_i_8_n_0
);
\hessian_out7_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out7_carry_n_0,
CO(3) => \hessian_out7_carry__0_n_0\,
CO(2) => \hessian_out7_carry__0_n_1\,
CO(1) => \hessian_out7_carry__0_n_2\,
CO(0) => \hessian_out7_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__0_i_1_n_0\,
DI(2) => \hessian_out7_carry__0_i_2_n_0\,
DI(1) => \hessian_out7_carry__0_i_3_n_0\,
DI(0) => \hessian_out7_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__0_i_5_n_0\,
S(2) => \hessian_out7_carry__0_i_6_n_0\,
S(1) => \hessian_out7_carry__0_i_7_n_0\,
S(0) => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_1_n_0\
);
\hessian_out7_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_2_n_0\
);
\hessian_out7_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_3_n_0\
);
\hessian_out7_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_4_n_0\
);
\hessian_out7_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_5_n_0\
);
\hessian_out7_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_6_n_0\
);
\hessian_out7_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_7_n_0\
);
\hessian_out7_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__0_n_0\,
CO(3) => \hessian_out7_carry__1_n_0\,
CO(2) => \hessian_out7_carry__1_n_1\,
CO(1) => \hessian_out7_carry__1_n_2\,
CO(0) => \hessian_out7_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__1_i_1_n_0\,
DI(2) => \hessian_out7_carry__1_i_2_n_0\,
DI(1) => \hessian_out7_carry__1_i_3_n_0\,
DI(0) => \hessian_out7_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__1_i_5_n_0\,
S(2) => \hessian_out7_carry__1_i_6_n_0\,
S(1) => \hessian_out7_carry__1_i_7_n_0\,
S(0) => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_1_n_0\
);
\hessian_out7_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_2_n_0\
);
\hessian_out7_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_3_n_0\
);
\hessian_out7_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_4_n_0\
);
\hessian_out7_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_5_n_0\
);
\hessian_out7_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_6_n_0\
);
\hessian_out7_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_7_n_0\
);
\hessian_out7_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__1_n_0\,
CO(3) => \hessian_out7_carry__2_n_0\,
CO(2) => \hessian_out7_carry__2_n_1\,
CO(1) => \hessian_out7_carry__2_n_2\,
CO(0) => \hessian_out7_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__2_i_1_n_0\,
DI(2) => \hessian_out7_carry__2_i_2_n_0\,
DI(1) => \hessian_out7_carry__2_i_3_n_0\,
DI(0) => \hessian_out7_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__2_i_5_n_0\,
S(2) => \hessian_out7_carry__2_i_6_n_0\,
S(1) => \hessian_out7_carry__2_i_7_n_0\,
S(0) => \hessian_out7_carry__2_i_8_n_0\
);
\hessian_out7_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[1]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_1_n_0\
);
\hessian_out7_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_2_n_0\
);
\hessian_out7_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_3_n_0\
);
\hessian_out7_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_4_n_0\
);
\hessian_out7_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[1]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_5_n_0\
);
\hessian_out7_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_6_n_0\
);
\hessian_out7_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_7_n_0\
);
\hessian_out7_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_8_n_0\
);
hessian_out7_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_1_n_0
);
hessian_out7_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_2_n_0
);
hessian_out7_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_3_n_0
);
hessian_out7_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_4_n_0
);
hessian_out7_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_5_n_0
);
hessian_out7_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_6_n_0
);
hessian_out7_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_7_n_0
);
hessian_out7_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_8_n_0
);
\hessian_out8__15_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hessian_out8__15_carry_n_0\,
CO(2) => \hessian_out8__15_carry_n_1\,
CO(1) => \hessian_out8__15_carry_n_2\,
CO(0) => \hessian_out8__15_carry_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry_i_1_n_0\,
DI(2) => \hessian_out8__15_carry_i_2_n_0\,
DI(1) => \hessian_out8__15_carry_i_3_n_0\,
DI(0) => \hessian_out8__15_carry_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry_i_5_n_0\,
S(2) => \hessian_out8__15_carry_i_6_n_0\,
S(1) => \hessian_out8__15_carry_i_7_n_0\,
S(0) => \hessian_out8__15_carry_i_8_n_0\
);
\hessian_out8__15_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry_n_0\,
CO(3) => \hessian_out8__15_carry__0_n_0\,
CO(2) => \hessian_out8__15_carry__0_n_1\,
CO(1) => \hessian_out8__15_carry__0_n_2\,
CO(0) => \hessian_out8__15_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__0_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__0_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__0_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__0_i_5_n_0\,
S(2) => \hessian_out8__15_carry__0_i_6_n_0\,
S(1) => \hessian_out8__15_carry__0_i_7_n_0\,
S(0) => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_1_n_0\
);
\hessian_out8__15_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_2_n_0\
);
\hessian_out8__15_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_3_n_0\
);
\hessian_out8__15_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_4_n_0\
);
\hessian_out8__15_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_5_n_0\
);
\hessian_out8__15_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_6_n_0\
);
\hessian_out8__15_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_7_n_0\
);
\hessian_out8__15_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__0_n_0\,
CO(3) => \hessian_out8__15_carry__1_n_0\,
CO(2) => \hessian_out8__15_carry__1_n_1\,
CO(1) => \hessian_out8__15_carry__1_n_2\,
CO(0) => \hessian_out8__15_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__1_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__1_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__1_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__1_i_5_n_0\,
S(2) => \hessian_out8__15_carry__1_i_6_n_0\,
S(1) => \hessian_out8__15_carry__1_i_7_n_0\,
S(0) => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_1_n_0\
);
\hessian_out8__15_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_2_n_0\
);
\hessian_out8__15_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_3_n_0\
);
\hessian_out8__15_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_4_n_0\
);
\hessian_out8__15_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_5_n_0\
);
\hessian_out8__15_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_6_n_0\
);
\hessian_out8__15_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_7_n_0\
);
\hessian_out8__15_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__1_n_0\,
CO(3) => \hessian_out8__15_carry__2_n_0\,
CO(2) => \hessian_out8__15_carry__2_n_1\,
CO(1) => \hessian_out8__15_carry__2_n_2\,
CO(0) => \hessian_out8__15_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__2_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__2_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__2_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__2_i_5_n_0\,
S(2) => \hessian_out8__15_carry__2_i_6_n_0\,
S(1) => \hessian_out8__15_carry__2_i_7_n_0\,
S(0) => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_1_n_0\
);
\hessian_out8__15_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_2_n_0\
);
\hessian_out8__15_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_3_n_0\
);
\hessian_out8__15_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_4_n_0\
);
\hessian_out8__15_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_5_n_0\
);
\hessian_out8__15_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_6_n_0\
);
\hessian_out8__15_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_7_n_0\
);
\hessian_out8__15_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_1_n_0\
);
\hessian_out8__15_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_2_n_0\
);
\hessian_out8__15_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_3_n_0\
);
\hessian_out8__15_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_4_n_0\
);
\hessian_out8__15_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_5_n_0\
);
\hessian_out8__15_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_6_n_0\
);
\hessian_out8__15_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_7_n_0\
);
\hessian_out8__15_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_8_n_0\
);
hessian_out8_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out8_carry_n_0,
CO(2) => hessian_out8_carry_n_1,
CO(1) => hessian_out8_carry_n_2,
CO(0) => hessian_out8_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out8_carry_i_1_n_0,
DI(2) => hessian_out8_carry_i_2_n_0,
DI(1) => hessian_out8_carry_i_3_n_0,
DI(0) => hessian_out8_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out8_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out8_carry_i_5_n_0,
S(2) => hessian_out8_carry_i_6_n_0,
S(1) => hessian_out8_carry_i_7_n_0,
S(0) => hessian_out8_carry_i_8_n_0
);
\hessian_out8_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out8_carry_n_0,
CO(3) => \hessian_out8_carry__0_n_0\,
CO(2) => \hessian_out8_carry__0_n_1\,
CO(1) => \hessian_out8_carry__0_n_2\,
CO(0) => \hessian_out8_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__0_i_1_n_0\,
DI(2) => \hessian_out8_carry__0_i_2_n_0\,
DI(1) => \hessian_out8_carry__0_i_3_n_0\,
DI(0) => \hessian_out8_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__0_i_5_n_0\,
S(2) => \hessian_out8_carry__0_i_6_n_0\,
S(1) => \hessian_out8_carry__0_i_7_n_0\,
S(0) => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[0]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_1_n_0\
);
\hessian_out8_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[0]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_2_n_0\
);
\hessian_out8_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[0]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_3_n_0\
);
\hessian_out8_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[0]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_4_n_0\
);
\hessian_out8_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[0]\(14),
I2 => \hessian_reg[6]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_5_n_0\
);
\hessian_out8_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[0]\(12),
I2 => \hessian_reg[6]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_6_n_0\
);
\hessian_out8_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[0]\(10),
I2 => \hessian_reg[6]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_7_n_0\
);
\hessian_out8_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[0]\(8),
I2 => \hessian_reg[6]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__0_n_0\,
CO(3) => \hessian_out8_carry__1_n_0\,
CO(2) => \hessian_out8_carry__1_n_1\,
CO(1) => \hessian_out8_carry__1_n_2\,
CO(0) => \hessian_out8_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__1_i_1_n_0\,
DI(2) => \hessian_out8_carry__1_i_2_n_0\,
DI(1) => \hessian_out8_carry__1_i_3_n_0\,
DI(0) => \hessian_out8_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__1_i_5_n_0\,
S(2) => \hessian_out8_carry__1_i_6_n_0\,
S(1) => \hessian_out8_carry__1_i_7_n_0\,
S(0) => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[0]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_1_n_0\
);
\hessian_out8_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[0]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_2_n_0\
);
\hessian_out8_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[0]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_3_n_0\
);
\hessian_out8_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[0]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_4_n_0\
);
\hessian_out8_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[0]\(22),
I2 => \hessian_reg[6]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_5_n_0\
);
\hessian_out8_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[0]\(20),
I2 => \hessian_reg[6]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_6_n_0\
);
\hessian_out8_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[0]\(18),
I2 => \hessian_reg[6]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_7_n_0\
);
\hessian_out8_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[0]\(16),
I2 => \hessian_reg[6]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__1_n_0\,
CO(3) => \hessian_out8_carry__2_n_0\,
CO(2) => \hessian_out8_carry__2_n_1\,
CO(1) => \hessian_out8_carry__2_n_2\,
CO(0) => \hessian_out8_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__2_i_1_n_0\,
DI(2) => \hessian_out8_carry__2_i_2_n_0\,
DI(1) => \hessian_out8_carry__2_i_3_n_0\,
DI(0) => \hessian_out8_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__2_i_5_n_0\,
S(2) => \hessian_out8_carry__2_i_6_n_0\,
S(1) => \hessian_out8_carry__2_i_7_n_0\,
S(0) => \hessian_out8_carry__2_i_8_n_0\
);
\hessian_out8_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[0]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_1_n_0\
);
\hessian_out8_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[0]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_2_n_0\
);
\hessian_out8_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[0]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_3_n_0\
);
\hessian_out8_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[0]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_4_n_0\
);
\hessian_out8_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[0]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_5_n_0\
);
\hessian_out8_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[0]\(28),
I2 => \hessian_reg[6]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_6_n_0\
);
\hessian_out8_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[0]\(26),
I2 => \hessian_reg[6]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_7_n_0\
);
\hessian_out8_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[0]\(24),
I2 => \hessian_reg[6]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_8_n_0\
);
hessian_out8_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[0]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_1_n_0
);
hessian_out8_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[0]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_2_n_0
);
hessian_out8_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[0]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_3_n_0
);
hessian_out8_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[0]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_4_n_0
);
hessian_out8_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[0]\(6),
I2 => \hessian_reg[6]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_5_n_0
);
hessian_out8_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[0]\(4),
I2 => \hessian_reg[6]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_6_n_0
);
hessian_out8_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[0]\(2),
I2 => \hessian_reg[6]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_7_n_0
);
hessian_out8_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[0]\(0),
I2 => \hessian_reg[6]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_8_n_0
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80000"
)
port map (
I0 => active,
I1 => \hessian_out8__15_carry__2_n_0\,
I2 => \hessian_out[31]_i_2_n_0\,
I3 => \hessian_out2_carry__2_n_0\,
I4 => enable,
O => \hessian_out[31]_i_1_n_0\
);
\hessian_out[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \hessian_out3_carry__2_n_0\,
I1 => \hessian_out5_carry__2_n_0\,
I2 => \hessian_out8_carry__2_n_0\,
I3 => \hessian_out7_carry__2_n_0\,
I4 => \hessian_out6_carry__2_n_0\,
I5 => \hessian_out4_carry__2_n_0\,
O => \hessian_out[31]_i_2_n_0\
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => hessian_out(0),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => hessian_out(10),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => hessian_out(11),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => hessian_out(12),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => hessian_out(13),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => hessian_out(14),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => hessian_out(15),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => hessian_out(16),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => hessian_out(17),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => hessian_out(18),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => hessian_out(19),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => hessian_out(1),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => hessian_out(20),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => hessian_out(21),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => hessian_out(22),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => hessian_out(23),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => hessian_out(24),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => hessian_out(25),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => hessian_out(26),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => hessian_out(27),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => hessian_out(28),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => hessian_out(29),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => hessian_out(2),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => hessian_out(30),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => hessian_out(31),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => hessian_out(3),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => hessian_out(4),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => hessian_out(5),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => hessian_out(6),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => hessian_out(7),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => hessian_out(8),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => hessian_out(9),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(0),
Q => \hessian_reg[0]\(0),
R => '0'
);
\hessian_reg[0][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(10),
Q => \hessian_reg[0]\(10),
R => '0'
);
\hessian_reg[0][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(11),
Q => \hessian_reg[0]\(11),
R => '0'
);
\hessian_reg[0][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(12),
Q => \hessian_reg[0]\(12),
R => '0'
);
\hessian_reg[0][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(13),
Q => \hessian_reg[0]\(13),
R => '0'
);
\hessian_reg[0][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(14),
Q => \hessian_reg[0]\(14),
R => '0'
);
\hessian_reg[0][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(15),
Q => \hessian_reg[0]\(15),
R => '0'
);
\hessian_reg[0][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(16),
Q => \hessian_reg[0]\(16),
R => '0'
);
\hessian_reg[0][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(17),
Q => \hessian_reg[0]\(17),
R => '0'
);
\hessian_reg[0][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(18),
Q => \hessian_reg[0]\(18),
R => '0'
);
\hessian_reg[0][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(19),
Q => \hessian_reg[0]\(19),
R => '0'
);
\hessian_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(1),
Q => \hessian_reg[0]\(1),
R => '0'
);
\hessian_reg[0][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(20),
Q => \hessian_reg[0]\(20),
R => '0'
);
\hessian_reg[0][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(21),
Q => \hessian_reg[0]\(21),
R => '0'
);
\hessian_reg[0][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(22),
Q => \hessian_reg[0]\(22),
R => '0'
);
\hessian_reg[0][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(23),
Q => \hessian_reg[0]\(23),
R => '0'
);
\hessian_reg[0][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(24),
Q => \hessian_reg[0]\(24),
R => '0'
);
\hessian_reg[0][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(25),
Q => \hessian_reg[0]\(25),
R => '0'
);
\hessian_reg[0][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(26),
Q => \hessian_reg[0]\(26),
R => '0'
);
\hessian_reg[0][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(27),
Q => \hessian_reg[0]\(27),
R => '0'
);
\hessian_reg[0][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(28),
Q => \hessian_reg[0]\(28),
R => '0'
);
\hessian_reg[0][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(29),
Q => \hessian_reg[0]\(29),
R => '0'
);
\hessian_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(2),
Q => \hessian_reg[0]\(2),
R => '0'
);
\hessian_reg[0][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(30),
Q => \hessian_reg[0]\(30),
R => '0'
);
\hessian_reg[0][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(31),
Q => \hessian_reg[0]\(31),
R => '0'
);
\hessian_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(3),
Q => \hessian_reg[0]\(3),
R => '0'
);
\hessian_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(4),
Q => \hessian_reg[0]\(4),
R => '0'
);
\hessian_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(5),
Q => \hessian_reg[0]\(5),
R => '0'
);
\hessian_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(6),
Q => \hessian_reg[0]\(6),
R => '0'
);
\hessian_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(7),
Q => \hessian_reg[0]\(7),
R => '0'
);
\hessian_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(8),
Q => \hessian_reg[0]\(8),
R => '0'
);
\hessian_reg[0][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(9),
Q => \hessian_reg[0]\(9),
R => '0'
);
\hessian_reg[10][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(0),
Q => \hessian_reg[10]\(0),
R => '0'
);
\hessian_reg[10][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(10),
Q => \hessian_reg[10]\(10),
R => '0'
);
\hessian_reg[10][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(11),
Q => \hessian_reg[10]\(11),
R => '0'
);
\hessian_reg[10][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(12),
Q => \hessian_reg[10]\(12),
R => '0'
);
\hessian_reg[10][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(13),
Q => \hessian_reg[10]\(13),
R => '0'
);
\hessian_reg[10][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(14),
Q => \hessian_reg[10]\(14),
R => '0'
);
\hessian_reg[10][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(15),
Q => \hessian_reg[10]\(15),
R => '0'
);
\hessian_reg[10][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(16),
Q => \hessian_reg[10]\(16),
R => '0'
);
\hessian_reg[10][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(17),
Q => \hessian_reg[10]\(17),
R => '0'
);
\hessian_reg[10][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(18),
Q => \hessian_reg[10]\(18),
R => '0'
);
\hessian_reg[10][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(19),
Q => \hessian_reg[10]\(19),
R => '0'
);
\hessian_reg[10][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(1),
Q => \hessian_reg[10]\(1),
R => '0'
);
\hessian_reg[10][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(20),
Q => \hessian_reg[10]\(20),
R => '0'
);
\hessian_reg[10][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(21),
Q => \hessian_reg[10]\(21),
R => '0'
);
\hessian_reg[10][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(22),
Q => \hessian_reg[10]\(22),
R => '0'
);
\hessian_reg[10][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(23),
Q => \hessian_reg[10]\(23),
R => '0'
);
\hessian_reg[10][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(24),
Q => \hessian_reg[10]\(24),
R => '0'
);
\hessian_reg[10][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(25),
Q => \hessian_reg[10]\(25),
R => '0'
);
\hessian_reg[10][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(26),
Q => \hessian_reg[10]\(26),
R => '0'
);
\hessian_reg[10][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(27),
Q => \hessian_reg[10]\(27),
R => '0'
);
\hessian_reg[10][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(28),
Q => \hessian_reg[10]\(28),
R => '0'
);
\hessian_reg[10][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(29),
Q => \hessian_reg[10]\(29),
R => '0'
);
\hessian_reg[10][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(2),
Q => \hessian_reg[10]\(2),
R => '0'
);
\hessian_reg[10][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(30),
Q => \hessian_reg[10]\(30),
R => '0'
);
\hessian_reg[10][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(31),
Q => \hessian_reg[10]\(31),
R => '0'
);
\hessian_reg[10][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(3),
Q => \hessian_reg[10]\(3),
R => '0'
);
\hessian_reg[10][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(4),
Q => \hessian_reg[10]\(4),
R => '0'
);
\hessian_reg[10][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(5),
Q => \hessian_reg[10]\(5),
R => '0'
);
\hessian_reg[10][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(6),
Q => \hessian_reg[10]\(6),
R => '0'
);
\hessian_reg[10][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(7),
Q => \hessian_reg[10]\(7),
R => '0'
);
\hessian_reg[10][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(8),
Q => \hessian_reg[10]\(8),
R => '0'
);
\hessian_reg[10][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(9),
Q => \hessian_reg[10]\(9),
R => '0'
);
\hessian_reg[11][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(0),
Q => \hessian_reg[11]\(0),
R => '0'
);
\hessian_reg[11][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(10),
Q => \hessian_reg[11]\(10),
R => '0'
);
\hessian_reg[11][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(11),
Q => \hessian_reg[11]\(11),
R => '0'
);
\hessian_reg[11][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(12),
Q => \hessian_reg[11]\(12),
R => '0'
);
\hessian_reg[11][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(13),
Q => \hessian_reg[11]\(13),
R => '0'
);
\hessian_reg[11][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(14),
Q => \hessian_reg[11]\(14),
R => '0'
);
\hessian_reg[11][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(15),
Q => \hessian_reg[11]\(15),
R => '0'
);
\hessian_reg[11][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(16),
Q => \hessian_reg[11]\(16),
R => '0'
);
\hessian_reg[11][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(17),
Q => \hessian_reg[11]\(17),
R => '0'
);
\hessian_reg[11][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(18),
Q => \hessian_reg[11]\(18),
R => '0'
);
\hessian_reg[11][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(19),
Q => \hessian_reg[11]\(19),
R => '0'
);
\hessian_reg[11][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(1),
Q => \hessian_reg[11]\(1),
R => '0'
);
\hessian_reg[11][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(20),
Q => \hessian_reg[11]\(20),
R => '0'
);
\hessian_reg[11][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(21),
Q => \hessian_reg[11]\(21),
R => '0'
);
\hessian_reg[11][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(22),
Q => \hessian_reg[11]\(22),
R => '0'
);
\hessian_reg[11][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(23),
Q => \hessian_reg[11]\(23),
R => '0'
);
\hessian_reg[11][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(24),
Q => \hessian_reg[11]\(24),
R => '0'
);
\hessian_reg[11][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(25),
Q => \hessian_reg[11]\(25),
R => '0'
);
\hessian_reg[11][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(26),
Q => \hessian_reg[11]\(26),
R => '0'
);
\hessian_reg[11][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(27),
Q => \hessian_reg[11]\(27),
R => '0'
);
\hessian_reg[11][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(28),
Q => \hessian_reg[11]\(28),
R => '0'
);
\hessian_reg[11][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(29),
Q => \hessian_reg[11]\(29),
R => '0'
);
\hessian_reg[11][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(2),
Q => \hessian_reg[11]\(2),
R => '0'
);
\hessian_reg[11][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(30),
Q => \hessian_reg[11]\(30),
R => '0'
);
\hessian_reg[11][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(31),
Q => \hessian_reg[11]\(31),
R => '0'
);
\hessian_reg[11][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(3),
Q => \hessian_reg[11]\(3),
R => '0'
);
\hessian_reg[11][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(4),
Q => \hessian_reg[11]\(4),
R => '0'
);
\hessian_reg[11][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(5),
Q => \hessian_reg[11]\(5),
R => '0'
);
\hessian_reg[11][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(6),
Q => \hessian_reg[11]\(6),
R => '0'
);
\hessian_reg[11][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(7),
Q => \hessian_reg[11]\(7),
R => '0'
);
\hessian_reg[11][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(8),
Q => \hessian_reg[11]\(8),
R => '0'
);
\hessian_reg[11][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(9),
Q => \hessian_reg[11]\(9),
R => '0'
);
\hessian_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(0),
Q => \hessian_reg[1]\(0),
R => '0'
);
\hessian_reg[1][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(10),
Q => \hessian_reg[1]\(10),
R => '0'
);
\hessian_reg[1][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(11),
Q => \hessian_reg[1]\(11),
R => '0'
);
\hessian_reg[1][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(12),
Q => \hessian_reg[1]\(12),
R => '0'
);
\hessian_reg[1][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(13),
Q => \hessian_reg[1]\(13),
R => '0'
);
\hessian_reg[1][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(14),
Q => \hessian_reg[1]\(14),
R => '0'
);
\hessian_reg[1][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(15),
Q => \hessian_reg[1]\(15),
R => '0'
);
\hessian_reg[1][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(16),
Q => \hessian_reg[1]\(16),
R => '0'
);
\hessian_reg[1][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(17),
Q => \hessian_reg[1]\(17),
R => '0'
);
\hessian_reg[1][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(18),
Q => \hessian_reg[1]\(18),
R => '0'
);
\hessian_reg[1][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(19),
Q => \hessian_reg[1]\(19),
R => '0'
);
\hessian_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(1),
Q => \hessian_reg[1]\(1),
R => '0'
);
\hessian_reg[1][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(20),
Q => \hessian_reg[1]\(20),
R => '0'
);
\hessian_reg[1][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(21),
Q => \hessian_reg[1]\(21),
R => '0'
);
\hessian_reg[1][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(22),
Q => \hessian_reg[1]\(22),
R => '0'
);
\hessian_reg[1][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(23),
Q => \hessian_reg[1]\(23),
R => '0'
);
\hessian_reg[1][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(24),
Q => \hessian_reg[1]\(24),
R => '0'
);
\hessian_reg[1][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(25),
Q => \hessian_reg[1]\(25),
R => '0'
);
\hessian_reg[1][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(26),
Q => \hessian_reg[1]\(26),
R => '0'
);
\hessian_reg[1][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(27),
Q => \hessian_reg[1]\(27),
R => '0'
);
\hessian_reg[1][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(28),
Q => \hessian_reg[1]\(28),
R => '0'
);
\hessian_reg[1][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(29),
Q => \hessian_reg[1]\(29),
R => '0'
);
\hessian_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(2),
Q => \hessian_reg[1]\(2),
R => '0'
);
\hessian_reg[1][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(30),
Q => \hessian_reg[1]\(30),
R => '0'
);
\hessian_reg[1][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(31),
Q => \hessian_reg[1]\(31),
R => '0'
);
\hessian_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(3),
Q => \hessian_reg[1]\(3),
R => '0'
);
\hessian_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(4),
Q => \hessian_reg[1]\(4),
R => '0'
);
\hessian_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(5),
Q => \hessian_reg[1]\(5),
R => '0'
);
\hessian_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(6),
Q => \hessian_reg[1]\(6),
R => '0'
);
\hessian_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(7),
Q => \hessian_reg[1]\(7),
R => '0'
);
\hessian_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(8),
Q => \hessian_reg[1]\(8),
R => '0'
);
\hessian_reg[1][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(9),
Q => \hessian_reg[1]\(9),
R => '0'
);
\hessian_reg[4][0]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(0),
Q => \hessian_reg[4][0]_srl3_n_0\
);
\hessian_reg[4][10]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(10),
Q => \hessian_reg[4][10]_srl3_n_0\
);
\hessian_reg[4][11]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(11),
Q => \hessian_reg[4][11]_srl3_n_0\
);
\hessian_reg[4][12]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(12),
Q => \hessian_reg[4][12]_srl3_n_0\
);
\hessian_reg[4][13]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(13),
Q => \hessian_reg[4][13]_srl3_n_0\
);
\hessian_reg[4][14]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(14),
Q => \hessian_reg[4][14]_srl3_n_0\
);
\hessian_reg[4][15]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(15),
Q => \hessian_reg[4][15]_srl3_n_0\
);
\hessian_reg[4][16]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(16),
Q => \hessian_reg[4][16]_srl3_n_0\
);
\hessian_reg[4][17]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(17),
Q => \hessian_reg[4][17]_srl3_n_0\
);
\hessian_reg[4][18]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(18),
Q => \hessian_reg[4][18]_srl3_n_0\
);
\hessian_reg[4][19]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(19),
Q => \hessian_reg[4][19]_srl3_n_0\
);
\hessian_reg[4][1]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(1),
Q => \hessian_reg[4][1]_srl3_n_0\
);
\hessian_reg[4][20]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(20),
Q => \hessian_reg[4][20]_srl3_n_0\
);
\hessian_reg[4][21]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(21),
Q => \hessian_reg[4][21]_srl3_n_0\
);
\hessian_reg[4][22]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(22),
Q => \hessian_reg[4][22]_srl3_n_0\
);
\hessian_reg[4][23]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(23),
Q => \hessian_reg[4][23]_srl3_n_0\
);
\hessian_reg[4][24]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(24),
Q => \hessian_reg[4][24]_srl3_n_0\
);
\hessian_reg[4][25]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(25),
Q => \hessian_reg[4][25]_srl3_n_0\
);
\hessian_reg[4][26]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(26),
Q => \hessian_reg[4][26]_srl3_n_0\
);
\hessian_reg[4][27]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(27),
Q => \hessian_reg[4][27]_srl3_n_0\
);
\hessian_reg[4][28]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(28),
Q => \hessian_reg[4][28]_srl3_n_0\
);
\hessian_reg[4][29]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(29),
Q => \hessian_reg[4][29]_srl3_n_0\
);
\hessian_reg[4][2]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(2),
Q => \hessian_reg[4][2]_srl3_n_0\
);
\hessian_reg[4][30]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(30),
Q => \hessian_reg[4][30]_srl3_n_0\
);
\hessian_reg[4][31]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(31),
Q => \hessian_reg[4][31]_srl3_n_0\
);
\hessian_reg[4][3]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(3),
Q => \hessian_reg[4][3]_srl3_n_0\
);
\hessian_reg[4][4]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(4),
Q => \hessian_reg[4][4]_srl3_n_0\
);
\hessian_reg[4][5]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(5),
Q => \hessian_reg[4][5]_srl3_n_0\
);
\hessian_reg[4][6]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(6),
Q => \hessian_reg[4][6]_srl3_n_0\
);
\hessian_reg[4][7]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(7),
Q => \hessian_reg[4][7]_srl3_n_0\
);
\hessian_reg[4][8]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(8),
Q => \hessian_reg[4][8]_srl3_n_0\
);
\hessian_reg[4][9]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(9),
Q => \hessian_reg[4][9]_srl3_n_0\
);
\hessian_reg[5][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][0]_srl3_n_0\,
Q => \hessian_reg[5]\(0),
R => '0'
);
\hessian_reg[5][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][10]_srl3_n_0\,
Q => \hessian_reg[5]\(10),
R => '0'
);
\hessian_reg[5][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][11]_srl3_n_0\,
Q => \hessian_reg[5]\(11),
R => '0'
);
\hessian_reg[5][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][12]_srl3_n_0\,
Q => \hessian_reg[5]\(12),
R => '0'
);
\hessian_reg[5][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][13]_srl3_n_0\,
Q => \hessian_reg[5]\(13),
R => '0'
);
\hessian_reg[5][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][14]_srl3_n_0\,
Q => \hessian_reg[5]\(14),
R => '0'
);
\hessian_reg[5][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][15]_srl3_n_0\,
Q => \hessian_reg[5]\(15),
R => '0'
);
\hessian_reg[5][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][16]_srl3_n_0\,
Q => \hessian_reg[5]\(16),
R => '0'
);
\hessian_reg[5][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][17]_srl3_n_0\,
Q => \hessian_reg[5]\(17),
R => '0'
);
\hessian_reg[5][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][18]_srl3_n_0\,
Q => \hessian_reg[5]\(18),
R => '0'
);
\hessian_reg[5][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][19]_srl3_n_0\,
Q => \hessian_reg[5]\(19),
R => '0'
);
\hessian_reg[5][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][1]_srl3_n_0\,
Q => \hessian_reg[5]\(1),
R => '0'
);
\hessian_reg[5][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][20]_srl3_n_0\,
Q => \hessian_reg[5]\(20),
R => '0'
);
\hessian_reg[5][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][21]_srl3_n_0\,
Q => \hessian_reg[5]\(21),
R => '0'
);
\hessian_reg[5][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][22]_srl3_n_0\,
Q => \hessian_reg[5]\(22),
R => '0'
);
\hessian_reg[5][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][23]_srl3_n_0\,
Q => \hessian_reg[5]\(23),
R => '0'
);
\hessian_reg[5][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][24]_srl3_n_0\,
Q => \hessian_reg[5]\(24),
R => '0'
);
\hessian_reg[5][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][25]_srl3_n_0\,
Q => \hessian_reg[5]\(25),
R => '0'
);
\hessian_reg[5][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][26]_srl3_n_0\,
Q => \hessian_reg[5]\(26),
R => '0'
);
\hessian_reg[5][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][27]_srl3_n_0\,
Q => \hessian_reg[5]\(27),
R => '0'
);
\hessian_reg[5][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][28]_srl3_n_0\,
Q => \hessian_reg[5]\(28),
R => '0'
);
\hessian_reg[5][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][29]_srl3_n_0\,
Q => \hessian_reg[5]\(29),
R => '0'
);
\hessian_reg[5][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][2]_srl3_n_0\,
Q => \hessian_reg[5]\(2),
R => '0'
);
\hessian_reg[5][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][30]_srl3_n_0\,
Q => \hessian_reg[5]\(30),
R => '0'
);
\hessian_reg[5][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][31]_srl3_n_0\,
Q => \hessian_reg[5]\(31),
R => '0'
);
\hessian_reg[5][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][3]_srl3_n_0\,
Q => \hessian_reg[5]\(3),
R => '0'
);
\hessian_reg[5][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][4]_srl3_n_0\,
Q => \hessian_reg[5]\(4),
R => '0'
);
\hessian_reg[5][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][5]_srl3_n_0\,
Q => \hessian_reg[5]\(5),
R => '0'
);
\hessian_reg[5][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][6]_srl3_n_0\,
Q => \hessian_reg[5]\(6),
R => '0'
);
\hessian_reg[5][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][7]_srl3_n_0\,
Q => \hessian_reg[5]\(7),
R => '0'
);
\hessian_reg[5][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][8]_srl3_n_0\,
Q => \hessian_reg[5]\(8),
R => '0'
);
\hessian_reg[5][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][9]_srl3_n_0\,
Q => \hessian_reg[5]\(9),
R => '0'
);
\hessian_reg[6][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(0),
Q => \hessian_reg[6]\(0),
R => '0'
);
\hessian_reg[6][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(10),
Q => \hessian_reg[6]\(10),
R => '0'
);
\hessian_reg[6][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(11),
Q => \hessian_reg[6]\(11),
R => '0'
);
\hessian_reg[6][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(12),
Q => \hessian_reg[6]\(12),
R => '0'
);
\hessian_reg[6][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(13),
Q => \hessian_reg[6]\(13),
R => '0'
);
\hessian_reg[6][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(14),
Q => \hessian_reg[6]\(14),
R => '0'
);
\hessian_reg[6][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(15),
Q => \hessian_reg[6]\(15),
R => '0'
);
\hessian_reg[6][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(16),
Q => \hessian_reg[6]\(16),
R => '0'
);
\hessian_reg[6][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(17),
Q => \hessian_reg[6]\(17),
R => '0'
);
\hessian_reg[6][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(18),
Q => \hessian_reg[6]\(18),
R => '0'
);
\hessian_reg[6][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(19),
Q => \hessian_reg[6]\(19),
R => '0'
);
\hessian_reg[6][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(1),
Q => \hessian_reg[6]\(1),
R => '0'
);
\hessian_reg[6][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(20),
Q => \hessian_reg[6]\(20),
R => '0'
);
\hessian_reg[6][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(21),
Q => \hessian_reg[6]\(21),
R => '0'
);
\hessian_reg[6][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(22),
Q => \hessian_reg[6]\(22),
R => '0'
);
\hessian_reg[6][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(23),
Q => \hessian_reg[6]\(23),
R => '0'
);
\hessian_reg[6][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(24),
Q => \hessian_reg[6]\(24),
R => '0'
);
\hessian_reg[6][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(25),
Q => \hessian_reg[6]\(25),
R => '0'
);
\hessian_reg[6][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(26),
Q => \hessian_reg[6]\(26),
R => '0'
);
\hessian_reg[6][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(27),
Q => \hessian_reg[6]\(27),
R => '0'
);
\hessian_reg[6][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(28),
Q => \hessian_reg[6]\(28),
R => '0'
);
\hessian_reg[6][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(29),
Q => \hessian_reg[6]\(29),
R => '0'
);
\hessian_reg[6][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(2),
Q => \hessian_reg[6]\(2),
R => '0'
);
\hessian_reg[6][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(30),
Q => \hessian_reg[6]\(30),
R => '0'
);
\hessian_reg[6][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(31),
Q => \hessian_reg[6]\(31),
R => '0'
);
\hessian_reg[6][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(3),
Q => \hessian_reg[6]\(3),
R => '0'
);
\hessian_reg[6][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(4),
Q => \hessian_reg[6]\(4),
R => '0'
);
\hessian_reg[6][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(5),
Q => \hessian_reg[6]\(5),
R => '0'
);
\hessian_reg[6][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(6),
Q => \hessian_reg[6]\(6),
R => '0'
);
\hessian_reg[6][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(7),
Q => \hessian_reg[6]\(7),
R => '0'
);
\hessian_reg[6][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(8),
Q => \hessian_reg[6]\(8),
R => '0'
);
\hessian_reg[6][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(9),
Q => \hessian_reg[6]\(9),
R => '0'
);
\hessian_reg[7][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => \hessian_reg[7]\(0),
R => '0'
);
\hessian_reg[7][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => \hessian_reg[7]\(10),
R => '0'
);
\hessian_reg[7][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => \hessian_reg[7]\(11),
R => '0'
);
\hessian_reg[7][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => \hessian_reg[7]\(12),
R => '0'
);
\hessian_reg[7][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => \hessian_reg[7]\(13),
R => '0'
);
\hessian_reg[7][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => \hessian_reg[7]\(14),
R => '0'
);
\hessian_reg[7][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => \hessian_reg[7]\(15),
R => '0'
);
\hessian_reg[7][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => \hessian_reg[7]\(16),
R => '0'
);
\hessian_reg[7][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => \hessian_reg[7]\(17),
R => '0'
);
\hessian_reg[7][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => \hessian_reg[7]\(18),
R => '0'
);
\hessian_reg[7][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => \hessian_reg[7]\(19),
R => '0'
);
\hessian_reg[7][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => \hessian_reg[7]\(1),
R => '0'
);
\hessian_reg[7][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => \hessian_reg[7]\(20),
R => '0'
);
\hessian_reg[7][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => \hessian_reg[7]\(21),
R => '0'
);
\hessian_reg[7][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => \hessian_reg[7]\(22),
R => '0'
);
\hessian_reg[7][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => \hessian_reg[7]\(23),
R => '0'
);
\hessian_reg[7][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => \hessian_reg[7]\(24),
R => '0'
);
\hessian_reg[7][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => \hessian_reg[7]\(25),
R => '0'
);
\hessian_reg[7][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => \hessian_reg[7]\(26),
R => '0'
);
\hessian_reg[7][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => \hessian_reg[7]\(27),
R => '0'
);
\hessian_reg[7][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => \hessian_reg[7]\(28),
R => '0'
);
\hessian_reg[7][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => \hessian_reg[7]\(29),
R => '0'
);
\hessian_reg[7][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => \hessian_reg[7]\(2),
R => '0'
);
\hessian_reg[7][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => \hessian_reg[7]\(30),
R => '0'
);
\hessian_reg[7][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => \hessian_reg[7]\(31),
R => '0'
);
\hessian_reg[7][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => \hessian_reg[7]\(3),
R => '0'
);
\hessian_reg[7][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => \hessian_reg[7]\(4),
R => '0'
);
\hessian_reg[7][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => \hessian_reg[7]\(5),
R => '0'
);
\hessian_reg[7][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => \hessian_reg[7]\(6),
R => '0'
);
\hessian_reg[7][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => \hessian_reg[7]\(7),
R => '0'
);
\hessian_reg[7][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => \hessian_reg[7]\(8),
R => '0'
);
\hessian_reg[7][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => \hessian_reg[7]\(9),
R => '0'
);
\hessian_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(0),
Q => \hessian_reg[8]\(0),
R => '0'
);
\hessian_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(10),
Q => \hessian_reg[8]\(10),
R => '0'
);
\hessian_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(11),
Q => \hessian_reg[8]\(11),
R => '0'
);
\hessian_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(12),
Q => \hessian_reg[8]\(12),
R => '0'
);
\hessian_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(13),
Q => \hessian_reg[8]\(13),
R => '0'
);
\hessian_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(14),
Q => \hessian_reg[8]\(14),
R => '0'
);
\hessian_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(15),
Q => \hessian_reg[8]\(15),
R => '0'
);
\hessian_reg[8][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(16),
Q => \hessian_reg[8]\(16),
R => '0'
);
\hessian_reg[8][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(17),
Q => \hessian_reg[8]\(17),
R => '0'
);
\hessian_reg[8][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(18),
Q => \hessian_reg[8]\(18),
R => '0'
);
\hessian_reg[8][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(19),
Q => \hessian_reg[8]\(19),
R => '0'
);
\hessian_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(1),
Q => \hessian_reg[8]\(1),
R => '0'
);
\hessian_reg[8][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(20),
Q => \hessian_reg[8]\(20),
R => '0'
);
\hessian_reg[8][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(21),
Q => \hessian_reg[8]\(21),
R => '0'
);
\hessian_reg[8][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(22),
Q => \hessian_reg[8]\(22),
R => '0'
);
\hessian_reg[8][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(23),
Q => \hessian_reg[8]\(23),
R => '0'
);
\hessian_reg[8][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(24),
Q => \hessian_reg[8]\(24),
R => '0'
);
\hessian_reg[8][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(25),
Q => \hessian_reg[8]\(25),
R => '0'
);
\hessian_reg[8][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(26),
Q => \hessian_reg[8]\(26),
R => '0'
);
\hessian_reg[8][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(27),
Q => \hessian_reg[8]\(27),
R => '0'
);
\hessian_reg[8][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(28),
Q => \hessian_reg[8]\(28),
R => '0'
);
\hessian_reg[8][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(29),
Q => \hessian_reg[8]\(29),
R => '0'
);
\hessian_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(2),
Q => \hessian_reg[8]\(2),
R => '0'
);
\hessian_reg[8][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(30),
Q => \hessian_reg[8]\(30),
R => '0'
);
\hessian_reg[8][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(31),
Q => \hessian_reg[8]\(31),
R => '0'
);
\hessian_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(3),
Q => \hessian_reg[8]\(3),
R => '0'
);
\hessian_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(4),
Q => \hessian_reg[8]\(4),
R => '0'
);
\hessian_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(5),
Q => \hessian_reg[8]\(5),
R => '0'
);
\hessian_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(6),
Q => \hessian_reg[8]\(6),
R => '0'
);
\hessian_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(7),
Q => \hessian_reg[8]\(7),
R => '0'
);
\hessian_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(8),
Q => \hessian_reg[8]\(8),
R => '0'
);
\hessian_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(9),
Q => \hessian_reg[8]\(9),
R => '0'
);
\hessian_reg[9][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(0),
Q => \hessian_reg[9]\(0),
R => '0'
);
\hessian_reg[9][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(10),
Q => \hessian_reg[9]\(10),
R => '0'
);
\hessian_reg[9][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(11),
Q => \hessian_reg[9]\(11),
R => '0'
);
\hessian_reg[9][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(12),
Q => \hessian_reg[9]\(12),
R => '0'
);
\hessian_reg[9][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(13),
Q => \hessian_reg[9]\(13),
R => '0'
);
\hessian_reg[9][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(14),
Q => \hessian_reg[9]\(14),
R => '0'
);
\hessian_reg[9][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(15),
Q => \hessian_reg[9]\(15),
R => '0'
);
\hessian_reg[9][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(16),
Q => \hessian_reg[9]\(16),
R => '0'
);
\hessian_reg[9][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(17),
Q => \hessian_reg[9]\(17),
R => '0'
);
\hessian_reg[9][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(18),
Q => \hessian_reg[9]\(18),
R => '0'
);
\hessian_reg[9][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(19),
Q => \hessian_reg[9]\(19),
R => '0'
);
\hessian_reg[9][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(1),
Q => \hessian_reg[9]\(1),
R => '0'
);
\hessian_reg[9][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(20),
Q => \hessian_reg[9]\(20),
R => '0'
);
\hessian_reg[9][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(21),
Q => \hessian_reg[9]\(21),
R => '0'
);
\hessian_reg[9][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(22),
Q => \hessian_reg[9]\(22),
R => '0'
);
\hessian_reg[9][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(23),
Q => \hessian_reg[9]\(23),
R => '0'
);
\hessian_reg[9][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(24),
Q => \hessian_reg[9]\(24),
R => '0'
);
\hessian_reg[9][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(25),
Q => \hessian_reg[9]\(25),
R => '0'
);
\hessian_reg[9][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(26),
Q => \hessian_reg[9]\(26),
R => '0'
);
\hessian_reg[9][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(27),
Q => \hessian_reg[9]\(27),
R => '0'
);
\hessian_reg[9][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(28),
Q => \hessian_reg[9]\(28),
R => '0'
);
\hessian_reg[9][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(29),
Q => \hessian_reg[9]\(29),
R => '0'
);
\hessian_reg[9][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(2),
Q => \hessian_reg[9]\(2),
R => '0'
);
\hessian_reg[9][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(30),
Q => \hessian_reg[9]\(30),
R => '0'
);
\hessian_reg[9][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(31),
Q => \hessian_reg[9]\(31),
R => '0'
);
\hessian_reg[9][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(3),
Q => \hessian_reg[9]\(3),
R => '0'
);
\hessian_reg[9][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(4),
Q => \hessian_reg[9]\(4),
R => '0'
);
\hessian_reg[9][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(5),
Q => \hessian_reg[9]\(5),
R => '0'
);
\hessian_reg[9][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(6),
Q => \hessian_reg[9]\(6),
R => '0'
);
\hessian_reg[9][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(7),
Q => \hessian_reg[9]\(7),
R => '0'
);
\hessian_reg[9][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(8),
Q => \hessian_reg[9]\(8),
R => '0'
);
\hessian_reg[9][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(9),
Q => \hessian_reg[9]\(9),
R => '0'
);
\minusOp_inferred__0/y_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => y_addr_in(0),
O => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\
);
\minusOp_inferred__0/y_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x_addr_in(0),
O => minusOp(0)
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x_addr_in(0),
I1 => x_addr_in(1),
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(1),
I1 => x_addr_in(0),
I2 => x_addr_in(2),
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(2),
I1 => x_addr_in(0),
I2 => x_addr_in(1),
I3 => x_addr_in(3),
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(3),
I1 => x_addr_in(1),
I2 => x_addr_in(0),
I3 => x_addr_in(2),
I4 => x_addr_in(4),
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_addr_out[9]_i_2_n_0\,
I1 => x_addr_in(6),
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(6),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(7),
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(7),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(6),
I3 => x_addr_in(8),
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(8),
I1 => x_addr_in(6),
I2 => \x_addr_out[9]_i_2_n_0\,
I3 => x_addr_in(7),
I4 => x_addr_in(9),
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[9]_i_2_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => minusOp(0),
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
\y_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => y_addr_in(0),
I1 => y_addr_in(1),
O => \y_addr_out[1]_i_1_n_0\
);
\y_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(1),
I1 => y_addr_in(0),
I2 => y_addr_in(2),
O => \y_addr_out[2]_i_1_n_0\
);
\y_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(2),
I1 => y_addr_in(0),
I2 => y_addr_in(1),
I3 => y_addr_in(3),
O => \y_addr_out[3]_i_1_n_0\
);
\y_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(3),
I1 => y_addr_in(1),
I2 => y_addr_in(0),
I3 => y_addr_in(2),
I4 => y_addr_in(4),
O => \y_addr_out[4]_i_1_n_0\
);
\y_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \y_addr_out[5]_i_1_n_0\
);
\y_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I1 => y_addr_in(6),
O => \y_addr_out[6]_i_1_n_0\
);
\y_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(6),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(7),
O => \y_addr_out[7]_i_1_n_0\
);
\y_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(7),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(6),
I3 => y_addr_in(8),
O => \y_addr_out[8]_i_1_n_0\
);
\y_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(8),
I1 => y_addr_in(6),
I2 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I3 => y_addr_in(7),
I4 => y_addr_in(9),
O => \y_addr_out[9]_i_1_n_0\
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\,
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[1]_i_1_n_0\,
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[2]_i_1_n_0\,
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[3]_i_1_n_0\,
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[4]_i_1_n_0\,
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[5]_i_1_n_0\,
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[6]_i_1_n_0\,
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[7]_i_1_n_0\,
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[8]_i_1_n_0\,
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[9]_i_1_n_0\,
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_nmsuppression_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_nmsuppression_0_0 : entity is "system_vga_nmsuppression_0_0,vga_nmsuppression,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_nmsuppression_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_nmsuppression_0_0 : entity is "vga_nmsuppression,Vivado 2016.4";
end system_vga_nmsuppression_0_0;
architecture STRUCTURE of system_vga_nmsuppression_0_0 is
begin
U0: entity work.system_vga_nmsuppression_0_0_vga_nmsuppression
port map (
active => active,
clk => clk,
enable => enable,
hessian_in(31 downto 0) => hessian_in(31 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
| mit | 0c63b164e90fd7da877412574445bab8 | 0.507156 | 2.525724 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/sim/system_vga_hessian_0_0.vhd | 1 | 3,768 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 40
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit | a4a669262d20d7de14d47d6788d6deb6 | 0.710456 | 3.809909 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/synth/system_comparator_0_0.vhd | 1 | 3,787 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:comparator:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_comparator_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC
);
END system_comparator_0_0;
ARCHITECTURE system_comparator_0_0_arch OF system_comparator_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_comparator_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT comparator IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC
);
END COMPONENT comparator;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_comparator_0_0_arch: ARCHITECTURE IS "comparator,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_comparator_0_0_arch : ARCHITECTURE IS "system_comparator_0_0,comparator,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_comparator_0_0_arch: ARCHITECTURE IS "system_comparator_0_0,comparator,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=comparator,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=32}";
BEGIN
U0 : comparator
GENERIC MAP (
WIDTH => 32
)
PORT MAP (
x => x,
y => y,
z => z
);
END system_comparator_0_0_arch;
| mit | b58ec149856de9e6fa13653a246977b7 | 0.736731 | 4.050267 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl | 1 | 3,209 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:50 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0_clock_splitter is
port (
clk_out : out STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clock_splitter_0_0_clock_splitter : entity is "clock_splitter";
end system_clock_splitter_0_0_clock_splitter;
architecture STRUCTURE of system_clock_splitter_0_0_clock_splitter is
signal clk_i_1_n_0 : STD_LOGIC;
signal \^clk_out\ : STD_LOGIC;
signal last_edge : STD_LOGIC;
begin
clk_out <= \^clk_out\;
clk_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => latch_edge,
I1 => last_edge,
I2 => \^clk_out\,
O => clk_i_1_n_0
);
clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => clk_i_1_n_0,
Q => \^clk_out\,
R => '0'
);
last_edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_in,
CE => '1',
D => latch_edge,
Q => last_edge,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clock_splitter_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_clock_splitter_0_0 : entity is "system_clock_splitter_0_0,clock_splitter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_clock_splitter_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_clock_splitter_0_0 : entity is "clock_splitter,Vivado 2016.4";
end system_clock_splitter_0_0;
architecture STRUCTURE of system_clock_splitter_0_0 is
begin
U0: entity work.system_clock_splitter_0_0_clock_splitter
port map (
clk_in => clk_in,
clk_out => clk_out,
latch_edge => latch_edge
);
end STRUCTURE;
| mit | fd4056335897aa2be1a943e4d70930d9 | 0.623559 | 3.491839 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cache/cpu_l1mem_data_cache_ctrl-rtl.vhdl | 1 | 144,322 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012-2014, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
-- pragma translate_off
use util.names_pkg.all;
library sim;
use sim.options_pkg.all;
use sim.monitor_pkg.all;
-- pragma translate_on
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_mmu_data_types_pkg.all;
use work.cpu_types_pkg.all;
library tech;
architecture rtl of cpu_l1mem_data_cache_ctrl is
-- There are 3 main subsystems:
-- Request subsystem: Handles a request from the pipeline.
-- Tracks the current request, determines which structures to access depending on the request made.
-- STB subsystem: The store buffer
-- Bus subsystem: manages off-core requests.
-- Tracks the current off-core request, handles cache-line fills and writebacks.
-- Cache has 4 parts: vram, mram, tram, dram.
-- Cache is passive and controlled by the 3 subsystems above.
-- All 3 subsystems can access the cache.
-- The subsystem currently accessing it is called its "owner".
-- Each component of the cache (vram, mram, tram, dram) can have a different, unique owner.
-- This allows e.g. the dram write for a store to occur in parallel with the tag check
-- for a store immediately after.
-- (A store that immediately precedes a load will usually have to wait for the load to
-- complete before completing itself.)
-- The bus can be accessed by a request or the STB, also be uniquely owned by either the STB or the request.
-- A fill/writeback may be performed on behalf of a request, in which case the request will have
-- ownership of the bus, and the bus will have ownership of the cache.
-- Cached load accesses vram, mram, tram, dram for all ways, replace, and mmu in parallel.
-- Cache hit is detected and result data is returned to pipeline in the same cycle.
-- Cached store accesses vram, mram, tram for all ways, replace, and mmu in parallel.
-- Cache hit is detected and address & data are written to stb.
-- cached load request: want vram, mram, tram, dram, replace
-- cached store request: want vram, tram
-- invalidate request: want vram
-- writeback/flush request: want vram, mram, tram
-- stb cache hit: want mram, dram, replace
-- stb cache miss: want vram, mram, tram, dram, replace
type request_type is record
code : cpu_l1mem_data_request_code_type;
be : std_ulogic;
cacheen : std_ulogic;
mmuen : std_ulogic;
writethrough : std_ulogic;
priv : std_ulogic;
alloc : std_ulogic;
end record;
constant request_x : request_type := (
code => (others => 'X'),
be => 'X',
cacheen => 'X',
mmuen => 'X',
writethrough => 'X',
priv => 'X',
alloc => 'X'
);
constant request_init : request_type := (
code => cpu_l1mem_data_request_code_none,
be => 'X',
cacheen => 'X',
mmuen => 'X',
writethrough => 'X',
priv => 'X',
alloc => 'X'
);
type request_state_index_type is (
request_state_index_none,
request_state_index_uncached_load_mmu_access,
request_state_index_uncached_load_bus_op,
request_state_index_uncached_store_mmu_access,
request_state_index_uncached_store_bus_op,
request_state_index_cached_load_l1_access,
request_state_index_cached_load_writeback,
request_state_index_cached_load_fill,
request_state_index_cached_store_stb_wait,
request_state_index_cached_store_l1_access,
request_state_index_invalidate_sync,
request_state_index_invalidate_l1_access,
request_state_index_writeback_sync,
request_state_index_writeback_l1_access,
request_state_index_writeback_bus_op,
request_state_index_flush_sync,
request_state_index_flush_l1_access,
request_state_index_flush_bus_op,
request_state_index_flush_invalidate_l1_access,
request_state_index_sync
);
type request_state_type is
array (request_state_index_type range
request_state_index_type'high downto
request_state_index_type'low) of std_ulogic;
constant request_state_none : request_state_type := "00000000000000000001";
constant request_state_uncached_load_mmu_access : request_state_type := "00000000000000000010";
constant request_state_uncached_load_bus_op : request_state_type := "00000000000000000100";
constant request_state_uncached_store_mmu_access : request_state_type := "00000000000000001000";
constant request_state_uncached_store_bus_op : request_state_type := "00000000000000010000";
constant request_state_cached_load_l1_access : request_state_type := "00000000000000100000";
constant request_state_cached_load_writeback : request_state_type := "00000000000001000000";
constant request_state_cached_load_fill : request_state_type := "00000000000010000000";
constant request_state_cached_store_stb_wait : request_state_type := "00000000000100000000";
constant request_state_cached_store_l1_access : request_state_type := "00000000001000000000";
constant request_state_invalidate_sync : request_state_type := "00000000010000000000";
constant request_state_invalidate_l1_access : request_state_type := "00000000100000000000";
constant request_state_writeback_sync : request_state_type := "00000001000000000000";
constant request_state_writeback_l1_access : request_state_type := "00000010000000000000";
constant request_state_writeback_bus_op : request_state_type := "00000100000000000000";
constant request_state_flush_sync : request_state_type := "00001000000000000000";
constant request_state_flush_l1_access : request_state_type := "00010000000000000000";
constant request_state_flush_bus_op : request_state_type := "00100000000000000000";
constant request_state_flush_invalidate_l1_access : request_state_type := "01000000000000000000";
constant request_state_sync : request_state_type := "10000000000000000000";
type bus_op_code_index_type is (
bus_op_code_index_none,
bus_op_code_index_load,
bus_op_code_index_store,
bus_op_code_index_fill,
bus_op_code_index_writeback
);
type bus_op_code_type is
array (bus_op_code_index_type range
bus_op_code_index_type'high downto
bus_op_code_index_type'low) of std_ulogic;
constant bus_op_code_none : bus_op_code_type := "00001";
constant bus_op_code_load : bus_op_code_type := "00010";
constant bus_op_code_store : bus_op_code_type := "00100";
constant bus_op_code_fill : bus_op_code_type := "01000";
constant bus_op_code_writeback : bus_op_code_type := "10000";
type bus_op_state_index_type is (
bus_op_state_index_none,
bus_op_state_index_load,
bus_op_state_index_store,
bus_op_state_index_fill_first,
bus_op_state_index_fill,
bus_op_state_index_fill_last,
bus_op_state_index_writeback_first,
bus_op_state_index_writeback,
bus_op_state_index_writeback_last
);
type bus_op_state_type is
array (bus_op_state_index_type range
bus_op_state_index_type'high downto
bus_op_state_index_type'low) of std_ulogic;
constant bus_op_state_none : bus_op_state_type := "000000001";
constant bus_op_state_load : bus_op_state_type := "000000010";
constant bus_op_state_store : bus_op_state_type := "000000100";
constant bus_op_state_fill_first : bus_op_state_type := "000001000";
constant bus_op_state_fill : bus_op_state_type := "000010000";
constant bus_op_state_fill_last : bus_op_state_type := "000100000";
constant bus_op_state_writeback_first : bus_op_state_type := "001000000";
constant bus_op_state_writeback : bus_op_state_type := "010000000";
constant bus_op_state_writeback_last : bus_op_state_type := "100000000";
type bus_op_type is record
code : bus_op_code_type;
way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
be : std_ulogic;
priv : std_ulogic;
end record;
constant bus_op_x : bus_op_type := (
code => (others => 'X'),
way => (others => 'X'),
be => 'X',
priv => 'X'
);
constant bus_op_init : bus_op_type := (
code => bus_op_code_none,
way => (others => 'X'),
be => 'X',
priv => 'X'
);
type stb_state_index_type is (
stb_state_index_init,
stb_state_index_replace_access,
stb_state_index_writeback,
stb_state_index_fill,
stb_state_index_write
);
type stb_state_type is
array (stb_state_index_type range
stb_state_index_type'high downto
stb_state_index_type'low) of std_ulogic;
constant stb_state_init : stb_state_type := "00001";
constant stb_state_replace_access : stb_state_type := "00010";
constant stb_state_writeback : stb_state_type := "00100";
constant stb_state_fill : stb_state_type := "01000";
constant stb_state_write : stb_state_type := "10000";
subtype stb_ptr_type is std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
pure function stb_ptr_init return stb_ptr_type is
variable ret : stb_ptr_type;
begin
if cpu_l1mem_data_cache_stb_entries > 0 then
ret := (0 => '1', others => '0');
end if;
return ret;
end function;
type reg_type is record
b_vtram_owner : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner : cpu_l1mem_data_cache_owner_type;
b_bus_op_owner : cpu_l1mem_data_cache_owner_type;
b_request_granted : std_ulogic;
b_request : request_type;
b_request_state : request_state_type;
b_request_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_mmu_accessed : std_ulogic;
b_request_cache_block_dirty : std_ulogic;
b_bus_op_granted : std_ulogic;
b_bus_op_state : bus_op_state_type;
b_bus_op_cacheable : std_ulogic;
b_bus_op_be : std_ulogic;
b_bus_op_priv : std_ulogic;
b_bus_op_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_bus_op_block_word : std_ulogic_vector(cpu_l1mem_data_cache_block_words-1 downto 0);
b_bus_op_requested : std_ulogic;
b_stb_state : stb_state_type;
b_stb_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_head_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_tail_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_write_cache : std_ulogic;
b_stb_write_bus : std_ulogic;
b_stb_array_valid : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_alloc : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_writethrough : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_be : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_priv : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_cache_hit : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_way : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_assoc-1 downto 0);
end record;
constant reg_x : reg_type := (
b_vtram_owner => (others => 'X'),
b_rmdram_owner => (others => 'X'),
b_bus_op_owner => (others => 'X'),
b_request_granted => 'X',
b_request => request_x,
b_request_state => (others => 'X'),
b_request_way => (others => 'X'),
b_request_mmu_accessed => 'X',
b_request_cache_block_dirty => 'X',
b_bus_op_granted => 'X',
b_bus_op_state => (others => 'X'),
b_bus_op_cacheable => 'X',
b_bus_op_be => 'X',
b_bus_op_priv => 'X',
b_bus_op_way => (others => 'X'),
b_bus_op_block_word => (others => 'X'),
b_bus_op_requested => 'X',
b_stb_state => (others => 'X'),
b_stb_way => (others => 'X'),
b_stb_head_ptr => (others => 'X'),
b_stb_tail_ptr => (others => 'X'),
b_stb_write_cache => 'X',
b_stb_write_bus => 'X',
b_stb_array_valid => (others => 'X'),
b_stb_array_alloc => (others => 'X'),
b_stb_array_writethrough => (others => 'X'),
b_stb_array_be => (others => 'X'),
b_stb_array_priv => (others => 'X'),
b_stb_array_cache_hit => (others => 'X'),
b_stb_array_way => (others => (others => 'X'))
);
constant reg_init : reg_type := (
b_vtram_owner => cpu_l1mem_data_cache_owner_none,
b_rmdram_owner => cpu_l1mem_data_cache_owner_none,
b_bus_op_owner => cpu_l1mem_data_cache_owner_none,
b_request_granted => 'X',
b_request => request_init,
b_request_state => request_state_none,
b_request_way => (others => 'X'),
b_request_mmu_accessed => 'X',
b_request_cache_block_dirty => 'X',
b_bus_op_granted => 'X',
b_bus_op_state => bus_op_state_none,
b_bus_op_cacheable => 'X',
b_bus_op_be => 'X',
b_bus_op_priv => 'X',
b_bus_op_way => (others => 'X'),
b_bus_op_block_word => (others => 'X'),
b_bus_op_requested => 'X',
b_stb_state => stb_state_init,
b_stb_way => (others => 'X'),
b_stb_head_ptr => stb_ptr_init,
b_stb_tail_ptr => stb_ptr_init,
b_stb_write_cache => 'X',
b_stb_write_bus => 'X',
b_stb_array_valid => (others => '0'),
b_stb_array_alloc => (others => 'X'),
b_stb_array_writethrough => (others => 'X'),
b_stb_array_be => (others => 'X'),
b_stb_array_priv => (others => 'X'),
b_stb_array_cache_hit => (others => 'X'),
b_stb_array_way => (others => (others => 'X'))
);
type comb_type is record
b_vram_rdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_vram_rdata_all_ones : std_ulogic;
b_vram_rdata_first_free : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_mram_rdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_replace_rway : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_replace_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_replace_way_valid : std_ulogic;
b_replace_way_dirty : std_ulogic;
b_bus_op_error : std_ulogic;
b_bus_op_cycle_complete : std_ulogic;
b_bus_op_fill_load_data_ready : std_ulogic;
b_bus_op_fill_complete : std_ulogic;
b_bus_op_writeback_complete : std_ulogic;
b_bus_op_complete_no_error : std_ulogic;
b_bus_op_complete : std_ulogic;
b_bus_op_state_next_fill_first : bus_op_state_type;
b_bus_op_state_next_fill : bus_op_state_type;
b_bus_op_state_next_fill_last : bus_op_state_type;
b_bus_op_state_next_writeback_first : bus_op_state_type;
b_bus_op_state_next_writeback : bus_op_state_type;
b_bus_op_state_next_writeback_last : bus_op_state_type;
b_bus_op_state_next_no_error : bus_op_state_type;
b_bus_op_state_next : bus_op_state_type;
b_bus_op_block_word_advance : std_ulogic;
b_bus_op_block_word_next : std_ulogic_vector(cpu_l1mem_data_cache_block_words-1 downto 0);
b_bus_op_vram_we : std_ulogic;
b_bus_op_vram_wdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_bus_op_mram_we : std_ulogic;
b_bus_op_mram_wdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_bus_op_replace_we : std_ulogic;
b_bus_op_replace_wway : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_block_change : std_ulogic;
b_block_change_valid : std_ulogic;
b_block_change_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_full : std_ulogic;
b_stb_empty : std_ulogic;
b_stb_state_next_replace_access : stb_state_type;
b_stb_state_next_writeback : stb_state_type;
b_stb_state_next_fill : stb_state_type;
b_stb_state_next_write : stb_state_type;
b_stb_state_next : stb_state_type;
b_stb_mram_we : std_ulogic;
b_stb_mram_wdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_replace_we : std_ulogic;
b_stb_replace_wway : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_pop_write : std_ulogic;
b_stb_pop : std_ulogic;
b_stb_head_ptr_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_can_push : std_ulogic;
b_request_sync : std_ulogic;
b_request_mmu_result_ready : std_ulogic;
b_request_mmu_result_valid : std_ulogic;
b_request_mmu_error : std_ulogic;
b_request_cache_way_hit : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_cache_hit : std_ulogic;
b_request_cache_miss : std_ulogic;
b_request_cache_way_hit_dirty : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_cache_hit_dirty : std_ulogic;
b_request_cache_way_hit_clean : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_cache_hit_clean : std_ulogic;
b_request_cache_block_valid : std_ulogic;
b_request_cache_block_dirty : std_ulogic;
b_request_stb_array_hit : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_conflict : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_hit : std_ulogic;
b_request_stb_head_hit : std_ulogic;
b_request_stb_conflict : std_ulogic;
b_request_stb_can_combine : std_ulogic;
b_request_complete_uncached_mmu_access : std_ulogic;
b_request_complete_uncached_bus_op : std_ulogic;
b_request_complete_cached_load_l1_access : std_ulogic;
b_request_complete_cached_load_fill : std_ulogic;
b_request_complete_cached_store_l1_access : std_ulogic;
b_request_complete_invalidate_l1_access : std_ulogic;
b_request_complete_writeback_l1_access : std_ulogic;
b_request_complete_writeback_bus_op : std_ulogic;
b_request_complete_flush_l1_access : std_ulogic;
b_request_complete_flush_bus_op : std_ulogic;
b_request_complete_sync : std_ulogic;
b_request_complete_no_error : std_ulogic;
b_request_complete : std_ulogic;
b_request_way_next : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_state_next_uncached_load_mmu_access : request_state_type;
b_request_state_next_uncached_store_mmu_access : request_state_type;
b_request_state_next_cached_load_l1_access : request_state_type;
b_request_state_next_cached_load_writeback : request_state_type;
b_request_state_next_cached_store_l1_access : request_state_type;
b_request_state_next_cached_store_stb_wait : request_state_type;
b_request_state_next_writeback_l1_access : request_state_type;
b_request_state_next_writeback_bus_op : request_state_type;
b_request_state_next_invalidate_sync : request_state_type;
b_request_state_next_writeback_sync : request_state_type;
b_request_state_next_flush_sync : request_state_type;
b_request_state_next_flush_l1_access : request_state_type;
b_request_state_next_sync : request_state_type;
b_request_state_next : request_state_type;
b_request_cache_accessed_next : std_ulogic;
b_request_replace_we : std_ulogic;
b_request_replace_wway : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_request_vram_we : std_ulogic;
b_request_vram_wdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_push : std_ulogic;
b_stb_combine : std_ulogic;
b_stb_tail_ptr_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_push_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_combine_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_push_entry_cache_hit : std_ulogic;
b_stb_push_entry_alloc : std_ulogic;
b_stb_push_entry_writethrough : std_ulogic;
b_stb_push_entry_be : std_ulogic;
b_stb_push_entry_priv : std_ulogic;
b_stb_push_entry_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_array_block_change : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_valid_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_cache_hit_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_alloc_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_writethrough_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_be_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_priv_next : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_way_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_assoc-1 downto 0);
b_stb_write_bus_next : std_ulogic;
b_stb_write_cache_next : std_ulogic;
b_stb_way_next : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_cache_read_data_be : std_ulogic;
b_cache_read_data_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_result_ready : std_ulogic;
b_result_code_mmu_access : cpu_l1mem_data_result_code_type;
b_result_code_no_error : cpu_l1mem_data_result_code_type;
b_result_code : cpu_l1mem_data_result_code_type;
b_result_data_sel_cached_load_l1_access : cpu_l1mem_data_cache_b_result_data_sel_type;
b_result_data_sel : cpu_l1mem_data_cache_b_result_data_sel_type;
b_replace_we_no_error : std_ulogic;
b_replace_we : std_ulogic;
b_replace_wway : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_vram_we_no_error : std_ulogic;
b_vram_we : std_ulogic;
b_vram_wdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_mram_we_no_error : std_ulogic;
b_mram_we : std_ulogic;
b_mram_wdata : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_cache_owner_next_bus_op_request : cpu_l1mem_data_cache_owner_type;
b_cache_owner_next_bus_op_bus_op : cpu_l1mem_data_cache_owner_type;
b_cache_owner_next_stb : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_request : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_bus_op_request : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_bus_op_stb : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_bus_op_bus_op : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_bus_op : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_stb : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next_no_error : cpu_l1mem_data_cache_owner_type;
b_vtram_owner_next : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_request : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_bus_op_request : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_bus_op_stb : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_bus_op_bus_op : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_bus_op : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_stb : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next_no_error : cpu_l1mem_data_cache_owner_type;
b_rmdram_owner_next : cpu_l1mem_data_cache_owner_type;
b_bus_op_owner_next_request : cpu_l1mem_data_cache_owner_type;
b_bus_op_owner_next_stb : cpu_l1mem_data_cache_owner_type;
b_bus_op_owner_next_bus_op : cpu_l1mem_data_cache_owner_type;
b_bus_op_owner_next_no_error : cpu_l1mem_data_cache_owner_type;
b_bus_op_owner_next : cpu_l1mem_data_cache_owner_type;
a_stb_head_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_tail_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_valid : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_alloc : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_writethrough : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_be : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_priv : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_cache_hit : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
a_stb_array_way : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_assoc-1 downto 0);
a_stb_head_valid : std_ulogic;
a_stb_head_alloc : std_ulogic;
a_stb_head_writethrough : std_ulogic;
a_stb_head_be : std_ulogic;
a_stb_head_priv : std_ulogic;
a_stb_head_cache_hit : std_ulogic;
a_stb_head_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_stb_full : std_ulogic;
a_stb_quick_store : std_ulogic;
a_new_request : request_type;
a_new_request_stb_wait : std_ulogic;
a_new_request_state_load : request_state_type;
a_new_request_state_store : request_state_type;
a_new_request_state : request_state_type;
a_request : request_type;
a_request_state : request_state_type;
a_request_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_request_cache_accessed : std_ulogic;
a_request_mmu_accessed : std_ulogic;
a_request_cache_block_valid : std_ulogic;
a_request_cache_block_dirty : std_ulogic;
a_request_want_vtram : std_ulogic;
a_request_want_rmdram : std_ulogic;
a_request_want_bus_op : std_ulogic;
a_request_can_own_vtram : std_ulogic;
a_request_can_own_rmdram : std_ulogic;
a_request_can_own_bus_op : std_ulogic;
a_request_granted : std_ulogic;
a_request_bus_op_code : bus_op_code_type;
a_request_vram_re : std_ulogic;
a_request_mram_re : std_ulogic;
a_request_tram_en : std_ulogic;
a_request_tram_we : std_ulogic;
a_request_tram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_request_dram_en : std_ulogic;
a_request_replace_re : std_ulogic;
a_request_mmu_accessed_next : std_ulogic;
a_stb_can_own_bus_op : std_ulogic;
a_stb_can_own_vtram : std_ulogic;
a_stb_can_own_rmdram : std_ulogic;
a_stb_can_activate : std_ulogic;
a_stb_activate : std_ulogic;
a_stb_write_cache : std_ulogic;
a_stb_write_bus : std_ulogic;
a_stb_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_stb_state : stb_state_type;
a_stb_active : std_ulogic;
a_stb_want_vtram : std_ulogic;
a_stb_want_rmdram : std_ulogic;
a_stb_want_bus_op : std_ulogic;
a_stb_vram_re : std_ulogic;
a_stb_mram_re : std_ulogic;
a_stb_tram_en : std_ulogic;
a_stb_tram_we : std_ulogic;
a_stb_tram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_stb_dram_en : std_ulogic;
a_stb_dram_we : std_ulogic;
a_stb_dram_wdata_be : std_ulogic;
a_stb_replace_re : std_ulogic;
a_stb_bus_op_code : bus_op_code_type;
a_stb_bus_op_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_new_bus_op_owner : cpu_l1mem_data_cache_owner_type;
a_new_bus_op_code : bus_op_code_type;
a_new_bus_op_state : bus_op_state_type;
a_new_bus_op_cacheable : std_ulogic;
a_new_bus_op_be : std_ulogic;
a_new_bus_op_priv : std_ulogic;
a_new_bus_op_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_new_bus_op_block_word : std_ulogic_vector(cpu_l1mem_data_cache_block_words-1 downto 0);
a_new_bus_op_paddr_tag_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type;
a_new_bus_op_paddr_index_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type;
a_new_bus_op_paddr_offset_sel_request : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type;
a_new_bus_op_paddr_tag_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type;
a_new_bus_op_paddr_index_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type;
a_new_bus_op_paddr_offset_sel_stb : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type;
a_new_bus_op_paddr_tag_sel : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type;
a_new_bus_op_paddr_index_sel : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type;
a_new_bus_op_paddr_offset_sel : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type;
a_new_bus_op_size_sel_request : cpu_l1mem_data_cache_a_bus_op_size_sel_type;
a_new_bus_op_size_sel_stb : cpu_l1mem_data_cache_a_bus_op_size_sel_type;
a_new_bus_op_size_sel : cpu_l1mem_data_cache_a_bus_op_size_sel_type;
a_bus_op_owner : cpu_l1mem_data_cache_owner_type;
a_bus_op_state : bus_op_state_type;
a_bus_op_be : std_ulogic;
a_bus_op_priv : std_ulogic;
a_bus_op_way : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_bus_op_cacheable : std_ulogic;
a_bus_op_block_word : std_ulogic_vector(cpu_l1mem_data_cache_block_words-1 downto 0);
a_bus_op_requested : std_ulogic;
a_bus_op_paddr_tag_sel : cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_type;
a_bus_op_paddr_index_sel : cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_type;
a_bus_op_paddr_offset_sel : cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_type;
a_bus_op_size_sel : cpu_l1mem_data_cache_a_bus_op_size_sel_type;
a_bus_op_cache_paddr_sel_old : std_ulogic;
a_bus_op_sys_paddr_sel_old : std_ulogic;
a_bus_op_sys_data_sel_cache : std_ulogic;
a_bus_op_want_cache : std_ulogic;
a_bus_op_vram_re : std_ulogic;
a_bus_op_mram_re : std_ulogic;
a_bus_op_tram_en : std_ulogic;
a_bus_op_tram_we : std_ulogic;
a_bus_op_tram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_bus_op_dram_en : std_ulogic;
a_bus_op_dram_we : std_ulogic;
a_bus_op_replace_re : std_ulogic;
a_bus_op_can_own_vtram : std_ulogic;
a_bus_op_can_own_rmdram : std_ulogic;
a_bus_op_granted : std_ulogic;
a_new_vtram_owner : cpu_l1mem_data_cache_owner_type;
a_new_rmdram_owner : cpu_l1mem_data_cache_owner_type;
a_vtram_owner : cpu_l1mem_data_cache_owner_type;
a_rmdram_owner : cpu_l1mem_data_cache_owner_type;
a_vram_re : std_ulogic;
a_mram_re : std_ulogic;
a_tram_en : std_ulogic;
a_tram_we : std_ulogic;
a_tram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
a_dram_en : std_ulogic;
a_dram_we : std_ulogic;
a_dram_wdata_be : std_ulogic;
a_replace_re : std_ulogic;
a_mmu_request : std_ulogic;
a_sys_request : std_ulogic;
a_sys_be : std_ulogic;
a_sys_write : std_ulogic;
a_sys_cacheable : std_ulogic;
a_sys_priv : std_ulogic;
a_sys_burst : std_ulogic;
a_sys_bcycles : sys_burst_cycles_type;
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
-------- post-phase
-- get data read from srams
c.b_vram_rdata <= cpu_l1mem_data_cache_ctrl_in_vram.rdata;
c.b_vram_rdata_all_ones <= all_ones(c.b_vram_rdata);
c.b_vram_rdata_first_free <= prioritize(not c.b_vram_rdata);
c.b_mram_rdata <= cpu_l1mem_data_cache_ctrl_in_mram.rdata;
c.b_replace_rway <= cpu_l1mem_data_cache_replace_ctrl_out.rway;
with c.b_vram_rdata_all_ones select
c.b_replace_way <= c.b_replace_rway when '1',
c.b_vram_rdata_first_free when '0',
(others => 'X') when others;
c.b_replace_way_valid <= reduce_or(c.b_replace_way and c.b_vram_rdata);
c.b_replace_way_dirty <= reduce_or(c.b_replace_way and c.b_mram_rdata);
---- bus operation post-phase
c.b_bus_op_error <= (
r.b_bus_op_requested and
sys_slave_ctrl_out.ready and
sys_slave_ctrl_out.error
);
c.b_bus_op_cycle_complete <= (
r.b_bus_op_requested and
sys_slave_ctrl_out.ready
);
with r.b_bus_op_state select
c.b_bus_op_fill_load_data_ready <= c.b_bus_op_cycle_complete when bus_op_state_fill_first,
sys_slave_ctrl_out.ready when bus_op_state_fill,
'X' when others;
c.b_bus_op_fill_complete <= (
r.b_bus_op_state(bus_op_state_index_fill_last)
);
c.b_bus_op_writeback_complete <= (
r.b_bus_op_state(bus_op_state_index_writeback_last) and
c.b_bus_op_cycle_complete
);
with r.b_bus_op_state select
c.b_bus_op_complete_no_error <= '1' when bus_op_state_none |
bus_op_state_fill_last,
c.b_bus_op_cycle_complete when bus_op_state_load |
bus_op_state_store |
bus_op_state_writeback_last,
'0' when bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_fill_first |
bus_op_state_fill,
'X' when others;
c.b_bus_op_complete <= c.b_bus_op_complete_no_error or c.b_bus_op_error;
b_bus_op_state_next_block_words_eq_1_gen : if cpu_l1mem_data_cache_block_words = 1 generate
c.b_bus_op_state_next_fill_first <= (
bus_op_state_index_fill_first => (
not c.b_bus_op_cycle_complete
),
bus_op_state_index_fill_last => (
c.b_bus_op_cycle_complete
),
others => '0'
);
c.b_bus_op_state_next_writeback_first <= (
bus_op_state_index_writeback_first => (
not c.b_bus_op_cycle_complete
),
bus_op_state_index_writeback_last => (
c.b_bus_op_cycle_complete
),
others => '0'
);
end generate;
b_bus_op_state_next_block_words_gt_1_gen : if cpu_l1mem_data_cache_block_words > 1 generate
c.b_bus_op_state_next_fill_first <= (
bus_op_state_index_fill_first => (
not r.b_bus_op_granted
),
bus_op_state_index_fill => (
r.b_bus_op_granted
),
others => '0'
);
c.b_bus_op_state_next_fill <= (
bus_op_state_index_fill => (
not c.b_bus_op_cycle_complete or
not r.b_bus_op_block_word(cpu_l1mem_data_cache_block_words-1)
),
bus_op_state_index_fill_last => (
c.b_bus_op_cycle_complete and
r.b_bus_op_block_word(cpu_l1mem_data_cache_block_words-1)
),
others => '0'
);
c.b_bus_op_state_next_writeback_first <= (
bus_op_state_index_writeback_first => (
not c.b_bus_op_cycle_complete
),
bus_op_state_index_writeback => (
c.b_bus_op_cycle_complete
),
others => '0'
);
c.b_bus_op_state_next_writeback <= (
bus_op_state_index_writeback => (
not c.b_bus_op_cycle_complete or
not r.b_bus_op_block_word(cpu_l1mem_data_cache_block_words-1)
),
bus_op_state_index_writeback_last => (
c.b_bus_op_cycle_complete and
r.b_bus_op_block_word(cpu_l1mem_data_cache_block_words-1)
),
others => '0'
);
end generate;
with r.b_bus_op_state select
c.b_bus_op_state_next_no_error <= bus_op_state_load when bus_op_state_load,
bus_op_state_store when bus_op_state_store,
c.b_bus_op_state_next_fill_first when bus_op_state_fill_first,
c.b_bus_op_state_next_fill when bus_op_state_fill,
bus_op_state_fill_last when bus_op_state_fill_last,
c.b_bus_op_state_next_writeback_first when bus_op_state_writeback_first,
c.b_bus_op_state_next_writeback when bus_op_state_writeback,
bus_op_state_writeback_last when bus_op_state_writeback_last,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_bus_op_state_next <= c.b_bus_op_state_next_no_error when '0',
bus_op_state_none when '1',
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_block_word_advance <= sys_slave_ctrl_out.ready when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback,
'0' when bus_op_state_load |
bus_op_state_store |
bus_op_state_writeback_last,
'X' when others;
with c.b_bus_op_block_word_advance select
c.b_bus_op_block_word_next <= r.b_bus_op_block_word when '0',
(r.b_bus_op_block_word(cpu_l1mem_data_cache_block_words-2 downto 0) &
r.b_bus_op_block_word(cpu_l1mem_data_cache_block_words-1)
) when '1',
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_vram_we <= '0' when bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
sys_slave_ctrl_out.ready and r.b_bus_op_block_word(0) when bus_op_state_fill_first,
'1' when bus_op_state_fill_last,
'X' when others;
with r.b_bus_op_state select
c.b_bus_op_vram_wdata <= c.b_vram_rdata and not r.b_bus_op_way when bus_op_state_fill,
c.b_vram_rdata or r.b_bus_op_way when bus_op_state_fill_last,
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_mram_we <= '0' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback,
'1' when bus_op_state_fill_last,
sys_slave_ctrl_out.ready when bus_op_state_writeback_last,
'X' when others;
with r.b_bus_op_state select
c.b_bus_op_mram_wdata <= c.b_mram_rdata and not r.b_bus_op_way when bus_op_state_fill_last |
bus_op_state_writeback_last,
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_replace_we <= '0' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
'1' when bus_op_state_fill_last,
'X' when others;
c.b_bus_op_replace_wway <= r.b_bus_op_way;
-- block change (fill/invalidation) notification
with r.b_bus_op_state select
c.b_block_change <= '1' when bus_op_state_fill_first |
bus_op_state_fill_last,
'0' when bus_op_state_none |
bus_op_state_load |
bus_op_state_store |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
'X' when others;
with r.b_bus_op_state select
c.b_block_change_valid <= '0' when bus_op_state_fill_first,
'1' when bus_op_state_fill_last,
'X' when others;
c.b_block_change_way <= r.b_bus_op_way;
---- stb operation post-phase
c.b_stb_full <= all_ones(r.b_stb_array_valid);
c.b_stb_empty <= all_zeros(r.b_stb_array_valid);
-- stb_state_init: stb is inactive
-- stb_state_replace_access:
-- vram, mram, & replace are already owned
-- valid, dirty, & replace way are now available.
-- stb_state_fill: waiting for bus fill operation to complete
-- stb_state_write: write to cache and/or bus, read/write replace state
c.b_stb_state_next_replace_access <= (
stb_state_index_writeback => (
c.b_replace_way_valid and
c.b_replace_way_dirty
),
stb_state_index_fill => (
not c.b_replace_way_valid or
not c.b_replace_way_dirty
),
others => '0'
);
c.b_stb_state_next_writeback <= (
stb_state_index_writeback => (
not c.b_bus_op_writeback_complete
),
stb_state_index_fill => (
c.b_bus_op_writeback_complete
),
others => '0'
);
c.b_stb_state_next_fill <= (
stb_state_index_fill => (
not c.b_bus_op_fill_complete
),
stb_state_index_write => (
c.b_bus_op_fill_complete
),
others => '0'
);
c.b_stb_state_next_write <= (
stb_state_index_init => (
not r.b_stb_write_bus or
c.b_bus_op_cycle_complete
),
stb_state_index_write => (
r.b_stb_write_bus and
not c.b_bus_op_cycle_complete
),
others => '0'
);
with r.b_stb_state select
c.b_stb_state_next <= stb_state_init when stb_state_init,
c.b_stb_state_next_replace_access when stb_state_replace_access,
c.b_stb_state_next_writeback when stb_state_writeback,
c.b_stb_state_next_fill when stb_state_fill,
c.b_stb_state_next_write when stb_state_write,
(others => 'X') when others;
with r.b_stb_state select
c.b_stb_mram_we <= '0' when stb_state_replace_access |
stb_state_writeback |
stb_state_fill,
r.b_stb_write_cache when stb_state_write,
'X' when others;
with r.b_stb_state select
c.b_stb_mram_wdata <= c.b_mram_rdata or r.b_stb_way when stb_state_write,
(others => 'X') when others;
with r.b_stb_state select
c.b_stb_replace_we <= '0' when stb_state_replace_access |
stb_state_writeback |
stb_state_fill,
(r.b_stb_write_cache and
(not r.b_stb_write_bus or
c.b_bus_op_cycle_complete)) when stb_state_write,
'X' when others;
c.b_stb_replace_wway <= r.b_stb_way;
c.b_stb_pop_write <= (
not r.b_stb_write_bus or
c.b_bus_op_cycle_complete
);
with r.b_stb_state select
c.b_stb_pop <= '0' when stb_state_init |
stb_state_replace_access |
stb_state_fill |
stb_state_writeback,
c.b_stb_pop_write when stb_state_write,
'X' when others;
b_stb_head_ptr_next_gen : if cpu_l1mem_data_cache_stb_entries > 0 generate
with c.b_stb_pop select
c.b_stb_head_ptr_next <= (r.b_stb_head_ptr(cpu_l1mem_data_cache_stb_entries-2 downto 0) &
r.b_stb_head_ptr(cpu_l1mem_data_cache_stb_entries-1)) when '1',
r.b_stb_head_ptr when '0',
(others => 'X') when others;
end generate;
c.b_stb_can_push <= not c.b_stb_full or c.b_stb_pop;
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.b_stb_head_ptr_next) and is_1hot(c.b_stb_head_ptr_next) = '1'
report "c.b_stb_head_ptr_next is invalid"
severity failure;
assert not is_x(c.b_stb_tail_ptr_next) and is_1hot(c.b_stb_tail_ptr_next) = '1'
report "c.b_stb_tail_ptr_next is invalid"
severity failure;
case r.b_stb_state is
when stb_state_init |
stb_state_replace_access |
stb_state_writeback |
stb_state_fill |
stb_state_write =>
when others =>
assert false
report "r.b_stb_state is invalid"
severity failure;
end case;
case c.b_stb_state_next is
when stb_state_init |
stb_state_replace_access |
stb_state_writeback |
stb_state_fill |
stb_state_write =>
null;
when others =>
assert false
report "c.b_stb_state_next is invalid"
severity failure;
end case;
assert not is_x(c.b_stb_pop)
report "c.b_stb_pop is invalid"
severity failure;
end if;
end process;
-- pragma translate_on
---- request post-phase
c.b_request_sync <= (
r.b_vtram_owner(cpu_l1mem_data_cache_owner_index_none) and
r.b_rmdram_owner(cpu_l1mem_data_cache_owner_index_none) and
r.b_bus_op_owner(cpu_l1mem_data_cache_owner_index_none) and
c.b_stb_empty
);
c.b_request_mmu_result_ready <= (
r.b_request_mmu_accessed and
cpu_mmu_data_ctrl_out.ready
);
c.b_request_mmu_result_valid <= (
r.b_request_mmu_accessed and
cpu_mmu_data_ctrl_out.ready and
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)
);
c.b_request_mmu_error <= (
r.b_request_mmu_accessed and
cpu_mmu_data_ctrl_out.ready and
not cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)
);
-- check for cache hit
c.b_request_cache_way_hit <= (c.b_vram_rdata and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_cache_tag_match);
c.b_request_cache_hit <= reduce_or(c.b_request_cache_way_hit);
c.b_request_cache_miss <= not c.b_request_cache_hit;
c.b_request_cache_way_hit_dirty <= (
c.b_request_cache_way_hit and c.b_mram_rdata
);
c.b_request_cache_hit_dirty <= reduce_or(c.b_request_cache_way_hit_dirty);
c.b_request_cache_way_hit_clean <= (
c.b_request_cache_way_hit and not c.b_mram_rdata
);
c.b_request_cache_hit_clean <= reduce_or(c.b_request_cache_way_hit_clean);
with r.b_request_state select
c.b_request_cache_block_valid <= c.b_replace_way_valid when request_state_cached_load_l1_access,
'X' when others;
with r.b_request_state select
c.b_request_cache_block_dirty <= c.b_replace_way_dirty when request_state_cached_load_l1_access,
'X' when others;
-- check for stb hit
b_request_stb_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
c.b_request_stb_array_hit(n) <= (
r.b_stb_array_valid(n) and
(r.b_request.be xnor r.b_stb_array_be(n)) and
(r.b_request.writethrough xnor r.b_stb_array_writethrough(n)) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_tag_match(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_index_match(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_block_word_offset_match(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_word_byte_offset_match(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_size_match(n)
);
c.b_request_stb_array_conflict(n) <= (
r.b_stb_array_valid(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_tag_match(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_index_match(n) and
cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_block_word_offset_match(n) and
((r.b_request.be xor r.b_stb_array_be(n)) or
not cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_word_byte_offset_match(n) or
not cpu_l1mem_data_cache_dp_out_ctrl.b_request_stb_array_size_match(n))
);
end generate;
c.b_request_stb_hit <= any_ones(c.b_request_stb_array_hit);
c.b_request_stb_head_hit <= any_ones(c.b_request_stb_array_hit and r.b_stb_head_ptr);
c.b_request_stb_conflict <= any_ones(c.b_request_stb_array_conflict);
-- a store request can combine with a request in the stb if
-- 1) the request address, size, and endianness match
-- 2) the matching stb entry has not started processing
-- (e.g. the matching entry is the head and is not in the init state)
-- 3) the request does not conflict with any other entries
c.b_request_stb_can_combine <= (
c.b_request_stb_hit and
not (c.b_request_stb_head_hit and
not r.b_stb_state(stb_state_index_init)) and
not c.b_request_stb_conflict
);
-- request completion
c.b_request_complete_uncached_mmu_access <= (
c.b_request_mmu_error
);
c.b_request_complete_uncached_bus_op <= (
r.b_request_granted and
c.b_bus_op_cycle_complete
);
c.b_request_complete_cached_load_l1_access <= (
(c.b_request_mmu_result_valid and
((r.b_request_granted and
c.b_request_cache_hit) or
c.b_request_stb_hit
)
) or
c.b_request_mmu_error
);
c.b_request_complete_cached_load_fill <= (
r.b_request_granted and
c.b_bus_op_fill_load_data_ready
);
c.b_request_complete_cached_store_l1_access <= (
(c.b_request_mmu_result_valid and
r.b_request_granted and
(c.b_stb_can_push or
c.b_request_stb_can_combine
)
) or
c.b_request_mmu_error
);
c.b_request_complete_invalidate_l1_access <= (
r.b_request_granted
);
c.b_request_complete_writeback_l1_access <= (
(r.b_request_granted and
c.b_request_mmu_result_valid and
(c.b_request_cache_miss or
c.b_request_cache_hit_clean)
) or
c.b_request_mmu_error
);
c.b_request_complete_writeback_bus_op <= (
r.b_request_granted and
c.b_bus_op_writeback_complete
);
c.b_request_complete_flush_l1_access <= (
c.b_request_mmu_error or
(r.b_request_granted and
c.b_request_cache_hit_clean)
);
c.b_request_complete_sync <= (
c.b_request_sync
);
with r.b_request_state select
c.b_request_complete_no_error <= '1' when request_state_none |
request_state_flush_invalidate_l1_access,
c.b_request_complete_uncached_mmu_access when request_state_uncached_load_mmu_access |
request_state_uncached_store_mmu_access,
c.b_request_complete_uncached_bus_op when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op,
c.b_request_complete_cached_load_l1_access when request_state_cached_load_l1_access,
c.b_request_complete_cached_load_fill when request_state_cached_load_fill,
c.b_request_complete_cached_store_l1_access when request_state_cached_store_l1_access,
c.b_request_complete_sync when request_state_sync,
c.b_request_complete_invalidate_l1_access when request_state_invalidate_l1_access,
c.b_request_complete_writeback_l1_access when request_state_writeback_l1_access,
c.b_request_complete_writeback_bus_op when request_state_writeback_bus_op,
c.b_request_complete_flush_l1_access when request_state_flush_l1_access,
'0' when request_state_cached_load_writeback |
request_state_cached_store_stb_wait |
request_state_invalidate_sync |
request_state_writeback_sync |
request_state_flush_sync |
request_state_flush_bus_op,
'X' when others;
c.b_request_complete <= c.b_request_complete_no_error or c.b_bus_op_error;
with r.b_request_state select
c.b_request_way_next <= c.b_replace_way when request_state_cached_load_l1_access,
c.b_request_cache_way_hit when request_state_writeback_l1_access |
request_state_flush_l1_access,
r.b_request_way when request_state_cached_load_fill |
request_state_cached_load_writeback,
(others => 'X') when others;
c.b_request_state_next_uncached_load_mmu_access <= (
request_state_index_uncached_load_mmu_access => (
not c.b_request_mmu_result_ready
),
request_state_index_uncached_load_bus_op => (
c.b_request_mmu_result_ready
),
others => '0'
);
c.b_request_state_next_cached_load_writeback <= (
request_state_index_cached_load_writeback => (
not c.b_bus_op_writeback_complete
),
request_state_index_cached_load_fill => (
c.b_bus_op_writeback_complete
),
others => '0'
);
c.b_request_state_next_uncached_store_mmu_access <= (
request_state_index_uncached_store_mmu_access => (
not c.b_request_mmu_result_ready
),
request_state_index_uncached_store_bus_op => (
c.b_request_mmu_result_ready
),
others => '0'
);
c.b_request_state_next_cached_load_l1_access <= (
request_state_index_cached_load_l1_access => (
not r.b_request_granted or
not c.b_request_mmu_result_ready
),
request_state_index_cached_load_writeback => (
r.b_request_granted and
r.b_request.alloc and
c.b_request_mmu_result_ready and
c.b_request_cache_block_valid and
c.b_request_cache_block_dirty
),
request_state_index_cached_load_fill => (
r.b_request_granted and
r.b_request.alloc and
c.b_request_mmu_result_ready and
(not c.b_request_cache_block_valid or
not c.b_request_cache_block_dirty)
),
request_state_index_uncached_load_bus_op => (
r.b_request_granted and
not r.b_request.alloc
),
others => '0'
);
c.b_request_state_next_cached_store_stb_wait <= (
request_state_index_cached_store_stb_wait => (
not c.b_stb_pop
),
request_state_index_cached_store_l1_access => (
c.b_stb_pop
),
others => '0'
);
c.b_request_state_next_writeback_l1_access <= (
request_state_index_writeback_l1_access => (
not r.b_request_granted or
not c.b_request_mmu_result_ready
),
request_state_index_writeback_bus_op => (
r.b_request_granted and
c.b_request_cache_hit_dirty
),
others => '0'
);
c.b_request_state_next_invalidate_sync <= (
request_state_index_invalidate_sync => (
not c.b_request_sync
),
request_state_index_invalidate_l1_access => (
c.b_request_sync
),
others => '0'
);
c.b_request_state_next_writeback_sync <= (
request_state_index_writeback_sync => (
not c.b_request_sync
),
request_state_index_writeback_l1_access => (
c.b_request_sync
),
others => '0'
);
c.b_request_state_next_flush_sync <= (
request_state_index_flush_sync => (
not c.b_request_sync
),
request_state_index_flush_l1_access => (
c.b_request_sync
),
others => '0'
);
c.b_request_state_next_flush_l1_access <= (
request_state_index_none => (
r.b_request_granted and
not c.b_request_cache_hit
),
request_state_index_flush_l1_access => (
not r.b_request_granted
),
request_state_index_flush_bus_op => (
r.b_request_granted and
c.b_request_cache_hit
),
others => '0'
);
with r.b_request_state select
c.b_request_state_next <= r.b_request_state when request_state_none |
request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op |
request_state_cached_store_l1_access |
request_state_invalidate_l1_access |
request_state_flush_invalidate_l1_access,
c.b_request_state_next_cached_load_writeback when request_state_cached_load_writeback,
request_state_cached_load_fill when request_state_cached_load_fill,
c.b_request_state_next_uncached_load_mmu_access when request_state_uncached_load_mmu_access,
c.b_request_state_next_uncached_store_mmu_access when request_state_uncached_store_mmu_access,
c.b_request_state_next_cached_load_l1_access when request_state_cached_load_l1_access,
c.b_request_state_next_cached_store_stb_wait when request_state_cached_store_stb_wait,
c.b_request_state_next_writeback_l1_access when request_state_writeback_l1_access,
request_state_writeback_bus_op when request_state_writeback_bus_op,
c.b_request_state_next_invalidate_sync when request_state_invalidate_sync,
c.b_request_state_next_writeback_sync when request_state_writeback_sync,
c.b_request_state_next_flush_sync when request_state_flush_sync,
c.b_request_state_next_flush_l1_access when request_state_flush_l1_access,
request_state_sync when request_state_sync,
(others => 'X') when others;
with r.b_request_state select
c.b_request_cache_accessed_next <= r.b_request_granted when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_invalidate_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access |
request_state_flush_invalidate_l1_access,
'0' when request_state_none |
request_state_cached_store_stb_wait |
request_state_invalidate_sync |
request_state_writeback_sync |
request_state_flush_sync |
request_state_flush_bus_op,
'X' when others;
with r.b_request_state select
c.b_request_replace_we <= (c.b_request_mmu_result_valid and
c.b_request_cache_hit
) when request_state_cached_load_l1_access,
'0' when request_state_cached_store_l1_access |
request_state_flush_invalidate_l1_access |
request_state_invalidate_l1_access,
'X' when others;
with r.b_request_state select
c.b_request_replace_wway <= c.b_request_cache_way_hit when request_state_cached_load_l1_access |
request_state_cached_store_l1_access,
(others => 'X') when others;
with r.b_request_state select
c.b_request_vram_we <= '1' when request_state_invalidate_l1_access |
request_state_flush_invalidate_l1_access,
'0' when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
'X' when others;
with r.b_request_state select
c.b_request_vram_wdata <= (others => '0') when request_state_invalidate_l1_access,
c.b_vram_rdata and not r.b_request_way when request_state_flush_invalidate_l1_access,
(others => 'X') when others;
-- stb update
c.b_stb_push <= (
r.b_request_state(request_state_index_cached_store_l1_access) and
c.b_request_mmu_result_valid and
r.b_request_granted and
not c.b_request_stb_can_combine and
c.b_stb_can_push
);
c.b_stb_combine <= (
r.b_request_state(request_state_index_cached_store_l1_access) and
c.b_request_mmu_result_valid and
r.b_request_granted and
c.b_request_stb_can_combine
);
b_stb_tail_ptr_next_gen : if cpu_l1mem_data_cache_stb_entries > 0 generate
with c.b_stb_push select
c.b_stb_tail_ptr_next <= (r.b_stb_tail_ptr(cpu_l1mem_data_cache_stb_entries-2 downto 0) &
r.b_stb_tail_ptr(cpu_l1mem_data_cache_stb_entries-1)) when '1',
r.b_stb_tail_ptr when '0',
(others => 'X') when others;
end generate;
c.b_stb_push_ptr <= (
((cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_push) and
r.b_stb_tail_ptr)
);
c.b_stb_combine_ptr <= (
(cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_combine) and
(not r.b_stb_head_ptr or
(cpu_l1mem_data_cache_stb_entries-1 downto 0 => r.b_stb_state(stb_state_index_init))) and
c.b_request_stb_array_hit
);
c.b_stb_push_entry_cache_hit <= c.b_request_cache_hit;
c.b_stb_push_entry_writethrough <= r.b_request.writethrough;
c.b_stb_push_entry_alloc <= r.b_request.alloc;
c.b_stb_push_entry_be <= r.b_request.be;
c.b_stb_push_entry_priv <= r.b_request.priv;
c.b_stb_push_entry_way <= c.b_request_cache_way_hit;
b_stb_array_block_change_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
c.b_stb_array_block_change(n) <= (
c.b_block_change and
cpu_l1mem_data_cache_dp_out_ctrl.b_stb_array_block_change_index_match(n) and
logic_if(c.b_block_change_valid,
cpu_l1mem_data_cache_dp_out_ctrl.b_stb_array_block_change_tag_match(n),
reduce_or(std_ulogic_vector2_slice2(r.b_stb_array_way, n) and
c.b_block_change_way))
);
end generate;
c.b_stb_array_valid_next <= (
((r.b_stb_array_valid and
not (r.b_stb_head_ptr and
(cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_pop))) or
c.b_stb_push_ptr) and
not (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_bus_op_error)
);
c.b_stb_array_cache_hit_next <= (
(c.b_stb_push_ptr and (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_push_entry_cache_hit)) or
(not c.b_stb_push_ptr and
((c.b_stb_array_block_change and (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_block_change_valid)) or
(not c.b_stb_array_block_change and r.b_stb_array_cache_hit))
)
);
c.b_stb_array_alloc_next <= (
(c.b_stb_push_ptr and (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_push_entry_alloc)) or
(not c.b_stb_push_ptr and r.b_stb_array_alloc)
);
c.b_stb_array_writethrough_next <= (
(c.b_stb_push_ptr and (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_push_entry_writethrough)) or
(not c.b_stb_push_ptr and r.b_stb_array_writethrough)
);
c.b_stb_array_be_next <= (
(c.b_stb_push_ptr and (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_push_entry_be)) or
(not c.b_stb_push_ptr and r.b_stb_array_be)
);
c.b_stb_array_priv_next <= (
(c.b_stb_push_ptr and (cpu_l1mem_data_cache_stb_entries-1 downto 0 => c.b_stb_push_entry_priv)) or
(not c.b_stb_push_ptr and r.b_stb_array_priv)
);
b_stb_array_way_next_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
blk : block
signal din : std_ulogic_vector2(2 downto 0, cpu_l1mem_data_cache_assoc-1 downto 0);
signal sel : std_ulogic_vector(2 downto 0);
signal dout : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
begin
sel <= (0 => c.b_stb_push_ptr(n),
1 => not c.b_stb_push_ptr(n) and not c.b_stb_array_block_change(n),
2 => not c.b_stb_push_ptr(n) and c.b_stb_array_block_change(n)
);
din_gen : for m in cpu_l1mem_data_cache_assoc-1 downto 0 generate
din(0, m) <= c.b_stb_push_entry_way(m);
din(1, m) <= r.b_stb_array_way(n, m);
din(2, m) <= c.b_block_change_way(m);
end generate;
mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_l1mem_data_cache_assoc,
sel_bits => 3
)
port map (
din => din,
sel => sel,
dout => dout
);
dout_gen : for m in cpu_l1mem_data_cache_assoc-1 downto 0 generate
c.b_stb_array_way_next(n, m) <= dout(m);
end generate;
end block;
end generate;
c.b_stb_write_bus_next <= r.b_stb_write_bus;
with r.b_stb_state select
c.b_stb_write_cache_next <= r.b_stb_write_cache when stb_state_replace_access |
stb_state_writeback |
stb_state_fill,
'0' when stb_state_write,
'X' when others;
with r.b_stb_state select
c.b_stb_way_next <= c.b_replace_way when stb_state_replace_access,
r.b_stb_way when stb_state_fill |
stb_state_writeback |
stb_state_write,
(others => 'X') when others;
-- cache read
with r.b_rmdram_owner select
c.b_cache_read_data_be <= r.b_bus_op_be when cpu_l1mem_data_cache_owner_bus_op,
r.b_request.be when cpu_l1mem_data_cache_owner_request,
'X' when others;
with r.b_rmdram_owner select
c.b_cache_read_data_way <= r.b_bus_op_way when cpu_l1mem_data_cache_owner_bus_op,
c.b_request_cache_way_hit when cpu_l1mem_data_cache_owner_request,
(others => 'X') when others;
-- request result processing
c.b_result_ready <= c.b_request_complete;
c.b_result_code_mmu_access <= (
cpu_l1mem_data_result_code_index_valid => (
not r.b_request.mmuen or
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_valid)
),
cpu_l1mem_data_result_code_index_error => (
r.b_request.mmuen and
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_error)
),
cpu_l1mem_data_result_code_index_tlbmiss => (
r.b_request.mmuen and
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_tlbmiss)
),
cpu_l1mem_data_result_code_index_pf => (
r.b_request.mmuen and
cpu_mmu_data_ctrl_out.result(cpu_mmu_data_result_code_index_pf)
)
);
with r.b_request_state select
c.b_result_code_no_error <= c.b_result_code_mmu_access when request_state_uncached_load_mmu_access |
request_state_uncached_store_mmu_access |
request_state_cached_load_l1_access |
request_state_cached_store_l1_access,
cpu_l1mem_data_result_code_valid when request_state_none |
request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op |
request_state_cached_load_fill |
request_state_invalidate_l1_access |
request_state_writeback_l1_access |
request_state_writeback_bus_op |
request_state_flush_l1_access |
request_state_flush_invalidate_l1_access |
request_state_sync,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_result_code <= cpu_l1mem_data_result_code_error when '1',
c.b_result_code_no_error when '0',
(others => 'X') when others;
with c.b_request_stb_hit select
c.b_result_data_sel_cached_load_l1_access <= cpu_l1mem_data_cache_b_result_data_sel_stb when '1',
cpu_l1mem_data_cache_b_result_data_sel_cache when '0',
(others => 'X') when others;
with r.b_request_state select
c.b_result_data_sel <= c.b_result_data_sel_cached_load_l1_access when request_state_cached_load_l1_access,
cpu_l1mem_data_cache_b_result_data_sel_bus when request_state_uncached_load_bus_op,
cpu_l1mem_data_cache_b_result_data_sel_bus_shifted when request_state_cached_load_fill,
(others => 'X') when others;
-- write vram, mram, replace ram
with r.b_rmdram_owner select
c.b_replace_we_no_error <= c.b_request_replace_we when cpu_l1mem_data_cache_owner_request,
c.b_stb_replace_we when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_replace_we when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_none,
'X' when others;
c.b_replace_we <= c.b_replace_we_no_error and not c.b_bus_op_error;
with r.b_rmdram_owner select
c.b_replace_wway <= c.b_request_replace_wway when cpu_l1mem_data_cache_owner_request,
c.b_stb_replace_wway when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_replace_wway when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with r.b_vtram_owner select
c.b_vram_we_no_error <= c.b_request_vram_we when cpu_l1mem_data_cache_owner_request,
c.b_bus_op_vram_we when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_none,
'X' when others;
c.b_vram_we <= c.b_vram_we_no_error and not c.b_bus_op_error;
with r.b_vtram_owner select
c.b_vram_wdata <= c.b_request_vram_wdata when cpu_l1mem_data_cache_owner_request,
c.b_bus_op_vram_wdata when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with r.b_rmdram_owner select
c.b_mram_we_no_error <= c.b_stb_mram_we when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_mram_we when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_none,
'X' when others;
c.b_mram_we <= c.b_mram_we_no_error and not c.b_bus_op_error;
with r.b_rmdram_owner select
c.b_mram_wdata <= c.b_stb_mram_wdata when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_mram_wdata when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
-- preserve ownerships for next cycle if necessary
-- current owner decides who gets it next
-- cache owner when the current owner is a bus op, that is in turn owned by a request
with r.b_request_state select
c.b_cache_owner_next_bus_op_request <=
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_error
),
cpu_l1mem_data_cache_owner_index_bus_op => (
not c.b_bus_op_error
),
others => '0'
) when request_state_cached_load_writeback,
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_fill_complete or
c.b_bus_op_error
),
cpu_l1mem_data_cache_owner_index_bus_op => (
not c.b_bus_op_fill_complete and
not c.b_bus_op_error
),
others => '0'
) when request_state_cached_load_fill,
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_writeback_complete
),
cpu_l1mem_data_cache_owner_index_bus_op => (
not c.b_bus_op_writeback_complete
),
others => '0'
) when request_state_writeback_bus_op,
(cpu_l1mem_data_cache_owner_index_request => (
c.b_bus_op_writeback_complete
),
cpu_l1mem_data_cache_owner_index_bus_op => (
not c.b_bus_op_writeback_complete
),
others => '0'
) when request_state_flush_bus_op,
(others => 'X') when others;
with r.b_bus_op_state select
c.b_cache_owner_next_bus_op_bus_op <=
cpu_l1mem_data_cache_owner_bus_op when bus_op_state_fill_first |
bus_op_state_fill,
cpu_l1mem_data_cache_owner_none when bus_op_state_fill_last,
(others => 'X') when others;
with r.b_stb_state select
c.b_cache_owner_next_stb <=
cpu_l1mem_data_cache_owner_bus_op when stb_state_replace_access,
cpu_l1mem_data_cache_owner_none when stb_state_write,
(others => 'X') when others;
-- Choose the next cache vram & tram owner when the current owner is the request
with r.b_request_state select
c.b_vtram_owner_next_request <=
(cpu_l1mem_data_cache_owner_index_none => (
c.b_request_mmu_result_ready
),
cpu_l1mem_data_cache_owner_index_request => (
not c.b_request_mmu_result_ready
),
others => '0'
) when request_state_cached_load_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
(cpu_l1mem_data_cache_owner_index_none => (
(c.b_request_mmu_result_ready and
(c.b_stb_can_push or
c.b_request_stb_can_combine
)) or
c.b_request_mmu_error
),
cpu_l1mem_data_cache_owner_index_request => (
not c.b_request_mmu_result_ready or
(not c.b_stb_can_push and
not c.b_request_stb_can_combine)
),
others => '0'
) when request_state_cached_store_l1_access,
cpu_l1mem_data_cache_owner_none when request_state_invalidate_l1_access,
(others => 'X') when others;
-- Choose the next cache vram & tram owner when the current owner is a bus op.
c.b_vtram_owner_next_bus_op_request <=
c.b_cache_owner_next_bus_op_request;
with r.b_stb_state select
c.b_vtram_owner_next_bus_op_stb <=
cpu_l1mem_data_cache_owner_bus_op when stb_state_writeback,
(cpu_l1mem_data_cache_owner_index_none => c.b_bus_op_fill_complete,
cpu_l1mem_data_cache_owner_index_bus_op => not c.b_bus_op_fill_complete,
others => '0'
) when stb_state_fill,
(others => 'X') when others;
c.b_vtram_owner_next_bus_op_bus_op <=
c.b_cache_owner_next_bus_op_bus_op;
with r.b_bus_op_owner select
c.b_vtram_owner_next_bus_op <= cpu_l1mem_data_cache_owner_none when cpu_l1mem_data_cache_owner_none,
c.b_vtram_owner_next_bus_op_request when cpu_l1mem_data_cache_owner_request,
c.b_vtram_owner_next_bus_op_stb when cpu_l1mem_data_cache_owner_stb,
c.b_vtram_owner_next_bus_op_bus_op when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
-- Choose the next cache vram & tram owner when the current owner is the stb
c.b_vtram_owner_next_stb <=
c.b_cache_owner_next_stb;
-- Choose the next cache vram & tram owner
with r.b_vtram_owner select
c.b_vtram_owner_next_no_error <= c.b_vtram_owner_next_request when cpu_l1mem_data_cache_owner_request,
c.b_vtram_owner_next_bus_op when cpu_l1mem_data_cache_owner_bus_op,
c.b_vtram_owner_next_stb when cpu_l1mem_data_cache_owner_stb,
cpu_l1mem_data_cache_owner_none when cpu_l1mem_data_cache_owner_none,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_vtram_owner_next <= c.b_vtram_owner_next_no_error when '0',
cpu_l1mem_data_cache_owner_none when '1',
(others => 'X') when others;
-- Choose the next cache mram & dram owner when the current cache mram & dram owner is the request
with r.b_request_state select
c.b_rmdram_owner_next_request <=
(cpu_l1mem_data_cache_owner_index_none => (
c.b_request_mmu_result_ready
),
cpu_l1mem_data_cache_owner_index_request => (
not c.b_request_mmu_result_ready
),
others => '0'
) when request_state_cached_load_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
cpu_l1mem_data_cache_owner_none when request_state_invalidate_l1_access,
(others => 'X') when others;
c.b_rmdram_owner_next_bus_op_request <=
c.b_cache_owner_next_bus_op_request;
-- when stb is requesting a line fill, ownership of data goes back to stb afterwards
with r.b_stb_state select
c.b_rmdram_owner_next_bus_op_stb <=
cpu_l1mem_data_cache_owner_bus_op when stb_state_writeback,
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_error
),
cpu_l1mem_data_cache_owner_index_stb => (
c.b_bus_op_fill_complete and
not c.b_bus_op_error
),
cpu_l1mem_data_cache_owner_index_bus_op => (
not c.b_bus_op_fill_complete and
not c.b_bus_op_error
),
others => '0'
) when stb_state_fill,
(others => 'X') when others;
c.b_rmdram_owner_next_bus_op_bus_op <=
c.b_cache_owner_next_bus_op_bus_op;
with r.b_bus_op_owner select
c.b_rmdram_owner_next_bus_op <= cpu_l1mem_data_cache_owner_none when cpu_l1mem_data_cache_owner_none,
c.b_rmdram_owner_next_bus_op_request when cpu_l1mem_data_cache_owner_request,
c.b_rmdram_owner_next_bus_op_stb when cpu_l1mem_data_cache_owner_stb,
c.b_rmdram_owner_next_bus_op_bus_op when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
-- Choose the next cache data owner when the current cache data owner is the stb
c.b_rmdram_owner_next_stb <=
c.b_cache_owner_next_stb;
-- Choose the next cache data owner
with r.b_rmdram_owner select
c.b_rmdram_owner_next_no_error <= c.b_rmdram_owner_next_request when cpu_l1mem_data_cache_owner_request,
c.b_rmdram_owner_next_bus_op when cpu_l1mem_data_cache_owner_bus_op,
c.b_rmdram_owner_next_stb when cpu_l1mem_data_cache_owner_stb,
cpu_l1mem_data_cache_owner_none when cpu_l1mem_data_cache_owner_none,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_rmdram_owner_next <= c.b_rmdram_owner_next_no_error when '0',
cpu_l1mem_data_cache_owner_none when '1',
(others => 'X') when others;
-- Choose the next bus owner when the current owner is a request.
-- Uncached requests hold ownership until the first word is returned.
-- Cached load requests that are waiting on a fill hold ownership until the first transfer completes, then drop ownership
-- Writeback and flush operations hold ownership until the block is complete.
with r.b_request_state select
c.b_bus_op_owner_next_request <=
(cpu_l1mem_data_cache_owner_index_none => c.b_bus_op_cycle_complete,
cpu_l1mem_data_cache_owner_index_request => not c.b_bus_op_cycle_complete,
others => '0'
) when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op,
(cpu_l1mem_data_cache_owner_index_none => c.b_bus_op_error,
cpu_l1mem_data_cache_owner_index_request => not c.b_bus_op_error,
others => '0'
) when request_state_cached_load_writeback,
(cpu_l1mem_data_cache_owner_index_none => c.b_bus_op_fill_complete or c.b_bus_op_error,
cpu_l1mem_data_cache_owner_index_bus_op => c.b_bus_op_fill_load_data_ready and not c.b_bus_op_fill_complete and not c.b_bus_op_error,
cpu_l1mem_data_cache_owner_index_request => not c.b_bus_op_fill_load_data_ready and not c.b_bus_op_error,
others => '0'
) when request_state_cached_load_fill,
(cpu_l1mem_data_cache_owner_index_none => c.b_bus_op_writeback_complete or c.b_bus_op_error,
cpu_l1mem_data_cache_owner_index_request => not c.b_bus_op_writeback_complete and not c.b_bus_op_error,
others => '0'
) when request_state_writeback_bus_op |
request_state_flush_bus_op,
(others => 'X'
) when others;
-- Choose the next bus owner when the current owner is the stb.
-- The stb shouldn't have ownership while in the init state
with r.b_stb_state select
c.b_bus_op_owner_next_stb <=
cpu_l1mem_data_cache_owner_stb when stb_state_replace_access,
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_error
),
cpu_l1mem_data_cache_owner_index_stb => (
not c.b_bus_op_error
),
others => '0'
) when stb_state_writeback,
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_error or
(c.b_bus_op_fill_complete and
not r.b_stb_write_bus
)
),
cpu_l1mem_data_cache_owner_index_stb => (
not c.b_bus_op_error and
(not c.b_bus_op_fill_complete or
r.b_stb_write_bus
)
),
others => '0'
) when stb_state_fill,
(cpu_l1mem_data_cache_owner_index_none => (
c.b_bus_op_cycle_complete
),
cpu_l1mem_data_cache_owner_index_stb => (
not c.b_bus_op_cycle_complete
),
others => '0'
) when stb_state_write,
(others => 'X') when others;
with r.b_bus_op_state select
c.b_bus_op_owner_next_bus_op <=
cpu_l1mem_data_cache_owner_bus_op when bus_op_state_fill,
cpu_l1mem_data_cache_owner_none when bus_op_state_fill_last,
(others => 'X') when others;
with r.b_bus_op_owner select
c.b_bus_op_owner_next_no_error <= cpu_l1mem_data_cache_owner_none when cpu_l1mem_data_cache_owner_none,
c.b_bus_op_owner_next_request when cpu_l1mem_data_cache_owner_request,
c.b_bus_op_owner_next_stb when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_owner_next_bus_op when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with c.b_bus_op_error select
c.b_bus_op_owner_next <= c.b_bus_op_owner_next_no_error when '0',
cpu_l1mem_data_cache_owner_none when '1',
(others => 'X') when others;
------ Pre-phase
-- stb stuff
c.a_stb_head_ptr <= c.b_stb_head_ptr_next;
c.a_stb_tail_ptr <= c.b_stb_tail_ptr_next;
c.a_stb_array_valid <= c.b_stb_array_valid_next;
c.a_stb_array_cache_hit <= c.b_stb_array_cache_hit_next;
c.a_stb_array_alloc <= c.b_stb_array_alloc_next;
c.a_stb_array_writethrough <= c.b_stb_array_writethrough_next;
c.a_stb_array_be <= c.b_stb_array_be_next;
c.a_stb_array_priv <= c.b_stb_array_priv_next;
c.a_stb_array_way <= c.b_stb_array_way_next;
c.a_stb_head_valid <= reduce_or(c.a_stb_head_ptr and c.a_stb_array_valid);
c.a_stb_head_alloc <= reduce_or(c.a_stb_head_ptr and c.a_stb_array_alloc);
c.a_stb_head_writethrough <= reduce_or(c.a_stb_head_ptr and c.a_stb_array_writethrough);
c.a_stb_head_cache_hit <= reduce_or(c.a_stb_head_ptr and c.a_stb_array_cache_hit);
c.a_stb_head_be <= reduce_or(c.a_stb_head_ptr and c.a_stb_array_be);
c.a_stb_head_priv <= reduce_or(c.a_stb_head_ptr and c.a_stb_array_priv);
a_stb_head_way_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_l1mem_data_cache_assoc,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_way,
sel => c.a_stb_head_ptr,
dout => c.a_stb_head_way
);
c.a_stb_full <= reduce_and(c.a_stb_array_valid);
c.a_stb_quick_store <= (
c.a_stb_head_cache_hit and
not c.a_stb_head_writethrough and
c.b_rmdram_owner_next(cpu_l1mem_data_cache_owner_index_none)
);
-- new request selection, declare wants
c.a_new_request <= (code => cpu_l1mem_data_cache_ctrl_in.request,
cacheen => cpu_l1mem_data_cache_ctrl_in.cacheen,
mmuen => cpu_l1mem_data_cache_ctrl_in.mmuen,
writethrough => cpu_l1mem_data_cache_ctrl_in.writethrough,
priv => cpu_l1mem_data_cache_ctrl_in.priv,
be => cpu_l1mem_data_cache_ctrl_in.be,
alloc => cpu_l1mem_data_cache_ctrl_in.alloc
);
c.a_new_request_stb_wait <= (
c.a_stb_full and
not c.a_stb_quick_store
);
with c.a_request.cacheen select
c.a_new_request_state_load <= request_state_uncached_load_mmu_access when '0',
request_state_cached_load_l1_access when '1',
(others => 'X') when others;
c.a_new_request_state_store <= (
request_state_index_uncached_store_mmu_access => (
not c.a_request.cacheen
),
request_state_index_cached_store_stb_wait => (
c.a_request.cacheen and
c.a_new_request_stb_wait
),
request_state_index_cached_store_l1_access => (
c.a_request.cacheen and
not c.a_new_request_stb_wait
),
others => '0'
);
with c.a_request.code select
c.a_new_request_state <= request_state_none when cpu_l1mem_data_request_code_none,
c.a_new_request_state_load when cpu_l1mem_data_request_code_load,
c.a_new_request_state_store when cpu_l1mem_data_request_code_store,
request_state_invalidate_sync when cpu_l1mem_data_request_code_invalidate,
request_state_flush_l1_access when cpu_l1mem_data_request_code_flush,
request_state_writeback_l1_access when cpu_l1mem_data_request_code_writeback,
request_state_sync when cpu_l1mem_data_request_code_sync,
(others => 'X') when others;
with c.b_request_complete select
c.a_request <= c.a_new_request when '1',
r.b_request when '0',
request_x when others;
with c.b_request_complete select
c.a_request_state <= c.a_new_request_state when '1',
c.b_request_state_next when '0',
(others => 'X') when others;
c.a_request_way <= c.b_request_way_next;
c.a_request_cache_accessed <= c.b_request_cache_accessed_next and not c.b_request_complete;
c.a_request_mmu_accessed <= r.b_request_mmu_accessed and not c.b_request_complete;
c.a_request_cache_block_valid <= c.b_request_cache_block_valid;
c.a_request_cache_block_dirty <= c.b_request_cache_block_dirty;
with c.a_request_state select
c.a_request_want_vtram <= '0' when request_state_none |
request_state_uncached_load_mmu_access |
request_state_uncached_load_bus_op |
request_state_uncached_store_mmu_access |
request_state_uncached_store_bus_op |
request_state_cached_load_writeback |
request_state_cached_load_fill |
request_state_cached_store_stb_wait |
request_state_writeback_bus_op |
request_state_invalidate_sync,
'1' when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_invalidate_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_want_rmdram <= '0' when request_state_none |
request_state_uncached_load_mmu_access |
request_state_uncached_load_bus_op |
request_state_uncached_store_mmu_access |
request_state_uncached_store_bus_op |
request_state_cached_load_writeback |
request_state_cached_load_fill |
request_state_cached_store_l1_access |
request_state_cached_store_stb_wait |
request_state_writeback_bus_op |
request_state_invalidate_sync,
'1' when request_state_cached_load_l1_access |
request_state_writeback_l1_access |
request_state_invalidate_l1_access |
request_state_flush_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_want_bus_op <= '0' when request_state_none |
request_state_uncached_load_mmu_access |
request_state_uncached_store_mmu_access |
request_state_cached_load_l1_access |
request_state_cached_store_stb_wait |
request_state_cached_store_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access |
request_state_flush_invalidate_l1_access |
request_state_invalidate_sync |
request_state_invalidate_l1_access,
'1' when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op |
request_state_cached_load_writeback |
request_state_cached_load_fill |
request_state_writeback_bus_op |
request_state_flush_bus_op,
'X' when others;
with c.b_bus_op_owner_next select
c.a_request_can_own_bus_op <= '1' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.b_vtram_owner_next select
c.a_request_can_own_vtram <= '1' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.b_rmdram_owner_next select
c.a_request_can_own_rmdram <= '1' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
c.a_request_granted <= (
not (c.a_request_want_vtram and
not c.a_request_can_own_vtram
) and
not (c.a_request_want_rmdram and
not c.a_request_can_own_rmdram
) and
not (c.a_request_want_bus_op and
not c.a_request_can_own_bus_op
)
);
with c.a_request_state select
c.a_request_bus_op_code <= bus_op_code_load when request_state_uncached_load_bus_op,
bus_op_code_store when request_state_uncached_store_bus_op,
bus_op_code_fill when request_state_cached_load_fill,
bus_op_code_writeback when request_state_writeback_bus_op |
request_state_cached_load_writeback,
(others => 'X') when others;
with c.a_request_state select
c.a_request_vram_re <= not c.a_request_cache_accessed when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_writeback_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_mram_re <= not c.a_request_cache_accessed when request_state_cached_load_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_tram_en <= not c.a_request_cache_accessed when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
'0' when request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_tram_we <= '0' when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_tram_banken <= (others => '1') when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access,
(others => 'X') when others;
with c.a_request_state select
c.a_request_dram_en <= not c.a_request_cache_accessed when request_state_cached_load_l1_access,
'0' when request_state_writeback_l1_access |
request_state_flush_l1_access |
request_state_invalidate_l1_access,
'X' when others;
with c.a_request_state select
c.a_request_replace_re <= not c.a_request_cache_accessed when request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_invalidate_l1_access,
'X' when others;
c.a_request_mmu_accessed_next <= c.a_request_mmu_accessed or cpu_mmu_data_ctrl_out.ready;
with c.b_bus_op_owner_next select
c.a_stb_can_own_bus_op <= '1' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.b_vtram_owner_next select
c.a_stb_can_own_vtram <= '1' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.b_rmdram_owner_next select
c.a_stb_can_own_rmdram <= '1' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.b_stb_state_next select
c.a_stb_can_activate <= '1' when stb_state_init,
'0' when stb_state_replace_access |
stb_state_writeback |
stb_state_fill |
stb_state_write,
'X' when others;
c.a_stb_activate <= (
c.a_stb_can_activate and
c.a_stb_head_valid and
not c.a_request_want_bus_op and
not (not c.a_stb_can_own_rmdram or
(c.a_request_granted and c.a_request_want_rmdram)
) and
not (not c.a_stb_head_cache_hit and
c.a_stb_head_alloc and
(not c.a_stb_can_own_vtram or
(c.a_request_granted and c.a_request_want_vtram) or
not c.a_stb_can_own_bus_op or
(c.a_request_granted and c.a_request_want_bus_op))
) and
not (((not c.a_stb_head_cache_hit and
not c.a_stb_head_alloc
) or
c.a_stb_head_writethrough) and
not c.a_stb_can_own_bus_op and
(c.a_request_granted and c.a_request_want_bus_op)
)
);
with c.a_stb_activate select
c.a_stb_write_cache <= (c.a_stb_head_cache_hit or
c.a_stb_head_alloc) when '1',
c.b_stb_write_cache_next when '0',
'X' when others;
with c.a_stb_activate select
c.a_stb_write_bus <= (c.a_stb_head_writethrough or
(not c.a_stb_head_alloc and
not c.a_stb_head_cache_hit)) when '1',
c.b_stb_write_bus_next when '0',
'X' when others;
with c.a_stb_activate select
c.a_stb_way <= c.a_stb_head_way when '1',
c.b_stb_way_next when '0',
(others => 'X') when others;
with c.a_stb_activate select
c.a_stb_state <= (stb_state_index_init => '0',
stb_state_index_replace_access => not c.a_stb_head_cache_hit and c.a_stb_head_alloc,
stb_state_index_write => c.a_stb_head_cache_hit or not c.a_stb_head_alloc,
others => '0'
) when '1',
c.b_stb_state_next when '0',
(others => 'X') when others;
with c.a_stb_state select
c.a_stb_active <= '0' when stb_state_init,
'1' when stb_state_replace_access |
stb_state_fill |
stb_state_writeback |
stb_state_write,
'X' when others;
with c.a_stb_state select
c.a_stb_want_vtram <= '1' when stb_state_replace_access,
'0' when stb_state_init |
stb_state_write |
stb_state_fill |
stb_state_writeback,
'X' when others;
with c.a_stb_state select
c.a_stb_want_rmdram <= '1' when stb_state_replace_access,
c.a_stb_write_cache when stb_state_write,
'0' when stb_state_init |
stb_state_fill |
stb_state_writeback,
'X' when others;
with c.a_stb_state select
c.a_stb_want_bus_op <= c.a_stb_write_bus when stb_state_write,
'1' when stb_state_replace_access |
stb_state_writeback |
stb_state_fill,
'0' when stb_state_init,
'X' when others;
with c.a_stb_state select
c.a_stb_vram_re <= '1' when stb_state_replace_access,
'X' when others;
with c.a_stb_state select
c.a_stb_mram_re <= '1' when stb_state_replace_access,
c.a_stb_write_cache when stb_state_write,
'X' when others;
with c.a_stb_state select
c.a_stb_tram_en <= '1' when stb_state_replace_access,
'X' when others;
with c.a_stb_state select
c.a_stb_tram_we <= '0' when stb_state_replace_access,
'X' when others;
with c.a_stb_state select
c.a_stb_tram_banken <= (others => '1') when stb_state_replace_access,
(others => 'X') when others;
with c.a_stb_state select
c.a_stb_dram_en <= '0' when stb_state_replace_access,
'1' when stb_state_write,
'X' when others;
with c.a_stb_state select
c.a_stb_dram_we <= '1' when stb_state_write,
'X' when others;
c.a_stb_dram_wdata_be <= c.a_stb_head_be;
with c.a_stb_state select
c.a_stb_replace_re <= '1' when stb_state_replace_access,
'0' when stb_state_writeback |
stb_state_fill |
stb_state_write,
'X' when others;
with c.a_stb_state select
c.a_stb_bus_op_code <= bus_op_code_none when stb_state_replace_access,
bus_op_code_writeback when stb_state_writeback,
bus_op_code_fill when stb_state_fill,
bus_op_code_store when stb_state_write,
(others => 'X') when others;
c.a_stb_bus_op_way <= c.a_stb_way;
c.a_new_bus_op_owner <= (
cpu_l1mem_data_cache_owner_index_none => (
not (c.a_request_granted and c.a_request_want_bus_op) and
not (c.a_stb_active and c.a_stb_want_bus_op)
),
cpu_l1mem_data_cache_owner_index_request => (
c.a_request_granted and c.a_request_want_bus_op
),
cpu_l1mem_data_cache_owner_index_stb => (
c.a_stb_active and c.a_stb_want_bus_op
),
cpu_l1mem_data_cache_owner_index_bus_op => '0'
);
with c.a_new_bus_op_owner select
c.a_new_bus_op_code <= c.a_request_bus_op_code when cpu_l1mem_data_cache_owner_request,
c.a_stb_bus_op_code when cpu_l1mem_data_cache_owner_stb,
bus_op_code_none when cpu_l1mem_data_cache_owner_none,
(others => 'X') when others;
with c.a_new_bus_op_code select
c.a_new_bus_op_state <= bus_op_state_none when bus_op_code_none,
bus_op_state_load when bus_op_code_load,
bus_op_state_store when bus_op_code_store,
bus_op_state_fill_first when bus_op_code_fill,
bus_op_state_writeback_first when bus_op_code_writeback,
(others => 'X') when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_cacheable <= c.a_request.cacheen when cpu_l1mem_data_cache_owner_request,
'1' when cpu_l1mem_data_cache_owner_stb,
'X' when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_be <= c.a_request.be when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_be when cpu_l1mem_data_cache_owner_stb,
'X' when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_priv <= c.a_request.priv when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_priv when cpu_l1mem_data_cache_owner_stb,
'X' when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_way <= c.a_request_way when cpu_l1mem_data_cache_owner_request,
c.a_stb_bus_op_way when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
c.a_new_bus_op_block_word <= (0 => '1', others => '0');
with c.a_request_state select
c.a_new_bus_op_paddr_tag_sel_request <=
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_request when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op |
request_state_cached_load_fill |
request_state_writeback_bus_op |
request_state_flush_bus_op,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_replace when request_state_cached_load_writeback,
(others => 'X') when others;
with c.a_request_state select
c.a_new_bus_op_paddr_index_sel_request <=
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_request when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op |
request_state_cached_load_fill |
request_state_cached_load_writeback |
request_state_writeback_bus_op |
request_state_flush_bus_op,
(others => 'X') when others;
with c.a_request_state select
c.a_new_bus_op_paddr_offset_sel_request <=
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word when request_state_cached_load_fill |
request_state_cached_load_writeback |
request_state_writeback_bus_op |
request_state_flush_bus_op,
(others => 'X') when others;
with c.a_stb_state select
c.a_new_bus_op_paddr_tag_sel_stb <=
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_stb when stb_state_write |
stb_state_fill,
cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_replace when stb_state_writeback,
(others => 'X') when others;
with c.a_stb_state select
c.a_new_bus_op_paddr_index_sel_stb <=
cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_stb when stb_state_write |
stb_state_fill |
stb_state_writeback,
(others => 'X') when others;
with c.a_stb_state select
c.a_new_bus_op_paddr_offset_sel_stb <=
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb when stb_state_write,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word when stb_state_fill |
stb_state_writeback,
(others => 'X') when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_paddr_tag_sel <= c.a_new_bus_op_paddr_tag_sel_request when cpu_l1mem_data_cache_owner_request,
c.a_new_bus_op_paddr_tag_sel_stb when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_paddr_index_sel <= c.a_new_bus_op_paddr_index_sel_request when cpu_l1mem_data_cache_owner_request,
c.a_new_bus_op_paddr_index_sel_stb when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_paddr_offset_sel <= c.a_new_bus_op_paddr_offset_sel_request when cpu_l1mem_data_cache_owner_request,
c.a_new_bus_op_paddr_offset_sel_stb when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
with c.a_request_state select
c.a_new_bus_op_size_sel_request <=
cpu_l1mem_data_cache_a_bus_op_size_sel_request when request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op,
cpu_l1mem_data_cache_a_bus_op_size_sel_word when request_state_cached_load_fill |
request_state_cached_load_writeback |
request_state_writeback_bus_op |
request_state_flush_bus_op,
(others => 'X') when others;
with c.a_stb_state select
c.a_new_bus_op_size_sel_stb <=
cpu_l1mem_data_cache_a_bus_op_size_sel_stb when stb_state_write,
cpu_l1mem_data_cache_a_bus_op_size_sel_word when stb_state_fill |
stb_state_writeback,
(others => 'X') when others;
with c.a_new_bus_op_owner select
c.a_new_bus_op_size_sel <= c.a_new_bus_op_size_sel_request when cpu_l1mem_data_cache_owner_request,
c.a_new_bus_op_size_sel_stb when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
with c.b_bus_op_owner_next(cpu_l1mem_data_cache_owner_index_none) select
c.a_bus_op_owner <= c.b_bus_op_owner_next when '0',
c.a_new_bus_op_owner when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_state <= c.b_bus_op_state_next when '0',
c.a_new_bus_op_state when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_cacheable <= r.b_bus_op_cacheable when '0',
c.a_new_bus_op_cacheable when '1',
'X' when others;
with c.b_bus_op_complete select
c.a_bus_op_be <= r.b_bus_op_be when '0',
c.a_new_bus_op_be when '1',
'X' when others;
with c.b_bus_op_complete select
c.a_bus_op_priv <= r.b_bus_op_priv when '0',
c.a_new_bus_op_priv when '1',
'X' when others;
with c.b_bus_op_complete select
c.a_bus_op_way <= r.b_bus_op_way when '0',
c.a_new_bus_op_way when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_block_word <= c.b_bus_op_block_word_next when '0',
c.a_new_bus_op_block_word when '1',
(others => 'X') when others;
c.a_bus_op_requested <= (
(r.b_bus_op_requested and
not c.b_bus_op_complete) or
sys_slave_ctrl_out.ready
);
with c.b_bus_op_complete select
c.a_bus_op_paddr_tag_sel <= cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_old when '0',
c.a_new_bus_op_paddr_tag_sel when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_paddr_index_sel <= cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_old when '0',
c.a_new_bus_op_paddr_index_sel when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_paddr_offset_sel <= (cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_old =>
not c.b_bus_op_block_word_advance,
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_index_next_word =>
c.b_bus_op_block_word_advance,
others => '0'
) when '0',
c.a_new_bus_op_paddr_offset_sel when '1',
(others => 'X') when others;
with c.b_bus_op_complete select
c.a_bus_op_size_sel <= cpu_l1mem_data_cache_a_bus_op_size_sel_old when '0',
c.a_new_bus_op_size_sel when '1',
(others => 'X') when others;
with c.a_bus_op_state select
c.a_bus_op_cache_paddr_sel_old <= '1' when bus_op_state_fill |
bus_op_state_fill_last,
'0' when bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last |
bus_op_state_fill_first,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_sys_paddr_sel_old <= '1' when bus_op_state_writeback |
bus_op_state_writeback_last,
'0' when bus_op_state_load |
bus_op_state_store |
bus_op_state_writeback_first |
bus_op_state_fill |
bus_op_state_fill_first,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_sys_data_sel_cache <= '1' when bus_op_state_writeback |
bus_op_state_writeback_last,
'0' when bus_op_state_store,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_want_cache <= '0' when bus_op_state_none |
bus_op_state_load |
bus_op_state_store,
'1' when bus_op_state_fill_first |
bus_op_state_writeback_first,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_vram_re <= '1' when bus_op_state_fill_first | -- clear valid bit
bus_op_state_fill_last, -- set valid bit
'0' when bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_mram_re <= '1' when bus_op_state_fill_last,
sys_slave_ctrl_out.ready when bus_op_state_writeback_last,
'0' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_tram_en <= '1' when bus_op_state_fill_last, -- write tag for fill
'0' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_tram_we <= '1' when bus_op_state_fill_last, -- write tag for fill
'X' when others;
c.a_bus_op_tram_banken <= c.a_bus_op_way;
with c.a_bus_op_state select
c.a_bus_op_dram_en <= '1' when bus_op_state_writeback_first,
sys_slave_ctrl_out.ready when bus_op_state_fill |
bus_op_state_fill_last |
bus_op_state_writeback,
'0' when bus_op_state_fill_first |
bus_op_state_writeback_last,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_dram_we <= '1' when bus_op_state_fill |
bus_op_state_fill_last,
'0' when bus_op_state_writeback_first |
bus_op_state_writeback,
'X' when others;
with c.a_bus_op_state select
c.a_bus_op_replace_re <= '1' when bus_op_state_fill_last,
'0' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
'X' when others;
with c.b_vtram_owner_next select
c.a_bus_op_can_own_vtram <= '1' when cpu_l1mem_data_cache_owner_bus_op |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_request,
'X' when others;
with c.b_rmdram_owner_next select
c.a_bus_op_can_own_rmdram <= '1' when cpu_l1mem_data_cache_owner_bus_op |
cpu_l1mem_data_cache_owner_none,
'0' when cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_request,
'X' when others;
c.a_bus_op_granted <= (
not (c.a_bus_op_want_cache and
(not c.a_bus_op_can_own_vtram or
not c.a_bus_op_can_own_rmdram or
(c.a_request_granted and (c.a_request_want_vtram or
c.a_request_want_rmdram)) or
(c.a_stb_active and (c.a_stb_want_vtram or
c.a_stb_want_rmdram))
)
)
);
c.a_new_vtram_owner <= (
cpu_l1mem_data_cache_owner_index_none => (
not (c.a_request_granted and c.a_request_want_vtram) and
not (c.a_stb_active and c.a_stb_want_vtram) and
not (c.a_bus_op_granted and c.a_bus_op_want_cache)
),
cpu_l1mem_data_cache_owner_index_request => (
c.a_request_granted and c.a_request_want_vtram
),
cpu_l1mem_data_cache_owner_index_stb => (
c.a_stb_active and c.a_stb_want_vtram
),
cpu_l1mem_data_cache_owner_index_bus_op => (
c.a_bus_op_granted and c.a_bus_op_want_cache
)
);
with c.b_vtram_owner_next select
c.a_vtram_owner <= c.a_new_vtram_owner when cpu_l1mem_data_cache_owner_none,
c.b_vtram_owner_next when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.a_new_rmdram_owner <= (
cpu_l1mem_data_cache_owner_index_none => (
not (c.a_request_granted and c.a_request_want_rmdram) and
not (c.a_stb_active and c.a_stb_want_rmdram) and
not (c.a_bus_op_granted and c.a_bus_op_want_cache)
),
cpu_l1mem_data_cache_owner_index_request => (
c.a_request_granted and c.a_request_want_rmdram
),
cpu_l1mem_data_cache_owner_index_stb => (
c.a_stb_active and c.a_stb_want_rmdram
),
cpu_l1mem_data_cache_owner_index_bus_op => (
c.a_bus_op_granted and c.a_bus_op_want_cache
)
);
with c.b_rmdram_owner_next select
c.a_rmdram_owner <= c.a_new_rmdram_owner when cpu_l1mem_data_cache_owner_none,
c.b_rmdram_owner_next when cpu_l1mem_data_cache_owner_request |
cpu_l1mem_data_cache_owner_stb |
cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
-- choose cache component inputs
with c.a_vtram_owner select
c.a_vram_re <= c.a_request_vram_re when cpu_l1mem_data_cache_owner_request,
c.a_stb_vram_re when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_vram_re when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_none,
'X' when others;
with c.a_rmdram_owner select
c.a_mram_re <= c.a_request_mram_re when cpu_l1mem_data_cache_owner_request,
c.a_stb_mram_re when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_mram_re when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_none,
'X' when others;
with c.a_vtram_owner select
c.a_tram_en <= c.a_request_tram_en when cpu_l1mem_data_cache_owner_request,
c.a_stb_tram_en when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_tram_en when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_none,
'X' when others;
with c.a_vtram_owner select
c.a_tram_we <= c.a_request_tram_we when cpu_l1mem_data_cache_owner_request,
c.a_stb_tram_we when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_tram_we when cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.a_vtram_owner select
c.a_tram_banken <= c.a_request_tram_banken when cpu_l1mem_data_cache_owner_request,
c.a_stb_tram_banken when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_tram_banken when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with c.a_rmdram_owner select
c.a_dram_en <= c.a_request_dram_en when cpu_l1mem_data_cache_owner_request,
c.a_stb_dram_en when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_dram_en when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_none,
'X' when others;
with c.a_rmdram_owner select
c.a_dram_we <= '0' when cpu_l1mem_data_cache_owner_request,
c.a_stb_dram_we when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_dram_we when cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.a_rmdram_owner select
c.a_dram_wdata_be <= c.a_stb_head_be when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_be when cpu_l1mem_data_cache_owner_bus_op,
'X' when others;
with c.a_rmdram_owner select
c.a_replace_re <= c.a_request_replace_re when cpu_l1mem_data_cache_owner_request,
c.a_stb_replace_re when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_replace_re when cpu_l1mem_data_cache_owner_bus_op,
'0' when cpu_l1mem_data_cache_owner_none,
'X' when others;
with c.a_request_state select
c.a_mmu_request <= '0' when request_state_none |
request_state_uncached_load_bus_op |
request_state_uncached_store_bus_op |
request_state_cached_load_fill |
request_state_cached_load_writeback |
request_state_cached_store_stb_wait |
request_state_invalidate_sync |
request_state_writeback_sync |
request_state_writeback_bus_op |
request_state_flush_sync |
request_state_flush_bus_op |
request_state_sync,
'1' when request_state_uncached_load_mmu_access |
request_state_uncached_store_mmu_access |
request_state_cached_load_l1_access |
request_state_cached_store_l1_access |
request_state_invalidate_l1_access |
request_state_writeback_l1_access |
request_state_flush_l1_access |
request_state_flush_invalidate_l1_access,
'X' when others;
with c.a_bus_op_state select
c.a_sys_request <= '1' when bus_op_state_load |
bus_op_state_store |
bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_writeback |
bus_op_state_writeback_last,
'0' when bus_op_state_none |
bus_op_state_fill_last |
bus_op_state_writeback_first,
'X' when others;
c.a_sys_be <= c.a_bus_op_be;
with c.a_bus_op_state select
c.a_sys_write <= '0' when bus_op_state_load |
bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_fill_last,
'1' when bus_op_state_store |
bus_op_state_writeback |
bus_op_state_writeback_last,
'X' when others;
with c.a_bus_op_state select
c.a_sys_cacheable <= '0' when bus_op_state_load |
bus_op_state_store,
'1' when bus_op_state_fill_first |
bus_op_state_fill |
bus_op_state_fill_last |
bus_op_state_writeback_first |
bus_op_state_writeback |
bus_op_state_writeback_last,
'X' when others;
c.a_sys_priv <= c.a_bus_op_priv;
a_sys_burst_gen_bursts : if sys_max_burst_cycles > 1 generate
with c.a_bus_op_state select
c.a_sys_burst <=
not c.a_bus_op_block_word(cpu_l1mem_data_cache_block_words-1) when bus_op_state_fill_first |
bus_op_state_fill,
'1' when bus_op_state_writeback,
'0' when bus_op_state_load |
bus_op_state_store |
bus_op_state_writeback_last,
'X' when others;
c.a_sys_bcycles <= std_ulogic_vector(to_unsigned(cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes, sys_burst_cycles_bits));
end generate;
a_sys_burst_gen_no_bursts : if sys_max_burst_cycles <= 1 generate
c.a_sys_burst <= '0';
c.a_sys_bcycles <= (others => 'X');
end generate;
r_next <= (
b_vtram_owner => c.a_vtram_owner,
b_rmdram_owner => c.a_rmdram_owner,
b_request_granted => c.a_request_granted,
b_request => c.a_request,
b_request_state => c.a_request_state,
b_request_way => c.a_request_way,
b_request_mmu_accessed => c.a_request_mmu_accessed_next,
b_request_cache_block_dirty => c.a_request_cache_block_dirty,
b_bus_op_granted => c.a_bus_op_granted,
b_bus_op_owner => c.a_bus_op_owner,
b_bus_op_state => c.a_bus_op_state,
b_bus_op_way => c.a_bus_op_way,
b_bus_op_be => c.a_bus_op_be,
b_bus_op_block_word => c.a_bus_op_block_word,
b_bus_op_cacheable => c.a_bus_op_cacheable,
b_bus_op_priv => c.a_bus_op_priv,
b_bus_op_requested => c.a_bus_op_requested,
b_stb_state => c.a_stb_state,
b_stb_head_ptr => c.a_stb_head_ptr,
b_stb_tail_ptr => c.a_stb_tail_ptr,
b_stb_way => c.a_stb_way,
b_stb_write_cache => c.a_stb_write_cache,
b_stb_write_bus => c.a_stb_write_bus,
b_stb_array_valid => c.a_stb_array_valid,
b_stb_array_alloc => c.a_stb_array_alloc,
b_stb_array_writethrough => c.a_stb_array_writethrough,
b_stb_array_be => c.a_stb_array_be,
b_stb_array_priv => c.a_stb_array_priv,
b_stb_array_cache_hit => c.a_stb_array_cache_hit,
b_stb_array_way => c.a_stb_array_way
);
cpu_l1mem_data_cache_ctrl_out <= (
ready => c.b_result_ready,
result => c.b_result_code
);
sys_master_ctrl_out <= (request => c.a_sys_request,
be => c.a_sys_be,
write => c.a_sys_write,
cacheable => c.a_sys_cacheable,
priv => c.a_sys_priv,
inst => '0',
burst => c.a_sys_burst,
bwrap => '1',
bcycles => c.a_sys_bcycles
);
cpu_l1mem_data_cache_ctrl_out_vram <= (re => c.a_vram_re,
we => c.b_vram_we,
wdata => c.b_vram_wdata
);
cpu_l1mem_data_cache_ctrl_out_mram <= (re => c.a_mram_re,
we => c.b_mram_we,
wdata => c.b_mram_wdata
);
cpu_l1mem_data_cache_ctrl_out_tram <= (en => c.a_tram_en,
we => c.a_tram_we,
banken => c.a_tram_banken
);
cpu_l1mem_data_cache_ctrl_out_dram <= (en => c.a_dram_en,
we => c.a_dram_we
);
cpu_l1mem_data_cache_dp_in_ctrl <= (
a_stb_head_ptr => c.a_stb_head_ptr,
a_stb_head_be => c.a_stb_head_be,
a_stb_way => c.a_stb_way,
a_vtram_owner => c.a_vtram_owner,
a_rmdram_owner => c.a_rmdram_owner,
a_bus_op_owner => c.a_bus_op_owner,
a_bus_op_way => c.a_bus_op_way,
a_bus_op_size_sel => c.a_bus_op_size_sel,
a_bus_op_paddr_tag_sel => c.a_bus_op_paddr_tag_sel,
a_bus_op_paddr_index_sel => c.a_bus_op_paddr_index_sel,
a_bus_op_paddr_offset_sel => c.a_bus_op_paddr_offset_sel,
a_bus_op_cache_paddr_sel_old => c.a_bus_op_cache_paddr_sel_old,
a_bus_op_sys_paddr_sel_old => c.a_bus_op_sys_paddr_sel_old,
a_bus_op_sys_data_sel_cache => c.a_bus_op_sys_data_sel_cache,
a_dram_wdata_be => c.a_dram_wdata_be,
b_vtram_owner => r.b_vtram_owner,
b_rmdram_owner => r.b_rmdram_owner,
b_stb_head_ptr => r.b_stb_head_ptr,
b_replace_way => c.b_replace_way,
b_stb_push_ptr => c.b_stb_push_ptr,
b_stb_combine_ptr => c.b_stb_combine_ptr,
b_cache_read_data_be => c.b_cache_read_data_be,
b_cache_read_data_way => c.b_cache_read_data_way,
b_request_be => r.b_request.be,
b_request_stb_array_hit => c.b_request_stb_array_hit,
b_request_complete => c.b_request_complete,
b_result_data_sel => c.b_result_data_sel
);
cpu_l1mem_data_cache_replace_ctrl_in <= (
re => c.a_replace_re,
we => c.b_replace_we,
wway => c.b_replace_wway
);
cpu_mmu_data_ctrl_in <= (
request => c.a_mmu_request,
mmuen => c.a_request.mmuen
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
end;
| apache-2.0 | 8c004e742a92cf87f127e1c75a43085c | 0.514107 | 3.467945 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/deadtime.vhd | 2 | 1,214 | -------------------------------------------------------------------------------
-- Title : Deadtime generation
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
entity deadtime is
generic (
T_DEAD : natural -- Number of Deadtime cycles
);
port (
in_p : in std_logic;
out_p : out std_logic := '0';
clk : in std_logic
);
end deadtime;
architecture behavioral of deadtime is
signal delay : integer range 0 to T_DEAD - 1 := 0;
begin
process
begin
wait until rising_edge(clk);
if (in_p = '0') then
out_p <= '0';
delay <= 0;
else
if (delay < (T_DEAD - 1)) then
delay <= delay + 1;
else
out_p <= '1';
end if;
end if;
end process;
end behavioral;
| bsd-3-clause | 96d8ff5d3f48fbf61e44e85d0223635e | 0.400329 | 4.56391 | false | false | false | false |
loa-org/loa-hdl | modules/uart/tb/uart_rx_disable_tb.vhd | 2 | 2,559 | -------------------------------------------------------------------------------
-- Title : Testbench for design "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx_disable_tb is
end entity uart_rx_disable_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_rx_disable_tb is
-- component ports
signal rxd : std_logic := '1';
signal disable : std_logic := '0';
signal data : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_rx
port map (
rxd_p => rxd,
disable_p => disable,
data_p => data,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
clk_rx_en <= '1';
wait until rising_edge(clk);
-- clk_rx_en <= '1';
-- wait until rising_edge(clk);
-- clk_rx_en <= '0';
-- wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
wait;
end process waveform;
gen_disable : process
begin
wait until rising_edge(clk);
wait for 50 ns;
disable <= '1';
wait for 20 ns;
disable <= '0';
wait for 3 us;
disable <= '1';
wait for 200 ns;
disable <= '0';
wait;
end process;
end architecture behavourial;
| bsd-3-clause | d0aec732525c7818ce106b800a8141f8 | 0.432591 | 4.435009 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/synth/system_ov7670_vga_1_0.vhd | 2 | 3,941 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 19
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_1_0 IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_1_0;
ARCHITECTURE system_ov7670_vga_1_0_arch OF system_ov7670_vga_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_1_0_arch : ARCHITECTURE IS "system_ov7670_vga_1_0,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "system_ov7670_vga_1_0,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=19,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF active: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : ov7670_vga
PORT MAP (
clk_x2 => clk_x2,
active => active,
data => data,
rgb => rgb
);
END system_ov7670_vga_1_0_arch;
| mit | a5ee8f5b3a9170b1031bd55a57e4229c | 0.736869 | 3.785783 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/sim/system_zed_vga_0_0.vhd | 1 | 3,529 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : zed_vga
PORT MAP (
clk => clk,
active => active,
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
| mit | 15f3b2d9e0a87b66bbc12ca772efcf8c | 0.717767 | 3.873765 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 196,508 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:12:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 1;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => S_AXI_HP0_ACLK,
S_AXI_HP0_ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => S_AXI_HP0_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => S_AXI_HP0_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => S_AXI_HP0_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => S_AXI_HP0_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => S_AXI_HP0_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => S_AXI_HP0_AWVALID,
S_AXI_HP0_BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
S_AXI_HP0_BREADY => S_AXI_HP0_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
S_AXI_HP0_BVALID => S_AXI_HP0_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
S_AXI_HP0_RLAST => S_AXI_HP0_RLAST,
S_AXI_HP0_RREADY => S_AXI_HP0_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
S_AXI_HP0_RVALID => S_AXI_HP0_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
S_AXI_HP0_WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
S_AXI_HP0_WLAST => S_AXI_HP0_WLAST,
S_AXI_HP0_WREADY => S_AXI_HP0_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => S_AXI_HP0_WVALID,
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | c454936749e1a5b19c90d51b4b14834c | 0.633481 | 2.754335 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl | 1 | 4,327 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 21 18:47:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
| mit | 6f4886a7f056187e1bf23ce247dc61e9 | 0.553732 | 2.921675 | false | false | false | false |
CampbellGroup/fpga | ltc1450/control.vhd | 1 | 1,895 | ----------------------------------------------------------------------------------
-- Campbell Group
--
-- Create Date: 12/08/2014
-- Module Name: controller
-- Description: DAC controller for Linear Technology FTC1450
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY FTC1450_Controller IS
PORT ( clock :IN STD_LOGIC;
reset : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(12 downto 0);
data_out : OUT STD_LOGIC_VECTOR(12 downto 0);
csmsb: OUT STD_LOGIC;
cslsb: OUT STD_LOGIC;
wr : OUT STD_LOGIC);
END ENTITY FTC1450_Controller ;
ARCHITECTURE behavior of FTC1450_Controller IS
SIGNAL count : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL update : STD_LOGIC;
BEGIN
PROCESS (update, reset, data_in)
BEGIN
IF (reset = '0') THEN
data_out(12 downto 0) <= (OTHERS => '0');
ELSIF (update'event AND update = '1') THEN
data_out(12 downto 0) <= data_in(12 downto 0);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (rest = '0') THEN
count(2 downto 0) <= "000";
ELSIF (clock'event AND clock='1') THEN
IF (count = "100") THEN
count <= "000";
ELSE
count <= count + 1;
END IF;
END IF;
END PROCESS;
PROCESS(count)
BEGIN
IF (count = "000") THEN
update <= '0';
csmsb <= '1';
cslsb <= '1';
wr <= '1';
ELSIF (count = "001") THEN
update <= '1';
csmsb <= '1';
cslsb <= '1';
wr <= '1';
ELSIF (count = "010") THEN
update <= '0';
csmsb <= '0';
cslsb <= '0';
wr <= '1';
ELSIF (count = "011") THEN
update <= '0';
csmsb <= '0';
cslsb <= '0';
wr <= '0';
ELSIF (count = "100") THEN
update <= '0';
csmsb <= '0';
cslsb <= '0';
wr <= '1';
ELSE
update <= '0';
csmsb <= '1';
cslsb <= '1';
wr <= '1';
END IF;
END PROCESS;
END ARCHITECTURE behavior
| mit | 95f50c7cc02721492336de0c577f6a52 | 0.539842 | 2.910906 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd | 1 | 8,468 | -- niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 74;
FIFO_DEPTH : integer := 4;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 1;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 1;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(73 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
out_data : out std_logic_vector(73 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
out_endofpacket : out std_logic; -- .endofpacket
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_error : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_error : out std_logic
);
end entity niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo;
architecture rtl of niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(73 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
out_endofpacket => out_endofpacket, -- .endofpacket
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo
| apache-2.0 | de1e09486c42035ec4319bad9d59d0bd | 0.435758 | 3.986817 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_0/synth/affine_block_ieee754_fp_adder_subtractor_0_0.vhd | 2 | 4,122 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_adder_subtractor:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_adder_subtractor_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_adder_subtractor_0_0;
ARCHITECTURE affine_block_ieee754_fp_adder_subtractor_0_0_arch OF affine_block_ieee754_fp_adder_subtractor_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_adder_subtractor IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_adder_subtractor;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "ieee754_fp_adder_subtractor,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_adder_subtractor_0_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_0,ieee754_fp_adder_subtractor,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_0,ieee754_fp_adder_subtractor,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_adder_subtractor,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_adder_subtractor
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_adder_subtractor_0_0_arch;
| mit | 0d551dda2826484c44558ea4ed9db364 | 0.751577 | 3.774725 | false | false | false | false |
adelapie/xtea | round_f.vhd | 1 | 1,451 |
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity round_f is
port(v_in : in std_logic_vector(31 downto 0);
last_val : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(31 downto 0));
end round_f;
architecture Behavioral of round_f is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_3_s : std_logic_vector(31 downto 0);
signal op_4_s : std_logic_vector(31 downto 0);
begin
op_1_s <= (v_in(27 downto 0) & "0000");
op_2_s <= "00000"& v_in(31 downto 5);
op_3_s <= op_1_s xor op_2_s;
op_4_s <= std_logic_vector(unsigned(op_3_s ) + unsigned(v_in));
v_out <= op_4_s xor last_val;
end Behavioral;
| gpl-3.0 | d4cf76fe62e9663ee1ce15f8ed52cd51 | 0.678153 | 3.154348 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough_vga/video_passthrough_vga.srcs/sources_1/bd/system/ip/system_zybo_vga_0_0/synth/system_zybo_vga_0_0.vhd | 1 | 4,122 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_vga:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_vga_0_0 IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END system_zybo_vga_0_0;
ARCHITECTURE system_zybo_vga_0_0_arch OF system_zybo_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_vga IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT zybo_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zybo_vga_0_0_arch: ARCHITECTURE IS "zybo_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zybo_vga_0_0_arch : ARCHITECTURE IS "system_zybo_vga_0_0,zybo_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zybo_vga_0_0_arch: ARCHITECTURE IS "system_zybo_vga_0_0,zybo_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zybo_vga,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : zybo_vga
PORT MAP (
clk => clk,
active => active,
rgb => rgb,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zybo_vga_0_0_arch;
| mit | dbb0eac8eb7218ab5a5a5120b0e8a9fe | 0.724163 | 3.693548 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/shifter_inferred-rtl.vhdl | 1 | 7,164 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.numeric_pkg.all;
use util.logic_pkg.all;
-- right shift unsigned result zero sel in_left in_right
-- 0 00 1 1234 1 00 XXXX XXXX
-- 0 01 1 234R 0 01 1234 RRRR
-- 0 10 1 34RR 0 10 1234 RRRR
-- 0 11 1 4RRR 0 11 1234 RRRR
-- 1 00 1 1234 1 00 XXXX XXXX
-- 1 01 1 L123 0 11 LLLL 1234
-- 1 10 1 LL12 0 10 LLLL 1234
-- 1 11 1 LLL1 0 01 LLLL 1234
-- 0 00 0 1234 1 00 XXXX XXXX
-- 0 01 0 234R 0 01 1234 RRRR
-- 0 10 0 LL12 0 10 LLLL 1234
-- 0 11 0 L123 0 11 LLLL 1234
-- 1 00 0 1234 1 00 XXXX XXXX
-- 1 01 0 L123 0 11 LLLL 1234
-- 1 10 0 34RR 0 10 1234 RRRR
-- 1 11 0 234R 0 01 1234 RRRR
-- right shift unsigned result zero sel in_left in_right
-- 0 000 1 12345678 1 XXX 12345678 RRRRRRRR
-- 0 001 1 2345678R 0 001 12345678 RRRRRRRR
-- 0 010 1 345678RR 0 010 12345678 RRRRRRRR
-- 0 011 1 45678RRR 0 011 12345678 RRRRRRRR
-- 0 100 1 5678RRRR 0 100 12345678 RRRRRRRR
-- 0 101 1 678RRRRR 0 101 12345678 RRRRRRRR
-- 0 110 1 78RRRRRR 0 110 12345678 RRRRRRRR
-- 0 111 1 8RRRRRRR 0 111 12345678 RRRRRRRR
-- 1 000 1 12345678 1 XXX LLLLLLLL 12345678
-- 1 001 1 L1234567 0 111 LLLLLLLL 12345678
-- 1 010 1 LL123456 0 110 LLLLLLLL 12345678
-- 1 011 1 LLL12345 0 101 LLLLLLLL 12345678
-- 1 100 1 LLLL1234 0 100 LLLLLLLL 12345678
-- 1 101 1 LLLLL123 0 011 LLLLLLLL 12345678
-- 1 110 1 LLLLLL12 0 010 LLLLLLLL 12345678
-- 1 111 1 LLLLLLL1 0 001 LLLLLLLL 12345678
-- 0 000 0 12345678 1 000 12345678 RRRRRRRR
-- 0 001 0 2345678R 0 001 12345678 RRRRRRRR
-- 0 010 0 345678RR 0 010 12345678 RRRRRRRR
-- 0 011 0 45678RRR 0 011 12345678 RRRRRRRR
-- 0 100 0 LLLL1234 0 100 LLLLLLLL 12345678
-- 0 101 0 LLL12345 0 101 LLLLLLLL 12345678
-- 0 110 0 LL123456 0 110 LLLLLLLL 12345678
-- 0 111 0 L1234567 0 111 LLLLLLLL 12345678
-- 1 000 0 12345678 1 000 LLLLLLLL 12345678
-- 1 001 0 L1234567 0 111 LLLLLLLL 12345678
-- 1 010 0 LL123456 0 110 LLLLLLLL 12345678
-- 1 011 0 LLL12345 0 101 LLLLLLLL 12345678
-- 1 100 0 5678RRRR 0 100 12345678 RRRRRRRR
-- 1 101 0 45678RRR 0 011 12345678 RRRRRRRR
-- 1 110 0 345678RR 0 010 12345678 RRRRRRRR
-- 1 111 0 2345678R 0 001 12345678 RRRRRRRR
architecture rtl of shifter_inferred is
constant barrel_size : natural := integer_minimum(shift_bits, log2ceil(src_bits));
type barrel_type is array(0 to barrel_size) of std_ulogic_vector(2*src_bits-1 downto 0);
type comb_type is record
shift_is_neg : std_ulogic;
right_shift : std_ulogic;
right_shift_fill : std_ulogic;
abs_shift : std_ulogic_vector(shift_bits downto 0);
barrel_sel : std_ulogic_vector(barrel_size-1 downto 0);
barrel : barrel_type;
shift_is_zero : std_ulogic;
end record;
signal c : comb_type;
begin
c.shift_is_neg <= not shift_unsgnd and shift(shift_bits-1);
c.right_shift <= (right xor c.shift_is_neg);
c.right_shift_fill <= not unsgnd and src(src_bits-1);
c.abs_shift <= logic_if(right, std_ulogic_vector(-signed(shift)), shift);
c.barrel_sel <= c.abs_shift(barrel_size-1 downto 0);
-- barrel shifter
with c.right_shift select
c.barrel(0) <= (src &
logic_if(rot, src, (src_bits-1 downto 0 => '0'))
) when '0',
(logic_if(rot, src, (src_bits-1 downto 0 => c.right_shift_fill)) &
src
) when '1',
(others => 'X') when others;
barrel_loop : for n in 0 to barrel_size-1 generate
with c.barrel_sel(n) select
c.barrel(n+1) <= c.barrel(n) when '0',
c.barrel(n)(2*src_bits-2**n-1 downto 0) & (2**n-1 downto 0 => 'X') when '1',
(others => 'X') when others;
end generate;
c.shift_is_zero <= all_zeros(shift);
result_1 : if shift_bits > log2(src_bits) generate
blk : block
signal shift_diff : std_ulogic_vector(shift_bits downto 0);
signal shift_overflow : std_ulogic;
signal result_sel : std_ulogic_vector(1 downto 0);
begin
shift_diff <= std_ulogic_vector(to_unsigned(src_bits-1, shift_bits+1) - unsigned('0' & c.abs_shift));
shift_overflow <= shift_diff(shift_bits-1);
result_sel <= (0 => c.shift_is_zero,
1 => shift_overflow
);
with result_sel select
result <= c.barrel(barrel_size)(2*src_bits-1 downto src_bits) when "00",
src when "01",
(others => c.right_shift and c.right_shift_fill) when "10",
(others => 'X') when others;
end block;
end generate;
result_2 : if shift_bits <= log2(src_bits) generate
with c.shift_is_zero select
result <= c.barrel(barrel_size)(2*src_bits-1 downto src_bits) when '0',
src when '1',
(others => 'X') when others;
end generate;
end;
| apache-2.0 | f176f6b99bc990c6264a8f898decd0dc | 0.504188 | 3.508325 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/sim/system_vga_buffer_1_0.vhd | 2 | 4,004 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_1_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_1_0;
ARCHITECTURE system_vga_buffer_1_0_arch OF system_vga_buffer_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_1_0_arch;
| mit | 0c574189bc1d7ebc79a4e4e33deb93cd | 0.697303 | 3.663312 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_pll_200/vga_pll_200.srcs/sources_1/new/vga_pll_200.vhd | 1 | 1,179 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_pll_200 is
port (
clk_200 : in std_logic;
clk_100 : out std_logic;
clk_50 : out std_logic;
clk_25 : out std_logic;
clk_12_5 : out std_logic
);
end vga_pll_200;
architecture Behavioral of vga_pll_200 is
signal clk_100_s : std_logic := '0';
signal clk_50_s : std_logic := '0';
signal clk_25_s : std_logic := '0';
signal clk_12_5_s : std_logic := '0';
begin
clk_100 <= clk_100_s;
clk_50 <= clk_50_s;
clk_25 <= clk_25_s;
clk_12_5 <= clk_12_5_s;
process(clk_200)
begin
if rising_edge(clk_200) then
clk_100_s <= not clk_100_s;
end if;
end process;
process(clk_100_s)
begin
if rising_edge(clk_100_s) then
clk_50_s <= not clk_50_s;
end if;
end process;
process(clk_50_s)
begin
if rising_edge(clk_50_s) then
clk_25_s <= not clk_25_s;
end if;
end process;
process(clk_25_s)
begin
if rising_edge(clk_25_s) then
clk_12_5_s <= not clk_12_5_s;
end if;
end process;
end Behavioral;
| mit | c11c388f996603972a7ee598beac3f8b | 0.526718 | 2.9475 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/addsub_inferred-rtl.vhdl | 1 | 2,391 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of addsub_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src_bits downto 0);
src2_tmp : std_ulogic_vector(src_bits downto 0);
result_tmp : std_ulogic_vector(src_bits downto 0);
result_msb : std_ulogic;
result_msb_carryin : std_ulogic;
carryout : std_ulogic;
end record;
signal c : comb_type;
begin
c.src1_tmp <= '0' & src1(src_bits-2 downto 0) & '1';
c.src2_tmp <= ('0' & src2(src_bits-2 downto 0) & carryin) xor (src_bits downto 0 => sub);
c.result_tmp <= std_ulogic_vector(unsigned(c.src1_tmp) + unsigned(c.src2_tmp));
c.result_msb_carryin <= c.result_tmp(src_bits);
c.result_msb <= (src1(src_bits-1) xor
src2(src_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor src1(src_bits-1)) and (src2(src_bits-1) or c.result_msb_carryin)) or
(src2(src_bits-1) and c.result_msb_carryin));
carryout <= c.carryout;
overflow <= c.carryout xor c.result_msb_carryin;
result <= c.result_msb & c.result_tmp(src_bits-1 downto 1);
end;
| apache-2.0 | a9f05a7979c12c77ff5e6b5fdafe86ce | 0.542033 | 3.978369 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/debounce/debounce.srcs/sources_1/new/debounce.vhd | 5 | 746 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debounce is
port (
clk : in std_logic;
signal_in : in std_logic;
signal_out : out std_logic
);
end debounce;
architecture Behavioral of debounce is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if signal_in = '1' then
if c = x"FFFFFF" then
signal_out <= '1';
else
signal_out <= '0';
end if;
c <= c + 1;
else
c <= (others => '0');
signal_out <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | 4ab2f4f81ea9d0273690c32fffbe3e66 | 0.466488 | 4.032432 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/superip_internal.vhd | 1 | 7,414 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity superip_internal is
port(
-- Outputs
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : out STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg26 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end entity superip_internal;
architecture RTL of superip_internal is
-- Outputs Register31
ALIAS OUT_RDY_L : STD_LOGIC is slv_reg31(0);
ALIAS VolCtrl_RDY_R : STD_LOGIC is slv_reg31(1);
ALIAS Filter_ready_out : STD_LOGIC is slv_reg31(2);
-- Inputs Register27
ALIAS Reset_in : STD_LOGIC is slv_reg27(0);
ALIAS SAMPLE_TRIG : STD_LOGIC is slv_reg27(1);
ALIAS HP_SW : STD_LOGIC is slv_reg27(2);
ALIAS BP_SW : STD_LOGIC is slv_reg27(3);
ALIAS LP_SW : STD_LOGIC is slv_reg27(4);
ALIAS Mux1_Mux2_Select_in : std_logic_vector is slv_reg27(6 downto 5);
--5th -> Mux1:= Volctrl or rawAudio; 0 for Volctrl pass
--6th -> Mux2:= Filter or Mux1; 0 for Filter pass
ALIAS sample_trigger_en : STD_LOGIC is slv_reg27(7);
--if this signal is '1' filter waits for sample triggers
--otherwise, its constantly calculating
-- Internals
signal Mux1_VolCtrlORAudio_Left_out : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Right_out : std_logic_vector(23 downto 0);
signal Filter_Left_out : std_logic_vector(23 downto 0);
signal Filter_Right_out : std_logic_vector(23 downto 0);
signal OUT_VOLCTRL_L : signed(23 downto 0);
signal OUT_VOLCTRL_R : signed(23 downto 0);
-- signal Volctrl_Left_out : std_logic_vector(23 downto 0);
-- signal Volctrl_Right_out : std_logic_vector(23 downto 0);
-- signal slv_reg15_s : signed(31 downto 0);
-- signal slv_reg16_s : signed(31 downto 0);
-- signal Audio_Left_in_s : signed(23 downto 0);
-- signal Audio_Right_in_s : signed(23 downto 0);
begin
--------------------------START VolCtrl--------------
--input
-- slv_reg15_s <= signed(slv_reg15);
-- slv_reg16_s <= signed(slv_reg16);
-- Audio_Left_in_s <= signed(Audio_Left_in);
-- Audio_Right_in_s <= signed(Audio_Right_in);
--------------------------END VolCtrl----------------
-- Mux2_FilterORMux1_Left_out <= Filter_Left_out;
-- Mux2_FilterORMux1_Right_out <= Filter_Right_out;
-- Mux1_VolCtrlORAudio_Left_out <= std_logic_vector(OUT_VOLCTRL_L);
-- Mux1_VolCtrlORAudio_Right_out <= std_logic_vector(OUT_VOLCTRL_R);
Tester_Comp : entity work.Tester
port map(
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
VolCtrl_Left_out_in => std_logic_vector(OUT_VOLCTRL_L),
VolCtrl_Right_out_in => std_logic_vector(OUT_VOLCTRL_R),
Mux1_VolCtrlORAudio_Left_out => Mux1_VolCtrlORAudio_Left_out,
Mux1_VolCtrlORAudio_Right_out => Mux1_VolCtrlORAudio_Right_out,
Filter_Left_out_in => Filter_Left_out,
Filter_Right_out_in => Filter_Right_out,
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left_out,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right_out,
Mux1_Mux2_Select_in => Mux1_Mux2_Select_in
);
VolCtrl_inst : entity work.VolCtrl
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8
)
port map(
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY_L => OUT_RDY_L,
OUT_RDY_R => VolCtrl_RDY_R,
IN_SIG_L => signed(Audio_Left_in),
IN_SIG_R => signed(Audio_Right_in),
IN_COEF_L => signed(slv_reg15),
IN_COEF_R => signed(slv_reg16),
RESET => Reset_in,
CLK_48 => CLK_48_in,
CLK_100M => CLK_100M_in
);
filter_Comp : entity work.Filter_Top_Level
port map(
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14,
CLK_48 => CLK_48_in,
RST => Reset_in,
SAMPLE_TRIG => SAMPLE_TRIG,
sample_trigger_en => sample_trigger_en,
HP_SW => HP_SW,
BP_SW => BP_SW,
LP_SW => LP_SW,
AUDIO_IN_L => Mux1_VolCtrlORAudio_Left_out,
AUDIO_IN_R => Mux1_VolCtrlORAudio_Right_out,
AUDIO_OUT_L => Filter_Left_out,
AUDIO_OUT_R => Filter_Right_out,
FILTER_DONE => Filter_ready_out
);
end architecture RTL;
| mit | f5f07c57d79a18e2082fcd4efced15a6 | 0.535878 | 3.132235 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_buffer_register_0_0/synth/system_buffer_register_0_0.vhd | 3 | 4,059 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:buffer_register:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_buffer_register_0_0 IS
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_buffer_register_0_0;
ARCHITECTURE system_buffer_register_0_0_arch OF system_buffer_register_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_buffer_register_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT buffer_register IS
GENERIC (
WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT buffer_register;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_buffer_register_0_0_arch: ARCHITECTURE IS "buffer_register,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_buffer_register_0_0_arch : ARCHITECTURE IS "system_buffer_register_0_0,buffer_register,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_buffer_register_0_0_arch: ARCHITECTURE IS "system_buffer_register_0_0,buffer_register,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=buffer_register,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : buffer_register
GENERIC MAP (
WIDTH => 32
)
PORT MAP (
clk => clk,
val_in => val_in,
val_out => val_out
);
END system_buffer_register_0_0_arch;
| mit | e1f97a8d3274f832dbfcd9a1a23a118f | 0.739837 | 3.948444 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/sim/system_vga_hessian_0_0.vhd | 1 | 3,768 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit | e18115c17222a37084602fe42471f0b3 | 0.710456 | 3.809909 | false | false | false | false |
sbourdeauducq/dspunit | sim/bench_dotop.vhd | 2 | 12,272 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dotop is
end bench_dotop;
--=----------------------------------------------------------------------------
architecture archi_bench_dotop of bench_dotop is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_dotop
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "sigl1.mif")
-- init_file => "Ones.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "sigl1.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000110" after 131 ns, "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
--s_data_in_cmdreg <= x"0000", x"004F" after 141 ns, x"0040" after 151 ns, x"02D7" after 161 ns, x"0002" after 171 ns, -- dotop, muladd m0,1>m0
s_data_in_cmdreg <= x"0000", x"0040" after 131 ns, x"004F" after 141 ns, x"0040" after 151 ns, x"02E7" after 161 ns, x"0002" after 171 ns, -- dotop, mul m0,1>m0
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 131 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_dotop;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=dotop.sav
-------------------------------------------------------------------------------
| gpl-3.0 | 2efa09203e8fc4b083ce6152918241b0 | 0.48248 | 3.393805 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/cpu_arch_pkg.vhdl | 1 | 3,126 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Architecture level constants
library ieee;
use ieee.std_logic_1164.all;
library isa;
use isa.or1k_pkg.all;
package cpu_arch_pkg is
constant cpu_context_bits : natural := or1k_cid_bits;
constant cpu_vaddr_bits : natural := or1k_vaddr_bits;
constant cpu_paddr_bits : natural := or1k_paddr_bits;
constant cpu_log2_word_bytes : natural := or1k_log2_word_bytes;
constant cpu_word_bytes : natural := or1k_word_bytes;
constant cpu_log2_inst_bytes : natural := or1k_log2_inst_bytes;
constant cpu_inst_bytes : natural := or1k_inst_bytes;
constant cpu_rfaddr_bits : natural := or1k_rfaddr_bits;
constant cpu_wmask_bits : natural := or1k_wmask_bits;
constant cpu_log2_data_size_bits : natural := or1k_log2_data_size_bits;
constant cpu_word_bits : natural := or1k_word_bits;
constant cpu_inst_bits : natural := or1k_inst_bits;
constant cpu_wvaddr_bits : natural := or1k_wvaddr_bits;
constant cpu_ivaddr_bits : natural := or1k_ivaddr_bits;
constant cpu_wpaddr_bits : natural := or1k_wpaddr_bits;
constant cpu_ipaddr_bits : natural := or1k_ipaddr_bits;
constant cpu_shift_bits : natural := or1k_shift_bits;
subtype cpu_vaddr_type is or1k_vaddr_type;
subtype cpu_paddr_type is or1k_paddr_type;
subtype cpu_wvaddr_type is or1k_wvaddr_type;
subtype cpu_ivaddr_type is or1k_ivaddr_type;
subtype cpu_wpaddr_type is or1k_wpaddr_type;
subtype cpu_ipaddr_type is or1k_ipaddr_type;
subtype cpu_word_bytes_type is or1k_word_bytes_type;
subtype cpu_word_type is or1k_word_type;
subtype cpu_dword_type is or1k_dword_type;
subtype cpu_inst_bytes_type is or1k_inst_bytes_type;
subtype cpu_inst_type is or1k_inst_type;
subtype cpu_rfaddr_type is or1k_rfaddr_type;
subtype cpu_shift_type is or1k_shift_type;
subtype cpu_wmask_type is or1k_wmask_type;
subtype cpu_log2_data_size_type is or1k_log2_data_size_type;
end package;
| apache-2.0 | 52e8613a3e462706876a824b49e8167c | 0.621241 | 3.593103 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cache/cpu_l1mem_data_cache_dp-rtl.vhdl | 1 | 45,685 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the Licensee for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_config_pkg.all;
use sys.sys_pkg.all;
library tech;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_types_pkg.all;
architecture rtl of cpu_l1mem_data_cache_dp is
type reg_type is record
b_request_size : cpu_data_size_type;
b_request_poffset : cpu_poffset_type;
b_request_vpn : cpu_vpn_type;
b_request_data : cpu_word_type;
b_bus_op_size : cpu_data_size_type;
b_bus_op_paddr : cpu_paddr_type;
b_stb_array_size : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_data_size_bits-1 downto 0);
b_stb_array_paddr : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_paddr_bits-1 downto 0);
b_stb_array_data : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_word_bits-1 downto 0);
end record;
type comb_type is record
b_replace_rstate : cpu_l1mem_data_cache_replace_state_type;
b_replace_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_tram_rdata : std_ulogic_vector2(cpu_l1mem_data_cache_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_dram_rdata : std_ulogic_vector2((cpu_l1mem_data_cache_assoc*cpu_word_bytes)-1 downto 0,
byte_bits-1 downto 0);
b_bus_op_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_bus_op_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_bus_op_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
b_request_ppn : cpu_ppn_type;
b_request_paddr : cpu_paddr_type;
b_request_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_request_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_request_block_word_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
b_request_word_byte_offset : std_ulogic_vector(cpu_log2_word_bytes-1 downto 0);
b_request_size_mask : std_ulogic_vector(cpu_log2_word_bytes-1 downto 0);
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_assoc-1 downto 0);
b_cache_way_read_data_le : std_ulogic_vector2(cpu_l1mem_data_cache_assoc-1 downto 0,
cpu_word_bits-1 downto 0);
b_cache_read_data_le : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_cache_read_data_be : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_cache_read_data : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_bus : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_cache_or_bus_unshifted : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_cache_or_bus_shifter : std_ulogic_vector2(cpu_log2_word_bytes downto 0,
cpu_word_bits-1 downto 0);
b_result_data_cache_or_bus_shifted : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_result_data_stb : std_ulogic_vector(cpu_word_bits-1 downto 0);
b_stb_update_data_ptr : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_tag : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_stb_array_index : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_index_bits-1 downto 0);
b_stb_array_block_word_offset : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
b_stb_array_word_byte_offset : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_log2_word_bytes-1 downto 0);
b_stb_array_size_mask : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_log2_word_bytes-1 downto 0);
b_stb_array_size_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_data_size_bits-1 downto 0);
b_stb_array_paddr_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_paddr_bits-1 downto 0);
b_stb_array_data_next : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_word_bits-1 downto 0);
b_stb_head_paddr : cpu_paddr_type;
b_stb_head_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_request_stb_array_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_block_word_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_word_byte_offset_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_request_stb_array_size_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_block_change_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_block_change_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
b_stb_array_block_change_index_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_stb_array_block_change_tag_match : std_ulogic_vector(cpu_l1mem_data_cache_stb_entries-1 downto 0);
b_result_paddr : cpu_paddr_type;
b_result_data : cpu_word_type;
b_replace_windex : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_replace_wstate : cpu_l1mem_data_cache_replace_state_type;
b_vram_waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
b_mram_waddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_new_request_size : cpu_data_size_type;
a_new_request_poffset : cpu_poffset_type;
a_new_request_vpn : cpu_vpn_type;
a_new_request_data : cpu_word_type;
a_request_poffset : cpu_poffset_type;
a_request_vpn : cpu_vpn_type;
a_request_ppn : cpu_ppn_type;
a_request_data : cpu_word_type;
a_request_bus_op_data : cpu_word_type;
a_request_size : cpu_data_size_type;
a_request_size_dec : std_ulogic_vector(cpu_log2_word_bytes downto 0);
a_request_word_byte_mask_by_size : std_ulogic_vector2(cpu_log2_word_bytes downto 0,
cpu_word_bytes-1 downto 0);
a_request_word_byte_mask : std_ulogic_vector(cpu_word_bytes-1 downto 0);
a_request_dram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc*cpu_word_bytes-1 downto 0);
a_request_vaddr : cpu_vaddr_type;
a_request_paddr : cpu_paddr_type;
a_request_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_request_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_request_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_stb_array_paddr : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_paddr_bits-1 downto 0);
a_stb_array_data : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_word_bits-1 downto 0);
a_stb_array_size : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_data_size_bits-1 downto 0);
a_stb_array_size_mask : std_ulogic_vector2(cpu_l1mem_data_cache_stb_entries-1 downto 0,
cpu_log2_word_bytes-1 downto 0);
a_stb_head_size : cpu_data_size_type;
a_stb_head_paddr : cpu_paddr_type;
a_stb_head_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_stb_head_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_stb_head_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_stb_head_data : cpu_word_type;
a_stb_head_size_dec : std_ulogic_vector(cpu_log2_word_bytes downto 0);
a_stb_word_byte_mask_by_size : std_ulogic_vector2(cpu_log2_word_bytes downto 0,
cpu_word_bytes-1 downto 0);
a_stb_word_byte_mask : std_ulogic_vector(cpu_word_bytes-1 downto 0);
a_stb_dram_banken : std_ulogic_vector((cpu_l1mem_data_cache_assoc*cpu_word_bytes)-1 downto 0);
a_stb_dram_wdata_sel : std_ulogic_vector(cpu_log2_word_bytes-1 downto 0);
a_stb_dram_wdata_word : std_ulogic_vector(cpu_word_bits-1 downto 0);
a_bus_op_paddr_block_word_offset_next : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
a_bus_op_paddr : cpu_paddr_type;
a_bus_op_size : cpu_data_size_type;
a_bus_op_data : cpu_word_type;
a_bus_op_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_bus_op_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_bus_op_cache_wtag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_bus_op_cache_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_bus_op_cache_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_bus_op_tram_wdata_tag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_bus_op_sys_paddr : cpu_paddr_type;
a_bus_op_sys_data : cpu_word_type;
a_bus_op_dram_banken : std_ulogic_vector((cpu_l1mem_data_cache_assoc*cpu_word_bytes)-1 downto 0);
a_bus_op_dram_wdata_word : std_ulogic_vector(cpu_word_bits-1 downto 0);
a_sys_size : sys_transfer_size_type;
a_sys_paddr : sys_paddr_type;
a_sys_data : sys_bus_type;
a_vtram_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_rmdram_index : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_rmdram_offset : std_ulogic_vector(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_vram_raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_mram_raddr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_tram_addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
a_tram_wtag : std_ulogic_vector(cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_tram_wdata : std_ulogic_vector2(cpu_l1mem_data_cache_assoc-1 downto 0,
cpu_l1mem_data_cache_tag_bits-1 downto 0);
a_dram_banken : std_ulogic_vector(cpu_l1mem_data_cache_assoc*cpu_word_bytes-1 downto 0);
a_dram_addr : std_ulogic_vector(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0);
a_dram_wdata_word : std_ulogic_vector(cpu_word_bits-1 downto 0);
a_dram_wdata_bytes_le : std_ulogic_vector2(cpu_word_bytes-1 downto 0, byte_bits-1 downto 0);
a_dram_wdata_bytes_be : std_ulogic_vector2(cpu_word_bytes-1 downto 0, byte_bits-1 downto 0);
a_dram_wdata_bytes : std_ulogic_vector2(cpu_word_bytes-1 downto 0, byte_bits-1 downto 0);
a_dram_wdata : std_ulogic_vector2(cpu_l1mem_data_cache_assoc*cpu_word_bytes-1 downto 0,
byte_bits-1 downto 0);
a_replace_rindex : std_ulogic_vector(cpu_l1mem_data_cache_index_bits-1 downto 0);
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.b_replace_rstate <= cpu_l1mem_data_cache_replace_dp_out.rstate;
c.b_tram_rdata <= cpu_l1mem_data_cache_dp_in_tram.rdata;
c.b_dram_rdata <= cpu_l1mem_data_cache_dp_in_dram.rdata;
b_replace_tag_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_l1mem_data_cache_tag_bits,
sel_bits => cpu_l1mem_data_cache_assoc
)
port map (
din => c.b_tram_rdata,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_replace_way,
dout => c.b_replace_tag
);
----------------------------------
c.b_request_ppn <= cpu_mmu_data_dp_out.ppn;
c.b_request_paddr <= cpu_mmu_data_dp_out.ppn & r.b_request_poffset;
c.b_request_tag <= c.b_request_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.b_request_index <= c.b_request_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1
downto cpu_l1mem_data_cache_offset_bits);
c.b_request_block_word_offset <= c.b_request_paddr(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes);
c.b_request_word_byte_offset <= c.b_request_paddr(cpu_log2_word_bytes-1 downto 0);
c.b_request_size_mask(0) <= all_zeros(r.b_request_size);
b_request_size_mask_gen : for n in 1 to cpu_log2_word_bytes-1 generate
c.b_request_size_mask(n) <= (c.b_request_size_mask(n-1) or
logic_eq(r.b_request_size,
std_ulogic_vector(to_unsigned(n, cpu_data_size_bits))));
end generate;
b_request_tag_match_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
c.b_request_cache_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_tram_rdata, n));
end generate;
----------------------------------
b_cache_read_data_way_words_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
byte_loop : for m in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.b_cache_way_read_data_le(n, m*byte_bits+b) <= c.b_dram_rdata(n*cpu_word_bytes+m, b);
end generate;
end generate;
end generate;
b_cache_read_data_word_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bits,
sel_bits => cpu_l1mem_data_cache_assoc
)
port map (
din => c.b_cache_way_read_data_le,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_cache_read_data_way,
dout => c.b_cache_read_data_le
);
b_cache_read_data_gen : for m in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.b_cache_read_data_be((cpu_word_bytes-m-1)*byte_bits+b) <= c.b_cache_read_data_le(m*byte_bits+b);
end generate;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.b_cache_read_data_be select
c.b_cache_read_data <= c.b_cache_read_data_le when '0',
c.b_cache_read_data_be when '1',
(others => 'X') when others;
----------------------------------
c.b_bus_op_tag <= r.b_bus_op_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.b_bus_op_index <= r.b_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.b_bus_op_offset <= r.b_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
----------------------------------
c.b_result_data_bus <= sys_slave_dp_out.data(cpu_word_bits-1 downto 0);
with cpu_l1mem_data_cache_dp_in_ctrl.b_result_data_sel select
c.b_result_data_cache_or_bus_unshifted <= c.b_cache_read_data when cpu_l1mem_data_cache_b_result_data_sel_cache,
c.b_result_data_bus when cpu_l1mem_data_cache_b_result_data_sel_bus_shifted,
(others => 'X') when others;
b_result_data_cache_or_bus_tmp_0_gen : for n in cpu_word_bits-1 downto 0 generate
c.b_result_data_cache_or_bus_shifter(cpu_log2_word_bytes, n) <= c.b_result_data_cache_or_bus_unshifted(n);
end generate;
b_result_data_cache_or_bus_shifter_gen : for n in cpu_log2_word_bytes-1 downto 0 generate
blk : block
signal sel : std_ulogic;
signal word : cpu_word_type;
signal part : std_ulogic_vector((2**n)*byte_bits-1 downto 0);
begin
-- align the result from the cache according to the least significant bits of the address
sel <= ((r.b_request_poffset(n) xor cpu_l1mem_data_cache_dp_in_ctrl.b_request_be) and c.b_request_size_mask(n));
word_loop : for b in cpu_word_bits-1 downto 0 generate
word(b) <= c.b_result_data_cache_or_bus_shifter(n+1, b);
end generate;
with sel select
part <= word(2*(2**n)*byte_bits-1 downto (2**n)*byte_bits) when '1',
word((2**n)*byte_bits-1 downto 0) when '0',
(others => 'X') when others;
out_hi_loop : for b in cpu_word_bits-1 downto (2**n)*byte_bits generate
c.b_result_data_cache_or_bus_shifter(n, b) <= word(b);
end generate;
out_lo_loop : for b in (2**n)*byte_bits-1 downto 0 generate
c.b_result_data_cache_or_bus_shifter(n, b) <= part(b);
end generate;
end block;
end generate;
b_result_data_cache_or_bus_gen : for n in cpu_word_bits-1 downto 0 generate
c.b_result_data_cache_or_bus_shifted(n) <= c.b_result_data_cache_or_bus_shifter(0, n);
end generate;
b_result_data_stb_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => r.b_stb_array_data,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_request_stb_array_hit,
dout => c.b_result_data_stb
);
with cpu_l1mem_data_cache_dp_in_ctrl.b_result_data_sel select
c.b_result_data <= c.b_result_data_cache_or_bus_shifted when cpu_l1mem_data_cache_b_result_data_sel_cache |
cpu_l1mem_data_cache_b_result_data_sel_bus_shifted,
c.b_result_data_bus when cpu_l1mem_data_cache_b_result_data_sel_bus,
c.b_result_data_stb when cpu_l1mem_data_cache_b_result_data_sel_stb,
(others => 'X') when others;
----------------------------------
c.b_block_change_index <= r.b_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.b_block_change_tag <= r.b_bus_op_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
b_stb_array_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
b_stb_array_word_byte_offset_gen : for m in cpu_log2_word_bytes-1 downto 0 generate
c.b_stb_array_word_byte_offset(n, m) <= r.b_stb_array_paddr(n, m);
end generate;
b_stb_array_block_word_offset_gen : for m in cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes-1 downto 0 generate
c.b_stb_array_block_word_offset(n, m) <= r.b_stb_array_paddr(n, m + cpu_log2_word_bytes);
end generate;
b_stb_array_index_gen : for m in cpu_l1mem_data_cache_index_bits-1 downto 0 generate
c.b_stb_array_index(n, m) <= r.b_stb_array_paddr(n, m + cpu_l1mem_data_cache_offset_bits);
end generate;
b_stb_array_tag_gen : for m in cpu_l1mem_data_cache_tag_bits-1 downto 0 generate
c.b_stb_array_tag(n, m) <= r.b_stb_array_paddr(n, m + cpu_l1mem_data_cache_offset_bits + cpu_l1mem_data_cache_index_bits);
end generate;
c.b_stb_array_size_mask(n, 0) <= all_zeros(std_ulogic_vector2_slice2(r.b_stb_array_size, n));
b_request_size_mask_gen : for m in 1 to cpu_log2_word_bytes-1 generate
c.b_stb_array_size_mask(n, m) <= (c.b_stb_array_size_mask(n, m-1) or
logic_eq(r.b_request_size,
std_ulogic_vector(to_unsigned(n, cpu_data_size_bits))));
end generate;
c.b_request_stb_array_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_stb_array_tag, n));
c.b_request_stb_array_index_match(n) <=
logic_eq(c.b_request_index,
std_ulogic_vector2_slice2(c.b_stb_array_index, n));
c.b_request_stb_array_block_word_offset_match(n) <=
logic_eq(c.b_request_block_word_offset,
std_ulogic_vector2_slice2(c.b_stb_array_block_word_offset, n));
c.b_request_stb_array_word_byte_offset_match(n) <=
logic_eq(c.b_request_word_byte_offset,
std_ulogic_vector2_slice2(c.b_stb_array_word_byte_offset, n)
);
c.b_request_stb_array_size_match(n) <=
logic_eq(r.b_request_size,
std_ulogic_vector2_slice2(r.b_stb_array_size, n));
c.b_stb_array_block_change_index_match(n) <=
logic_eq(c.b_block_change_index,
std_ulogic_vector2_slice2(c.b_stb_array_index, n));
c.b_stb_array_block_change_tag_match(n) <=
logic_eq(c.b_block_change_tag,
std_ulogic_vector2_slice2(c.b_stb_array_tag, n));
end generate;
b_stb_head_paddr_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_paddr_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => r.b_stb_array_paddr,
sel => cpu_l1mem_data_cache_dp_in_ctrl.b_stb_head_ptr,
dout => c.b_stb_head_paddr
);
c.b_stb_head_index <= c.b_stb_head_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.b_stb_update_data_ptr <= (
cpu_l1mem_data_cache_dp_in_ctrl.b_stb_push_ptr or
cpu_l1mem_data_cache_dp_in_ctrl.b_stb_combine_ptr
);
b_stb_array_next_gen : for n in cpu_l1mem_data_cache_stb_entries-1 downto 0 generate
blk : block
signal size : cpu_data_size_type;
signal data : cpu_word_type;
signal paddr : cpu_paddr_type;
begin
with cpu_l1mem_data_cache_dp_in_ctrl.b_stb_push_ptr(n) select
paddr <= std_ulogic_vector2_slice2(r.b_stb_array_paddr, n) when '0',
c.b_request_paddr when '1',
(others => 'X') when others;
paddr_bit_loop : for m in cpu_paddr_bits-1 downto 0 generate
c.b_stb_array_paddr_next(n, m) <= paddr(m);
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.b_stb_push_ptr(n) select
size <= std_ulogic_vector2_slice2(r.b_stb_array_size, n) when '0',
r.b_request_size when '1',
(others => 'X') when others;
size_bit_loop : for m in cpu_data_size_bits-1 downto 0 generate
c.b_stb_array_size_next(n, m) <= size(m);
end generate;
with c.b_stb_update_data_ptr(n) select
data <= std_ulogic_vector2_slice2(r.b_stb_array_data, n) when '0',
r.b_request_data when '1',
(others => 'X') when others;
data_bit_loop : for m in cpu_word_bits-1 downto 0 generate
c.b_stb_array_data_next(n, m) <= data(m);
end generate;
end block;
end generate;
--------------------------
with cpu_l1mem_data_cache_dp_in_ctrl.b_rmdram_owner select
c.b_replace_windex <= c.b_request_index when cpu_l1mem_data_cache_owner_request,
c.b_stb_head_index when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.b_replace_wstate <= c.b_replace_rstate;
with cpu_l1mem_data_cache_dp_in_ctrl.b_vtram_owner select
c.b_vram_waddr <= c.b_request_index when cpu_l1mem_data_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.b_rmdram_owner select
c.b_mram_waddr <= c.b_stb_head_index when cpu_l1mem_data_cache_owner_stb,
c.b_bus_op_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
--------------------------
c.a_stb_array_paddr <= c.b_stb_array_paddr_next;
c.a_stb_array_size <= c.b_stb_array_size_next;
c.a_stb_array_data <= c.b_stb_array_data_next;
a_stb_head_paddr_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_paddr_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_paddr,
sel => cpu_l1mem_data_cache_dp_in_ctrl.a_stb_head_ptr,
dout => c.a_stb_head_paddr
);
c.a_stb_head_tag <= c.a_stb_head_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.a_stb_head_index <= c.a_stb_head_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.a_stb_head_offset <= c.a_stb_head_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
a_stb_head_data_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_data,
sel => cpu_l1mem_data_cache_dp_in_ctrl.a_stb_head_ptr,
dout => c.a_stb_head_data
);
a_stb_head_size_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_data_size_bits,
sel_bits => cpu_l1mem_data_cache_stb_entries
)
port map (
din => c.a_stb_array_size,
sel => cpu_l1mem_data_cache_dp_in_ctrl.a_stb_head_ptr,
dout => c.a_stb_head_size
);
a_stb_head_size_decoder : entity tech.decoder(rtl)
generic map (
output_bits => cpu_log2_word_bytes + 1
)
port map (
datain => c.a_stb_head_size,
dataout => c.a_stb_head_size_dec
);
a_stb_word_byte_mask_gen : for m in cpu_word_bytes-1 downto 0 generate
c.a_stb_word_byte_mask_by_size(cpu_log2_word_bytes, m) <= '1';
size_loop : for n in cpu_log2_word_bytes-1 downto 0 generate
c.a_stb_word_byte_mask_by_size(n, m) <= logic_eq(c.a_stb_head_offset(cpu_log2_word_bytes-1 downto n),
std_ulogic_vector(to_unsigned(m/(2**n), cpu_log2_word_bytes-n)));
end generate;
end generate;
a_stb_word_byte_mask_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bytes,
sel_bits => cpu_log2_word_bytes + 1
)
port map (
din => c.a_stb_word_byte_mask_by_size,
sel => c.a_stb_head_size_dec,
dout => c.a_stb_word_byte_mask
);
a_stb_dram_banken_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
word_byte_loop : for m in cpu_word_bytes-1 downto 0 generate
c.a_stb_dram_banken(n*cpu_word_bytes+m) <= (
cpu_l1mem_data_cache_dp_in_ctrl.a_stb_way(n) and
c.a_stb_word_byte_mask(m)
);
end generate;
end generate;
-- log2_word_bytes size wdata
-- 0 0 0
-- 1 0 00
-- 1 1 10
-- 2 0 0000
-- 2 1 1010
-- 2 2 3210
-- 3 0 00000000
-- 3 1 10101010
-- 3 2 32103210
-- 3 3 76543210
c.a_stb_dram_wdata_sel(0) <= c.a_stb_head_size_dec(0);
a_stb_dram_wdata_word_sel_gen : for n in 1 to cpu_log2_word_bytes-1 generate
c.a_stb_dram_wdata_sel(n) <= c.a_stb_dram_wdata_sel(n-1) or c.a_stb_head_size_dec(n);
end generate;
c.a_stb_dram_wdata_word(byte_bits-1 downto 0) <= c.a_stb_head_data(byte_bits-1 downto 0);
a_stb_dram_wdata_word_gen : for n in cpu_log2_word_bytes-1 downto 0 generate
with c.a_stb_dram_wdata_sel(n) select
c.a_stb_dram_wdata_word((2**(n+1))*byte_bits-1 downto (2**n)*byte_bits) <=
c.a_stb_head_data((2**(n+1))*byte_bits-1 downto (2**n)*byte_bits) when '0',
c.a_stb_dram_wdata_word((2**n)*byte_bits-1 downto 0) when '1',
(others => 'X') when others;
end generate;
--------------------------
c.a_new_request_size <= cpu_l1mem_data_cache_dp_in.size;
c.a_new_request_poffset <= cpu_l1mem_data_cache_dp_in.vaddr(cpu_poffset_bits-1 downto 0);
c.a_new_request_vpn <= cpu_l1mem_data_cache_dp_in.vaddr(cpu_vaddr_bits-1 downto cpu_poffset_bits);
c.a_new_request_data <= cpu_l1mem_data_cache_dp_in.data;
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_size <= c.a_new_request_size when '1',
r.b_request_size when '0',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_poffset <= c.a_new_request_poffset when '1',
r.b_request_poffset when '0',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_vpn <= c.a_new_request_vpn when '1',
r.b_request_vpn when '0',
(others => 'X') when others;
c.a_request_ppn <= c.b_request_ppn;
c.a_request_paddr <= c.a_request_ppn & c.a_request_poffset;
c.a_request_tag <= c.a_request_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
c.a_request_index <= c.a_request_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.a_request_offset <= c.a_request_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
with cpu_l1mem_data_cache_dp_in_ctrl.b_request_complete select
c.a_request_data <= c.a_new_request_data when '1',
r.b_request_data when '0',
(others => 'X') when others;
c.a_request_bus_op_data <= r.b_request_data;
a_request_size_decoder : entity tech.decoder(rtl)
generic map (
output_bits => cpu_log2_word_bytes + 1
)
port map (
datain => c.a_request_size,
dataout => c.a_request_size_dec
);
a_request_word_byte_mask_gen : for m in cpu_word_bytes-1 downto 0 generate
c.a_request_word_byte_mask_by_size(cpu_log2_word_bytes, m) <= '1';
size_loop : for n in cpu_log2_word_bytes-1 downto 0 generate
c.a_request_word_byte_mask_by_size(n, m) <= logic_eq(c.a_request_poffset(cpu_log2_word_bytes-1 downto n),
std_ulogic_vector(to_unsigned(m/(2**n), cpu_log2_word_bytes-n)));
end generate;
end generate;
a_request_word_byte_mask_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_word_bytes,
sel_bits => cpu_log2_word_bytes + 1
)
port map (
din => c.a_request_word_byte_mask_by_size,
sel => c.a_request_size_dec,
dout => c.a_request_word_byte_mask
);
a_request_dram_banken_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
word_byte_loop : for m in cpu_word_bytes-1 downto 0 generate
c.a_request_dram_banken(n*cpu_word_bytes+m) <= c.a_request_word_byte_mask(m);
end generate;
end generate;
--------------------------------
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_size_sel select
c.a_bus_op_size <= r.b_bus_op_size when cpu_l1mem_data_cache_a_bus_op_size_sel_old,
c.a_request_size when cpu_l1mem_data_cache_a_bus_op_size_sel_request,
c.a_stb_head_size when cpu_l1mem_data_cache_a_bus_op_size_sel_stb,
std_ulogic_vector(to_unsigned(cpu_log2_word_bytes, cpu_data_size_bits)) when cpu_l1mem_data_cache_a_bus_op_size_sel_word,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_owner select
c.a_bus_op_data <= c.a_request_bus_op_data when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_data when cpu_l1mem_data_cache_owner_stb,
(others => 'X') when others;
a_bus_op_dram_banken_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
word_byte_loop : for m in cpu_word_bytes-1 downto 0 generate
c.a_bus_op_dram_banken(n*cpu_word_bytes+m) <= cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_way(n);
end generate;
end generate;
c.a_bus_op_dram_wdata_word <= sys_slave_dp_out.data;
a_bus_op_paddr_block_word_offset_next_gen : if cpu_l1mem_data_cache_offset_bits > cpu_log2_word_bytes generate
c.a_bus_op_paddr_block_word_offset_next <=
std_ulogic_vector(unsigned(r.b_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)) +
to_unsigned(1, cpu_l1mem_data_cache_offset_bits-cpu_log2_word_bytes));
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_tag_sel select
c.a_bus_op_paddr(cpu_paddr_bits-1 downto cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits) <=
c.a_request_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_request,
c.a_stb_head_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_stb,
c.b_bus_op_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_old,
c.b_replace_tag when cpu_l1mem_data_cache_a_bus_op_paddr_tag_sel_replace,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_index_sel select
c.a_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto cpu_l1mem_data_cache_offset_bits) <=
c.a_request_index when cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_request,
c.a_stb_head_index when cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_stb,
c.b_bus_op_index when cpu_l1mem_data_cache_a_bus_op_paddr_index_sel_old,
(others => 'X') when others;
a_bus_op_paddr_block_word_offset_gen : if cpu_l1mem_data_cache_offset_bits > cpu_log2_word_bytes generate
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes) <=
c.b_bus_op_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)
when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_old,
c.a_bus_op_paddr_block_word_offset_next when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_next_word,
c.a_request_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)
when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word,
c.a_stb_head_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes)
when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word,
(others => 'X') when others;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_log2_word_bytes-1 downto 0) <=
r.b_bus_op_paddr(cpu_log2_word_bytes-1 downto 0) when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_old,
c.a_request_paddr(cpu_log2_word_bytes-1 downto 0) when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request,
c.a_stb_head_paddr(cpu_log2_word_bytes-1 downto 0) when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb,
(cpu_log2_word_bytes-1 downto 0 => '0') when cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_next_word |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_request_word |
cpu_l1mem_data_cache_a_bus_op_paddr_offset_sel_stb_word,
(others => 'X') when others;
c.a_bus_op_index <= c.a_bus_op_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1 downto
cpu_l1mem_data_cache_offset_bits);
c.a_bus_op_offset <= c.a_bus_op_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0);
c.a_bus_op_cache_wtag <= r.b_bus_op_paddr(cpu_paddr_bits-1 downto
cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits);
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_index <=
c.a_bus_op_index when '0',
c.b_bus_op_index when '1',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_offset <=
c.a_bus_op_offset when '0',
c.b_bus_op_offset when '1',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_sys_paddr_sel_old select
c.a_bus_op_sys_paddr <=
c.a_bus_op_paddr when '0',
r.b_bus_op_paddr when '1',
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_bus_op_sys_data_sel_cache select
c.a_bus_op_sys_data <=
c.a_bus_op_data when '0',
c.b_cache_read_data when '1',
(others => 'X') when others;
--------------------------------
with cpu_l1mem_data_cache_dp_in_ctrl.a_vtram_owner select
c.a_vtram_index <= c.a_request_index when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_index when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_cache_index when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.a_vram_raddr <= c.a_vtram_index;
c.a_tram_addr <= c.a_vtram_index;
c.a_tram_wtag <= c.a_bus_op_cache_wtag;
a_tram_wdata_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
bit_gen : for b in cpu_l1mem_data_cache_tag_bits-1 downto 0 generate
c.a_tram_wdata(n, b) <= c.a_tram_wtag(b);
end generate;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_rmdram_index <= c.a_request_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1
downto cpu_l1mem_data_cache_offset_bits)
when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_paddr(cpu_l1mem_data_cache_index_bits+cpu_l1mem_data_cache_offset_bits-1
downto cpu_l1mem_data_cache_offset_bits)
when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_cache_index
when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_rmdram_offset <= c.a_request_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0)
when cpu_l1mem_data_cache_owner_request,
c.a_stb_head_paddr(cpu_l1mem_data_cache_offset_bits-1 downto 0)
when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_cache_offset
when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
c.a_mram_raddr <= c.a_rmdram_index;
c.a_replace_rindex <= c.a_rmdram_index;
c.a_dram_addr <= c.a_rmdram_index & c.a_rmdram_offset(cpu_l1mem_data_cache_offset_bits-1 downto cpu_log2_word_bytes);
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_dram_banken <= c.a_request_dram_banken when cpu_l1mem_data_cache_owner_request,
c.a_stb_dram_banken when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_dram_banken when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_data_cache_dp_in_ctrl.a_rmdram_owner select
c.a_dram_wdata_word <= c.a_stb_dram_wdata_word when cpu_l1mem_data_cache_owner_stb,
c.a_bus_op_dram_wdata_word when cpu_l1mem_data_cache_owner_bus_op,
(others => 'X') when others;
a_dram_wdata_bytes_gen : for n in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.a_dram_wdata_bytes_le(n, b) <= c.a_dram_wdata_word(n*byte_bits+b);
c.a_dram_wdata_bytes_be(cpu_word_bytes-n-1, b) <= c.a_dram_wdata_word(n*byte_bits+b);
end generate;
end generate;
with cpu_l1mem_data_cache_dp_in_ctrl.a_dram_wdata_be select
c.a_dram_wdata_bytes <= c.a_dram_wdata_bytes_le when '0',
c.a_dram_wdata_bytes_be when '1',
(others => (others => 'X')) when others;
a_dram_wdata_gen : for n in cpu_l1mem_data_cache_assoc-1 downto 0 generate
byte_loop : for m in cpu_word_bytes-1 downto 0 generate
bit_loop : for b in byte_bits-1 downto 0 generate
c.a_dram_wdata(n*cpu_word_bytes+m, b) <= c.a_dram_wdata_bytes(m, b);
end generate;
end generate;
end generate;
c.a_sys_size <= (sys_transfer_size_bits-1 downto cpu_data_size_bits => '0') & c.a_bus_op_size;
c.a_sys_paddr <= (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.a_bus_op_sys_paddr;
c.a_sys_data <= c.a_bus_op_sys_data;
c.b_result_paddr <= r.b_bus_op_paddr;
r_next <= (
b_request_size => c.a_request_size,
b_request_poffset => c.a_request_poffset,
b_request_vpn => c.a_request_vpn,
b_request_data => c.a_request_data,
b_bus_op_size => c.a_bus_op_size,
b_bus_op_paddr => c.a_bus_op_paddr,
b_stb_array_paddr => c.a_stb_array_paddr,
b_stb_array_data => c.a_stb_array_data,
b_stb_array_size => c.a_stb_array_size
);
cpu_l1mem_data_cache_dp_out_ctrl <= (
b_request_cache_tag_match => c.b_request_cache_tag_match,
b_request_stb_array_tag_match => c.b_request_stb_array_tag_match,
b_request_stb_array_index_match => c.b_request_stb_array_index_match,
b_request_stb_array_block_word_offset_match => c.b_request_stb_array_block_word_offset_match,
b_request_stb_array_word_byte_offset_match => c.b_request_stb_array_word_byte_offset_match,
b_request_stb_array_size_match => c.b_request_stb_array_size_match,
b_stb_array_block_change_index_match => c.b_stb_array_block_change_index_match,
b_stb_array_block_change_tag_match => c.b_stb_array_block_change_tag_match
);
cpu_l1mem_data_cache_dp_out_vram <= (
raddr => c.a_vram_raddr,
waddr => c.b_vram_waddr
);
cpu_l1mem_data_cache_dp_out_mram <= (
raddr => c.a_mram_raddr,
waddr => c.b_mram_waddr
);
cpu_l1mem_data_cache_dp_out_tram <= (
addr => c.a_tram_addr,
wdata => c.a_tram_wdata
);
cpu_l1mem_data_cache_dp_out_dram <= (
banken => c.a_dram_banken,
addr => c.a_dram_addr,
wdata => c.a_dram_wdata
);
cpu_l1mem_data_cache_replace_dp_in <= (
rindex => c.a_replace_rindex,
windex => c.b_replace_windex,
wstate => c.b_replace_wstate
);
cpu_l1mem_data_cache_dp_out <= (
paddr => c.b_result_paddr,
data => c.b_result_data
);
cpu_mmu_data_dp_in <= (
vpn => c.a_request_vpn
);
sys_master_dp_out <= (
size => c.a_sys_size,
paddr => c.a_sys_paddr,
data => c.a_sys_data
);
process (clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | 6a8a376cd8d8d7a3a67a5880639a215a | 0.592383 | 2.925712 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/test_benches/DES_Encrypt_Testbench.vhd | 2 | 5,647 | --******************************************************************************
-- Copyright (c) 2016 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
--------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 20:45:11 02/14/2017
-- Design Name:
-- Module Name: DES_ENCRYPT Testbench.vhd
-- Project Name: DES_Fully_Pipelined
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies: DES_Fully_Pipelined Design and txt_util.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
--------------------------------------------------------------------------------
LIBRARY ieee;
Use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use work.txt_util.all;
ENTITY DES_testBench IS
END DES_testBench;
ARCHITECTURE behavior OF DES_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DES_CRYPTO_CORE --desCryptoCore
PORT(
reset : IN std_logic;
EN : IN std_logic;
clk : IN std_logic;
DES_IN : IN std_logic_vector(63 downto 0);
USER_KEY : IN std_logic_vector(63 downto 0);
DES_OUT : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
COMPONENT DES IS
PORT(
PT : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
KIN: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
CT: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RST: IN STD_LOGIC;
CLK: IN STD_LOGIC;
TEST_MODE: IN STD_LOGIC;
SCAN_OUT : OUT STD_LOGIC);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal EN : std_logic := '0';
signal clk : std_logic := '0';
signal DES_IN : std_logic_vector(63 downto 0) := (others => '0');
signal USER_KEY : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal DES_OUT : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal ERROR,ERRORD: integer :=0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DES_CRYPTO_CORE PORT MAP (
reset => reset,
EN => EN,
clk => clk,
DES_IN => DES_IN,
USER_KEY => USER_KEY,
DES_OUT => DES_OUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
readcmd: process
file CryptoCore_TestVectors: TEXT;
variable file_line: Line;
variable test_vector_key_in: std_logic_vector (63 downto 0);
variable test_vector_din: std_logic_vector (63 downto 0);
variable test_vector_expected_dout : std_logic_vector (63 downto 0);
Begin
reset <= '1';
USER_KEY <= (others => '0');
DES_IN <= (others => '0');
En <= '1';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
reset <= '0';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
print ("DES Test#1 has begun.");
FILE_OPEN (CryptoCore_TestVectors, "../src/test_vectors/DES_TV_Triplets_NBS.txt", READ_MODE); --In case of problems, use absolute path
loop
If endfile (CryptoCore_TestVectors) then
exit;
End If;
readline (CryptoCore_TestVectors, file_line);
hread (file_line, test_vector_key_in);
hread (file_line, test_vector_din);
hread (file_line, test_vector_expected_dout);
USER_KEY <= test_vector_key_in;
-- din_vld_T <= '1'; --# When Designs have din and key valid use this
-- Key_vld <= '1';
DES_IN <= test_vector_din;
wait until rising_edge (clk);
-- din_vld_T <= '0';
-- wait until dout_rdy_T = '1'; --# When Designs have dout use this to get the result
wait for 20*clk_period; -- Currently DES takes 19 clock cycles to complete processing
wait until rising_edge (clk);
If DES_OUT /= test_vector_expected_dout then
print ("***ERROR: test vector failed to compare"); ERROR<=ERROR+1;
print ((" Expected PT: ") & hstr (test_vector_expected_dout (63 downto 0)) & (" Received PT: ") & hstr (DES_OUT (63 downto 0)));
End If;
End loop;
print ("Test#1 completed");
print ("");
print ("");
if ERROR=0 then
print ("All tests complete- PASS");
else
print (("All tests complete 4 Decrypt - FAIL --> Total ERRORS=") & integer'image(ERROR));
end if;
wait;
end process;
END;
| mit | 5e105a7abaf9592d003381fab21c5dc3 | 0.603506 | 3.58085 | false | true | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_sim_netlist.vhdl | 1 | 18,057 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:12 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_debounce_0_0 -prefix
-- system_debounce_0_0_ system_debounce_0_0_sim_netlist.vhdl
-- Design : system_debounce_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0_debounce is
port (
signal_out : out STD_LOGIC;
clk : in STD_LOGIC;
signal_in : in STD_LOGIC
);
end system_debounce_0_0_debounce;
architecture STRUCTURE of system_debounce_0_0_debounce is
signal \c[0]_i_3_n_0\ : STD_LOGIC;
signal \c[0]_i_4_n_0\ : STD_LOGIC;
signal \c[0]_i_5_n_0\ : STD_LOGIC;
signal \c[0]_i_6_n_0\ : STD_LOGIC;
signal \c[12]_i_2_n_0\ : STD_LOGIC;
signal \c[12]_i_3_n_0\ : STD_LOGIC;
signal \c[12]_i_4_n_0\ : STD_LOGIC;
signal \c[12]_i_5_n_0\ : STD_LOGIC;
signal \c[16]_i_2_n_0\ : STD_LOGIC;
signal \c[16]_i_3_n_0\ : STD_LOGIC;
signal \c[16]_i_4_n_0\ : STD_LOGIC;
signal \c[16]_i_5_n_0\ : STD_LOGIC;
signal \c[20]_i_2_n_0\ : STD_LOGIC;
signal \c[20]_i_3_n_0\ : STD_LOGIC;
signal \c[20]_i_4_n_0\ : STD_LOGIC;
signal \c[20]_i_5_n_0\ : STD_LOGIC;
signal \c[4]_i_2_n_0\ : STD_LOGIC;
signal \c[4]_i_3_n_0\ : STD_LOGIC;
signal \c[4]_i_4_n_0\ : STD_LOGIC;
signal \c[4]_i_5_n_0\ : STD_LOGIC;
signal \c[8]_i_2_n_0\ : STD_LOGIC;
signal \c[8]_i_3_n_0\ : STD_LOGIC;
signal \c[8]_i_4_n_0\ : STD_LOGIC;
signal \c[8]_i_5_n_0\ : STD_LOGIC;
signal c_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \c_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \c_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \c_reg[8]_i_1_n_7\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal signal_out_i_1_n_0 : STD_LOGIC;
signal signal_out_i_2_n_0 : STD_LOGIC;
signal signal_out_i_3_n_0 : STD_LOGIC;
signal signal_out_i_4_n_0 : STD_LOGIC;
signal signal_out_i_5_n_0 : STD_LOGIC;
signal \NLW_c_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\c[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => signal_in,
O => clear
);
\c[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(3),
O => \c[0]_i_3_n_0\
);
\c[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(2),
O => \c[0]_i_4_n_0\
);
\c[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(1),
O => \c[0]_i_5_n_0\
);
\c[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => c_reg(0),
O => \c[0]_i_6_n_0\
);
\c[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(15),
O => \c[12]_i_2_n_0\
);
\c[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(14),
O => \c[12]_i_3_n_0\
);
\c[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(13),
O => \c[12]_i_4_n_0\
);
\c[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(12),
O => \c[12]_i_5_n_0\
);
\c[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(19),
O => \c[16]_i_2_n_0\
);
\c[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(18),
O => \c[16]_i_3_n_0\
);
\c[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(17),
O => \c[16]_i_4_n_0\
);
\c[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(16),
O => \c[16]_i_5_n_0\
);
\c[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(23),
O => \c[20]_i_2_n_0\
);
\c[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(22),
O => \c[20]_i_3_n_0\
);
\c[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(21),
O => \c[20]_i_4_n_0\
);
\c[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(20),
O => \c[20]_i_5_n_0\
);
\c[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(7),
O => \c[4]_i_2_n_0\
);
\c[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(6),
O => \c[4]_i_3_n_0\
);
\c[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(5),
O => \c[4]_i_4_n_0\
);
\c[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(4),
O => \c[4]_i_5_n_0\
);
\c[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(11),
O => \c[8]_i_2_n_0\
);
\c[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(10),
O => \c[8]_i_3_n_0\
);
\c[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(9),
O => \c[8]_i_4_n_0\
);
\c[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => c_reg(8),
O => \c[8]_i_5_n_0\
);
\c_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_7\,
Q => c_reg(0),
R => clear
);
\c_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \c_reg[0]_i_2_n_0\,
CO(2) => \c_reg[0]_i_2_n_1\,
CO(1) => \c_reg[0]_i_2_n_2\,
CO(0) => \c_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \c_reg[0]_i_2_n_4\,
O(2) => \c_reg[0]_i_2_n_5\,
O(1) => \c_reg[0]_i_2_n_6\,
O(0) => \c_reg[0]_i_2_n_7\,
S(3) => \c[0]_i_3_n_0\,
S(2) => \c[0]_i_4_n_0\,
S(1) => \c[0]_i_5_n_0\,
S(0) => \c[0]_i_6_n_0\
);
\c_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_5\,
Q => c_reg(10),
R => clear
);
\c_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_4\,
Q => c_reg(11),
R => clear
);
\c_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_7\,
Q => c_reg(12),
R => clear
);
\c_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[8]_i_1_n_0\,
CO(3) => \c_reg[12]_i_1_n_0\,
CO(2) => \c_reg[12]_i_1_n_1\,
CO(1) => \c_reg[12]_i_1_n_2\,
CO(0) => \c_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[12]_i_1_n_4\,
O(2) => \c_reg[12]_i_1_n_5\,
O(1) => \c_reg[12]_i_1_n_6\,
O(0) => \c_reg[12]_i_1_n_7\,
S(3) => \c[12]_i_2_n_0\,
S(2) => \c[12]_i_3_n_0\,
S(1) => \c[12]_i_4_n_0\,
S(0) => \c[12]_i_5_n_0\
);
\c_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_6\,
Q => c_reg(13),
R => clear
);
\c_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_5\,
Q => c_reg(14),
R => clear
);
\c_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[12]_i_1_n_4\,
Q => c_reg(15),
R => clear
);
\c_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_7\,
Q => c_reg(16),
R => clear
);
\c_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[12]_i_1_n_0\,
CO(3) => \c_reg[16]_i_1_n_0\,
CO(2) => \c_reg[16]_i_1_n_1\,
CO(1) => \c_reg[16]_i_1_n_2\,
CO(0) => \c_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[16]_i_1_n_4\,
O(2) => \c_reg[16]_i_1_n_5\,
O(1) => \c_reg[16]_i_1_n_6\,
O(0) => \c_reg[16]_i_1_n_7\,
S(3) => \c[16]_i_2_n_0\,
S(2) => \c[16]_i_3_n_0\,
S(1) => \c[16]_i_4_n_0\,
S(0) => \c[16]_i_5_n_0\
);
\c_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_6\,
Q => c_reg(17),
R => clear
);
\c_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_5\,
Q => c_reg(18),
R => clear
);
\c_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[16]_i_1_n_4\,
Q => c_reg(19),
R => clear
);
\c_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_6\,
Q => c_reg(1),
R => clear
);
\c_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_7\,
Q => c_reg(20),
R => clear
);
\c_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[16]_i_1_n_0\,
CO(3) => \NLW_c_reg[20]_i_1_CO_UNCONNECTED\(3),
CO(2) => \c_reg[20]_i_1_n_1\,
CO(1) => \c_reg[20]_i_1_n_2\,
CO(0) => \c_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[20]_i_1_n_4\,
O(2) => \c_reg[20]_i_1_n_5\,
O(1) => \c_reg[20]_i_1_n_6\,
O(0) => \c_reg[20]_i_1_n_7\,
S(3) => \c[20]_i_2_n_0\,
S(2) => \c[20]_i_3_n_0\,
S(1) => \c[20]_i_4_n_0\,
S(0) => \c[20]_i_5_n_0\
);
\c_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_6\,
Q => c_reg(21),
R => clear
);
\c_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_5\,
Q => c_reg(22),
R => clear
);
\c_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[20]_i_1_n_4\,
Q => c_reg(23),
R => clear
);
\c_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_5\,
Q => c_reg(2),
R => clear
);
\c_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[0]_i_2_n_4\,
Q => c_reg(3),
R => clear
);
\c_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_7\,
Q => c_reg(4),
R => clear
);
\c_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[0]_i_2_n_0\,
CO(3) => \c_reg[4]_i_1_n_0\,
CO(2) => \c_reg[4]_i_1_n_1\,
CO(1) => \c_reg[4]_i_1_n_2\,
CO(0) => \c_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[4]_i_1_n_4\,
O(2) => \c_reg[4]_i_1_n_5\,
O(1) => \c_reg[4]_i_1_n_6\,
O(0) => \c_reg[4]_i_1_n_7\,
S(3) => \c[4]_i_2_n_0\,
S(2) => \c[4]_i_3_n_0\,
S(1) => \c[4]_i_4_n_0\,
S(0) => \c[4]_i_5_n_0\
);
\c_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_6\,
Q => c_reg(5),
R => clear
);
\c_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_5\,
Q => c_reg(6),
R => clear
);
\c_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[4]_i_1_n_4\,
Q => c_reg(7),
R => clear
);
\c_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_7\,
Q => c_reg(8),
R => clear
);
\c_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \c_reg[4]_i_1_n_0\,
CO(3) => \c_reg[8]_i_1_n_0\,
CO(2) => \c_reg[8]_i_1_n_1\,
CO(1) => \c_reg[8]_i_1_n_2\,
CO(0) => \c_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \c_reg[8]_i_1_n_4\,
O(2) => \c_reg[8]_i_1_n_5\,
O(1) => \c_reg[8]_i_1_n_6\,
O(0) => \c_reg[8]_i_1_n_7\,
S(3) => \c[8]_i_2_n_0\,
S(2) => \c[8]_i_3_n_0\,
S(1) => \c[8]_i_4_n_0\,
S(0) => \c[8]_i_5_n_0\
);
\c_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \c_reg[8]_i_1_n_6\,
Q => c_reg(9),
R => clear
);
signal_out_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => signal_out_i_2_n_0,
I1 => signal_out_i_3_n_0,
I2 => signal_out_i_4_n_0,
I3 => c_reg(0),
I4 => signal_out_i_5_n_0,
O => signal_out_i_1_n_0
);
signal_out_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(3),
I1 => c_reg(4),
I2 => c_reg(1),
I3 => c_reg(2),
I4 => c_reg(6),
I5 => c_reg(5),
O => signal_out_i_2_n_0
);
signal_out_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(21),
I1 => c_reg(22),
I2 => c_reg(19),
I3 => c_reg(20),
I4 => signal_in,
I5 => c_reg(23),
O => signal_out_i_3_n_0
);
signal_out_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(15),
I1 => c_reg(16),
I2 => c_reg(13),
I3 => c_reg(14),
I4 => c_reg(18),
I5 => c_reg(17),
O => signal_out_i_4_n_0
);
signal_out_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => c_reg(9),
I1 => c_reg(10),
I2 => c_reg(7),
I3 => c_reg(8),
I4 => c_reg(12),
I5 => c_reg(11),
O => signal_out_i_5_n_0
);
signal_out_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => signal_out_i_1_n_0,
Q => signal_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_debounce_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_debounce_0_0 : entity is "system_debounce_0_0,debounce,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_debounce_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_debounce_0_0 : entity is "debounce,Vivado 2016.4";
end system_debounce_0_0;
architecture STRUCTURE of system_debounce_0_0 is
begin
U0: entity work.system_debounce_0_0_debounce
port map (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
end STRUCTURE;
| mit | 858b5d87601581b2a470379cbab12de5 | 0.461428 | 2.369685 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/shifter-rtl.vhdl | 1 | 1,633 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of shifter is
begin
shifter : entity work.shifter_inferred(rtl)
generic map (
src_bits => src_bits,
shift_bits => shift_bits
)
port map (
right => right,
rot => rot,
unsgnd => unsgnd,
src => src,
shift => shift,
shift_unsgnd => shift_unsgnd,
result => result
);
end;
| apache-2.0 | be3eb946723475e0812a1ee67041f9ae | 0.466626 | 5.407285 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 20,266 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 27 19:47:32 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished : out STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
href : in STD_LOGIC;
pclk : in STD_LOGIC;
resend : in STD_LOGIC;
scl : out STD_LOGIC;
sda : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=9,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_board_cnt=2,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_ov7670_vga_0_1 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_1;
component system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
end component system_zybo_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_util_vector_logic_0_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_vector_logic_0_0;
component system_inverter_1_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_1_0;
signal Net : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal hdmi_cec_1 : STD_LOGIC;
signal hdmi_hpd_1 : STD_LOGIC;
signal href_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal inverter_1_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_controller_0_xclk : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal resend_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
signal vsync_1 : STD_LOGIC;
signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC;
signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
config_finished <= ov7670_controller_0_config_finished;
data_1(7 downto 0) <= data(7 downto 0);
hdmi_cec_1 <= hdmi_cec;
hdmi_hpd_1 <= hdmi_hpd;
hdmi_out_en <= zybo_hdmi_0_hdmi_out_en;
href_1 <= href;
pclk_1 <= pclk;
resend_1 <= resend;
scl <= ov7670_controller_0_sioc;
tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0);
tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0);
vsync_1 <= vsync;
xclk <= ov7670_controller_0_xclk;
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => vsync_1,
x_not => inverter_0_x_not
);
inverter_1: component system_inverter_1_0
port map (
x => href_1,
x_not => inverter_1_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => clk_wiz_0_clk_out1,
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => resend_1,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => sda,
xclk => ov7670_controller_0_xclk
);
ov7670_vga_0: component system_ov7670_vga_0_1
port map (
data(7 downto 0) => data_1(7 downto 0),
pclk => pclk_1,
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
util_vector_logic_0: component system_util_vector_logic_0_0
port map (
Op1(0) => href_1,
Op2(0) => inverter_0_x_not,
Res(0) => util_vector_logic_0_Res(0)
);
zybo_hdmi_0: component system_zybo_hdmi_0_0
port map (
active => util_vector_logic_0_Res(0),
clk_125 => processing_system7_0_FCLK_CLK0,
clk_25 => clk_wiz_0_clk_out1,
hdmi_cec => hdmi_cec_1,
hdmi_hpd => hdmi_hpd_1,
hdmi_out_en => zybo_hdmi_0_hdmi_out_en,
hsync => inverter_1_x_not,
rgb(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0),
tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0),
vsync => vsync_1
);
end STRUCTURE;
| mit | bc25aeccf70bbc8a35f0b3b747788113 | 0.662736 | 2.926076 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_1r1w-rtl.vhdl | 1 | 4,085 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
library tech;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of cache_core_1r1w is
constant assoc : natural := 2**log2_assoc;
type comb_type is record
tag_we : std_ulogic;
tag_wbanken : std_ulogic_vector(assoc-1 downto 0);
tag_waddr : std_ulogic_vector(index_bits-1 downto 0);
tag_wdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
tag_re : std_ulogic;
tag_rbanken : std_ulogic_vector(assoc-1 downto 0);
tag_raddr : std_ulogic_vector(index_bits-1 downto 0);
tag_rdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
data_we : std_ulogic;
data_wbanken : std_ulogic_vector(assoc-1 downto 0);
data_waddr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_wdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
data_re : std_ulogic;
data_rbanken : std_ulogic_vector(assoc-1 downto 0);
data_raddr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_rdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.tag_we <= we and wtagen;
c.tag_wbanken <= wway;
c.tag_waddr <= windex;
c.tag_re <= re and rtagen;
c.tag_rbanken <= rway;
c.tag_raddr <= rindex;
c.data_we <= we and wdataen;
c.data_wbanken <= wway;
c.data_waddr <= windex & woffset;
c.data_re <= re and rdataen;
c.data_rbanken <= rway;
c.data_raddr <= rindex & roffset;
way_loop : for n in assoc-1 downto 0 generate
tag_bit_loop : for m in tag_bits-1 downto 0 generate
c.tag_wdata(n, m) <= wtag(m);
rtag(n, m) <= c.tag_rdata(n, m);
end generate;
data_bit_loop : for m in word_bits-1 downto 0 generate
c.data_wdata(n, m) <= wdata(m);
rdata(n, m) <= c.data_rdata(n, m);
end generate;
end generate;
tag_sram : entity tech.syncram_banked_1r1w(rtl)
generic map (
addr_bits => index_bits,
word_bits => tag_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
we => c.tag_we,
wbanken => c.tag_wbanken,
waddr => c.tag_waddr,
wdata => c.tag_wdata,
re => c.tag_re,
rbanken => c.tag_rbanken,
raddr => c.tag_raddr,
rdata => c.tag_rdata
);
data_sram : entity tech.syncram_banked_1r1w(rtl)
generic map (
addr_bits => index_bits + offset_bits,
word_bits => word_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
we => c.data_we,
wbanken => c.data_wbanken,
waddr => c.data_waddr,
wdata => c.data_wdata,
re => c.data_re,
rbanken => c.data_rbanken,
raddr => c.data_raddr,
rdata => c.data_rdata
);
end;
| apache-2.0 | 30d9364e04707c6918d61979c5b69e4b | 0.55814 | 3.450169 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/synth/system_vga_transform_0_0.vhd | 1 | 5,001 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_transform:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_transform_0_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_transform_0_0;
ARCHITECTURE system_vga_transform_0_0_arch OF system_vga_transform_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_transform_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_transform IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rot_m00 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_transform;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_transform_0_0_arch: ARCHITECTURE IS "vga_transform,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_transform_0_0_arch : ARCHITECTURE IS "system_vga_transform_0_0,vga_transform,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_transform_0_0_arch: ARCHITECTURE IS "system_vga_transform_0_0,vga_transform,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_transform,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_transform
PORT MAP (
clk => clk,
enable => enable,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out
);
END system_vga_transform_0_0_arch;
| mit | 0e3d396670fe951669df37c7308849e6 | 0.708658 | 3.567047 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_laplacian_fusion_0_0/sim/system_vga_laplacian_fusion_0_0.vhd | 1 | 3,668 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_laplacian_fusion:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_laplacian_fusion_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rgb_blur_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_blur_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_laplacian_fusion_0_0;
ARCHITECTURE system_vga_laplacian_fusion_0_0_arch OF system_vga_laplacian_fusion_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_laplacian_fusion_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_laplacian_fusion IS
PORT (
clk_25 : IN STD_LOGIC;
rgb_blur_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_blur_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_laplacian_fusion;
BEGIN
U0 : vga_laplacian_fusion
PORT MAP (
clk_25 => clk_25,
rgb_blur_0 => rgb_blur_0,
rgb_pass_0 => rgb_pass_0,
rgb_blur_1 => rgb_blur_1,
rgb_pass_1 => rgb_pass_1,
rgb_out => rgb_out
);
END system_vga_laplacian_fusion_0_0_arch;
| mit | 604309026dcfc4a8cdc2186b2d755649 | 0.7241 | 3.720081 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/mmu/data/pass/cpu_or1knd_i5_mmu_data_pass-rtl.vhdl | 1 | 1,670 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of cpu_or1knd_i5_mmu_data_pass is
begin
mmu : entity work.cpu_mmu_data_pass(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_pass_ctrl_in => cpu_or1knd_i5_mmu_data_pass_ctrl_in,
cpu_mmu_data_pass_ctrl_out => cpu_or1knd_i5_mmu_data_pass_ctrl_out,
cpu_mmu_data_pass_dp_in => cpu_or1knd_i5_mmu_data_pass_dp_in,
cpu_mmu_data_pass_dp_out => cpu_or1knd_i5_mmu_data_pass_dp_out
);
end;
| apache-2.0 | ffe8acb5049cc5416d7aac61f911dc22 | 0.511377 | 4.304124 | false | false | false | false |
pgavin/carpe | hdl/sim/monitor_pkg.vhdl | 1 | 22,346 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.names_pkg.all;
use work.options_pkg.all;
package monitor_pkg is
signal monitor_enable : boolean;
type monitor_event_code_type is (
monitor_event_code_error,
monitor_event_code_cycle,
monitor_event_code_reset,
monitor_event_code_exit,
monitor_event_code_watch
);
subtype monitor_event_source_id_type is natural;
impure function monitor_event_source(instance : string;
code : monitor_event_code_type;
name : string) return monitor_event_source_id_type;
procedure monitor_event(source : monitor_event_source_id_type;
data : std_ulogic_vector);
impure function monitor_has_event return boolean;
impure function monitor_event_timestamp return time;
impure function monitor_event_instance return string;
impure function monitor_event_code return monitor_event_code_type;
impure function monitor_event_name return string;
impure function monitor_event_data return std_ulogic_vector;
procedure monitor_event_finish;
procedure monitor_finish;
end package;
package body monitor_pkg is
type monitor_type is protected
impure function event_source(instance : in string;
code : in monitor_event_code_type;
name : in string) return monitor_event_source_id_type;
impure function event_source_instance(source : in monitor_event_source_id_type) return string;
impure function event_source_code(source : in monitor_event_source_id_type) return monitor_event_code_type;
impure function event_source_name(source : in monitor_event_source_id_type) return string;
impure function has_event return boolean;
procedure push_event(timestamp : in time;
source : in monitor_event_source_id_type;
data : in std_ulogic_vector);
procedure pop_event;
impure function head_timestamp return time;
impure function head_source return monitor_event_source_id_type;
impure function head_instance return string;
impure function head_code return monitor_event_code_type;
impure function head_name return string;
impure function head_data return std_ulogic_vector;
procedure finish;
end protected;
type monitor_event_queue_type is protected
impure function empty return boolean;
impure function head_timestamp return time;
impure function head_source return monitor_event_source_id_type;
impure function head_data return std_ulogic_vector;
procedure push(timestamp : in time;
source : in monitor_event_source_id_type;
data : in std_ulogic_vector);
procedure pop;
procedure free;
end protected;
type monitor_event_queue_type is protected body
constant initial_entry_queue_capacity : natural := 64;
constant initial_data_queue_capacity : natural := 2048;
type monitor_event_queue_entry_type is record
timestamp : time;
source : monitor_event_source_id_type;
data_length : natural;
end record;
type monitor_event_queue_entry_array_type is array (natural range <>) of monitor_event_queue_entry_type;
type monitor_event_queue_entry_array_ptr_type is access monitor_event_queue_entry_array_type;
type std_ulogic_vector_ptr_type is access std_ulogic_vector;
variable entry_queue_size : natural := 0;
variable entry_queue : monitor_event_queue_entry_array_ptr_type := null;
variable entry_queue_head_index : natural := 0;
variable entry_queue_tail_index : natural := 0;
variable data_queue_size : natural := 0;
variable data_queue : std_ulogic_vector_ptr_type := null;
variable data_queue_head_index : natural := 0;
variable data_queue_tail_index : natural := 0;
procedure check is
begin
if data_queue_size /= 0 or entry_queue_size /= 0 then
assert (data_queue /= null and data_queue.all'length >= data_queue_size and
0 <= data_queue_head_index and data_queue_head_index < data_queue.all'length and
0 <= data_queue_tail_index and data_queue_tail_index < data_queue.all'length and
((data_queue_size = 0) or
(data_queue_head_index = data_queue_tail_index and data_queue_size = data_queue.all'length) or
(data_queue_head_index < data_queue_tail_index and data_queue_size = data_queue_tail_index - data_queue_head_index) or
(data_queue_tail_index < data_queue_head_index and data_queue_size = data_queue.all'length - data_queue_head_index + data_queue_tail_index)
)
)
report "inconsistent queue data"
severity failure;
assert (entry_queue /= null and entry_queue.all'length >= entry_queue_size and
0 <= entry_queue_head_index and entry_queue_head_index < entry_queue.all'length and
0 <= entry_queue_tail_index and entry_queue_tail_index < entry_queue.all'length and
((entry_queue_head_index = entry_queue_tail_index and entry_queue_size = entry_queue.all'length) or
(entry_queue_head_index < entry_queue_tail_index and entry_queue_size = entry_queue_tail_index - entry_queue_head_index) or
(entry_queue_tail_index < entry_queue_head_index and entry_queue_size = entry_queue.all'length - entry_queue_head_index + entry_queue_tail_index)
)
)
report "inconsistent queue entry_queue"
severity failure;
end if;
end;
impure function empty return boolean is
begin
return entry_queue_size = 0;
end function;
procedure grow(new_data_length : natural) is
constant new_entry_queue_size : natural := entry_queue_size + 1;
variable entry_queue_capacity : natural;
variable new_entry_queue_capacity : natural;
variable new_entry_queue : monitor_event_queue_entry_array_ptr_type := null;
constant new_data_queue_size : natural := data_queue_size + new_data_length;
variable data_queue_capacity : natural;
variable new_data_queue_capacity : natural;
variable new_data_queue : std_ulogic_vector_ptr_type := null;
begin
if entry_queue = null then
--report "allocating vector queue";
assert entry_queue_size = 0
report "inconsistent queue"
severity failure;
new_entry_queue_capacity := initial_entry_queue_capacity;
--report "new entry_queue capacity: " & integer'image(new_entry_queue_capacity);
entry_queue := new monitor_event_queue_entry_array_type'(
0 to new_entry_queue_capacity-1 => (
timestamp => time'high,
source => monitor_event_source_id_type'high,
data_length => natural'high
)
);
entry_queue_head_index := 0;
entry_queue_tail_index := 0;
assert data_queue = null and data_queue_size = 0
report "inconsistent queue"
severity failure;
new_data_queue_capacity := initial_data_queue_capacity;
while new_data_queue_capacity < new_data_length loop
new_data_queue_capacity := new_data_queue_capacity * 2;
end loop;
--report "new data_queue capacity: " & integer'image(new_data_queue_capacity);
data_queue := new std_ulogic_vector(new_data_queue_capacity-1 downto 0);
data_queue_head_index := 0;
data_queue_tail_index := 0;
return;
end if;
entry_queue_capacity := entry_queue.all'length;
if entry_queue_capacity < new_entry_queue_size then
--report "growing vector entry_queue";
new_entry_queue_capacity := entry_queue_capacity;
while new_entry_queue_capacity < new_entry_queue_size loop
new_entry_queue_capacity := 2 * new_entry_queue_capacity;
end loop;
new_entry_queue := new monitor_event_queue_entry_array_type'(
0 to new_entry_queue_capacity-1 => (
timestamp => time'high,
source => monitor_event_source_id_type'high,
data_length => natural'high
)
);
if entry_queue_size > 0 then
if entry_queue_head_index < entry_queue_tail_index then
new_entry_queue(0 to entry_queue_size-1) := entry_queue(entry_queue_head_index to entry_queue_tail_index-1);
else
new_entry_queue(0 to entry_queue_capacity-entry_queue_head_index-1) := entry_queue(entry_queue_head_index to entry_queue_capacity-1);
new_entry_queue(entry_queue_capacity-entry_queue_head_index to entry_queue_size-1) := entry_queue(0 to entry_queue_tail_index-1);
end if;
end if;
deallocate(entry_queue);
entry_queue := new_entry_queue;
entry_queue_head_index := 0;
if entry_queue_size > 0 then
entry_queue_tail_index := entry_queue_size;
else
entry_queue_tail_index := 0;
end if;
end if;
data_queue_capacity := data_queue.all'length;
if data_queue_capacity < new_data_queue_size then
--report "growing data_queue";
new_data_queue_capacity := data_queue_capacity;
while new_data_queue_capacity < new_data_queue_size loop
new_data_queue_capacity := 2 * new_data_queue_capacity;
end loop;
new_data_queue := new std_ulogic_vector'(new_data_queue_capacity-1 downto 0 => 'U');
if data_queue_size > 0 then
if data_queue_head_index < data_queue_tail_index then
new_data_queue.all(data_queue_size-1 downto 0) := data_queue.all(data_queue_tail_index-1 downto data_queue_head_index);
else
new_data_queue.all(data_queue_capacity-data_queue_head_index-1 downto 0) := data_queue.all(data_queue_capacity-1 downto data_queue_head_index);
new_data_queue.all(data_queue_capacity-data_queue_head_index+data_queue_tail_index-1 downto data_queue_capacity-data_queue_head_index) := data_queue.all(data_queue_tail_index-1 downto 0);
end if;
end if;
deallocate(data_queue);
data_queue := new_data_queue;
data_queue_head_index := 0;
data_queue_tail_index := data_queue_size;
end if;
check;
end;
impure function head_timestamp return time is
begin
assert entry_queue_size > 0
report "tried to get head of empty queue"
severity failure;
return entry_queue(entry_queue_head_index).timestamp;
end function;
impure function head_source return monitor_event_source_id_type is
begin
assert entry_queue_size > 0
report "tried to get head of empty queue"
severity failure;
return entry_queue(entry_queue_head_index).source;
end function;
impure function head_data return std_ulogic_vector is
variable data_length : natural;
begin
assert entry_queue_size > 0
report "tried to get head of empty queue"
severity failure;
data_length := entry_queue(entry_queue_head_index).data_length;
if data_length = 0 then
return "";
end if;
assert data_queue /= null
report "inconsistent queue"
severity failure;
assert data_queue.all'length > 0
report "inconsistent queue"
severity failure;
assert data_queue_size > 0
report "inconsistent queue"
severity failure;
if data_queue_head_index < data_queue_tail_index then
return data_queue.all(data_queue_head_index+data_length-1 downto data_queue_head_index);
else
return data_queue.all(data_length-(data_queue'length-data_queue_head_index)-1 downto 0) & data_queue.all(data_queue.all'length-1 downto data_queue_head_index);
end if;
end function;
procedure push(timestamp : in time;
source : in monitor_event_source_id_type;
data : in std_ulogic_vector) is
begin
--report string'("push event time ") & time'image(timestamp) & " source " & monitor_event_source_id_type'image(source);
check;
grow(data'length);
assert data_queue.all'length >= data'length
report "inconsistent queue"
severity failure;
entry_queue(entry_queue_tail_index) := (
timestamp => timestamp,
source => source,
data_length => data'length
);
if entry_queue_tail_index = entry_queue'right then
entry_queue_tail_index := 0;
else
entry_queue_tail_index := entry_queue_tail_index + 1;
end if;
entry_queue_size := entry_queue_size + 1;
if data'length = 0 then
return;
end if;
for n in 0 to data'high loop
data_queue.all(data_queue_tail_index) := data(n);
if data_queue_tail_index /= data_queue.all'length-1 then
data_queue_tail_index := data_queue_tail_index + 1;
else
data_queue_tail_index := 0;
end if;
end loop;
data_queue_size := data_queue_size + data'length;
check;
end procedure;
procedure pop is
variable data_length : natural;
begin
check;
assert entry_queue_size > 0
report "pop on empty queue"
severity failure;
--report string'("pop event time ") & time'image(head_timestamp) & " source " & monitor_event_source_id_type'image(head_source);
data_length := entry_queue(entry_queue_head_index).data_length;
assert (data_length <= data_queue_size and
data_length <= data_queue.all'length)
report "pop length mismatch"
severity failure;
if data_length > 0 then
if data_queue_size > data_length then
data_queue_size := data_queue_size-data_length;
if data_queue_tail_index <= data_queue_head_index and data_queue'length - data_length < data_queue_head_index then
data_queue_head_index := data_length - (data_queue'length - data_queue_head_index);
else
data_queue_head_index := data_queue_head_index + data_length;
end if;
else
assert data_queue_size = data_length
report "pop length mismatch";
data_queue_size := 0;
data_queue_head_index := 0;
data_queue_tail_index := 0;
end if;
end if;
if entry_queue_size > 1 then
entry_queue_size := entry_queue_size - 1;
if entry_queue_head_index = entry_queue'right then
entry_queue_head_index := 0;
else
entry_queue_head_index := entry_queue_head_index + 1;
end if;
else
entry_queue_size := 0;
entry_queue_head_index := 0;
entry_queue_tail_index := 0;
end if;
check;
end procedure;
procedure free is
begin
check;
deallocate(data_queue);
data_queue := null;
data_queue_head_index := 0;
data_queue_tail_index := 0;
data_queue_size := 0;
entry_queue := null;
deallocate(entry_queue);
entry_queue := null;
entry_queue_head_index := 0;
entry_queue_tail_index := 0;
entry_queue_size := 0;
end procedure;
end protected body;
constant initial_source_array_capacity : natural := 64;
type monitor_type is protected body
type monitor_event_source_type is record
instance : line;
code : monitor_event_code_type;
name : line;
end record;
type monitor_event_source_array_type is array(natural range <>) of monitor_event_source_type;
type monitor_event_source_array_ptr_type is access monitor_event_source_array_type;
variable initialized : boolean := false;
variable source_array : monitor_event_source_array_ptr_type := null;
variable source_array_tail : natural := 0;
variable event_queue : monitor_event_queue_type;
impure function event_source(instance : in string;
code : in monitor_event_code_type;
name : in string) return monitor_event_source_id_type is
variable ret : natural;
begin
if source_array = null then
assert source_array_tail = 0
report "inconsistent source array"
severity failure;
source_array := new monitor_event_source_array_type'(
0 to initial_source_array_capacity-1 => (
instance => null,
code => monitor_event_code_error,
name => null)
);
else
for n in 0 to source_array_tail-1 loop
if source_array.all(n).instance.all = instance and
source_array.all(n).code = code and
source_array.all(n).name.all = name then
return n;
end if;
end loop;
end if;
--report string'("new event source: instance ") & instance & string'(", code ") & monitor_event_code_type'image(code) & string'(", name ") & name;
source_array.all(source_array_tail) := (
instance => new string'(instance),
code => code,
name => new string'(name)
);
ret := source_array_tail;
source_array_tail := source_array_tail + 1;
return ret;
end;
impure function event_source_instance(source : in monitor_event_source_id_type) return string is
begin
assert source < source_array_tail
report "invalid source: " & monitor_event_source_id_type'image(source)
severity failure;
return source_array.all(source).instance.all;
end;
impure function event_source_code(source : in monitor_event_source_id_type) return monitor_event_code_type is
begin
assert source < source_array_tail
report "invalid source: " & monitor_event_source_id_type'image(source)
severity failure;
return source_array.all(source).code;
end;
impure function event_source_name(source : in monitor_event_source_id_type) return string is
begin
assert source < source_array_tail
report "invalid source: " & monitor_event_source_id_type'image(source)
severity failure;
return source_array.all(source).name.all;
end;
impure function has_event return boolean is
begin
return not event_queue.empty;
end;
procedure push_event(timestamp : in time;
source : in monitor_event_source_id_type;
data : in std_ulogic_vector) is
begin
event_queue.push(timestamp, source, data);
end;
procedure pop_event is
begin
event_queue.pop;
end;
impure function head_timestamp return time is
begin
return event_queue.head_timestamp;
end function;
impure function head_source return monitor_event_source_id_type is
begin
return event_queue.head_source;
end function;
impure function head_instance return string is
begin
return source_array(head_source).instance.all;
end function;
impure function head_code return monitor_event_code_type is
begin
return source_array(head_source).code;
end function;
impure function head_name return string is
begin
return source_array(head_source).name.all;
end function;
impure function head_data return std_ulogic_vector is
begin
return event_queue.head_data;
end function;
procedure finish is
begin
event_queue.free;
end;
end protected body;
shared variable the_monitor : monitor_type;
impure function monitor_event_source(instance : string;
code : monitor_event_code_type;
name : string) return monitor_event_source_id_type is
begin
return the_monitor.event_source(instance, code, name);
end;
procedure monitor_event(source : monitor_event_source_id_type;
data : std_ulogic_vector) is
begin
the_monitor.push_event(now, source, data);
end;
impure function monitor_has_event return boolean is
begin
return the_monitor.has_event;
end;
impure function monitor_event_timestamp return time is
begin
return the_monitor.head_timestamp;
end;
impure function monitor_event_instance return string is
begin
return the_monitor.head_instance;
end;
impure function monitor_event_code return monitor_event_code_type is
begin
return the_monitor.head_code;
end;
impure function monitor_event_name return string is
begin
return the_monitor.head_name;
end;
impure function monitor_event_data return std_ulogic_vector is
begin
return the_monitor.head_data;
end;
procedure monitor_event_finish is
begin
the_monitor.pop_event;
end;
procedure monitor_finish is
begin
the_monitor.finish;
end;
end package body;
| apache-2.0 | f2d1d1b4a003dddcc72ae6a74efc2992 | 0.619798 | 4.04233 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_1_0/synth/system_vga_gaussian_blur_1_0.vhd | 1 | 5,235 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_1_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_1_0;
ARCHITECTURE system_vga_gaussian_blur_1_0_arch OF system_vga_gaussian_blur_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_1_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_1_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_1_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_1_0,vga_gaussian_blur,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_1_0_arch;
| mit | 20c3342f2db91f8596f0bbc44271d5cd | 0.698185 | 3.487675 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/tb/reg_file_bram_tb.vhd | 2 | 4,740 | -------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file_bram"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram_tb is
end entity reg_file_bram_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_bram_tb is
-- component generics
constant BASE_ADDRESS : integer := 16#0400#;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal bram_data_i : std_logic_vector(15 downto 0) := (others => '0');
signal bram_data_o : std_logic_vector(15 downto 0) := (others => '0');
signal bram_addr_i : std_logic_vector(9 downto 0) := (others => '0');
signal bram_we_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.reg_file_bram
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
bus_o => bus_o,
bus_i => bus_i,
bram_data_i => bram_data_i,
bram_data_o => bram_data_o,
bram_addr_i => bram_addr_i,
bram_we_p => bram_we_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '1';
-- write a word to valid addresses
writeWord(addr => BASE_ADDRESS + 0, data => 16#55aa#, bus_i => bus_i, clk => clk);
writeWord(addr => BASE_ADDRESS + 1, data => 16#33dd#, bus_i => bus_i, clk => clk);
-- write to invalid address
writeWord(addr => 0, data => 16#2211#, bus_i => bus_i, clk => clk);
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
-- read from valid address
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
-- read from invalid address
readWord(addr => BASE_ADDRESS - 1, bus_i => bus_i, clk => clk);
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
-- read from valid address
readWord(addr => BASE_ADDRESS + 0, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 2, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 3, bus_i => bus_i, clk => clk);
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
-- write all the block ram
bram_we_p <= '1';
for ii in 0 to 16#00ff# loop
bram_addr_i <= std_logic_vector(to_unsigned(ii, 10));
bram_data_i <= std_logic_vector(to_unsigned(ii, 16));
wait until clk = '1';
end loop; -- ii
bram_we_p <= '0';
-- read from port A
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
readWord(addr => BASE_ADDRESS + 16#23#, bus_i => bus_i, clk => clk);
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
-- test the address match
-- the addr_match_a signal is only '1' when the bus address
-- matches the range between including BASE_ADDRESS to BASE_ADDRESS + 0x03ff
bus_i.re <= '1';
for addr in 0 to 16#0800# loop
bus_i.addr <= std_logic_vector(to_unsigned(addr, bus_i.addr'length));
wait until rising_edge(clk);
end loop; -- addr
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end architecture tb;
| bsd-3-clause | 91bb4f9f3c58f2a7ad5b029e44d9be96 | 0.464346 | 3.866232 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_3/Uart_working/des_decrypt_wit_out - Copy.vhd | 2 | 15,062 | ------------------------------------------
--------------PACKET----------------------
----MSB--- EN G1 G2 G3 G6 G7 ---LSB-------
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DISPLAY_UNIT is
generic (N: integer := 20; M: integer:= 5);--- N = No of Bits in Test vector + 1 (For Enable)
--- M = No of Bits Reuired to count the N
port(
TXD : out std_logic := '1';RXD: in std_logic := '1';
st_indicator: OUT std_logic_vector(2 downto 0);
--DU : in STD_LOGIC; EN : in STD_LOGIC;
ROC : in STD_LOGIC;REF : in STD_LOGIC;
--G1,G2,G3,G6: in STD_LOGIC;
LEDS: out std_logic_vector(7 downto 0) := "11111111";
clk : in std_logic; OUTDIGIT: out STD_LOGIC_VECTOR (7 downto 0);
seg_out: out std_logic_vector(6 downto 0);
dis: out std_logic_vector(7 downto 0);
ANODE : out STD_LOGIC_VECTOR (3 downto 0);RST: in std_logic := '0'
);
end DISPLAY_UNIT;
architecture behavior of DISPLAY_UNIT is
component Dec2LED
port (CLK: in STD_LOGIC; X: in STD_LOGIC_VECTOR (3 downto 0); Y: out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal DIGIT : STD_LOGIC_VECTOR(7 downto 0) :="00000000";
type arr is array(0 to 15) of std_logic_vector(7 downto 0);
signal NAME: arr;
type ARR2 is array(0 to 3) of std_logic_vector(7 downto 0);
signal TMPDGT: ARR2;
signal TEMP: STD_LOGIC_VECTOR(3 downto 0) :="0111";
signal CLKM : STD_LOGIC :='0';
signal Z : integer :=0;
signal G : integer :=30;
signal NAMEA : integer :=3;
signal NAMEB : integer :=2;
signal NAMEC : integer :=1;
signal NAMED : integer :=0;
signal pt1:STD_LOGIC_VECTOR(32 downto 0);
COMPONENT Circuit17
PORT(
TE,ROSEL : IN std_logic;
G1 : IN std_logic;
G2 : IN std_logic;
G3 : IN std_logic;
G6 : IN std_logic;
G7 : IN std_logic;
G22 : OUT std_logic;
G23 : OUT std_logic;
GEX: OUT std_logic
);
END COMPONENT;
component RS232RefComp
Port ( TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic;
DBIN : in std_logic_vector (7 downto 0);
DBOUT : out std_logic_vector (7 downto 0);
RDA : inout std_logic;
TBE : inout std_logic := '1';
RD : in std_logic;
WR : in std_logic;
PE : out std_logic;
FE : out std_logic;
OE : out std_logic;
RST : in std_logic := '0');
end component;
COMPONENT HEX2ASC
PORT(
VAL : IN std_logic_vector(3 downto 0);
CLK : IN std_logic;
Y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
component ascii_hex
Port ( clk : in std_logic; ascii : in std_logic_vector(7 downto 0);hex : inout std_logic_vector(3 downto 0)
);
end component;
type StateType is (Idle, cnt, receive,Decide, send1, send2,
stInput,stOutput,Test_vector,DisplayI );
signal dbInSig : std_logic_vector(7 downto 0);
signal dbOutSig, dbOutSig2, dbOutSig3: std_logic_vector(7 downto 0);
signal hex0, hex1, hex2, hex3, hex4, hex5 : std_logic_vector(3 downto 0);
signal rdaSig : std_logic;
signal tbeSig : std_logic;
signal rdSig : std_logic;
signal wrSig : std_logic;
signal peSig : std_logic;
signal feSig : std_logic;
signal oeSig : std_logic;
signal state : StateType;
signal RST_TEMP: Std_logic;
signal reg_in : std_logic_vector(7 downto 0);
signal count : std_logic_vector(3 downto 0);
signal ro : std_logic_vector(63 downto 0);
signal St_indic: std_logic_vector(2 downto 0);
signal Rflag : std_logic_vector(M-1 downto 0);
Signal Shift_Length: std_logic_vector(M-1 downto 0);
signal tv : std_logic_vector(N-1 downto 0);
signal i_cntx: std_logic_vector(2 downto 0);
signal big_counter: std_logic_vector(31 downto 0);
signal temps: std_logic_vector (3 downto 0);
signal osc,out1,GEX : std_logic;
signal G1,G2,G3,G6,G7,EN,D: std_logic;
--signal G1,G2,G3,G6,G7,DU,EN,D: std_logic;
signal ROSEL,DU: std_logic:='1';
signal countR,count_RO,count_RO_t,count1: std_logic_vector(31 downto 0);
signal packet: std_logic_vector(N-1 downto 0);
begin
st_indicator<=St_indic;
PROCESS(clk) BEGIN
IF(clk'EVENT AND clk='1') THEN
big_counter<=big_counter+'1';
END IF;
END PROCESS;
i_cntx <= big_counter(13 downto 11);
with temps select
seg_out <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"1111110" when others;
with i_cntx select
dis<= "11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others;
with i_cntx select
temps <= dbOutSig(3 downto 0) when "000",
dbOutSig(7 downto 4) when "001",
dbOutSig2(3 downto 0) when "010",
dbOutSig2(7 downto 4) when "011",
dbOutSig3(3 downto 0) when "100",
dbOutSig3(7 downto 4) when "101",
--dbOutSig2(11 downto 8) when "110",
x"0" when others;
Shift_Length<= std_logic_vector( to_unsigned( N,M ));
-- LEDS(7) <= Count_RO_t(0);
-- LEDS(6) <= Count_RO_t(1);
-- LEDS(5) <= Count_RO_t(2);
-- LEDS(4) <= Count_RO_t(3);
-- LEDS(3) <= Count_RO_t(4);
-- LEDS(2) <= Count_RO_t(5);
-- LEDS(1) <= Count_RO_t(6);
-- LEDS(0) <= OSC;
G7<=Packet(N-6);
G6<=Packet(N-5);
G3<=Packet(N-4);
G2<=Packet(N-3);
G1<=Packet(N-2);
EN<=Packet(N-1);
LEDS(7) <= G7;
LEDS(6) <= G6;
LEDS(5) <= G3;
LEDS(4) <= G2;
LEDS(3) <= G1;
LEDS(2) <= Du;
LEDS(1) <= En;
LEDS(0) <= OSC;
UART: RS232RefComp port map ( TXD => TXD,
RXD => RXD,
CLK => CLK,
DBIN => dbInSig,
DBOUT => dbOutSig,
RDA => rdaSig,
TBE => tbeSig,
RD => rdSig,
WR => wrSig,
PE => peSig,
FE => feSig,
OE => oeSig,
RST => RST);
--------------RO1------------------
RO2: Circuit17 PORT MAP(EN,ROSEL,G1,G2,G3,G6,G7,GEX,out1,osc);
-------------REFERENCE COUNT-------
process(clk,en)
Begin
if en ='0' then
countR <= (others=>'0');
elsif clk='1' and clk'event then
if countR<x"40000000" then
countR <= countR +'1';
end if;
end if;
end process;
-------------RO COUNT-------------
process(osc,en,countR,clk)
Begin
if en ='0' then
count_RO_t <= (others=>'0');
elsif osc='1' and osc'event then
if countR<x"40000000" then
count_RO_t <= count_RO_t +'1';
elsif countR=x"40000000" then
count_RO<= count_RO_t;
count1<= countR;
end if;
end if;
end process;
----------------------------------
-----------------------------CONVERSION TO ASCII----------------------------
--D1: HEX2ASC PORT MAP(count_RO(31 DOWNTO 28),CLK,RO(63 downto 56));
--D2: HEX2ASC PORT MAP(count_RO(27 DOWNTO 24),CLK,RO(55 downto 48));
--D3: HEX2ASC PORT MAP(count_RO(23 DOWNTO 20),CLK,RO(47 downto 40));
--D4: HEX2ASC PORT MAP(count_RO(19 DOWNTO 16),CLK,RO(39 downto 32));
--D5: HEX2ASC PORT MAP(count_RO(15 DOWNTO 12),CLK,RO(31 downto 24));
--D6: HEX2ASC PORT MAP(count_RO(11 DOWNTO 8),CLK,RO(23 downto 16));
--D7: HEX2ASC PORT MAP(count_RO(7 DOWNTO 4),CLK,RO(15 downto 8));
--D8: HEX2ASC PORT MAP(count_RO(3 DOWNTO 0),CLK,RO(7 downto 0));
----------------------------------------------------------------------------
H1: ascii_hex port map(clk=>clk, ascii=>dbOutSig, hex=>hex0);
--H1: ascii_hex PORT MAP(CLK,RO(63 downto 56),count_RO(31 DOWNTO 28));
--H2: ascii_hex PORT MAP(CLK,RO(55 downto 48),count_RO(27 DOWNTO 24));
--H3: ascii_hex PORT MAP(CLK,RO(47 downto 40),count_RO(23 DOWNTO 20));
--H4: ascii_hex PORT MAP(CLK,RO(39 downto 32),count_RO(19 DOWNTO 16));
--H5: ascii_hex PORT MAP(CLK,RO(31 downto 24),count_RO(15 DOWNTO 12));
--H6: ascii_hex PORT MAP(CLK,RO(23 downto 16),count_RO(11 DOWNTO 8));
--H7: ascii_hex PORT MAP(CLK,RO(15 downto 8),count_RO(7 DOWNTO 4));
--H8: ascii_hex PORT MAP(CLK,RO(7 downto 0),count_RO(3 DOWNTO 0));
process(clk, rst)
begin
if(rst = '1')then
state <= idle;
rdSig <= '0';
wrSig <= '0';
RST_TEMP <='1';
reg_in <= (others =>'0');
dbInSig <= (others =>'0');
count <= "1111";
Rflag<=(Others=>'0');
tv<=(Others=>'0');
elsif(clk'event and clk = '1')then
case state is
when idle => rdSig <= '0';
wrSig <= '0';
RST_TEMP <='0';
Rflag<=(Others=>'0');
count<= "0000";
St_indic<= "111";
if(rdaSig = '1')then
state <= receive;
end if;
when receive => reg_in <= dbOutSig;
state <= decide;
when decide => St_indic<="100";
if (dbOutSig = x"49") then
state <= StInput;
elsif (dbOutSig<=x"69") then
state <= StInput;
elsif (dbOutSig = x"4F") then
state <= StOutput;
elsif (dbOutSig<=x"6F") then
state <= StOutput;
else
state<= Idle;
End if;
when StInput =>
St_indic<="000";
rdsig <= '0';
wrsig <= '0';
if (rdaSig = '1') then
state<= test_vector;
end if;
when test_vector =>
-- if (dboutsig > x"2F" and dboutsig < x"3A") then
-- tv<=tv(N-5 downto 0) & hex0;
-- Rflag<= Rflag +'1';
-- state<= displayI;
-- elsif (dboutsig > x"60" and dboutsig < x"67") then
-- tv<=tv(N-5 downto 0) & hex0;
-- Rflag<= Rflag +'1';
-- state<= displayI;
if dboutsig = x"30" then
tv<=tv(N-2 downto 0) & '0';
Rflag<= Rflag +'1';
state<= displayI;
elsif dboutsig = x"31" then
tv<=tv(N-2 downto 0) & '1';
Rflag<= Rflag +'1';
state<= displayI;
elsif (dboutsig = x"72") then
tv<=(Others=>'0');
state<= Idle ;
elsif (dboutsig = x"52") then
tv<=(Others=>'0');
state<= Idle;
elsif (dbOutSig = x"4F") then
state <= StOutput;
elsif (dbOutSig<=x"6F") then
state <= StOutput;
else
tv<= tv;
state<= idle;
end if;
state<= displayI;
St_indic<="110";
When displayI =>
St_indic<="001";
wrsig<='1'; rdsig<='1';
dbInsig<=dbOutsig;
If Rflag =Shift_length then
state<= Idle;
else
state <= StInput;
end if;
when stoutput =>
if count = "0001" then
dbInSig <=x"20";
ELSif count = "1010" then
dbInSig <=x"0A";
elsif count = "0010" then
dbInSig <=ro (63 downto 56);
elsif count = "0011" then
dbInSig <=ro (55 downto 48);
elsif count = "0100" then
dbInSig <=ro (47 downto 40);
elsif count = "0101" then
dbInSig <=ro (39 downto 32);
elsif count = "0110" then
dbInSig <=ro (31 downto 24);
elsif count = "0111" then
dbInSig <=ro (23 downto 16);
elsif count = "1000" then
dbInSig <=ro (15 downto 8);
elsif count = "1001" then
dbInSig <=ro (7 downto 0);
end if;
rdsig<='0'; wrsig<='0';
if TBEsig='1' then
state <= send1;
end if;
when send1 => rdSig <= '1';
wrSig <= '1';
state <= cnt;
when cnt => count <= count +'1';
state<= send2;
when send2 => if (count > "1010") then
state <= idle;
rdsig<= '0';
wrsig<='0';
else
-- count <= "0000";
state <= stOutput;
end if;
end case;
end if;
end process;
Packet <=TV(N-1 Downto 0);
HCONV1: HEX2ASC port map (CLK => CLK, VAL =>packet(3 downto 0), Y =>ro(7 downto 0));
HCONV2: HEX2ASC port map (CLK => CLK, VAL =>packet(7 downto 4), Y =>ro(15 downto 8));
HCONV3: HEX2ASC port map (CLK => CLK, VAL =>packet(11 downto 8), Y =>ro(23 downto 16));
HCONV4: HEX2ASC port map (CLK => CLK, VAL =>packet(15 downto 12), Y =>ro(31 downto 24));
--Packet <= '0' & hex0 & hex1 ;
-----INTERFACING TO FPGA-------
----- 7 SEGMENT CLOCK----------
process (CLK)
begin
if CLK'event and CLK='1' then
if Z=200000 then
CLKM <= '1';
elsif Z=400000 then
CLKM <= '0';
Z <= 0;
end if;
if Z /=400000 then
Z <= Z+1;
end if;
end if;
end process;
NAME(14)<= "11111111";
NAME(13)<= "11111111";
NAME(12)<= "11111111";
NAME(15)<= "11111111";
process(ROC,REF,EN,DU,countR,count_RO)
begin
if REF='1' and DU='1' then
pt1(32 downto 1)<= countr;
NAME(0)<= "10101111";
NAME(1)<= "10000110";
NAME(2)<= "10001110";
NAME(3)<= "10111111";
elsif ROC='1' then
pt1(32 downto 1)<= count_RO;
NAME(0)<= "10101111";
NAME(1)<= "11000000";
NAME(2)<= "11000110";
NAME(3)<= "10111111";
else
pt1(32 downto 1)<= "00000000000000000000000000000" & GEX & out1 & osc;
NAME(0)<= "10111111";
NAME(1)<= "10111111";
NAME(2)<= "10111111";
NAME(3)<= "10111111";
end if;
end process;
CONV1: Dec2LED port map (CLK => CLK, X => pt1(32 downto 29), Y => NAME(4));
CONV2: Dec2LED port map (CLK => CLK, X => pt1(28 downto 25), Y => NAME(5));
CONV3: Dec2LED port map (CLK => CLK, X => pt1(24 downto 21), Y => NAME(6));
CONV4: Dec2LED port map (CLK => CLK, X => pt1(20 downto 17), Y => NAME(7));
CONV5: Dec2LED port map (CLK => CLK, X => pt1(16 downto 13), Y => NAME(8));
CONV6: Dec2LED port map (CLK => CLK, X => pt1(12 downto 9), Y => NAME(9));
CONV7: Dec2LED port map (CLK => CLK, X => pt1(8 downto 5), Y => NAME(10));
CONV8: Dec2LED port map (CLK => CLK, X => pt1(4 downto 1), Y => NAME(11));
process (CLKM)
begin
if CLKM'event and CLKM='1' then
if DU='1' then
if G=60 then
TMPDGT(0) <= NAME(NAMEA);
if NAMEA=15 then
NAMEA <= 0;
else
NAMEA <= NAMEA + 1;
end if;
TMPDGT(1) <= NAME(NAMEB);
if NAMEB=15 then
NAMEB <= 0;
else
NAMEB <= NAMEB + 1;
end if;
TMPDGT(2) <= NAME(NAMEC);
if NAMEC=15 then
NAMEC <= 0;
else
NAMEC <= NAMEC + 1;
end if;
TMPDGT(3) <= NAME(NAMED);
if NAMED=15 then
NAMED <= 0;
else
NAMED <= NAMED + 1;
end if;
G <= 0;
else
G <= G + 1;
end if;
end if;
end if;
end process;
process (CLKM)
begin
if CLKM'event and CLKM='1' then
if DU='1' then
if TEMP="0111" then
TEMP <= "1110";
DIGIT <= TMPDGT(0);
elsif TEMP="1110" then
TEMP <= "1101";
DIGIT <= TMPDGT(1);
elsif TEMP="1101" then
TEMP <= "1011";
DIGIT <= TMPDGT(2);
else
TEMP <= "0111";
DIGIT <= TMPDGT(3);
end if;
end if;
end if;
end process;
ANODE <= TEMP;
OUTDIGIT <= DIGIT;
end behavior; | mit | 60fd7a5e895cfc9df2e3f3330bad04c5 | 0.545877 | 2.901002 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_sim_netlist.vhdl | 1 | 760,068 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 10:58:36 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_sim_netlist.vhdl
-- Design : system_vga_hessian_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_bindec : entity is "bindec";
end system_vga_hessian_1_0_bindec;
architecture STRUCTURE of system_vga_hessian_1_0_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => ena,
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => addra(1),
O => ena_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_bindec_0 is
port (
enb_array : out STD_LOGIC_VECTOR ( 2 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_bindec_0 : entity is "bindec";
end system_vga_hessian_1_0_bindec_0;
architecture STRUCTURE of system_vga_hessian_1_0_bindec_0 is
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => enb,
I1 => addrb(0),
I2 => addrb(1),
O => enb_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(1),
I1 => addrb(0),
I2 => enb,
O => enb_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => addrb(0),
I1 => enb,
I2 => addrb(1),
O => enb_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end system_vga_hessian_1_0_blk_mem_gen_mux;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe_d1(0),
O => douta(3)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe_d1(0),
O => douta(4)
);
\douta[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe_d1(0),
O => douta(5)
);
\douta[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe_d1(0),
O => douta(6)
);
\douta[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe_d1(0),
O => douta(7)
);
\douta[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => sel_pipe_d1(0),
O => douta(8)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe_d1(0),
O => douta(0)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe_d1(0),
O => douta(1)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe_d1(0),
O => douta(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 8 downto 0 );
enb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
clkb : in STD_LOGIC;
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\ is
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC;
begin
\doutb[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(3)
);
\doutb[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(4)
);
\doutb[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(5)
);
\doutb[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(6)
);
\doutb[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(7)
);
\doutb[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPBDOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(8)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(0)
);
\doutb[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(1)
);
\doutb[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOBDO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
I3 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2),
I5 => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
O => doutb(2)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0]\,
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
Q => \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(0),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => enb,
D => addrb(1),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end system_vga_hessian_1_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => addrb(13 downto 0),
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 1) => B"000000000000000",
DIBDI(0) => dinb(0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => doutb(0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => enb,
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \bottom_left_0_reg[15]\(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \top_right_1_reg[15]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 1) => B"000",
DIPBDIP(0) => dinb(8),
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => DOPBDOP(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => enb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addra(13),
I1 => addra(12),
I2 => ena,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
I2 => enb,
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
doutb : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
dinb : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end system_vga_hessian_1_0_blk_mem_gen_prim_width;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.system_vga_hessian_1_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\ is
port (
\bottom_left_0_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\top_right_1_reg[14]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\bottom_left_0_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\top_right_1_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
enb_array : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7 downto 0) => \bottom_left_0_reg[14]\(7 downto 0),
\bottom_left_0_reg[15]\(0) => \bottom_left_0_reg[15]\(0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7 downto 0) => \top_right_1_reg[14]\(7 downto 0),
\top_right_1_reg[15]\(0) => \top_right_1_reg[15]\(0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(0) => DOPBDOP(0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
dinb(8 downto 0) => dinb(8 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end system_vga_hessian_1_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal enb_array : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_16\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_17\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_9\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.system_vga_hessian_1_0_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena => ena,
ena_array(2 downto 0) => ena_array(2 downto 0)
);
\bindec_b.bindec_inst_b\: entity work.system_vga_hessian_1_0_bindec_0
port map (
addrb(1 downto 0) => addrb(13 downto 12),
enb => enb,
enb_array(2 downto 0) => enb_array(2 downto 0)
);
\has_mux_a.A\: entity work.system_vga_hessian_1_0_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_16\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_16\,
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(15 downto 7),
ena => ena
);
\has_mux_b.B\: entity work.\system_vga_hessian_1_0_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[5].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[5].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[5].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[5].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[5].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[5].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[5].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[6].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[6].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[6].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[6].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[6].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[6].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[6].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[4].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[4].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[4].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[4].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[4].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[4].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_17\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[4].ram.r_n_17\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addrb(1 downto 0) => addrb(13 downto 12),
clkb => clkb,
doutb(8 downto 0) => doutb(15 downto 7),
enb => enb
);
\ramloop[0].ram.r\: entity work.system_vga_hessian_1_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
dinb(0) => dinb(0),
douta(0) => douta(0),
doutb(0) => doutb(0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(2 downto 1),
dinb(1 downto 0) => dinb(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
doutb(1 downto 0) => doutb(2 downto 1),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(4 downto 3),
dinb(1 downto 0) => dinb(4 downto 3),
douta(1 downto 0) => douta(4 downto 3),
doutb(1 downto 0) => doutb(4 downto 3),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(6 downto 5),
dinb(1 downto 0) => dinb(6 downto 5),
douta(1 downto 0) => douta(6 downto 5),
doutb(1 downto 0) => doutb(6 downto 5),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[4].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[4].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[4].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[4].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[4].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[4].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[4].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[4].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[4].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(0),
enb => enb,
enb_array(0) => enb_array(0),
\top_right_1_reg[14]\(7) => \ramloop[4].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[4].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[4].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[4].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[4].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[4].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[4].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[4].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[4].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[5].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[5].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[5].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[5].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[5].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[5].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[5].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[5].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[5].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[5].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(1),
enb => enb,
enb_array(0) => enb_array(1),
\top_right_1_reg[14]\(7) => \ramloop[5].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[5].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[5].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[5].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[5].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[5].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[5].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[5].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[5].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[6].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => addrb(11 downto 0),
\bottom_left_0_reg[14]\(7) => \ramloop[6].ram.r_n_0\,
\bottom_left_0_reg[14]\(6) => \ramloop[6].ram.r_n_1\,
\bottom_left_0_reg[14]\(5) => \ramloop[6].ram.r_n_2\,
\bottom_left_0_reg[14]\(4) => \ramloop[6].ram.r_n_3\,
\bottom_left_0_reg[14]\(3) => \ramloop[6].ram.r_n_4\,
\bottom_left_0_reg[14]\(2) => \ramloop[6].ram.r_n_5\,
\bottom_left_0_reg[14]\(1) => \ramloop[6].ram.r_n_6\,
\bottom_left_0_reg[14]\(0) => \ramloop[6].ram.r_n_7\,
\bottom_left_0_reg[15]\(0) => \ramloop[6].ram.r_n_16\,
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
ena_array(0) => ena_array(2),
enb => enb,
enb_array(0) => enb_array(2),
\top_right_1_reg[14]\(7) => \ramloop[6].ram.r_n_8\,
\top_right_1_reg[14]\(6) => \ramloop[6].ram.r_n_9\,
\top_right_1_reg[14]\(5) => \ramloop[6].ram.r_n_10\,
\top_right_1_reg[14]\(4) => \ramloop[6].ram.r_n_11\,
\top_right_1_reg[14]\(3) => \ramloop[6].ram.r_n_12\,
\top_right_1_reg[14]\(2) => \ramloop[6].ram.r_n_13\,
\top_right_1_reg[14]\(1) => \ramloop[6].ram.r_n_14\,
\top_right_1_reg[14]\(0) => \ramloop[6].ram.r_n_15\,
\top_right_1_reg[15]\(0) => \ramloop[6].ram.r_n_17\,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[7].ram.r\: entity work.\system_vga_hessian_1_0_blk_mem_gen_prim_width__parameterized6\
port map (
DOADO(7) => \ramloop[7].ram.r_n_0\,
DOADO(6) => \ramloop[7].ram.r_n_1\,
DOADO(5) => \ramloop[7].ram.r_n_2\,
DOADO(4) => \ramloop[7].ram.r_n_3\,
DOADO(3) => \ramloop[7].ram.r_n_4\,
DOADO(2) => \ramloop[7].ram.r_n_5\,
DOADO(1) => \ramloop[7].ram.r_n_6\,
DOADO(0) => \ramloop[7].ram.r_n_7\,
DOBDO(7) => \ramloop[7].ram.r_n_8\,
DOBDO(6) => \ramloop[7].ram.r_n_9\,
DOBDO(5) => \ramloop[7].ram.r_n_10\,
DOBDO(4) => \ramloop[7].ram.r_n_11\,
DOBDO(3) => \ramloop[7].ram.r_n_12\,
DOBDO(2) => \ramloop[7].ram.r_n_13\,
DOBDO(1) => \ramloop[7].ram.r_n_14\,
DOBDO(0) => \ramloop[7].ram.r_n_15\,
DOPADOP(0) => \ramloop[7].ram.r_n_16\,
DOPBDOP(0) => \ramloop[7].ram.r_n_17\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(15 downto 7),
dinb(8 downto 0) => dinb(15 downto 7),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end system_vga_hessian_1_0_blk_mem_gen_top;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.system_vga_hessian_1_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
ena : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
enb : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.system_vga_hessian_1_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 22.1485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 : entity is "yes";
end system_vga_hessian_1_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.system_vga_hessian_1_0_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
ena => ena,
enb => enb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "blk_mem_gen_0";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_1_0_blk_mem_gen_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end system_vga_hessian_1_0_blk_mem_gen_0;
architecture STRUCTURE of system_vga_hessian_1_0_blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 22.1485 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_vga_hessian_1_0_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(15 downto 0) => dina(15 downto 0),
dinb(15 downto 0) => dinb(15 downto 0),
douta(15 downto 0) => douta(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(15 downto 0) => B"0000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0_vga_hessian is
port (
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
clk_x16 : in STD_LOGIC;
rst : in STD_LOGIC;
active : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_hessian_1_0_vga_hessian : entity is "vga_hessian";
end system_vga_hessian_1_0_vga_hessian;
architecture STRUCTURE of system_vga_hessian_1_0_vga_hessian is
signal A : STD_LOGIC_VECTOR ( 15 downto 0 );
signal B : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx : STD_LOGIC;
signal \Lxx0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_0\ : STD_LOGIC;
signal \Lxx0_carry__0_n_1\ : STD_LOGIC;
signal \Lxx0_carry__0_n_2\ : STD_LOGIC;
signal \Lxx0_carry__0_n_3\ : STD_LOGIC;
signal \Lxx0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__1_n_1\ : STD_LOGIC;
signal \Lxx0_carry__1_n_2\ : STD_LOGIC;
signal \Lxx0_carry__1_n_3\ : STD_LOGIC;
signal \Lxx0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx0_carry__2_n_1\ : STD_LOGIC;
signal \Lxx0_carry__2_n_2\ : STD_LOGIC;
signal \Lxx0_carry__2_n_3\ : STD_LOGIC;
signal Lxx0_carry_i_1_n_0 : STD_LOGIC;
signal Lxx0_carry_i_2_n_0 : STD_LOGIC;
signal Lxx0_carry_i_3_n_0 : STD_LOGIC;
signal Lxx0_carry_i_4_n_0 : STD_LOGIC;
signal Lxx0_carry_i_5_n_0 : STD_LOGIC;
signal Lxx0_carry_i_6_n_0 : STD_LOGIC;
signal Lxx0_carry_n_0 : STD_LOGIC;
signal Lxx0_carry_n_1 : STD_LOGIC;
signal Lxx0_carry_n_2 : STD_LOGIC;
signal Lxx0_carry_n_3 : STD_LOGIC;
signal Lxx_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxx_00 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_00__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_00__1_carry_n_3\ : STD_LOGIC;
signal Lxx_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lxx_11 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lxx_11__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_0\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_1\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_2\ : STD_LOGIC;
signal \Lxx_11__1_carry_n_3\ : STD_LOGIC;
signal \Lxx_2[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxx_2_reg_n_0_[9]\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__0_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__1_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry__2_n_7\ : STD_LOGIC;
signal \Lxy0__1_carry_i_10_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_0\ : STD_LOGIC;
signal \Lxy0__1_carry_n_1\ : STD_LOGIC;
signal \Lxy0__1_carry_n_2\ : STD_LOGIC;
signal \Lxy0__1_carry_n_3\ : STD_LOGIC;
signal \Lxy0__1_carry_n_4\ : STD_LOGIC;
signal \Lxy0__1_carry_n_5\ : STD_LOGIC;
signal \Lxy0__1_carry_n_6\ : STD_LOGIC;
signal \Lxy0__1_carry_n_7\ : STD_LOGIC;
signal \Lxy_0[15]_i_1_n_0\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_1 : STD_LOGIC;
signal \Lxy_1_reg_n_0_[0]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[10]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[11]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[12]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[13]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[14]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[15]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[1]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[2]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[3]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[4]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[5]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[6]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[7]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[8]\ : STD_LOGIC;
signal \Lxy_1_reg_n_0_[9]\ : STD_LOGIC;
signal Lxy_2 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lxy_3 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy0_carry__2_n_3\ : STD_LOGIC;
signal Lyy0_carry_i_1_n_0 : STD_LOGIC;
signal Lyy0_carry_i_2_n_0 : STD_LOGIC;
signal Lyy0_carry_i_3_n_0 : STD_LOGIC;
signal Lyy0_carry_i_4_n_0 : STD_LOGIC;
signal Lyy0_carry_i_5_n_0 : STD_LOGIC;
signal Lyy0_carry_i_6_n_0 : STD_LOGIC;
signal Lyy0_carry_n_0 : STD_LOGIC;
signal Lyy0_carry_n_1 : STD_LOGIC;
signal Lyy0_carry_n_2 : STD_LOGIC;
signal Lyy0_carry_n_3 : STD_LOGIC;
signal Lyy_0 : STD_LOGIC;
signal \Lyy_0_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_0_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_1 : STD_LOGIC_VECTOR ( 15 downto 1 );
signal Lyy_20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_20__1_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_0\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_1\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_2\ : STD_LOGIC;
signal \Lyy_20__1_carry_n_3\ : STD_LOGIC;
signal \Lyy_2[15]_i_1_n_0\ : STD_LOGIC;
signal Lyy_2_bottom_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_bottom_right01_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__0_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__1_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry__2_n_3\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_10_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_11_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_8_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_i_9_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_0\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_1\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_2\ : STD_LOGIC;
signal \Lyy_2_bottom_right0__0_carry_n_3\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[0]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[10]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[11]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[12]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[13]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[14]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[15]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[1]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[2]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[3]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[4]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[5]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[6]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[7]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[8]\ : STD_LOGIC;
signal \Lyy_2_reg_n_0_[9]\ : STD_LOGIC;
signal Lyy_2_top_left : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Lyy_2_top_right : STD_LOGIC_VECTOR ( 15 downto 0 );
signal addr_0 : STD_LOGIC;
signal \addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal bottom_left_0 : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \bottom_right_0[0]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[10]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[11]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[12]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[13]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[14]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_3_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_4_n_0\ : STD_LOGIC;
signal \bottom_right_0[15]_i_5_n_0\ : STD_LOGIC;
signal \bottom_right_0[1]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[2]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[3]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[4]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[5]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[6]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[7]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[8]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0[9]_i_2_n_0\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal bottom_right_1 : STD_LOGIC;
signal \bottom_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \bottom_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \cache[10]_5\ : STD_LOGIC;
signal \cache[9][15]_i_1_n_0\ : STD_LOGIC;
signal \cache_reg[0]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[10]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[3][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[3][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[4]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\ : STD_LOGIC;
signal \cache_reg[7][0]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][10]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][11]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][12]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][13]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][14]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][15]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][1]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][2]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][3]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][4]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][5]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][6]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][7]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][8]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[7][9]_U0_cache_reg_r_1_n_0\ : STD_LOGIC;
signal \cache_reg[8]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg[9]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \cache_reg_gate__0_n_0\ : STD_LOGIC;
signal \cache_reg_gate__10_n_0\ : STD_LOGIC;
signal \cache_reg_gate__11_n_0\ : STD_LOGIC;
signal \cache_reg_gate__12_n_0\ : STD_LOGIC;
signal \cache_reg_gate__13_n_0\ : STD_LOGIC;
signal \cache_reg_gate__14_n_0\ : STD_LOGIC;
signal \cache_reg_gate__15_n_0\ : STD_LOGIC;
signal \cache_reg_gate__16_n_0\ : STD_LOGIC;
signal \cache_reg_gate__17_n_0\ : STD_LOGIC;
signal \cache_reg_gate__18_n_0\ : STD_LOGIC;
signal \cache_reg_gate__19_n_0\ : STD_LOGIC;
signal \cache_reg_gate__1_n_0\ : STD_LOGIC;
signal \cache_reg_gate__20_n_0\ : STD_LOGIC;
signal \cache_reg_gate__21_n_0\ : STD_LOGIC;
signal \cache_reg_gate__22_n_0\ : STD_LOGIC;
signal \cache_reg_gate__23_n_0\ : STD_LOGIC;
signal \cache_reg_gate__24_n_0\ : STD_LOGIC;
signal \cache_reg_gate__25_n_0\ : STD_LOGIC;
signal \cache_reg_gate__26_n_0\ : STD_LOGIC;
signal \cache_reg_gate__27_n_0\ : STD_LOGIC;
signal \cache_reg_gate__28_n_0\ : STD_LOGIC;
signal \cache_reg_gate__29_n_0\ : STD_LOGIC;
signal \cache_reg_gate__2_n_0\ : STD_LOGIC;
signal \cache_reg_gate__30_n_0\ : STD_LOGIC;
signal \cache_reg_gate__3_n_0\ : STD_LOGIC;
signal \cache_reg_gate__4_n_0\ : STD_LOGIC;
signal \cache_reg_gate__5_n_0\ : STD_LOGIC;
signal \cache_reg_gate__6_n_0\ : STD_LOGIC;
signal \cache_reg_gate__7_n_0\ : STD_LOGIC;
signal \cache_reg_gate__8_n_0\ : STD_LOGIC;
signal \cache_reg_gate__9_n_0\ : STD_LOGIC;
signal cache_reg_gate_n_0 : STD_LOGIC;
signal cache_reg_r_0_n_0 : STD_LOGIC;
signal cache_reg_r_1_n_0 : STD_LOGIC;
signal cache_reg_r_n_0 : STD_LOGIC;
signal compute_addr_0 : STD_LOGIC;
signal \compute_addr_0[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[11]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_0[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_0[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0[9]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_0_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_1[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_1[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_1[9]_i_1_n_0\ : STD_LOGIC;
signal compute_addr_2 : STD_LOGIC;
signal \compute_addr_2[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_2[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_3_n_0\ : STD_LOGIC;
signal \compute_addr_2[13]_i_4_n_0\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[0]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[10]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[11]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[12]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[13]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[1]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[2]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[3]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[4]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[5]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[6]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[7]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[8]\ : STD_LOGIC;
signal \compute_addr_2_reg_n_0_[9]\ : STD_LOGIC;
signal compute_addr_3 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \compute_addr_3[0]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[10]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[11]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[12]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[13]_i_2_n_0\ : STD_LOGIC;
signal \compute_addr_3[1]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[2]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[3]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[4]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[5]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[6]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[7]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[8]_i_1_n_0\ : STD_LOGIC;
signal \compute_addr_3[9]_i_1_n_0\ : STD_LOGIC;
signal corner : STD_LOGIC;
signal \corner_reg_n_0_[0]\ : STD_LOGIC;
signal \corner_reg_n_0_[10]\ : STD_LOGIC;
signal \corner_reg_n_0_[11]\ : STD_LOGIC;
signal \corner_reg_n_0_[12]\ : STD_LOGIC;
signal \corner_reg_n_0_[13]\ : STD_LOGIC;
signal \corner_reg_n_0_[14]\ : STD_LOGIC;
signal \corner_reg_n_0_[15]\ : STD_LOGIC;
signal \corner_reg_n_0_[1]\ : STD_LOGIC;
signal \corner_reg_n_0_[2]\ : STD_LOGIC;
signal \corner_reg_n_0_[3]\ : STD_LOGIC;
signal \corner_reg_n_0_[4]\ : STD_LOGIC;
signal \corner_reg_n_0_[5]\ : STD_LOGIC;
signal \corner_reg_n_0_[6]\ : STD_LOGIC;
signal \corner_reg_n_0_[7]\ : STD_LOGIC;
signal \corner_reg_n_0_[8]\ : STD_LOGIC;
signal \corner_reg_n_0_[9]\ : STD_LOGIC;
signal cycle : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cycle[0]_i_1_n_0\ : STD_LOGIC;
signal \cycle[0]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_i_1_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1__0_n_0\ : STD_LOGIC;
signal \cycle[1]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_i_1_n_0\ : STD_LOGIC;
signal \cycle[2]_rep_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_1_n_0\ : STD_LOGIC;
signal \cycle[3]_i_2_n_0\ : STD_LOGIC;
signal \cycle_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cycle_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cycle_reg[2]_rep_n_0\ : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data2 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal data5 : STD_LOGIC_VECTOR ( 13 downto 10 );
signal det_0 : STD_LOGIC;
signal det_0_reg_i_2_n_0 : STD_LOGIC;
signal det_0_reg_n_106 : STD_LOGIC;
signal det_0_reg_n_107 : STD_LOGIC;
signal det_0_reg_n_108 : STD_LOGIC;
signal det_0_reg_n_109 : STD_LOGIC;
signal det_0_reg_n_110 : STD_LOGIC;
signal det_0_reg_n_111 : STD_LOGIC;
signal det_0_reg_n_112 : STD_LOGIC;
signal det_0_reg_n_113 : STD_LOGIC;
signal det_0_reg_n_114 : STD_LOGIC;
signal det_0_reg_n_115 : STD_LOGIC;
signal det_0_reg_n_116 : STD_LOGIC;
signal det_0_reg_n_117 : STD_LOGIC;
signal det_0_reg_n_118 : STD_LOGIC;
signal det_0_reg_n_119 : STD_LOGIC;
signal det_0_reg_n_120 : STD_LOGIC;
signal det_0_reg_n_121 : STD_LOGIC;
signal det_0_reg_n_122 : STD_LOGIC;
signal det_0_reg_n_123 : STD_LOGIC;
signal det_0_reg_n_124 : STD_LOGIC;
signal det_0_reg_n_125 : STD_LOGIC;
signal det_0_reg_n_126 : STD_LOGIC;
signal det_0_reg_n_127 : STD_LOGIC;
signal det_0_reg_n_128 : STD_LOGIC;
signal det_0_reg_n_129 : STD_LOGIC;
signal det_0_reg_n_130 : STD_LOGIC;
signal det_0_reg_n_131 : STD_LOGIC;
signal det_0_reg_n_132 : STD_LOGIC;
signal det_0_reg_n_133 : STD_LOGIC;
signal det_0_reg_n_134 : STD_LOGIC;
signal det_0_reg_n_135 : STD_LOGIC;
signal det_0_reg_n_136 : STD_LOGIC;
signal det_0_reg_n_137 : STD_LOGIC;
signal det_0_reg_n_138 : STD_LOGIC;
signal det_0_reg_n_139 : STD_LOGIC;
signal det_0_reg_n_140 : STD_LOGIC;
signal det_0_reg_n_141 : STD_LOGIC;
signal det_0_reg_n_142 : STD_LOGIC;
signal det_0_reg_n_143 : STD_LOGIC;
signal det_0_reg_n_144 : STD_LOGIC;
signal det_0_reg_n_145 : STD_LOGIC;
signal det_0_reg_n_146 : STD_LOGIC;
signal det_0_reg_n_147 : STD_LOGIC;
signal det_0_reg_n_148 : STD_LOGIC;
signal det_0_reg_n_149 : STD_LOGIC;
signal det_0_reg_n_150 : STD_LOGIC;
signal det_0_reg_n_151 : STD_LOGIC;
signal det_0_reg_n_152 : STD_LOGIC;
signal det_0_reg_n_153 : STD_LOGIC;
signal det_abs : STD_LOGIC_VECTOR ( 31 downto 0 );
signal det_abs0 : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \det_abs[10]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[11]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[12]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[13]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[14]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[15]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[16]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[17]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[18]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[19]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[1]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[20]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[21]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[22]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[23]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[24]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[25]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[26]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[27]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[28]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[29]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[2]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[30]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[31]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[3]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[4]_i_7_n_0\ : STD_LOGIC;
signal \det_abs[5]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[6]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[7]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_1_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_3_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_4_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_5_n_0\ : STD_LOGIC;
signal \det_abs[8]_i_6_n_0\ : STD_LOGIC;
signal \det_abs[9]_i_1_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[31]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \det_abs_reg[8]_i_2_n_3\ : STD_LOGIC;
signal det_reg_n_100 : STD_LOGIC;
signal det_reg_n_101 : STD_LOGIC;
signal det_reg_n_102 : STD_LOGIC;
signal det_reg_n_103 : STD_LOGIC;
signal det_reg_n_104 : STD_LOGIC;
signal det_reg_n_105 : STD_LOGIC;
signal det_reg_n_74 : STD_LOGIC;
signal det_reg_n_75 : STD_LOGIC;
signal det_reg_n_76 : STD_LOGIC;
signal det_reg_n_77 : STD_LOGIC;
signal det_reg_n_78 : STD_LOGIC;
signal det_reg_n_79 : STD_LOGIC;
signal det_reg_n_80 : STD_LOGIC;
signal det_reg_n_81 : STD_LOGIC;
signal det_reg_n_82 : STD_LOGIC;
signal det_reg_n_83 : STD_LOGIC;
signal det_reg_n_84 : STD_LOGIC;
signal det_reg_n_85 : STD_LOGIC;
signal det_reg_n_86 : STD_LOGIC;
signal det_reg_n_87 : STD_LOGIC;
signal det_reg_n_88 : STD_LOGIC;
signal det_reg_n_89 : STD_LOGIC;
signal det_reg_n_90 : STD_LOGIC;
signal det_reg_n_91 : STD_LOGIC;
signal det_reg_n_92 : STD_LOGIC;
signal det_reg_n_93 : STD_LOGIC;
signal det_reg_n_94 : STD_LOGIC;
signal det_reg_n_95 : STD_LOGIC;
signal det_reg_n_96 : STD_LOGIC;
signal det_reg_n_97 : STD_LOGIC;
signal det_reg_n_98 : STD_LOGIC;
signal det_reg_n_99 : STD_LOGIC;
signal \din_reg_n_0_[0]\ : STD_LOGIC;
signal \din_reg_n_0_[10]\ : STD_LOGIC;
signal \din_reg_n_0_[11]\ : STD_LOGIC;
signal \din_reg_n_0_[12]\ : STD_LOGIC;
signal \din_reg_n_0_[13]\ : STD_LOGIC;
signal \din_reg_n_0_[14]\ : STD_LOGIC;
signal \din_reg_n_0_[15]\ : STD_LOGIC;
signal \din_reg_n_0_[1]\ : STD_LOGIC;
signal \din_reg_n_0_[2]\ : STD_LOGIC;
signal \din_reg_n_0_[3]\ : STD_LOGIC;
signal \din_reg_n_0_[4]\ : STD_LOGIC;
signal \din_reg_n_0_[5]\ : STD_LOGIC;
signal \din_reg_n_0_[6]\ : STD_LOGIC;
signal \din_reg_n_0_[7]\ : STD_LOGIC;
signal \din_reg_n_0_[8]\ : STD_LOGIC;
signal \din_reg_n_0_[9]\ : STD_LOGIC;
signal dout_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal dout_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal last_value : STD_LOGIC_VECTOR ( 7 downto 0 );
signal left : STD_LOGIC;
signal \left[15]_i_2_n_0\ : STD_LOGIC;
signal \left[15]_i_3_n_0\ : STD_LOGIC;
signal \left_reg_n_0_[0]\ : STD_LOGIC;
signal \left_reg_n_0_[10]\ : STD_LOGIC;
signal \left_reg_n_0_[11]\ : STD_LOGIC;
signal \left_reg_n_0_[12]\ : STD_LOGIC;
signal \left_reg_n_0_[13]\ : STD_LOGIC;
signal \left_reg_n_0_[14]\ : STD_LOGIC;
signal \left_reg_n_0_[15]\ : STD_LOGIC;
signal \left_reg_n_0_[1]\ : STD_LOGIC;
signal \left_reg_n_0_[2]\ : STD_LOGIC;
signal \left_reg_n_0_[3]\ : STD_LOGIC;
signal \left_reg_n_0_[4]\ : STD_LOGIC;
signal \left_reg_n_0_[5]\ : STD_LOGIC;
signal \left_reg_n_0_[6]\ : STD_LOGIC;
signal \left_reg_n_0_[7]\ : STD_LOGIC;
signal \left_reg_n_0_[8]\ : STD_LOGIC;
signal \left_reg_n_0_[9]\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \plusOp_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__0_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry__1_n_7\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_4\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_5\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_6\ : STD_LOGIC;
signal \plusOp_inferred__0/i__carry_n_7\ : STD_LOGIC;
signal top : STD_LOGIC;
signal \top[15]_i_2_n_0\ : STD_LOGIC;
signal top_left_0 : STD_LOGIC;
signal \top_left_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_left_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_left_1 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \top_left_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_left_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_left_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_reg_n_0_[0]\ : STD_LOGIC;
signal \top_reg_n_0_[10]\ : STD_LOGIC;
signal \top_reg_n_0_[11]\ : STD_LOGIC;
signal \top_reg_n_0_[12]\ : STD_LOGIC;
signal \top_reg_n_0_[13]\ : STD_LOGIC;
signal \top_reg_n_0_[14]\ : STD_LOGIC;
signal \top_reg_n_0_[15]\ : STD_LOGIC;
signal \top_reg_n_0_[1]\ : STD_LOGIC;
signal \top_reg_n_0_[2]\ : STD_LOGIC;
signal \top_reg_n_0_[3]\ : STD_LOGIC;
signal \top_reg_n_0_[4]\ : STD_LOGIC;
signal \top_reg_n_0_[5]\ : STD_LOGIC;
signal \top_reg_n_0_[6]\ : STD_LOGIC;
signal \top_reg_n_0_[7]\ : STD_LOGIC;
signal \top_reg_n_0_[8]\ : STD_LOGIC;
signal \top_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_0 : STD_LOGIC;
signal \top_right_0[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_0[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_0_reg_n_0_[9]\ : STD_LOGIC;
signal top_right_1 : STD_LOGIC;
signal \top_right_1[0]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[10]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[11]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[12]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[13]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[14]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[15]_i_2_n_0\ : STD_LOGIC;
signal \top_right_1[1]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[2]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[3]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[4]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[5]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[6]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[7]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[8]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1[9]_i_1_n_0\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[0]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[10]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[11]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[12]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[13]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[14]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[15]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[1]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[2]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[3]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[4]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[5]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[6]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[7]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[8]\ : STD_LOGIC;
signal \top_right_1_reg_n_0_[9]\ : STD_LOGIC;
signal \value_reg_n_0_[0]\ : STD_LOGIC;
signal \value_reg_n_0_[1]\ : STD_LOGIC;
signal \value_reg_n_0_[2]\ : STD_LOGIC;
signal \value_reg_n_0_[3]\ : STD_LOGIC;
signal \value_reg_n_0_[4]\ : STD_LOGIC;
signal \value_reg_n_0_[5]\ : STD_LOGIC;
signal \value_reg_n_0_[6]\ : STD_LOGIC;
signal \value_reg_n_0_[7]\ : STD_LOGIC;
signal wen_i_1_n_0 : STD_LOGIC;
signal wen_i_2_n_0 : STD_LOGIC;
signal wen_reg_n_0 : STD_LOGIC;
signal x : STD_LOGIC;
signal \x0[0]_i_2_n_0\ : STD_LOGIC;
signal \x0[0]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_2_n_0\ : STD_LOGIC;
signal \x0[1]_i_3_n_0\ : STD_LOGIC;
signal \x0[1]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_1_n_0\ : STD_LOGIC;
signal \x0[2]_i_2_n_0\ : STD_LOGIC;
signal \x0[2]_i_3_n_0\ : STD_LOGIC;
signal \x0[2]_i_4_n_0\ : STD_LOGIC;
signal \x0[2]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_1_n_0\ : STD_LOGIC;
signal \x0[3]_i_2_n_0\ : STD_LOGIC;
signal \x0[3]_i_3_n_0\ : STD_LOGIC;
signal \x0[3]_i_4_n_0\ : STD_LOGIC;
signal \x0[3]_i_5_n_0\ : STD_LOGIC;
signal \x0[3]_i_6_n_0\ : STD_LOGIC;
signal \x0[4]_i_1_n_0\ : STD_LOGIC;
signal \x0[4]_i_2_n_0\ : STD_LOGIC;
signal \x0[4]_i_3_n_0\ : STD_LOGIC;
signal \x0[4]_i_4_n_0\ : STD_LOGIC;
signal \x0[4]_i_5_n_0\ : STD_LOGIC;
signal \x0[5]_i_1_n_0\ : STD_LOGIC;
signal \x0[5]_i_2_n_0\ : STD_LOGIC;
signal \x0[5]_i_3_n_0\ : STD_LOGIC;
signal \x0[5]_i_4_n_0\ : STD_LOGIC;
signal \x0[5]_i_5_n_0\ : STD_LOGIC;
signal \x0[6]_i_1_n_0\ : STD_LOGIC;
signal \x0[6]_i_2_n_0\ : STD_LOGIC;
signal \x0[6]_i_3_n_0\ : STD_LOGIC;
signal \x0[6]_i_4_n_0\ : STD_LOGIC;
signal \x0[6]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_1_n_0\ : STD_LOGIC;
signal \x0[7]_i_2_n_0\ : STD_LOGIC;
signal \x0[7]_i_3_n_0\ : STD_LOGIC;
signal \x0[7]_i_4_n_0\ : STD_LOGIC;
signal \x0[7]_i_5_n_0\ : STD_LOGIC;
signal \x0[7]_i_6_n_0\ : STD_LOGIC;
signal \x0[7]_i_7_n_0\ : STD_LOGIC;
signal \x0[8]_i_1_n_0\ : STD_LOGIC;
signal \x0[8]_i_2_n_0\ : STD_LOGIC;
signal \x0[8]_i_3_n_0\ : STD_LOGIC;
signal \x0[8]_i_4_n_0\ : STD_LOGIC;
signal \x0[8]_i_5_n_0\ : STD_LOGIC;
signal \x0[8]_i_6_n_0\ : STD_LOGIC;
signal \x0[8]_i_7_n_0\ : STD_LOGIC;
signal \x0[9]_i_1_n_0\ : STD_LOGIC;
signal \x0[9]_i_2_n_0\ : STD_LOGIC;
signal \x0[9]_i_3_n_0\ : STD_LOGIC;
signal \x0[9]_i_4_n_0\ : STD_LOGIC;
signal \x0[9]_i_5_n_0\ : STD_LOGIC;
signal \x0[9]_i_6_n_0\ : STD_LOGIC;
signal \x0[9]_i_7_n_0\ : STD_LOGIC;
signal \x0_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \x0_reg[1]_i_1_n_0\ : STD_LOGIC;
signal x1 : STD_LOGIC;
signal \x1[0]_i_1_n_0\ : STD_LOGIC;
signal \x1[1]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_1_n_0\ : STD_LOGIC;
signal \x1[2]_i_2_n_0\ : STD_LOGIC;
signal \x1[2]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_1_n_0\ : STD_LOGIC;
signal \x1[3]_i_2_n_0\ : STD_LOGIC;
signal \x1[3]_i_3_n_0\ : STD_LOGIC;
signal \x1[3]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_1_n_0\ : STD_LOGIC;
signal \x1[4]_i_2_n_0\ : STD_LOGIC;
signal \x1[4]_i_3_n_0\ : STD_LOGIC;
signal \x1[4]_i_4_n_0\ : STD_LOGIC;
signal \x1[4]_i_5_n_0\ : STD_LOGIC;
signal \x1[5]_i_1_n_0\ : STD_LOGIC;
signal \x1[5]_i_2_n_0\ : STD_LOGIC;
signal \x1[5]_i_3_n_0\ : STD_LOGIC;
signal \x1[5]_i_4_n_0\ : STD_LOGIC;
signal \x1[5]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_1_n_0\ : STD_LOGIC;
signal \x1[6]_i_2_n_0\ : STD_LOGIC;
signal \x1[6]_i_3_n_0\ : STD_LOGIC;
signal \x1[6]_i_4_n_0\ : STD_LOGIC;
signal \x1[6]_i_5_n_0\ : STD_LOGIC;
signal \x1[6]_i_6_n_0\ : STD_LOGIC;
signal \x1[6]_i_7_n_0\ : STD_LOGIC;
signal \x1[6]_i_8_n_0\ : STD_LOGIC;
signal \x1[7]_i_1_n_0\ : STD_LOGIC;
signal \x1[7]_i_2_n_0\ : STD_LOGIC;
signal \x1[7]_i_3_n_0\ : STD_LOGIC;
signal \x1[7]_i_4_n_0\ : STD_LOGIC;
signal \x1[7]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_1_n_0\ : STD_LOGIC;
signal \x1[8]_i_2_n_0\ : STD_LOGIC;
signal \x1[8]_i_3_n_0\ : STD_LOGIC;
signal \x1[8]_i_4_n_0\ : STD_LOGIC;
signal \x1[8]_i_5_n_0\ : STD_LOGIC;
signal \x1[8]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_2_n_0\ : STD_LOGIC;
signal \x1[9]_i_3_n_0\ : STD_LOGIC;
signal \x1[9]_i_4_n_0\ : STD_LOGIC;
signal \x1[9]_i_5_n_0\ : STD_LOGIC;
signal \x1[9]_i_6_n_0\ : STD_LOGIC;
signal \x1[9]_i_7_n_0\ : STD_LOGIC;
signal \x1[9]_i_8_n_0\ : STD_LOGIC;
signal \x_reg_n_0_[0]\ : STD_LOGIC;
signal \x_reg_n_0_[1]\ : STD_LOGIC;
signal \x_reg_n_0_[2]\ : STD_LOGIC;
signal \x_reg_n_0_[3]\ : STD_LOGIC;
signal \x_reg_n_0_[4]\ : STD_LOGIC;
signal \x_reg_n_0_[5]\ : STD_LOGIC;
signal \x_reg_n_0_[6]\ : STD_LOGIC;
signal \x_reg_n_0_[7]\ : STD_LOGIC;
signal \x_reg_n_0_[8]\ : STD_LOGIC;
signal \x_reg_n_0_[9]\ : STD_LOGIC;
signal y1 : STD_LOGIC;
signal \y1[2]_i_1_n_0\ : STD_LOGIC;
signal \y1[3]_i_1_n_0\ : STD_LOGIC;
signal \y1_reg_n_0_[0]\ : STD_LOGIC;
signal \y1_reg_n_0_[1]\ : STD_LOGIC;
signal \y1_reg_n_0_[2]\ : STD_LOGIC;
signal \y1_reg_n_0_[3]\ : STD_LOGIC;
signal y2 : STD_LOGIC;
signal \y2[1]_i_1_n_0\ : STD_LOGIC;
signal \y2[2]_i_1_n_0\ : STD_LOGIC;
signal \y2[3]_i_1_n_0\ : STD_LOGIC;
signal \y2_reg_n_0_[0]\ : STD_LOGIC;
signal \y2_reg_n_0_[1]\ : STD_LOGIC;
signal \y2_reg_n_0_[2]\ : STD_LOGIC;
signal \y2_reg_n_0_[3]\ : STD_LOGIC;
signal y3 : STD_LOGIC;
signal \y3[1]_i_1_n_0\ : STD_LOGIC;
signal \y3[2]_i_1_n_0\ : STD_LOGIC;
signal \y3[3]_i_1_n_0\ : STD_LOGIC;
signal \y3_reg_n_0_[0]\ : STD_LOGIC;
signal \y3_reg_n_0_[1]\ : STD_LOGIC;
signal \y3_reg_n_0_[2]\ : STD_LOGIC;
signal \y3_reg_n_0_[3]\ : STD_LOGIC;
signal \y4[2]_i_1_n_0\ : STD_LOGIC;
signal \y4[3]_i_1_n_0\ : STD_LOGIC;
signal y5 : STD_LOGIC;
signal \y5[0]_i_1_n_0\ : STD_LOGIC;
signal \y5[1]_i_1_n_0\ : STD_LOGIC;
signal \y5[2]_i_1_n_0\ : STD_LOGIC;
signal \y5[3]_i_1_n_0\ : STD_LOGIC;
signal y6 : STD_LOGIC;
signal \y6[2]_i_1_n_0\ : STD_LOGIC;
signal \y6[3]_i_1_n_0\ : STD_LOGIC;
signal \y6_reg_n_0_[0]\ : STD_LOGIC;
signal \y6_reg_n_0_[1]\ : STD_LOGIC;
signal \y6_reg_n_0_[2]\ : STD_LOGIC;
signal \y6_reg_n_0_[3]\ : STD_LOGIC;
signal y7 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y7[2]_i_1_n_0\ : STD_LOGIC;
signal \y7[3]_i_1_n_0\ : STD_LOGIC;
signal y8 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y8[3]_i_1_n_0\ : STD_LOGIC;
signal y9 : STD_LOGIC;
signal \y9[3]_i_1_n_0\ : STD_LOGIC;
signal \y_actual_reg_n_0_[0]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[1]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[2]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[3]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[4]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[5]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[6]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[7]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[8]\ : STD_LOGIC;
signal \y_actual_reg_n_0_[9]\ : STD_LOGIC;
signal \NLW_Lxx0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_0_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_0_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_0_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_0_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_det_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_det_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_det_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_det_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_det_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_det_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute HLUTNM : string;
attribute HLUTNM of \Lxx0_carry__0_i_1\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_2\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_3\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__0_i_4\ : label is "lutpair1";
attribute HLUTNM of \Lxx0_carry__0_i_5\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__0_i_6\ : label is "lutpair4";
attribute HLUTNM of \Lxx0_carry__0_i_7\ : label is "lutpair3";
attribute HLUTNM of \Lxx0_carry__0_i_8\ : label is "lutpair2";
attribute HLUTNM of \Lxx0_carry__1_i_1\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_2\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_3\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__1_i_4\ : label is "lutpair5";
attribute HLUTNM of \Lxx0_carry__1_i_5\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__1_i_6\ : label is "lutpair8";
attribute HLUTNM of \Lxx0_carry__1_i_7\ : label is "lutpair7";
attribute HLUTNM of \Lxx0_carry__1_i_8\ : label is "lutpair6";
attribute HLUTNM of \Lxx0_carry__2_i_1\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_2\ : label is "lutpair10";
attribute HLUTNM of \Lxx0_carry__2_i_3\ : label is "lutpair9";
attribute HLUTNM of \Lxx0_carry__2_i_6\ : label is "lutpair11";
attribute HLUTNM of \Lxx0_carry__2_i_7\ : label is "lutpair10";
attribute HLUTNM of Lxx0_carry_i_1 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_2 : label is "lutpair24";
attribute HLUTNM of Lxx0_carry_i_3 : label is "lutpair1";
attribute HLUTNM of Lxx0_carry_i_4 : label is "lutpair0";
attribute HLUTNM of Lxx0_carry_i_5 : label is "lutpair24";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_10\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_00__1_carry__2_i_8\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_10\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxx_11__1_carry__2_i_8\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_10\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \Lxy0__1_carry__2_i_8\ : label is "soft_lutpair32";
attribute HLUTNM of \Lyy0_carry__0_i_1\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_2\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_3\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__0_i_4\ : label is "lutpair13";
attribute HLUTNM of \Lyy0_carry__0_i_5\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__0_i_6\ : label is "lutpair16";
attribute HLUTNM of \Lyy0_carry__0_i_7\ : label is "lutpair15";
attribute HLUTNM of \Lyy0_carry__0_i_8\ : label is "lutpair14";
attribute HLUTNM of \Lyy0_carry__1_i_1\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_2\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_3\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__1_i_4\ : label is "lutpair17";
attribute HLUTNM of \Lyy0_carry__1_i_5\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__1_i_6\ : label is "lutpair20";
attribute HLUTNM of \Lyy0_carry__1_i_7\ : label is "lutpair19";
attribute HLUTNM of \Lyy0_carry__1_i_8\ : label is "lutpair18";
attribute HLUTNM of \Lyy0_carry__2_i_1\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_2\ : label is "lutpair22";
attribute HLUTNM of \Lyy0_carry__2_i_3\ : label is "lutpair21";
attribute HLUTNM of \Lyy0_carry__2_i_6\ : label is "lutpair23";
attribute HLUTNM of \Lyy0_carry__2_i_7\ : label is "lutpair22";
attribute HLUTNM of Lyy0_carry_i_1 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_2 : label is "lutpair25";
attribute HLUTNM of Lyy0_carry_i_3 : label is "lutpair13";
attribute HLUTNM of Lyy0_carry_i_4 : label is "lutpair12";
attribute HLUTNM of Lyy0_carry_i_5 : label is "lutpair25";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_10\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_11\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__0_i_9\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_10\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__1_i_9\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_10\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry__2_i_8\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \Lyy_20__1_carry_i_8\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_11\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \Lyy_2_bottom_right0__0_carry__2_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \addr_0[0]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[10]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[11]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[12]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[13]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_0[2]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \addr_0[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \addr_0[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \addr_0[5]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \addr_0[6]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \addr_0[7]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[8]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \addr_0[9]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \addr_1[0]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \addr_1[10]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[11]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[12]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \addr_1[13]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \addr_1[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[2]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[3]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[4]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \addr_1[5]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[6]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \addr_1[7]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \addr_1[8]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \addr_1[9]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \bottom_right_0[0]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bottom_right_0[14]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bottom_right_0[15]_i_5\ : label is "soft_lutpair12";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_0 : label is "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_0 : label is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_0 : label is "blk_mem_gen_v8_3_5,Vivado 2016.4";
attribute srl_bus_name : string;
attribute srl_bus_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name : string;
attribute srl_name of \cache_reg[2][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2] ";
attribute srl_name of \cache_reg[2][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][0]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][10]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][11]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][12]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][13]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][14]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][15]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][1]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][2]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][3]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][4]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][5]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][6]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][7]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][8]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 ";
attribute srl_bus_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6] ";
attribute srl_name of \cache_reg[6][9]_srl2___U0_cache_reg_r_0\ : label is "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 ";
attribute SOFT_HLUTNM of cache_reg_gate : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__10\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \cache_reg_gate__11\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__12\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \cache_reg_gate__13\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__14\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \cache_reg_gate__15\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__16\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \cache_reg_gate__17\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__18\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \cache_reg_gate__19\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__20\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \cache_reg_gate__21\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__22\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \cache_reg_gate__23\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__24\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \cache_reg_gate__25\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__26\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \cache_reg_gate__27\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__28\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \cache_reg_gate__29\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__3\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__30\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \cache_reg_gate__4\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \cache_reg_gate__5\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \cache_reg_gate__6\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cache_reg_gate__7\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \cache_reg_gate__8\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \cache_reg_gate__9\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \compute_addr_0[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \compute_addr_2[10]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[11]_i_2\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \compute_addr_2[12]_i_2\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \compute_addr_2[13]_i_4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \compute_addr_3[10]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[11]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \compute_addr_3[12]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \compute_addr_3[13]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \cycle[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \cycle[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \cycle[3]_i_2\ : label is "soft_lutpair15";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cycle_reg[0]\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[0]_rep\ : label is "cycle_reg[0]";
attribute ORIG_CELL_NAME of \cycle_reg[1]\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[1]_rep__0\ : label is "cycle_reg[1]";
attribute ORIG_CELL_NAME of \cycle_reg[2]\ : label is "cycle_reg[2]";
attribute ORIG_CELL_NAME of \cycle_reg[2]_rep\ : label is "cycle_reg[2]";
attribute SOFT_HLUTNM of \det_abs[10]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[11]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[12]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[13]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[14]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[15]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \det_abs[16]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \det_abs[17]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \det_abs[18]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \det_abs[19]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \det_abs[1]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[21]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[22]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[24]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[25]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \det_abs[26]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[27]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \det_abs[28]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \det_abs[30]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \det_abs[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \det_abs[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \det_abs[5]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \det_abs[6]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \det_abs[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \det_abs[8]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \det_abs[9]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \left[15]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \left[15]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x0[1]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x0[2]_i_4\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[2]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x0[3]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \x0[3]_i_5\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \x0[4]_i_4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[4]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[5]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x0[5]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \x0[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[7]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x0[7]_i_6\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \x0[8]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x0[8]_i_5\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x0[8]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x0[8]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x0[9]_i_6\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x1[3]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \x1[4]_i_5\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[5]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[5]_i_5\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \x1[6]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x1[6]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \x1[6]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \x1[6]_i_8\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \x1[7]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \x1[7]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \x1[8]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \x1[9]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x1[9]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \y1[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \y1[3]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y2[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y2[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y3[1]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y3[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y3[3]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y4[2]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y4[3]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \y5[0]_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \y5[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y5[2]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y5[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \y6[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y6[3]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \y7[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \y7[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \y9[3]_i_1\ : label is "soft_lutpair20";
begin
Lxx0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lxx0_carry_n_0,
CO(2) => Lxx0_carry_n_1,
CO(1) => Lxx0_carry_n_2,
CO(0) => Lxx0_carry_n_3,
CYINIT => '0',
DI(3) => Lxx0_carry_i_1_n_0,
DI(2) => Lxx0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lxx_2_reg_n_0_[0]\,
O(3 downto 0) => A(3 downto 0),
S(3) => Lxx0_carry_i_3_n_0,
S(2) => Lxx0_carry_i_4_n_0,
S(1) => Lxx0_carry_i_5_n_0,
S(0) => Lxx0_carry_i_6_n_0
);
\Lxx0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lxx0_carry_n_0,
CO(3) => \Lxx0_carry__0_n_0\,
CO(2) => \Lxx0_carry__0_n_1\,
CO(1) => \Lxx0_carry__0_n_2\,
CO(0) => \Lxx0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__0_i_1_n_0\,
DI(2) => \Lxx0_carry__0_i_2_n_0\,
DI(1) => \Lxx0_carry__0_i_3_n_0\,
DI(0) => \Lxx0_carry__0_i_4_n_0\,
O(3 downto 0) => A(7 downto 4),
S(3) => \Lxx0_carry__0_i_5_n_0\,
S(2) => \Lxx0_carry__0_i_6_n_0\,
S(1) => \Lxx0_carry__0_i_7_n_0\,
S(0) => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
O => \Lxx0_carry__0_i_1_n_0\
);
\Lxx0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
O => \Lxx0_carry__0_i_2_n_0\
);
\Lxx0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
O => \Lxx0_carry__0_i_3_n_0\
);
\Lxx0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
O => \Lxx0_carry__0_i_4_n_0\
);
\Lxx0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
I3 => \Lxx0_carry__0_i_1_n_0\,
O => \Lxx0_carry__0_i_5_n_0\
);
\Lxx0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(6),
I1 => \Lxx_2_reg_n_0_[6]\,
I2 => Lxx_0(6),
I3 => \Lxx0_carry__0_i_2_n_0\,
O => \Lxx0_carry__0_i_6_n_0\
);
\Lxx0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(5),
I1 => \Lxx_2_reg_n_0_[5]\,
I2 => Lxx_0(5),
I3 => \Lxx0_carry__0_i_3_n_0\,
O => \Lxx0_carry__0_i_7_n_0\
);
\Lxx0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(4),
I1 => \Lxx_2_reg_n_0_[4]\,
I2 => Lxx_0(4),
I3 => \Lxx0_carry__0_i_4_n_0\,
O => \Lxx0_carry__0_i_8_n_0\
);
\Lxx0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__0_n_0\,
CO(3) => \Lxx0_carry__1_n_0\,
CO(2) => \Lxx0_carry__1_n_1\,
CO(1) => \Lxx0_carry__1_n_2\,
CO(0) => \Lxx0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx0_carry__1_i_1_n_0\,
DI(2) => \Lxx0_carry__1_i_2_n_0\,
DI(1) => \Lxx0_carry__1_i_3_n_0\,
DI(0) => \Lxx0_carry__1_i_4_n_0\,
O(3 downto 0) => A(11 downto 8),
S(3) => \Lxx0_carry__1_i_5_n_0\,
S(2) => \Lxx0_carry__1_i_6_n_0\,
S(1) => \Lxx0_carry__1_i_7_n_0\,
S(0) => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
O => \Lxx0_carry__1_i_1_n_0\
);
\Lxx0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
O => \Lxx0_carry__1_i_2_n_0\
);
\Lxx0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
O => \Lxx0_carry__1_i_3_n_0\
);
\Lxx0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(7),
I1 => \Lxx_2_reg_n_0_[7]\,
I2 => Lxx_0(7),
O => \Lxx0_carry__1_i_4_n_0\
);
\Lxx0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
I3 => \Lxx0_carry__1_i_1_n_0\,
O => \Lxx0_carry__1_i_5_n_0\
);
\Lxx0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(10),
I1 => \Lxx_2_reg_n_0_[10]\,
I2 => Lxx_0(10),
I3 => \Lxx0_carry__1_i_2_n_0\,
O => \Lxx0_carry__1_i_6_n_0\
);
\Lxx0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(9),
I1 => \Lxx_2_reg_n_0_[9]\,
I2 => Lxx_0(9),
I3 => \Lxx0_carry__1_i_3_n_0\,
O => \Lxx0_carry__1_i_7_n_0\
);
\Lxx0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(8),
I1 => \Lxx_2_reg_n_0_[8]\,
I2 => Lxx_0(8),
I3 => \Lxx0_carry__1_i_4_n_0\,
O => \Lxx0_carry__1_i_8_n_0\
);
\Lxx0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx0_carry__1_n_0\,
CO(3) => \NLW_Lxx0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx0_carry__2_n_1\,
CO(1) => \Lxx0_carry__2_n_2\,
CO(0) => \Lxx0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx0_carry__2_i_1_n_0\,
DI(1) => \Lxx0_carry__2_i_2_n_0\,
DI(0) => \Lxx0_carry__2_i_3_n_0\,
O(3 downto 0) => A(15 downto 12),
S(3) => \Lxx0_carry__2_i_4_n_0\,
S(2) => \Lxx0_carry__2_i_5_n_0\,
S(1) => \Lxx0_carry__2_i_6_n_0\,
S(0) => \Lxx0_carry__2_i_7_n_0\
);
\Lxx0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
O => \Lxx0_carry__2_i_1_n_0\
);
\Lxx0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
O => \Lxx0_carry__2_i_2_n_0\
);
\Lxx0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(11),
I1 => \Lxx_2_reg_n_0_[11]\,
I2 => Lxx_0(11),
O => \Lxx0_carry__2_i_3_n_0\
);
\Lxx0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => Lxx_0(14),
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => \Lxx_2_reg_n_0_[15]\,
I4 => Lxx_1(15),
I5 => Lxx_0(15),
O => \Lxx0_carry__2_i_4_n_0\
);
\Lxx0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxx0_carry__2_i_1_n_0\,
I1 => \Lxx_2_reg_n_0_[14]\,
I2 => Lxx_1(14),
I3 => Lxx_0(14),
O => \Lxx0_carry__2_i_5_n_0\
);
\Lxx0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(13),
I1 => \Lxx_2_reg_n_0_[13]\,
I2 => Lxx_0(13),
I3 => \Lxx0_carry__2_i_2_n_0\,
O => \Lxx0_carry__2_i_6_n_0\
);
\Lxx0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(12),
I1 => \Lxx_2_reg_n_0_[12]\,
I2 => Lxx_0(12),
I3 => \Lxx0_carry__2_i_3_n_0\,
O => \Lxx0_carry__2_i_7_n_0\
);
Lxx0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
O => Lxx0_carry_i_1_n_0
);
Lxx0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_2_n_0
);
Lxx0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(3),
I1 => \Lxx_2_reg_n_0_[3]\,
I2 => Lxx_0(3),
I3 => Lxx0_carry_i_1_n_0,
O => Lxx0_carry_i_3_n_0
);
Lxx0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lxx_1(2),
I1 => \Lxx_2_reg_n_0_[2]\,
I2 => Lxx_0(2),
I3 => Lxx0_carry_i_2_n_0,
O => Lxx0_carry_i_4_n_0
);
Lxx0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxx_1(1),
I1 => \Lxx_2_reg_n_0_[1]\,
I2 => Lxx_0(1),
O => Lxx0_carry_i_5_n_0
);
Lxx0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lxx_2_reg_n_0_[0]\,
I1 => Lxx_0(0),
O => Lxx0_carry_i_6_n_0
);
\Lxx_00__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_00__1_carry_n_0\,
CO(2) => \Lxx_00__1_carry_n_1\,
CO(1) => \Lxx_00__1_carry_n_2\,
CO(0) => \Lxx_00__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry_i_1_n_0\,
DI(2) => \Lxx_00__1_carry_i_2_n_0\,
DI(1) => \Lxx_00__1_carry_i_3_n_0\,
DI(0) => \bottom_right_0_reg_n_0_[0]\,
O(3 downto 0) => Lxx_00(3 downto 0),
S(3) => \Lxx_00__1_carry_i_4_n_0\,
S(2) => \Lxx_00__1_carry_i_5_n_0\,
S(1) => \Lxx_00__1_carry_i_6_n_0\,
S(0) => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry_n_0\,
CO(3) => \Lxx_00__1_carry__0_n_0\,
CO(2) => \Lxx_00__1_carry__0_n_1\,
CO(1) => \Lxx_00__1_carry__0_n_2\,
CO(0) => \Lxx_00__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_00(7 downto 4),
S(3) => \Lxx_00__1_carry__0_i_5_n_0\,
S(2) => \Lxx_00__1_carry__0_i_6_n_0\,
S(1) => \Lxx_00__1_carry__0_i_7_n_0\,
S(0) => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[6]\,
I1 => \Lxx_00__1_carry__0_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[5]\,
I3 => \top_right_0_reg_n_0_[5]\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_1_n_0\
);
\Lxx_00__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[5]\,
I1 => \top_right_0_reg_n_0_[5]\,
I2 => \top_left_0_reg_n_0_[5]\,
O => \Lxx_00__1_carry__0_i_10_n_0\
);
\Lxx_00__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[4]\,
I1 => \top_right_0_reg_n_0_[4]\,
I2 => \top_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_11_n_0\
);
\Lxx_00__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[7]\,
I1 => \top_right_0_reg_n_0_[7]\,
I2 => \top_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__0_i_12_n_0\
);
\Lxx_00__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[5]\,
I1 => \Lxx_00__1_carry__0_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[4]\,
I3 => \top_right_0_reg_n_0_[4]\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \Lxx_00__1_carry__0_i_2_n_0\
);
\Lxx_00__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[4]\,
I1 => \Lxx_00__1_carry__0_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[3]\,
I3 => \top_right_0_reg_n_0_[3]\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry__0_i_3_n_0\
);
\Lxx_00__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[3]\,
I1 => \Lxx_00__1_carry_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[2]\,
I3 => \top_right_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry__0_i_4_n_0\
);
\Lxx_00__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[6]\,
I2 => \top_right_0_reg_n_0_[6]\,
I3 => \bottom_left_0_reg_n_0_[6]\,
I4 => \bottom_right_0_reg_n_0_[7]\,
I5 => \Lxx_00__1_carry__0_i_12_n_0\,
O => \Lxx_00__1_carry__0_i_5_n_0\
);
\Lxx_00__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[5]\,
I2 => \top_right_0_reg_n_0_[5]\,
I3 => \bottom_left_0_reg_n_0_[5]\,
I4 => \bottom_right_0_reg_n_0_[6]\,
I5 => \Lxx_00__1_carry__0_i_9_n_0\,
O => \Lxx_00__1_carry__0_i_6_n_0\
);
\Lxx_00__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[4]\,
I2 => \top_right_0_reg_n_0_[4]\,
I3 => \bottom_left_0_reg_n_0_[4]\,
I4 => \bottom_right_0_reg_n_0_[5]\,
I5 => \Lxx_00__1_carry__0_i_10_n_0\,
O => \Lxx_00__1_carry__0_i_7_n_0\
);
\Lxx_00__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__0_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[3]\,
I2 => \top_right_0_reg_n_0_[3]\,
I3 => \bottom_left_0_reg_n_0_[3]\,
I4 => \bottom_right_0_reg_n_0_[4]\,
I5 => \Lxx_00__1_carry__0_i_11_n_0\,
O => \Lxx_00__1_carry__0_i_8_n_0\
);
\Lxx_00__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[6]\,
I1 => \top_right_0_reg_n_0_[6]\,
I2 => \top_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__0_i_9_n_0\
);
\Lxx_00__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__0_n_0\,
CO(3) => \Lxx_00__1_carry__1_n_0\,
CO(2) => \Lxx_00__1_carry__1_n_1\,
CO(1) => \Lxx_00__1_carry__1_n_2\,
CO(0) => \Lxx_00__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_00__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_00__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_00__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_00__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_00(11 downto 8),
S(3) => \Lxx_00__1_carry__1_i_5_n_0\,
S(2) => \Lxx_00__1_carry__1_i_6_n_0\,
S(1) => \Lxx_00__1_carry__1_i_7_n_0\,
S(0) => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[10]\,
I1 => \Lxx_00__1_carry__1_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[9]\,
I3 => \top_right_0_reg_n_0_[9]\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_1_n_0\
);
\Lxx_00__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[9]\,
I1 => \top_right_0_reg_n_0_[9]\,
I2 => \top_left_0_reg_n_0_[9]\,
O => \Lxx_00__1_carry__1_i_10_n_0\
);
\Lxx_00__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[8]\,
I1 => \top_right_0_reg_n_0_[8]\,
I2 => \top_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_11_n_0\
);
\Lxx_00__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[11]\,
I1 => \top_right_0_reg_n_0_[11]\,
I2 => \top_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__1_i_12_n_0\
);
\Lxx_00__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[9]\,
I1 => \Lxx_00__1_carry__1_i_10_n_0\,
I2 => \top_left_0_reg_n_0_[8]\,
I3 => \top_right_0_reg_n_0_[8]\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \Lxx_00__1_carry__1_i_2_n_0\
);
\Lxx_00__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[8]\,
I1 => \Lxx_00__1_carry__1_i_11_n_0\,
I2 => \top_left_0_reg_n_0_[7]\,
I3 => \top_right_0_reg_n_0_[7]\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \Lxx_00__1_carry__1_i_3_n_0\
);
\Lxx_00__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[7]\,
I1 => \Lxx_00__1_carry__0_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[6]\,
I3 => \top_right_0_reg_n_0_[6]\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \Lxx_00__1_carry__1_i_4_n_0\
);
\Lxx_00__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[10]\,
I2 => \top_right_0_reg_n_0_[10]\,
I3 => \bottom_left_0_reg_n_0_[10]\,
I4 => \bottom_right_0_reg_n_0_[11]\,
I5 => \Lxx_00__1_carry__1_i_12_n_0\,
O => \Lxx_00__1_carry__1_i_5_n_0\
);
\Lxx_00__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[9]\,
I2 => \top_right_0_reg_n_0_[9]\,
I3 => \bottom_left_0_reg_n_0_[9]\,
I4 => \bottom_right_0_reg_n_0_[10]\,
I5 => \Lxx_00__1_carry__1_i_9_n_0\,
O => \Lxx_00__1_carry__1_i_6_n_0\
);
\Lxx_00__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[8]\,
I2 => \top_right_0_reg_n_0_[8]\,
I3 => \bottom_left_0_reg_n_0_[8]\,
I4 => \bottom_right_0_reg_n_0_[9]\,
I5 => \Lxx_00__1_carry__1_i_10_n_0\,
O => \Lxx_00__1_carry__1_i_7_n_0\
);
\Lxx_00__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__1_i_4_n_0\,
I1 => \top_left_0_reg_n_0_[7]\,
I2 => \top_right_0_reg_n_0_[7]\,
I3 => \bottom_left_0_reg_n_0_[7]\,
I4 => \bottom_right_0_reg_n_0_[8]\,
I5 => \Lxx_00__1_carry__1_i_11_n_0\,
O => \Lxx_00__1_carry__1_i_8_n_0\
);
\Lxx_00__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[10]\,
I1 => \top_right_0_reg_n_0_[10]\,
I2 => \top_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__1_i_9_n_0\
);
\Lxx_00__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_00__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_00__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_00__1_carry__2_n_1\,
CO(1) => \Lxx_00__1_carry__2_n_2\,
CO(0) => \Lxx_00__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_00__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_00__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_00__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_00(15 downto 12),
S(3) => \Lxx_00__1_carry__2_i_4_n_0\,
S(2) => \Lxx_00__1_carry__2_i_5_n_0\,
S(1) => \Lxx_00__1_carry__2_i_6_n_0\,
S(0) => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[13]\,
I1 => \Lxx_00__1_carry__2_i_8_n_0\,
I2 => \top_left_0_reg_n_0_[12]\,
I3 => \top_right_0_reg_n_0_[12]\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_1_n_0\
);
\Lxx_00__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => \top_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \bottom_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_10_n_0\
);
\Lxx_00__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_0_reg_n_0_[15]\,
I1 => \bottom_left_0_reg_n_0_[15]\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \top_left_0_reg_n_0_[15]\,
O => \Lxx_00__1_carry__2_i_11_n_0\
);
\Lxx_00__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[14]\,
I1 => \top_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
O => \Lxx_00__1_carry__2_i_12_n_0\
);
\Lxx_00__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[12]\,
I1 => \Lxx_00__1_carry__2_i_9_n_0\,
I2 => \top_left_0_reg_n_0_[11]\,
I3 => \top_right_0_reg_n_0_[11]\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \Lxx_00__1_carry__2_i_2_n_0\
);
\Lxx_00__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[11]\,
I1 => \Lxx_00__1_carry__1_i_12_n_0\,
I2 => \top_left_0_reg_n_0_[10]\,
I3 => \top_right_0_reg_n_0_[10]\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \Lxx_00__1_carry__2_i_3_n_0\
);
\Lxx_00__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_00__1_carry__2_i_10_n_0\,
I1 => \bottom_right_0_reg_n_0_[14]\,
I2 => \top_left_0_reg_n_0_[14]\,
I3 => \top_right_0_reg_n_0_[14]\,
I4 => \bottom_left_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_11_n_0\,
O => \Lxx_00__1_carry__2_i_4_n_0\
);
\Lxx_00__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[13]\,
I2 => \top_right_0_reg_n_0_[13]\,
I3 => \bottom_left_0_reg_n_0_[13]\,
I4 => \bottom_right_0_reg_n_0_[14]\,
I5 => \Lxx_00__1_carry__2_i_12_n_0\,
O => \Lxx_00__1_carry__2_i_5_n_0\
);
\Lxx_00__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_2_n_0\,
I1 => \top_left_0_reg_n_0_[12]\,
I2 => \top_right_0_reg_n_0_[12]\,
I3 => \bottom_left_0_reg_n_0_[12]\,
I4 => \bottom_right_0_reg_n_0_[13]\,
I5 => \Lxx_00__1_carry__2_i_8_n_0\,
O => \Lxx_00__1_carry__2_i_6_n_0\
);
\Lxx_00__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry__2_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[11]\,
I2 => \top_right_0_reg_n_0_[11]\,
I3 => \bottom_left_0_reg_n_0_[11]\,
I4 => \bottom_right_0_reg_n_0_[12]\,
I5 => \Lxx_00__1_carry__2_i_9_n_0\,
O => \Lxx_00__1_carry__2_i_7_n_0\
);
\Lxx_00__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[13]\,
I1 => \top_right_0_reg_n_0_[13]\,
I2 => \top_left_0_reg_n_0_[13]\,
O => \Lxx_00__1_carry__2_i_8_n_0\
);
\Lxx_00__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[12]\,
I1 => \top_right_0_reg_n_0_[12]\,
I2 => \top_left_0_reg_n_0_[12]\,
O => \Lxx_00__1_carry__2_i_9_n_0\
);
\Lxx_00__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_0_reg_n_0_[2]\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_left_0_reg_n_0_[1]\,
I5 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_1_n_0\
);
\Lxx_00__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => \bottom_left_0_reg_n_0_[1]\,
I1 => \top_right_0_reg_n_0_[1]\,
I2 => \top_left_0_reg_n_0_[1]\,
I3 => \bottom_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_2_n_0\
);
\Lxx_00__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_0_reg_n_0_[1]\,
I1 => \bottom_left_0_reg_n_0_[1]\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \top_left_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_3_n_0\
);
\Lxx_00__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_00__1_carry_i_1_n_0\,
I1 => \top_left_0_reg_n_0_[2]\,
I2 => \top_right_0_reg_n_0_[2]\,
I3 => \bottom_left_0_reg_n_0_[2]\,
I4 => \bottom_right_0_reg_n_0_[3]\,
I5 => \Lxx_00__1_carry_i_8_n_0\,
O => \Lxx_00__1_carry_i_4_n_0\
);
\Lxx_00__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_00__1_carry_i_2_n_0\,
I1 => \bottom_right_0_reg_n_0_[2]\,
I2 => \Lxx_00__1_carry_i_9_n_0\,
I3 => \bottom_left_0_reg_n_0_[1]\,
I4 => \top_right_0_reg_n_0_[1]\,
O => \Lxx_00__1_carry_i_5_n_0\
);
\Lxx_00__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_00__1_carry_i_3_n_0\,
I1 => \top_left_0_reg_n_0_[0]\,
I2 => \top_right_0_reg_n_0_[0]\,
I3 => \bottom_left_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_6_n_0\
);
\Lxx_00__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \bottom_left_0_reg_n_0_[0]\,
I1 => \top_right_0_reg_n_0_[0]\,
I2 => \top_left_0_reg_n_0_[0]\,
I3 => \bottom_right_0_reg_n_0_[0]\,
O => \Lxx_00__1_carry_i_7_n_0\
);
\Lxx_00__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[3]\,
I1 => \top_right_0_reg_n_0_[3]\,
I2 => \top_left_0_reg_n_0_[3]\,
O => \Lxx_00__1_carry_i_8_n_0\
);
\Lxx_00__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \bottom_left_0_reg_n_0_[2]\,
I1 => \top_right_0_reg_n_0_[2]\,
I2 => \top_left_0_reg_n_0_[2]\,
O => \Lxx_00__1_carry_i_9_n_0\
);
\Lxx_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(0),
Q => Lxx_0(0),
R => '0'
);
\Lxx_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(10),
Q => Lxx_0(10),
R => '0'
);
\Lxx_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(11),
Q => Lxx_0(11),
R => '0'
);
\Lxx_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(12),
Q => Lxx_0(12),
R => '0'
);
\Lxx_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(13),
Q => Lxx_0(13),
R => '0'
);
\Lxx_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(14),
Q => Lxx_0(14),
R => '0'
);
\Lxx_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(15),
Q => Lxx_0(15),
R => '0'
);
\Lxx_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(1),
Q => Lxx_0(1),
R => '0'
);
\Lxx_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(2),
Q => Lxx_0(2),
R => '0'
);
\Lxx_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(3),
Q => Lxx_0(3),
R => '0'
);
\Lxx_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(4),
Q => Lxx_0(4),
R => '0'
);
\Lxx_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(5),
Q => Lxx_0(5),
R => '0'
);
\Lxx_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(6),
Q => Lxx_0(6),
R => '0'
);
\Lxx_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(7),
Q => Lxx_0(7),
R => '0'
);
\Lxx_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(8),
Q => Lxx_0(8),
R => '0'
);
\Lxx_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => Lxx_00(9),
Q => Lxx_0(9),
R => '0'
);
\Lxx_11__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxx_11__1_carry_n_0\,
CO(2) => \Lxx_11__1_carry_n_1\,
CO(1) => \Lxx_11__1_carry_n_2\,
CO(0) => \Lxx_11__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry_i_1_n_0\,
DI(2) => \Lxx_11__1_carry_i_2_n_0\,
DI(1) => \Lxx_11__1_carry_i_3_n_0\,
DI(0) => \bottom_right_1_reg_n_0_[0]\,
O(3 downto 0) => Lxx_11(3 downto 0),
S(3) => \Lxx_11__1_carry_i_4_n_0\,
S(2) => \Lxx_11__1_carry_i_5_n_0\,
S(1) => \Lxx_11__1_carry_i_6_n_0\,
S(0) => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry_n_0\,
CO(3) => \Lxx_11__1_carry__0_n_0\,
CO(2) => \Lxx_11__1_carry__0_n_1\,
CO(1) => \Lxx_11__1_carry__0_n_2\,
CO(0) => \Lxx_11__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__0_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__0_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__0_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lxx_11(7 downto 4),
S(3) => \Lxx_11__1_carry__0_i_5_n_0\,
S(2) => \Lxx_11__1_carry__0_i_6_n_0\,
S(1) => \Lxx_11__1_carry__0_i_7_n_0\,
S(0) => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[6]\,
I1 => \Lxx_11__1_carry__0_i_9_n_0\,
I2 => top_left_1(5),
I3 => \top_right_1_reg_n_0_[5]\,
I4 => bottom_left_1(5),
O => \Lxx_11__1_carry__0_i_1_n_0\
);
\Lxx_11__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(5),
I1 => \top_right_1_reg_n_0_[5]\,
I2 => top_left_1(5),
O => \Lxx_11__1_carry__0_i_10_n_0\
);
\Lxx_11__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(4),
I1 => \top_right_1_reg_n_0_[4]\,
I2 => top_left_1(4),
O => \Lxx_11__1_carry__0_i_11_n_0\
);
\Lxx_11__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(7),
I1 => \top_right_1_reg_n_0_[7]\,
I2 => top_left_1(7),
O => \Lxx_11__1_carry__0_i_12_n_0\
);
\Lxx_11__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[5]\,
I1 => \Lxx_11__1_carry__0_i_10_n_0\,
I2 => top_left_1(4),
I3 => \top_right_1_reg_n_0_[4]\,
I4 => bottom_left_1(4),
O => \Lxx_11__1_carry__0_i_2_n_0\
);
\Lxx_11__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[4]\,
I1 => \Lxx_11__1_carry__0_i_11_n_0\,
I2 => top_left_1(3),
I3 => \top_right_1_reg_n_0_[3]\,
I4 => bottom_left_1(3),
O => \Lxx_11__1_carry__0_i_3_n_0\
);
\Lxx_11__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[3]\,
I1 => \Lxx_11__1_carry_i_8_n_0\,
I2 => top_left_1(2),
I3 => \top_right_1_reg_n_0_[2]\,
I4 => bottom_left_1(2),
O => \Lxx_11__1_carry__0_i_4_n_0\
);
\Lxx_11__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_1_n_0\,
I1 => top_left_1(6),
I2 => \top_right_1_reg_n_0_[6]\,
I3 => bottom_left_1(6),
I4 => \bottom_right_1_reg_n_0_[7]\,
I5 => \Lxx_11__1_carry__0_i_12_n_0\,
O => \Lxx_11__1_carry__0_i_5_n_0\
);
\Lxx_11__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_2_n_0\,
I1 => top_left_1(5),
I2 => \top_right_1_reg_n_0_[5]\,
I3 => bottom_left_1(5),
I4 => \bottom_right_1_reg_n_0_[6]\,
I5 => \Lxx_11__1_carry__0_i_9_n_0\,
O => \Lxx_11__1_carry__0_i_6_n_0\
);
\Lxx_11__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_3_n_0\,
I1 => top_left_1(4),
I2 => \top_right_1_reg_n_0_[4]\,
I3 => bottom_left_1(4),
I4 => \bottom_right_1_reg_n_0_[5]\,
I5 => \Lxx_11__1_carry__0_i_10_n_0\,
O => \Lxx_11__1_carry__0_i_7_n_0\
);
\Lxx_11__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__0_i_4_n_0\,
I1 => top_left_1(3),
I2 => \top_right_1_reg_n_0_[3]\,
I3 => bottom_left_1(3),
I4 => \bottom_right_1_reg_n_0_[4]\,
I5 => \Lxx_11__1_carry__0_i_11_n_0\,
O => \Lxx_11__1_carry__0_i_8_n_0\
);
\Lxx_11__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(6),
I1 => \top_right_1_reg_n_0_[6]\,
I2 => top_left_1(6),
O => \Lxx_11__1_carry__0_i_9_n_0\
);
\Lxx_11__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__0_n_0\,
CO(3) => \Lxx_11__1_carry__1_n_0\,
CO(2) => \Lxx_11__1_carry__1_n_1\,
CO(1) => \Lxx_11__1_carry__1_n_2\,
CO(0) => \Lxx_11__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxx_11__1_carry__1_i_1_n_0\,
DI(2) => \Lxx_11__1_carry__1_i_2_n_0\,
DI(1) => \Lxx_11__1_carry__1_i_3_n_0\,
DI(0) => \Lxx_11__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lxx_11(11 downto 8),
S(3) => \Lxx_11__1_carry__1_i_5_n_0\,
S(2) => \Lxx_11__1_carry__1_i_6_n_0\,
S(1) => \Lxx_11__1_carry__1_i_7_n_0\,
S(0) => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[10]\,
I1 => \Lxx_11__1_carry__1_i_9_n_0\,
I2 => top_left_1(9),
I3 => \top_right_1_reg_n_0_[9]\,
I4 => bottom_left_1(9),
O => \Lxx_11__1_carry__1_i_1_n_0\
);
\Lxx_11__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(9),
I1 => \top_right_1_reg_n_0_[9]\,
I2 => top_left_1(9),
O => \Lxx_11__1_carry__1_i_10_n_0\
);
\Lxx_11__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(8),
I1 => \top_right_1_reg_n_0_[8]\,
I2 => top_left_1(8),
O => \Lxx_11__1_carry__1_i_11_n_0\
);
\Lxx_11__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(11),
I1 => \top_right_1_reg_n_0_[11]\,
I2 => top_left_1(11),
O => \Lxx_11__1_carry__1_i_12_n_0\
);
\Lxx_11__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[9]\,
I1 => \Lxx_11__1_carry__1_i_10_n_0\,
I2 => top_left_1(8),
I3 => \top_right_1_reg_n_0_[8]\,
I4 => bottom_left_1(8),
O => \Lxx_11__1_carry__1_i_2_n_0\
);
\Lxx_11__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[8]\,
I1 => \Lxx_11__1_carry__1_i_11_n_0\,
I2 => top_left_1(7),
I3 => \top_right_1_reg_n_0_[7]\,
I4 => bottom_left_1(7),
O => \Lxx_11__1_carry__1_i_3_n_0\
);
\Lxx_11__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[7]\,
I1 => \Lxx_11__1_carry__0_i_12_n_0\,
I2 => top_left_1(6),
I3 => \top_right_1_reg_n_0_[6]\,
I4 => bottom_left_1(6),
O => \Lxx_11__1_carry__1_i_4_n_0\
);
\Lxx_11__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_1_n_0\,
I1 => top_left_1(10),
I2 => \top_right_1_reg_n_0_[10]\,
I3 => bottom_left_1(10),
I4 => \bottom_right_1_reg_n_0_[11]\,
I5 => \Lxx_11__1_carry__1_i_12_n_0\,
O => \Lxx_11__1_carry__1_i_5_n_0\
);
\Lxx_11__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_2_n_0\,
I1 => top_left_1(9),
I2 => \top_right_1_reg_n_0_[9]\,
I3 => bottom_left_1(9),
I4 => \bottom_right_1_reg_n_0_[10]\,
I5 => \Lxx_11__1_carry__1_i_9_n_0\,
O => \Lxx_11__1_carry__1_i_6_n_0\
);
\Lxx_11__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_3_n_0\,
I1 => top_left_1(8),
I2 => \top_right_1_reg_n_0_[8]\,
I3 => bottom_left_1(8),
I4 => \bottom_right_1_reg_n_0_[9]\,
I5 => \Lxx_11__1_carry__1_i_10_n_0\,
O => \Lxx_11__1_carry__1_i_7_n_0\
);
\Lxx_11__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__1_i_4_n_0\,
I1 => top_left_1(7),
I2 => \top_right_1_reg_n_0_[7]\,
I3 => bottom_left_1(7),
I4 => \bottom_right_1_reg_n_0_[8]\,
I5 => \Lxx_11__1_carry__1_i_11_n_0\,
O => \Lxx_11__1_carry__1_i_8_n_0\
);
\Lxx_11__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(10),
I1 => \top_right_1_reg_n_0_[10]\,
I2 => top_left_1(10),
O => \Lxx_11__1_carry__1_i_9_n_0\
);
\Lxx_11__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxx_11__1_carry__1_n_0\,
CO(3) => \NLW_Lxx_11__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxx_11__1_carry__2_n_1\,
CO(1) => \Lxx_11__1_carry__2_n_2\,
CO(0) => \Lxx_11__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxx_11__1_carry__2_i_1_n_0\,
DI(1) => \Lxx_11__1_carry__2_i_2_n_0\,
DI(0) => \Lxx_11__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lxx_11(15 downto 12),
S(3) => \Lxx_11__1_carry__2_i_4_n_0\,
S(2) => \Lxx_11__1_carry__2_i_5_n_0\,
S(1) => \Lxx_11__1_carry__2_i_6_n_0\,
S(0) => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[13]\,
I1 => \Lxx_11__1_carry__2_i_8_n_0\,
I2 => top_left_1(12),
I3 => \top_right_1_reg_n_0_[12]\,
I4 => bottom_left_1(12),
O => \Lxx_11__1_carry__2_i_1_n_0\
);
\Lxx_11__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => top_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => bottom_left_1(13),
O => \Lxx_11__1_carry__2_i_10_n_0\
);
\Lxx_11__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \top_right_1_reg_n_0_[15]\,
I1 => bottom_left_1(15),
I2 => \bottom_right_1_reg_n_0_[15]\,
I3 => top_left_1(15),
O => \Lxx_11__1_carry__2_i_11_n_0\
);
\Lxx_11__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(14),
I1 => \top_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
O => \Lxx_11__1_carry__2_i_12_n_0\
);
\Lxx_11__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[12]\,
I1 => \Lxx_11__1_carry__2_i_9_n_0\,
I2 => top_left_1(11),
I3 => \top_right_1_reg_n_0_[11]\,
I4 => bottom_left_1(11),
O => \Lxx_11__1_carry__2_i_2_n_0\
);
\Lxx_11__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"88E8E8EE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[11]\,
I1 => \Lxx_11__1_carry__1_i_12_n_0\,
I2 => top_left_1(10),
I3 => \top_right_1_reg_n_0_[10]\,
I4 => bottom_left_1(10),
O => \Lxx_11__1_carry__2_i_3_n_0\
);
\Lxx_11__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"178181E8E87E7E17"
)
port map (
I0 => \Lxx_11__1_carry__2_i_10_n_0\,
I1 => \bottom_right_1_reg_n_0_[14]\,
I2 => top_left_1(14),
I3 => \top_right_1_reg_n_0_[14]\,
I4 => bottom_left_1(14),
I5 => \Lxx_11__1_carry__2_i_11_n_0\,
O => \Lxx_11__1_carry__2_i_4_n_0\
);
\Lxx_11__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_1_n_0\,
I1 => top_left_1(13),
I2 => \top_right_1_reg_n_0_[13]\,
I3 => bottom_left_1(13),
I4 => \bottom_right_1_reg_n_0_[14]\,
I5 => \Lxx_11__1_carry__2_i_12_n_0\,
O => \Lxx_11__1_carry__2_i_5_n_0\
);
\Lxx_11__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_2_n_0\,
I1 => top_left_1(12),
I2 => \top_right_1_reg_n_0_[12]\,
I3 => bottom_left_1(12),
I4 => \bottom_right_1_reg_n_0_[13]\,
I5 => \Lxx_11__1_carry__2_i_8_n_0\,
O => \Lxx_11__1_carry__2_i_6_n_0\
);
\Lxx_11__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry__2_i_3_n_0\,
I1 => top_left_1(11),
I2 => \top_right_1_reg_n_0_[11]\,
I3 => bottom_left_1(11),
I4 => \bottom_right_1_reg_n_0_[12]\,
I5 => \Lxx_11__1_carry__2_i_9_n_0\,
O => \Lxx_11__1_carry__2_i_7_n_0\
);
\Lxx_11__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(13),
I1 => \top_right_1_reg_n_0_[13]\,
I2 => top_left_1(13),
O => \Lxx_11__1_carry__2_i_8_n_0\
);
\Lxx_11__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(12),
I1 => \top_right_1_reg_n_0_[12]\,
I2 => top_left_1(12),
O => \Lxx_11__1_carry__2_i_9_n_0\
);
\Lxx_11__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228EBBEEBBEEBBE"
)
port map (
I0 => \bottom_right_1_reg_n_0_[2]\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => bottom_left_1(1),
I5 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_1_n_0\
);
\Lxx_11__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => bottom_left_1(1),
I1 => \top_right_1_reg_n_0_[1]\,
I2 => top_left_1(1),
I3 => \bottom_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_2_n_0\
);
\Lxx_11__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \top_right_1_reg_n_0_[1]\,
I1 => bottom_left_1(1),
I2 => \bottom_right_1_reg_n_0_[1]\,
I3 => top_left_1(1),
O => \Lxx_11__1_carry_i_3_n_0\
);
\Lxx_11__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A665599A599AA665"
)
port map (
I0 => \Lxx_11__1_carry_i_1_n_0\,
I1 => top_left_1(2),
I2 => \top_right_1_reg_n_0_[2]\,
I3 => bottom_left_1(2),
I4 => \bottom_right_1_reg_n_0_[3]\,
I5 => \Lxx_11__1_carry_i_8_n_0\,
O => \Lxx_11__1_carry_i_4_n_0\
);
\Lxx_11__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \Lxx_11__1_carry_i_2_n_0\,
I1 => \bottom_right_1_reg_n_0_[2]\,
I2 => \Lxx_11__1_carry_i_9_n_0\,
I3 => bottom_left_1(1),
I4 => \top_right_1_reg_n_0_[1]\,
O => \Lxx_11__1_carry_i_5_n_0\
);
\Lxx_11__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"A665"
)
port map (
I0 => \Lxx_11__1_carry_i_3_n_0\,
I1 => top_left_1(0),
I2 => \top_right_1_reg_n_0_[0]\,
I3 => bottom_left_1(0),
O => \Lxx_11__1_carry_i_6_n_0\
);
\Lxx_11__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => bottom_left_1(0),
I1 => \top_right_1_reg_n_0_[0]\,
I2 => top_left_1(0),
I3 => \bottom_right_1_reg_n_0_[0]\,
O => \Lxx_11__1_carry_i_7_n_0\
);
\Lxx_11__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(3),
I1 => \top_right_1_reg_n_0_[3]\,
I2 => top_left_1(3),
O => \Lxx_11__1_carry_i_8_n_0\
);
\Lxx_11__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => bottom_left_1(2),
I1 => \top_right_1_reg_n_0_[2]\,
I2 => top_left_1(2),
O => \Lxx_11__1_carry_i_9_n_0\
);
\Lxx_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(9),
Q => Lxx_1(10),
R => '0'
);
\Lxx_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(10),
Q => Lxx_1(11),
R => '0'
);
\Lxx_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(11),
Q => Lxx_1(12),
R => '0'
);
\Lxx_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(12),
Q => Lxx_1(13),
R => '0'
);
\Lxx_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(13),
Q => Lxx_1(14),
R => '0'
);
\Lxx_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(14),
Q => Lxx_1(15),
R => '0'
);
\Lxx_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(0),
Q => Lxx_1(1),
R => '0'
);
\Lxx_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(1),
Q => Lxx_1(2),
R => '0'
);
\Lxx_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(2),
Q => Lxx_1(3),
R => '0'
);
\Lxx_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(3),
Q => Lxx_1(4),
R => '0'
);
\Lxx_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(4),
Q => Lxx_1(5),
R => '0'
);
\Lxx_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(5),
Q => Lxx_1(6),
R => '0'
);
\Lxx_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(6),
Q => Lxx_1(7),
R => '0'
);
\Lxx_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(7),
Q => Lxx_1(8),
R => '0'
);
\Lxx_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lxx_11(8),
Q => Lxx_1(9),
R => '0'
);
\Lxx_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => cycle(2),
I4 => rst,
I5 => active,
O => \Lxx_2[15]_i_1_n_0\
);
\Lxx_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxx_2_reg_n_0_[0]\,
R => '0'
);
\Lxx_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxx_2_reg_n_0_[10]\,
R => '0'
);
\Lxx_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxx_2_reg_n_0_[11]\,
R => '0'
);
\Lxx_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxx_2_reg_n_0_[12]\,
R => '0'
);
\Lxx_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxx_2_reg_n_0_[13]\,
R => '0'
);
\Lxx_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxx_2_reg_n_0_[14]\,
R => '0'
);
\Lxx_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxx_2_reg_n_0_[15]\,
R => '0'
);
\Lxx_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxx_2_reg_n_0_[1]\,
R => '0'
);
\Lxx_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxx_2_reg_n_0_[2]\,
R => '0'
);
\Lxx_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxx_2_reg_n_0_[3]\,
R => '0'
);
\Lxx_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxx_2_reg_n_0_[4]\,
R => '0'
);
\Lxx_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxx_2_reg_n_0_[5]\,
R => '0'
);
\Lxx_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxx_2_reg_n_0_[6]\,
R => '0'
);
\Lxx_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxx_2_reg_n_0_[7]\,
R => '0'
);
\Lxx_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxx_2_reg_n_0_[8]\,
R => '0'
);
\Lxx_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxx_2[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxx_2_reg_n_0_[9]\,
R => '0'
);
\Lxy0__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lxy0__1_carry_n_0\,
CO(2) => \Lxy0__1_carry_n_1\,
CO(1) => \Lxy0__1_carry_n_2\,
CO(0) => \Lxy0__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry_i_1_n_0\,
DI(2) => \Lxy0__1_carry_i_2_n_0\,
DI(1) => \Lxy0__1_carry_i_3_n_0\,
DI(0) => \Lxy_0_reg_n_0_[0]\,
O(3) => \Lxy0__1_carry_n_4\,
O(2) => \Lxy0__1_carry_n_5\,
O(1) => \Lxy0__1_carry_n_6\,
O(0) => \Lxy0__1_carry_n_7\,
S(3) => \Lxy0__1_carry_i_4_n_0\,
S(2) => \Lxy0__1_carry_i_5_n_0\,
S(1) => \Lxy0__1_carry_i_6_n_0\,
S(0) => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry_n_0\,
CO(3) => \Lxy0__1_carry__0_n_0\,
CO(2) => \Lxy0__1_carry__0_n_1\,
CO(1) => \Lxy0__1_carry__0_n_2\,
CO(0) => \Lxy0__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__0_i_1_n_0\,
DI(2) => \Lxy0__1_carry__0_i_2_n_0\,
DI(1) => \Lxy0__1_carry__0_i_3_n_0\,
DI(0) => \Lxy0__1_carry__0_i_4_n_0\,
O(3) => \Lxy0__1_carry__0_n_4\,
O(2) => \Lxy0__1_carry__0_n_5\,
O(1) => \Lxy0__1_carry__0_n_6\,
O(0) => \Lxy0__1_carry__0_n_7\,
S(3) => \Lxy0__1_carry__0_i_5_n_0\,
S(2) => \Lxy0__1_carry__0_i_6_n_0\,
S(1) => \Lxy0__1_carry__0_i_7_n_0\,
S(0) => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[6]\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => Lxy_3(5),
I3 => Lxy_2(5),
I4 => \Lxy_1_reg_n_0_[5]\,
O => \Lxy0__1_carry__0_i_1_n_0\
);
\Lxy0__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(5),
I1 => \Lxy_1_reg_n_0_[5]\,
I2 => Lxy_2(5),
O => \Lxy0__1_carry__0_i_10_n_0\
);
\Lxy0__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(4),
I1 => \Lxy_1_reg_n_0_[4]\,
I2 => Lxy_2(4),
O => \Lxy0__1_carry__0_i_11_n_0\
);
\Lxy0__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(7),
I1 => \Lxy_1_reg_n_0_[7]\,
I2 => Lxy_2(7),
O => \Lxy0__1_carry__0_i_12_n_0\
);
\Lxy0__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[5]\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => Lxy_3(4),
I3 => Lxy_2(4),
I4 => \Lxy_1_reg_n_0_[4]\,
O => \Lxy0__1_carry__0_i_2_n_0\
);
\Lxy0__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[4]\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => Lxy_3(3),
I3 => Lxy_2(3),
I4 => \Lxy_1_reg_n_0_[3]\,
O => \Lxy0__1_carry__0_i_3_n_0\
);
\Lxy0__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[3]\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => Lxy_3(2),
I3 => Lxy_2(2),
I4 => \Lxy_1_reg_n_0_[2]\,
O => \Lxy0__1_carry__0_i_4_n_0\
);
\Lxy0__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_1_n_0\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[7]\,
I3 => \Lxy_1_reg_n_0_[6]\,
I4 => Lxy_2(6),
I5 => Lxy_3(6),
O => \Lxy0__1_carry__0_i_5_n_0\
);
\Lxy0__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_2_n_0\,
I1 => \Lxy0__1_carry__0_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[6]\,
I3 => \Lxy_1_reg_n_0_[5]\,
I4 => Lxy_2(5),
I5 => Lxy_3(5),
O => \Lxy0__1_carry__0_i_6_n_0\
);
\Lxy0__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_3_n_0\,
I1 => \Lxy0__1_carry__0_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[5]\,
I3 => \Lxy_1_reg_n_0_[4]\,
I4 => Lxy_2(4),
I5 => Lxy_3(4),
O => \Lxy0__1_carry__0_i_7_n_0\
);
\Lxy0__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__0_i_4_n_0\,
I1 => \Lxy0__1_carry__0_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[4]\,
I3 => \Lxy_1_reg_n_0_[3]\,
I4 => Lxy_2(3),
I5 => Lxy_3(3),
O => \Lxy0__1_carry__0_i_8_n_0\
);
\Lxy0__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(6),
I1 => \Lxy_1_reg_n_0_[6]\,
I2 => Lxy_2(6),
O => \Lxy0__1_carry__0_i_9_n_0\
);
\Lxy0__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__0_n_0\,
CO(3) => \Lxy0__1_carry__1_n_0\,
CO(2) => \Lxy0__1_carry__1_n_1\,
CO(1) => \Lxy0__1_carry__1_n_2\,
CO(0) => \Lxy0__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lxy0__1_carry__1_i_1_n_0\,
DI(2) => \Lxy0__1_carry__1_i_2_n_0\,
DI(1) => \Lxy0__1_carry__1_i_3_n_0\,
DI(0) => \Lxy0__1_carry__1_i_4_n_0\,
O(3) => \Lxy0__1_carry__1_n_4\,
O(2) => \Lxy0__1_carry__1_n_5\,
O(1) => \Lxy0__1_carry__1_n_6\,
O(0) => \Lxy0__1_carry__1_n_7\,
S(3) => \Lxy0__1_carry__1_i_5_n_0\,
S(2) => \Lxy0__1_carry__1_i_6_n_0\,
S(1) => \Lxy0__1_carry__1_i_7_n_0\,
S(0) => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[10]\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => Lxy_3(9),
I3 => Lxy_2(9),
I4 => \Lxy_1_reg_n_0_[9]\,
O => \Lxy0__1_carry__1_i_1_n_0\
);
\Lxy0__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(9),
I1 => \Lxy_1_reg_n_0_[9]\,
I2 => Lxy_2(9),
O => \Lxy0__1_carry__1_i_10_n_0\
);
\Lxy0__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(8),
I1 => \Lxy_1_reg_n_0_[8]\,
I2 => Lxy_2(8),
O => \Lxy0__1_carry__1_i_11_n_0\
);
\Lxy0__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(11),
I1 => \Lxy_1_reg_n_0_[11]\,
I2 => Lxy_2(11),
O => \Lxy0__1_carry__1_i_12_n_0\
);
\Lxy0__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[9]\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => Lxy_3(8),
I3 => Lxy_2(8),
I4 => \Lxy_1_reg_n_0_[8]\,
O => \Lxy0__1_carry__1_i_2_n_0\
);
\Lxy0__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[8]\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => Lxy_3(7),
I3 => Lxy_2(7),
I4 => \Lxy_1_reg_n_0_[7]\,
O => \Lxy0__1_carry__1_i_3_n_0\
);
\Lxy0__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[7]\,
I1 => \Lxy0__1_carry__0_i_12_n_0\,
I2 => Lxy_3(6),
I3 => Lxy_2(6),
I4 => \Lxy_1_reg_n_0_[6]\,
O => \Lxy0__1_carry__1_i_4_n_0\
);
\Lxy0__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_1_n_0\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[11]\,
I3 => \Lxy_1_reg_n_0_[10]\,
I4 => Lxy_2(10),
I5 => Lxy_3(10),
O => \Lxy0__1_carry__1_i_5_n_0\
);
\Lxy0__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_2_n_0\,
I1 => \Lxy0__1_carry__1_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[10]\,
I3 => \Lxy_1_reg_n_0_[9]\,
I4 => Lxy_2(9),
I5 => Lxy_3(9),
O => \Lxy0__1_carry__1_i_6_n_0\
);
\Lxy0__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_3_n_0\,
I1 => \Lxy0__1_carry__1_i_10_n_0\,
I2 => \Lxy_0_reg_n_0_[9]\,
I3 => \Lxy_1_reg_n_0_[8]\,
I4 => Lxy_2(8),
I5 => Lxy_3(8),
O => \Lxy0__1_carry__1_i_7_n_0\
);
\Lxy0__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__1_i_4_n_0\,
I1 => \Lxy0__1_carry__1_i_11_n_0\,
I2 => \Lxy_0_reg_n_0_[8]\,
I3 => \Lxy_1_reg_n_0_[7]\,
I4 => Lxy_2(7),
I5 => Lxy_3(7),
O => \Lxy0__1_carry__1_i_8_n_0\
);
\Lxy0__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(10),
I1 => \Lxy_1_reg_n_0_[10]\,
I2 => Lxy_2(10),
O => \Lxy0__1_carry__1_i_9_n_0\
);
\Lxy0__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lxy0__1_carry__1_n_0\,
CO(3) => \NLW_Lxy0__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lxy0__1_carry__2_n_1\,
CO(1) => \Lxy0__1_carry__2_n_2\,
CO(0) => \Lxy0__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lxy0__1_carry__2_i_1_n_0\,
DI(1) => \Lxy0__1_carry__2_i_2_n_0\,
DI(0) => \Lxy0__1_carry__2_i_3_n_0\,
O(3) => \Lxy0__1_carry__2_n_4\,
O(2) => \Lxy0__1_carry__2_n_5\,
O(1) => \Lxy0__1_carry__2_n_6\,
O(0) => \Lxy0__1_carry__2_n_7\,
S(3) => \Lxy0__1_carry__2_i_4_n_0\,
S(2) => \Lxy0__1_carry__2_i_5_n_0\,
S(1) => \Lxy0__1_carry__2_i_6_n_0\,
S(0) => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[13]\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => Lxy_3(12),
I3 => Lxy_2(12),
I4 => \Lxy_1_reg_n_0_[12]\,
O => \Lxy0__1_carry__2_i_1_n_0\
);
\Lxy0__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => \Lxy_1_reg_n_0_[13]\,
I1 => Lxy_2(13),
I2 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_10_n_0\
);
\Lxy0__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(15),
I1 => \Lxy_1_reg_n_0_[15]\,
I2 => Lxy_3(15),
I3 => \Lxy_0_reg_n_0_[15]\,
O => \Lxy0__1_carry__2_i_11_n_0\
);
\Lxy0__1_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(14),
I1 => \Lxy_1_reg_n_0_[14]\,
I2 => Lxy_2(14),
O => \Lxy0__1_carry__2_i_12_n_0\
);
\Lxy0__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[12]\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => Lxy_3(11),
I3 => Lxy_2(11),
I4 => \Lxy_1_reg_n_0_[11]\,
O => \Lxy0__1_carry__2_i_2_n_0\
);
\Lxy0__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8E88EE8E"
)
port map (
I0 => \Lxy_0_reg_n_0_[11]\,
I1 => \Lxy0__1_carry__1_i_12_n_0\,
I2 => Lxy_3(10),
I3 => Lxy_2(10),
I4 => \Lxy_1_reg_n_0_[10]\,
O => \Lxy0__1_carry__2_i_3_n_0\
);
\Lxy0__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E87781E87E11E87"
)
port map (
I0 => \Lxy0__1_carry__2_i_10_n_0\,
I1 => \Lxy_0_reg_n_0_[14]\,
I2 => \Lxy0__1_carry__2_i_11_n_0\,
I3 => \Lxy_1_reg_n_0_[14]\,
I4 => Lxy_2(14),
I5 => Lxy_3(14),
O => \Lxy0__1_carry__2_i_4_n_0\
);
\Lxy0__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_1_n_0\,
I1 => \Lxy0__1_carry__2_i_12_n_0\,
I2 => \Lxy_0_reg_n_0_[14]\,
I3 => \Lxy_1_reg_n_0_[13]\,
I4 => Lxy_2(13),
I5 => Lxy_3(13),
O => \Lxy0__1_carry__2_i_5_n_0\
);
\Lxy0__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_2_n_0\,
I1 => \Lxy0__1_carry__2_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[13]\,
I3 => \Lxy_1_reg_n_0_[12]\,
I4 => Lxy_2(12),
I5 => Lxy_3(12),
O => \Lxy0__1_carry__2_i_6_n_0\
);
\Lxy0__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry__2_i_3_n_0\,
I1 => \Lxy0__1_carry__2_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[12]\,
I3 => \Lxy_1_reg_n_0_[11]\,
I4 => Lxy_2(11),
I5 => Lxy_3(11),
O => \Lxy0__1_carry__2_i_7_n_0\
);
\Lxy0__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(13),
I1 => \Lxy_1_reg_n_0_[13]\,
I2 => Lxy_2(13),
O => \Lxy0__1_carry__2_i_8_n_0\
);
\Lxy0__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(12),
I1 => \Lxy_1_reg_n_0_[12]\,
I2 => Lxy_2(12),
O => \Lxy0__1_carry__2_i_9_n_0\
);
\Lxy0__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBEEBBE8228EBBE"
)
port map (
I0 => \Lxy_0_reg_n_0_[2]\,
I1 => Lxy_2(2),
I2 => \Lxy_1_reg_n_0_[2]\,
I3 => Lxy_3(2),
I4 => \Lxy_1_reg_n_0_[1]\,
I5 => Lxy_2(1),
O => \Lxy0__1_carry_i_1_n_0\
);
\Lxy0__1_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => Lxy_2(1),
I1 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_10_n_0\
);
\Lxy0__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4DD4"
)
port map (
I0 => Lxy_3(1),
I1 => \Lxy_0_reg_n_0_[1]\,
I2 => \Lxy_1_reg_n_0_[1]\,
I3 => Lxy_2(1),
O => \Lxy0__1_carry_i_2_n_0\
);
\Lxy0__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lxy_1_reg_n_0_[1]\,
I1 => Lxy_2(1),
I2 => Lxy_3(1),
I3 => \Lxy_0_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_3_n_0\
);
\Lxy0__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy0__1_carry_i_1_n_0\,
I1 => \Lxy0__1_carry_i_8_n_0\,
I2 => \Lxy_0_reg_n_0_[3]\,
I3 => \Lxy_1_reg_n_0_[2]\,
I4 => Lxy_2(2),
I5 => Lxy_3(2),
O => \Lxy0__1_carry_i_4_n_0\
);
\Lxy0__1_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"69966969"
)
port map (
I0 => \Lxy0__1_carry_i_2_n_0\,
I1 => \Lxy0__1_carry_i_9_n_0\,
I2 => \Lxy_0_reg_n_0_[2]\,
I3 => Lxy_2(1),
I4 => \Lxy_1_reg_n_0_[1]\,
O => \Lxy0__1_carry_i_5_n_0\
);
\Lxy0__1_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lxy_0_reg_n_0_[1]\,
I1 => Lxy_3(1),
I2 => \Lxy0__1_carry_i_10_n_0\,
I3 => Lxy_3(0),
I4 => Lxy_2(0),
I5 => \Lxy_1_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_6_n_0\
);
\Lxy0__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lxy_2(0),
I1 => \Lxy_1_reg_n_0_[0]\,
I2 => Lxy_3(0),
I3 => \Lxy_0_reg_n_0_[0]\,
O => \Lxy0__1_carry_i_7_n_0\
);
\Lxy0__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(3),
I1 => \Lxy_1_reg_n_0_[3]\,
I2 => Lxy_2(3),
O => \Lxy0__1_carry_i_8_n_0\
);
\Lxy0__1_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lxy_3(2),
I1 => \Lxy_1_reg_n_0_[2]\,
I2 => Lxy_2(2),
O => \Lxy0__1_carry_i_9_n_0\
);
\Lxy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => \Lxy_0[15]_i_1_n_0\
);
\Lxy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(0),
Q => \Lxy_0_reg_n_0_[0]\,
R => '0'
);
\Lxy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(10),
Q => \Lxy_0_reg_n_0_[10]\,
R => '0'
);
\Lxy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(11),
Q => \Lxy_0_reg_n_0_[11]\,
R => '0'
);
\Lxy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(12),
Q => \Lxy_0_reg_n_0_[12]\,
R => '0'
);
\Lxy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(13),
Q => \Lxy_0_reg_n_0_[13]\,
R => '0'
);
\Lxy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(14),
Q => \Lxy_0_reg_n_0_[14]\,
R => '0'
);
\Lxy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(15),
Q => \Lxy_0_reg_n_0_[15]\,
R => '0'
);
\Lxy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(1),
Q => \Lxy_0_reg_n_0_[1]\,
R => '0'
);
\Lxy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(2),
Q => \Lxy_0_reg_n_0_[2]\,
R => '0'
);
\Lxy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(3),
Q => \Lxy_0_reg_n_0_[3]\,
R => '0'
);
\Lxy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(4),
Q => \Lxy_0_reg_n_0_[4]\,
R => '0'
);
\Lxy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(5),
Q => \Lxy_0_reg_n_0_[5]\,
R => '0'
);
\Lxy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(6),
Q => \Lxy_0_reg_n_0_[6]\,
R => '0'
);
\Lxy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(7),
Q => \Lxy_0_reg_n_0_[7]\,
R => '0'
);
\Lxy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(8),
Q => \Lxy_0_reg_n_0_[8]\,
R => '0'
);
\Lxy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lxy_0[15]_i_1_n_0\,
D => Lxx_00(9),
Q => \Lxy_0_reg_n_0_[9]\,
R => '0'
);
\Lxy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(3),
I2 => active,
I3 => rst,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => Lxy_1
);
\Lxy_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(0),
Q => \Lxy_1_reg_n_0_[0]\,
R => '0'
);
\Lxy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(10),
Q => \Lxy_1_reg_n_0_[10]\,
R => '0'
);
\Lxy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(11),
Q => \Lxy_1_reg_n_0_[11]\,
R => '0'
);
\Lxy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(12),
Q => \Lxy_1_reg_n_0_[12]\,
R => '0'
);
\Lxy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(13),
Q => \Lxy_1_reg_n_0_[13]\,
R => '0'
);
\Lxy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(14),
Q => \Lxy_1_reg_n_0_[14]\,
R => '0'
);
\Lxy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(15),
Q => \Lxy_1_reg_n_0_[15]\,
R => '0'
);
\Lxy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(1),
Q => \Lxy_1_reg_n_0_[1]\,
R => '0'
);
\Lxy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(2),
Q => \Lxy_1_reg_n_0_[2]\,
R => '0'
);
\Lxy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(3),
Q => \Lxy_1_reg_n_0_[3]\,
R => '0'
);
\Lxy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(4),
Q => \Lxy_1_reg_n_0_[4]\,
R => '0'
);
\Lxy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(5),
Q => \Lxy_1_reg_n_0_[5]\,
R => '0'
);
\Lxy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(6),
Q => \Lxy_1_reg_n_0_[6]\,
R => '0'
);
\Lxy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(7),
Q => \Lxy_1_reg_n_0_[7]\,
R => '0'
);
\Lxy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(8),
Q => \Lxy_1_reg_n_0_[8]\,
R => '0'
);
\Lxy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lxy_1,
D => Lxx_11(9),
Q => \Lxy_1_reg_n_0_[9]\,
R => '0'
);
\Lxy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(0),
Q => Lxy_2(0),
R => '0'
);
\Lxy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(10),
Q => Lxy_2(10),
R => '0'
);
\Lxy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(11),
Q => Lxy_2(11),
R => '0'
);
\Lxy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(12),
Q => Lxy_2(12),
R => '0'
);
\Lxy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(13),
Q => Lxy_2(13),
R => '0'
);
\Lxy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(14),
Q => Lxy_2(14),
R => '0'
);
\Lxy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(15),
Q => Lxy_2(15),
R => '0'
);
\Lxy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(1),
Q => Lxy_2(1),
R => '0'
);
\Lxy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(2),
Q => Lxy_2(2),
R => '0'
);
\Lxy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(3),
Q => Lxy_2(3),
R => '0'
);
\Lxy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(4),
Q => Lxy_2(4),
R => '0'
);
\Lxy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(5),
Q => Lxy_2(5),
R => '0'
);
\Lxy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(6),
Q => Lxy_2(6),
R => '0'
);
\Lxy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(7),
Q => Lxy_2(7),
R => '0'
);
\Lxy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(8),
Q => Lxy_2(8),
R => '0'
);
\Lxy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0,
D => Lxx_00(9),
Q => Lxy_2(9),
R => '0'
);
\Lxy_3[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => cycle(3),
O => y6
);
\Lxy_3_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(0),
Q => Lxy_3(0),
R => '0'
);
\Lxy_3_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(10),
Q => Lxy_3(10),
R => '0'
);
\Lxy_3_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(11),
Q => Lxy_3(11),
R => '0'
);
\Lxy_3_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(12),
Q => Lxy_3(12),
R => '0'
);
\Lxy_3_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(13),
Q => Lxy_3(13),
R => '0'
);
\Lxy_3_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(14),
Q => Lxy_3(14),
R => '0'
);
\Lxy_3_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(15),
Q => Lxy_3(15),
R => '0'
);
\Lxy_3_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(1),
Q => Lxy_3(1),
R => '0'
);
\Lxy_3_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(2),
Q => Lxy_3(2),
R => '0'
);
\Lxy_3_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(3),
Q => Lxy_3(3),
R => '0'
);
\Lxy_3_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(4),
Q => Lxy_3(4),
R => '0'
);
\Lxy_3_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(5),
Q => Lxy_3(5),
R => '0'
);
\Lxy_3_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(6),
Q => Lxy_3(6),
R => '0'
);
\Lxy_3_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(7),
Q => Lxy_3(7),
R => '0'
);
\Lxy_3_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(8),
Q => Lxy_3(8),
R => '0'
);
\Lxy_3_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => Lxx_11(9),
Q => Lxy_3(9),
R => '0'
);
Lyy0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => Lyy0_carry_n_0,
CO(2) => Lyy0_carry_n_1,
CO(1) => Lyy0_carry_n_2,
CO(0) => Lyy0_carry_n_3,
CYINIT => '0',
DI(3) => Lyy0_carry_i_1_n_0,
DI(2) => Lyy0_carry_i_2_n_0,
DI(1) => '1',
DI(0) => \Lyy_2_reg_n_0_[0]\,
O(3 downto 0) => B(3 downto 0),
S(3) => Lyy0_carry_i_3_n_0,
S(2) => Lyy0_carry_i_4_n_0,
S(1) => Lyy0_carry_i_5_n_0,
S(0) => Lyy0_carry_i_6_n_0
);
\Lyy0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => Lyy0_carry_n_0,
CO(3) => \Lyy0_carry__0_n_0\,
CO(2) => \Lyy0_carry__0_n_1\,
CO(1) => \Lyy0_carry__0_n_2\,
CO(0) => \Lyy0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__0_i_1_n_0\,
DI(2) => \Lyy0_carry__0_i_2_n_0\,
DI(1) => \Lyy0_carry__0_i_3_n_0\,
DI(0) => \Lyy0_carry__0_i_4_n_0\,
O(3 downto 0) => B(7 downto 4),
S(3) => \Lyy0_carry__0_i_5_n_0\,
S(2) => \Lyy0_carry__0_i_6_n_0\,
S(1) => \Lyy0_carry__0_i_7_n_0\,
S(0) => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
O => \Lyy0_carry__0_i_1_n_0\
);
\Lyy0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
O => \Lyy0_carry__0_i_2_n_0\
);
\Lyy0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
O => \Lyy0_carry__0_i_3_n_0\
);
\Lyy0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
O => \Lyy0_carry__0_i_4_n_0\
);
\Lyy0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
I3 => \Lyy0_carry__0_i_1_n_0\,
O => \Lyy0_carry__0_i_5_n_0\
);
\Lyy0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(6),
I1 => \Lyy_2_reg_n_0_[6]\,
I2 => \Lyy_0_reg_n_0_[6]\,
I3 => \Lyy0_carry__0_i_2_n_0\,
O => \Lyy0_carry__0_i_6_n_0\
);
\Lyy0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(5),
I1 => \Lyy_2_reg_n_0_[5]\,
I2 => \Lyy_0_reg_n_0_[5]\,
I3 => \Lyy0_carry__0_i_3_n_0\,
O => \Lyy0_carry__0_i_7_n_0\
);
\Lyy0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(4),
I1 => \Lyy_2_reg_n_0_[4]\,
I2 => \Lyy_0_reg_n_0_[4]\,
I3 => \Lyy0_carry__0_i_4_n_0\,
O => \Lyy0_carry__0_i_8_n_0\
);
\Lyy0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__0_n_0\,
CO(3) => \Lyy0_carry__1_n_0\,
CO(2) => \Lyy0_carry__1_n_1\,
CO(1) => \Lyy0_carry__1_n_2\,
CO(0) => \Lyy0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy0_carry__1_i_1_n_0\,
DI(2) => \Lyy0_carry__1_i_2_n_0\,
DI(1) => \Lyy0_carry__1_i_3_n_0\,
DI(0) => \Lyy0_carry__1_i_4_n_0\,
O(3 downto 0) => B(11 downto 8),
S(3) => \Lyy0_carry__1_i_5_n_0\,
S(2) => \Lyy0_carry__1_i_6_n_0\,
S(1) => \Lyy0_carry__1_i_7_n_0\,
S(0) => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
O => \Lyy0_carry__1_i_1_n_0\
);
\Lyy0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
O => \Lyy0_carry__1_i_2_n_0\
);
\Lyy0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
O => \Lyy0_carry__1_i_3_n_0\
);
\Lyy0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(7),
I1 => \Lyy_2_reg_n_0_[7]\,
I2 => \Lyy_0_reg_n_0_[7]\,
O => \Lyy0_carry__1_i_4_n_0\
);
\Lyy0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
I3 => \Lyy0_carry__1_i_1_n_0\,
O => \Lyy0_carry__1_i_5_n_0\
);
\Lyy0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(10),
I1 => \Lyy_2_reg_n_0_[10]\,
I2 => \Lyy_0_reg_n_0_[10]\,
I3 => \Lyy0_carry__1_i_2_n_0\,
O => \Lyy0_carry__1_i_6_n_0\
);
\Lyy0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(9),
I1 => \Lyy_2_reg_n_0_[9]\,
I2 => \Lyy_0_reg_n_0_[9]\,
I3 => \Lyy0_carry__1_i_3_n_0\,
O => \Lyy0_carry__1_i_7_n_0\
);
\Lyy0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(8),
I1 => \Lyy_2_reg_n_0_[8]\,
I2 => \Lyy_0_reg_n_0_[8]\,
I3 => \Lyy0_carry__1_i_4_n_0\,
O => \Lyy0_carry__1_i_8_n_0\
);
\Lyy0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy0_carry__1_n_0\,
CO(3) => \NLW_Lyy0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy0_carry__2_n_1\,
CO(1) => \Lyy0_carry__2_n_2\,
CO(0) => \Lyy0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy0_carry__2_i_1_n_0\,
DI(1) => \Lyy0_carry__2_i_2_n_0\,
DI(0) => \Lyy0_carry__2_i_3_n_0\,
O(3 downto 0) => B(15 downto 12),
S(3) => \Lyy0_carry__2_i_4_n_0\,
S(2) => \Lyy0_carry__2_i_5_n_0\,
S(1) => \Lyy0_carry__2_i_6_n_0\,
S(0) => \Lyy0_carry__2_i_7_n_0\
);
\Lyy0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
O => \Lyy0_carry__2_i_1_n_0\
);
\Lyy0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
O => \Lyy0_carry__2_i_2_n_0\
);
\Lyy0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(11),
I1 => \Lyy_2_reg_n_0_[11]\,
I2 => \Lyy_0_reg_n_0_[11]\,
O => \Lyy0_carry__2_i_3_n_0\
);
\Lyy0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \Lyy_0_reg_n_0_[14]\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_2_reg_n_0_[15]\,
I4 => Lyy_1(15),
I5 => \Lyy_0_reg_n_0_[15]\,
O => \Lyy0_carry__2_i_4_n_0\
);
\Lyy0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \Lyy0_carry__2_i_1_n_0\,
I1 => \Lyy_2_reg_n_0_[14]\,
I2 => Lyy_1(14),
I3 => \Lyy_0_reg_n_0_[14]\,
O => \Lyy0_carry__2_i_5_n_0\
);
\Lyy0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(13),
I1 => \Lyy_2_reg_n_0_[13]\,
I2 => \Lyy_0_reg_n_0_[13]\,
I3 => \Lyy0_carry__2_i_2_n_0\,
O => \Lyy0_carry__2_i_6_n_0\
);
\Lyy0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(12),
I1 => \Lyy_2_reg_n_0_[12]\,
I2 => \Lyy_0_reg_n_0_[12]\,
I3 => \Lyy0_carry__2_i_3_n_0\,
O => \Lyy0_carry__2_i_7_n_0\
);
Lyy0_carry_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
O => Lyy0_carry_i_1_n_0
);
Lyy0_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_2_n_0
);
Lyy0_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(3),
I1 => \Lyy_2_reg_n_0_[3]\,
I2 => \Lyy_0_reg_n_0_[3]\,
I3 => Lyy0_carry_i_1_n_0,
O => Lyy0_carry_i_3_n_0
);
Lyy0_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_1(2),
I1 => \Lyy_2_reg_n_0_[2]\,
I2 => \Lyy_0_reg_n_0_[2]\,
I3 => Lyy0_carry_i_2_n_0,
O => Lyy0_carry_i_4_n_0
);
Lyy0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_1(1),
I1 => \Lyy_2_reg_n_0_[1]\,
I2 => \Lyy_0_reg_n_0_[1]\,
O => Lyy0_carry_i_5_n_0
);
Lyy0_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Lyy_2_reg_n_0_[0]\,
I1 => \Lyy_0_reg_n_0_[0]\,
O => Lyy0_carry_i_6_n_0
);
\Lyy_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[0]_rep_n_0\,
O => Lyy_0
);
\Lyy_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(0),
Q => \Lyy_0_reg_n_0_[0]\,
R => '0'
);
\Lyy_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(10),
Q => \Lyy_0_reg_n_0_[10]\,
R => '0'
);
\Lyy_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(11),
Q => \Lyy_0_reg_n_0_[11]\,
R => '0'
);
\Lyy_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(12),
Q => \Lyy_0_reg_n_0_[12]\,
R => '0'
);
\Lyy_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(13),
Q => \Lyy_0_reg_n_0_[13]\,
R => '0'
);
\Lyy_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(14),
Q => \Lyy_0_reg_n_0_[14]\,
R => '0'
);
\Lyy_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(15),
Q => \Lyy_0_reg_n_0_[15]\,
R => '0'
);
\Lyy_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(1),
Q => \Lyy_0_reg_n_0_[1]\,
R => '0'
);
\Lyy_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(2),
Q => \Lyy_0_reg_n_0_[2]\,
R => '0'
);
\Lyy_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(3),
Q => \Lyy_0_reg_n_0_[3]\,
R => '0'
);
\Lyy_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(4),
Q => \Lyy_0_reg_n_0_[4]\,
R => '0'
);
\Lyy_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(5),
Q => \Lyy_0_reg_n_0_[5]\,
R => '0'
);
\Lyy_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(6),
Q => \Lyy_0_reg_n_0_[6]\,
R => '0'
);
\Lyy_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(7),
Q => \Lyy_0_reg_n_0_[7]\,
R => '0'
);
\Lyy_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(8),
Q => \Lyy_0_reg_n_0_[8]\,
R => '0'
);
\Lyy_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => Lyy_0,
D => Lxx_00(9),
Q => \Lyy_0_reg_n_0_[9]\,
R => '0'
);
\Lyy_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => rst,
I3 => active,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y1
);
\Lyy_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(9),
Q => Lyy_1(10),
R => '0'
);
\Lyy_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(10),
Q => Lyy_1(11),
R => '0'
);
\Lyy_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(11),
Q => Lyy_1(12),
R => '0'
);
\Lyy_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(12),
Q => Lyy_1(13),
R => '0'
);
\Lyy_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(13),
Q => Lyy_1(14),
R => '0'
);
\Lyy_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(14),
Q => Lyy_1(15),
R => '0'
);
\Lyy_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(0),
Q => Lyy_1(1),
R => '0'
);
\Lyy_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(1),
Q => Lyy_1(2),
R => '0'
);
\Lyy_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(2),
Q => Lyy_1(3),
R => '0'
);
\Lyy_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(3),
Q => Lyy_1(4),
R => '0'
);
\Lyy_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(4),
Q => Lyy_1(5),
R => '0'
);
\Lyy_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(5),
Q => Lyy_1(6),
R => '0'
);
\Lyy_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(6),
Q => Lyy_1(7),
R => '0'
);
\Lyy_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(7),
Q => Lyy_1(8),
R => '0'
);
\Lyy_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => Lxx_11(8),
Q => Lyy_1(9),
R => '0'
);
\Lyy_20__1_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_20__1_carry_n_0\,
CO(2) => \Lyy_20__1_carry_n_1\,
CO(1) => \Lyy_20__1_carry_n_2\,
CO(0) => \Lyy_20__1_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry_i_1_n_0\,
DI(2) => \Lyy_20__1_carry_i_2_n_0\,
DI(1) => \Lyy_20__1_carry_i_3_n_0\,
DI(0) => Lyy_2_bottom_right(0),
O(3 downto 0) => Lyy_20(3 downto 0),
S(3) => \Lyy_20__1_carry_i_4_n_0\,
S(2) => \Lyy_20__1_carry_i_5_n_0\,
S(1) => \Lyy_20__1_carry_i_6_n_0\,
S(0) => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry_n_0\,
CO(3) => \Lyy_20__1_carry__0_n_0\,
CO(2) => \Lyy_20__1_carry__0_n_1\,
CO(1) => \Lyy_20__1_carry__0_n_2\,
CO(0) => \Lyy_20__1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__0_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__0_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__0_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_20(7 downto 4),
S(3) => \Lyy_20__1_carry__0_i_5_n_0\,
S(2) => \Lyy_20__1_carry__0_i_6_n_0\,
S(1) => \Lyy_20__1_carry__0_i_7_n_0\,
S(0) => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(6),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_right(6),
I3 => \Lyy_20__1_carry__0_i_9_n_0\,
I4 => Lyy_2_bottom_right(6),
O => \Lyy_20__1_carry__0_i_1_n_0\
);
\Lyy_20__1_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(5),
I1 => Lyy_2_bottom_left(5),
I2 => Lyy_2_top_right(5),
O => \Lyy_20__1_carry__0_i_10_n_0\
);
\Lyy_20__1_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(3),
I1 => Lyy_2_top_left(3),
I2 => Lyy_2_bottom_left(3),
O => \Lyy_20__1_carry__0_i_11_n_0\
);
\Lyy_20__1_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(7),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_right(7),
O => \Lyy_20__1_carry__0_i_12_n_0\
);
\Lyy_20__1_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(5),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_left(4),
I3 => Lyy_2_top_right(4),
I4 => \Lyy_20__1_carry__0_i_10_n_0\,
O => \Lyy_20__1_carry__0_i_2_n_0\
);
\Lyy_20__1_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(4),
I1 => Lyy_2_bottom_left(4),
I2 => Lyy_2_top_right(4),
I3 => \Lyy_20__1_carry__0_i_11_n_0\,
I4 => Lyy_2_bottom_right(4),
O => \Lyy_20__1_carry__0_i_3_n_0\
);
\Lyy_20__1_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(3),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_left(2),
I3 => Lyy_2_top_right(2),
I4 => \Lyy_20__1_carry_i_8_n_0\,
O => \Lyy_20__1_carry__0_i_4_n_0\
);
\Lyy_20__1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_1_n_0\,
I1 => \Lyy_20__1_carry__0_i_12_n_0\,
I2 => Lyy_2_bottom_right(7),
I3 => Lyy_2_top_right(6),
I4 => Lyy_2_top_left(6),
I5 => Lyy_2_bottom_left(6),
O => \Lyy_20__1_carry__0_i_5_n_0\
);
\Lyy_20__1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_2_n_0\,
I1 => Lyy_2_top_right(6),
I2 => Lyy_2_bottom_left(6),
I3 => Lyy_2_top_left(6),
I4 => Lyy_2_bottom_right(6),
I5 => \Lyy_20__1_carry__0_i_9_n_0\,
O => \Lyy_20__1_carry__0_i_6_n_0\
);
\Lyy_20__1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__0_i_3_n_0\,
I1 => \Lyy_20__1_carry__0_i_10_n_0\,
I2 => Lyy_2_bottom_right(5),
I3 => Lyy_2_top_right(4),
I4 => Lyy_2_top_left(4),
I5 => Lyy_2_bottom_left(4),
O => \Lyy_20__1_carry__0_i_7_n_0\
);
\Lyy_20__1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__0_i_4_n_0\,
I1 => Lyy_2_top_right(4),
I2 => Lyy_2_bottom_left(4),
I3 => Lyy_2_top_left(4),
I4 => Lyy_2_bottom_right(4),
I5 => \Lyy_20__1_carry__0_i_11_n_0\,
O => \Lyy_20__1_carry__0_i_8_n_0\
);
\Lyy_20__1_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(5),
I1 => Lyy_2_top_left(5),
I2 => Lyy_2_bottom_left(5),
O => \Lyy_20__1_carry__0_i_9_n_0\
);
\Lyy_20__1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__0_n_0\,
CO(3) => \Lyy_20__1_carry__1_n_0\,
CO(2) => \Lyy_20__1_carry__1_n_1\,
CO(1) => \Lyy_20__1_carry__1_n_2\,
CO(0) => \Lyy_20__1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_20__1_carry__1_i_1_n_0\,
DI(2) => \Lyy_20__1_carry__1_i_2_n_0\,
DI(1) => \Lyy_20__1_carry__1_i_3_n_0\,
DI(0) => \Lyy_20__1_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_20(11 downto 8),
S(3) => \Lyy_20__1_carry__1_i_5_n_0\,
S(2) => \Lyy_20__1_carry__1_i_6_n_0\,
S(1) => \Lyy_20__1_carry__1_i_7_n_0\,
S(0) => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(10),
I1 => Lyy_2_bottom_left(10),
I2 => Lyy_2_top_right(10),
I3 => \Lyy_20__1_carry__1_i_9_n_0\,
I4 => Lyy_2_bottom_right(10),
O => \Lyy_20__1_carry__1_i_1_n_0\
);
\Lyy_20__1_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(9),
I1 => Lyy_2_bottom_left(9),
I2 => Lyy_2_top_right(9),
O => \Lyy_20__1_carry__1_i_10_n_0\
);
\Lyy_20__1_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(8),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_right(8),
O => \Lyy_20__1_carry__1_i_11_n_0\
);
\Lyy_20__1_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(10),
I1 => Lyy_2_top_left(10),
I2 => Lyy_2_bottom_left(10),
O => \Lyy_20__1_carry__1_i_12_n_0\
);
\Lyy_20__1_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(9),
I1 => Lyy_2_bottom_left(8),
I2 => Lyy_2_top_left(8),
I3 => Lyy_2_top_right(8),
I4 => \Lyy_20__1_carry__1_i_10_n_0\,
O => \Lyy_20__1_carry__1_i_2_n_0\
);
\Lyy_20__1_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(8),
I1 => Lyy_2_bottom_left(7),
I2 => Lyy_2_top_left(7),
I3 => Lyy_2_top_right(7),
I4 => \Lyy_20__1_carry__1_i_11_n_0\,
O => \Lyy_20__1_carry__1_i_3_n_0\
);
\Lyy_20__1_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(7),
I1 => Lyy_2_bottom_left(6),
I2 => Lyy_2_top_left(6),
I3 => Lyy_2_top_right(6),
I4 => \Lyy_20__1_carry__0_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_4_n_0\
);
\Lyy_20__1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_1_n_0\,
I1 => Lyy_2_top_right(11),
I2 => Lyy_2_bottom_left(11),
I3 => Lyy_2_top_left(11),
I4 => Lyy_2_bottom_right(11),
I5 => \Lyy_20__1_carry__1_i_12_n_0\,
O => \Lyy_20__1_carry__1_i_5_n_0\
);
\Lyy_20__1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__1_i_2_n_0\,
I1 => Lyy_2_top_right(10),
I2 => Lyy_2_bottom_left(10),
I3 => Lyy_2_top_left(10),
I4 => Lyy_2_bottom_right(10),
I5 => \Lyy_20__1_carry__1_i_9_n_0\,
O => \Lyy_20__1_carry__1_i_6_n_0\
);
\Lyy_20__1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_3_n_0\,
I1 => \Lyy_20__1_carry__1_i_10_n_0\,
I2 => Lyy_2_bottom_right(9),
I3 => Lyy_2_top_right(8),
I4 => Lyy_2_top_left(8),
I5 => Lyy_2_bottom_left(8),
O => \Lyy_20__1_carry__1_i_7_n_0\
);
\Lyy_20__1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__1_i_4_n_0\,
I1 => \Lyy_20__1_carry__1_i_11_n_0\,
I2 => Lyy_2_bottom_right(8),
I3 => Lyy_2_top_right(7),
I4 => Lyy_2_top_left(7),
I5 => Lyy_2_bottom_left(7),
O => \Lyy_20__1_carry__1_i_8_n_0\
);
\Lyy_20__1_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4D"
)
port map (
I0 => Lyy_2_top_right(9),
I1 => Lyy_2_top_left(9),
I2 => Lyy_2_bottom_left(9),
O => \Lyy_20__1_carry__1_i_9_n_0\
);
\Lyy_20__1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_20__1_carry__1_n_0\,
CO(3) => \NLW_Lyy_20__1_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_20__1_carry__2_n_1\,
CO(1) => \Lyy_20__1_carry__2_n_2\,
CO(0) => \Lyy_20__1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_20__1_carry__2_i_1_n_0\,
DI(1) => \Lyy_20__1_carry__2_i_2_n_0\,
DI(0) => \Lyy_20__1_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_20(15 downto 12),
S(3) => \Lyy_20__1_carry__2_i_4_n_0\,
S(2) => \Lyy_20__1_carry__2_i_5_n_0\,
S(1) => \Lyy_20__1_carry__2_i_6_n_0\,
S(0) => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(13),
I1 => Lyy_2_top_right(12),
I2 => Lyy_2_top_left(12),
I3 => Lyy_2_bottom_left(12),
I4 => \Lyy_20__1_carry__2_i_8_n_0\,
O => \Lyy_20__1_carry__2_i_1_n_0\
);
\Lyy_20__1_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"2B"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_10_n_0\
);
\Lyy_20__1_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(15),
I1 => Lyy_2_bottom_left(15),
I2 => Lyy_2_top_left(15),
I3 => Lyy_2_bottom_right(15),
O => \Lyy_20__1_carry__2_i_11_n_0\
);
\Lyy_20__1_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAFB20A2"
)
port map (
I0 => Lyy_2_bottom_right(12),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_left(11),
I3 => Lyy_2_top_right(11),
I4 => \Lyy_20__1_carry__2_i_9_n_0\,
O => \Lyy_20__1_carry__2_i_2_n_0\
);
\Lyy_20__1_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => Lyy_2_top_left(11),
I1 => Lyy_2_bottom_left(11),
I2 => Lyy_2_top_right(11),
I3 => \Lyy_20__1_carry__1_i_12_n_0\,
I4 => Lyy_2_bottom_right(11),
O => \Lyy_20__1_carry__2_i_3_n_0\
);
\Lyy_20__1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E78871E871EE187"
)
port map (
I0 => Lyy_2_bottom_right(14),
I1 => \Lyy_20__1_carry__2_i_10_n_0\,
I2 => \Lyy_20__1_carry__2_i_11_n_0\,
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_left(14),
I5 => Lyy_2_top_right(14),
O => \Lyy_20__1_carry__2_i_4_n_0\
);
\Lyy_20__1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry__2_i_1_n_0\,
I1 => Lyy_2_top_right(14),
I2 => Lyy_2_bottom_left(14),
I3 => Lyy_2_top_left(14),
I4 => Lyy_2_bottom_right(14),
I5 => \Lyy_20__1_carry__2_i_10_n_0\,
O => \Lyy_20__1_carry__2_i_5_n_0\
);
\Lyy_20__1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_2_n_0\,
I1 => \Lyy_20__1_carry__2_i_8_n_0\,
I2 => Lyy_2_bottom_right(13),
I3 => Lyy_2_bottom_left(12),
I4 => Lyy_2_top_left(12),
I5 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_6_n_0\
);
\Lyy_20__1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry__2_i_3_n_0\,
I1 => \Lyy_20__1_carry__2_i_9_n_0\,
I2 => Lyy_2_bottom_right(12),
I3 => Lyy_2_top_right(11),
I4 => Lyy_2_top_left(11),
I5 => Lyy_2_bottom_left(11),
O => \Lyy_20__1_carry__2_i_7_n_0\
);
\Lyy_20__1_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(13),
I1 => Lyy_2_bottom_left(13),
I2 => Lyy_2_top_right(13),
O => \Lyy_20__1_carry__2_i_8_n_0\
);
\Lyy_20__1_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(12),
I1 => Lyy_2_bottom_left(12),
I2 => Lyy_2_top_right(12),
O => \Lyy_20__1_carry__2_i_9_n_0\
);
\Lyy_20__1_carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FFFFFF00969696"
)
port map (
I0 => Lyy_2_top_left(2),
I1 => Lyy_2_bottom_left(2),
I2 => Lyy_2_top_right(2),
I3 => Lyy_2_top_right(1),
I4 => Lyy_2_bottom_left(1),
I5 => Lyy_2_bottom_right(2),
O => \Lyy_20__1_carry_i_1_n_0\
);
\Lyy_20__1_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => Lyy_2_top_right(1),
I1 => Lyy_2_bottom_left(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_2_n_0\
);
\Lyy_20__1_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
I2 => Lyy_2_top_left(1),
I3 => Lyy_2_bottom_right(1),
O => \Lyy_20__1_carry_i_3_n_0\
);
\Lyy_20__1_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669969669699669"
)
port map (
I0 => \Lyy_20__1_carry_i_1_n_0\,
I1 => \Lyy_20__1_carry_i_8_n_0\,
I2 => Lyy_2_bottom_right(3),
I3 => Lyy_2_top_right(2),
I4 => Lyy_2_top_left(2),
I5 => Lyy_2_bottom_left(2),
O => \Lyy_20__1_carry_i_4_n_0\
);
\Lyy_20__1_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \Lyy_20__1_carry_i_2_n_0\,
I1 => Lyy_2_top_right(2),
I2 => Lyy_2_bottom_left(2),
I3 => Lyy_2_top_left(2),
I4 => Lyy_2_bottom_right(2),
I5 => \Lyy_20__1_carry_i_9_n_0\,
O => \Lyy_20__1_carry_i_5_n_0\
);
\Lyy_20__1_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A59"
)
port map (
I0 => \Lyy_20__1_carry_i_3_n_0\,
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_top_right(0),
O => \Lyy_20__1_carry_i_6_n_0\
);
\Lyy_20__1_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Lyy_2_top_right(0),
I1 => Lyy_2_bottom_left(0),
I2 => Lyy_2_top_left(0),
I3 => Lyy_2_bottom_right(0),
O => \Lyy_20__1_carry_i_7_n_0\
);
\Lyy_20__1_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Lyy_2_top_left(3),
I1 => Lyy_2_bottom_left(3),
I2 => Lyy_2_top_right(3),
O => \Lyy_20__1_carry_i_8_n_0\
);
\Lyy_20__1_carry_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => Lyy_2_bottom_left(1),
I1 => Lyy_2_top_right(1),
O => \Lyy_20__1_carry_i_9_n_0\
);
\Lyy_2[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \Lyy_2[15]_i_1_n_0\
);
\Lyy_2_bottom_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(0),
Q => Lyy_2_bottom_left(0),
R => '0'
);
\Lyy_2_bottom_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(10),
Q => Lyy_2_bottom_left(10),
R => '0'
);
\Lyy_2_bottom_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(11),
Q => Lyy_2_bottom_left(11),
R => '0'
);
\Lyy_2_bottom_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(12),
Q => Lyy_2_bottom_left(12),
R => '0'
);
\Lyy_2_bottom_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(13),
Q => Lyy_2_bottom_left(13),
R => '0'
);
\Lyy_2_bottom_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(14),
Q => Lyy_2_bottom_left(14),
R => '0'
);
\Lyy_2_bottom_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(15),
Q => Lyy_2_bottom_left(15),
R => '0'
);
\Lyy_2_bottom_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(1),
Q => Lyy_2_bottom_left(1),
R => '0'
);
\Lyy_2_bottom_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(2),
Q => Lyy_2_bottom_left(2),
R => '0'
);
\Lyy_2_bottom_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(3),
Q => Lyy_2_bottom_left(3),
R => '0'
);
\Lyy_2_bottom_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(4),
Q => Lyy_2_bottom_left(4),
R => '0'
);
\Lyy_2_bottom_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(5),
Q => Lyy_2_bottom_left(5),
R => '0'
);
\Lyy_2_bottom_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(6),
Q => Lyy_2_bottom_left(6),
R => '0'
);
\Lyy_2_bottom_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(7),
Q => Lyy_2_bottom_left(7),
R => '0'
);
\Lyy_2_bottom_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(8),
Q => Lyy_2_bottom_left(8),
R => '0'
);
\Lyy_2_bottom_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => \cache_reg[4]_0\(9),
Q => Lyy_2_bottom_left(9),
R => '0'
);
\Lyy_2_bottom_right0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(3 downto 0),
S(3) => \Lyy_2_bottom_right0__0_carry_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__0_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__0_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(7 downto 4),
S(3) => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(6),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => \corner_reg_n_0_[5]\,
I3 => \top_reg_n_0_[5]\,
I4 => \left_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[5]\,
I1 => \left_reg_n_0_[5]\,
I2 => \top_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[4]\,
I1 => \left_reg_n_0_[4]\,
I2 => \top_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[7]\,
I1 => \left_reg_n_0_[7]\,
I2 => \top_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(5),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => \corner_reg_n_0_[4]\,
I3 => \top_reg_n_0_[4]\,
I4 => \left_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(4),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => \corner_reg_n_0_[3]\,
I3 => \top_reg_n_0_[3]\,
I4 => \left_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(3),
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => \corner_reg_n_0_[2]\,
I3 => \top_reg_n_0_[2]\,
I4 => \left_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => last_value(7),
I3 => \left_reg_n_0_[6]\,
I4 => \top_reg_n_0_[6]\,
I5 => \corner_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\,
I2 => last_value(6),
I3 => \left_reg_n_0_[5]\,
I4 => \top_reg_n_0_[5]\,
I5 => \corner_reg_n_0_[5]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_10_n_0\,
I2 => last_value(5),
I3 => \left_reg_n_0_[4]\,
I4 => \top_reg_n_0_[4]\,
I5 => \corner_reg_n_0_[4]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__0_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__0_i_11_n_0\,
I2 => last_value(4),
I3 => \left_reg_n_0_[3]\,
I4 => \top_reg_n_0_[3]\,
I5 => \corner_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[6]\,
I1 => \left_reg_n_0_[6]\,
I2 => \top_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__0_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__0_n_0\,
CO(3) => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(2) => \Lyy_2_bottom_right0__0_carry__1_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__1_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
DI(2) => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(11 downto 8),
S(3) => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \corner_reg_n_0_[10]\,
I3 => \corner_reg_n_0_[9]\,
I4 => \top_reg_n_0_[9]\,
I5 => \left_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[10]\,
I1 => \left_reg_n_0_[10]\,
I2 => \top_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \top_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \top_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[9]\,
I1 => \left_reg_n_0_[9]\,
I2 => \corner_reg_n_0_[9]\,
I3 => \corner_reg_n_0_[8]\,
I4 => \top_reg_n_0_[8]\,
I5 => \left_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[8]\,
I1 => \left_reg_n_0_[8]\,
I2 => \corner_reg_n_0_[8]\,
I3 => \corner_reg_n_0_[7]\,
I4 => \top_reg_n_0_[7]\,
I5 => \left_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(7),
I1 => \Lyy_2_bottom_right0__0_carry__0_i_12_n_0\,
I2 => \corner_reg_n_0_[6]\,
I3 => \top_reg_n_0_[6]\,
I4 => \left_reg_n_0_[6]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\,
I2 => \left_reg_n_0_[10]\,
I3 => \top_reg_n_0_[10]\,
I4 => \corner_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_10_n_0\,
I2 => \left_reg_n_0_[9]\,
I3 => \top_reg_n_0_[9]\,
I4 => \corner_reg_n_0_[9]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_11_n_0\,
I2 => \left_reg_n_0_[8]\,
I3 => \top_reg_n_0_[8]\,
I4 => \corner_reg_n_0_[8]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__1_i_4_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__1_i_12_n_0\,
I2 => \left_reg_n_0_[7]\,
I3 => \top_reg_n_0_[7]\,
I4 => \corner_reg_n_0_[7]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \top_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__1_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \Lyy_2_bottom_right0__0_carry__1_n_0\,
CO(3) => \NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \Lyy_2_bottom_right0__0_carry__2_n_1\,
CO(1) => \Lyy_2_bottom_right0__0_carry__2_n_2\,
CO(0) => \Lyy_2_bottom_right0__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
DI(1) => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
DI(0) => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
O(3 downto 0) => Lyy_2_bottom_right01_out(15 downto 12),
S(3) => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\,
S(2) => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\,
S(1) => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\,
S(0) => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
I3 => \corner_reg_n_0_[12]\,
I4 => \top_reg_n_0_[12]\,
I5 => \left_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \left_reg_n_0_[14]\,
I2 => \top_reg_n_0_[14]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[13]\,
I1 => \left_reg_n_0_[13]\,
I2 => \top_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \top_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[12]\,
I1 => \left_reg_n_0_[12]\,
I2 => \corner_reg_n_0_[12]\,
I3 => \corner_reg_n_0_[11]\,
I4 => \top_reg_n_0_[11]\,
I5 => \left_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969006900690000"
)
port map (
I0 => \top_reg_n_0_[11]\,
I1 => \left_reg_n_0_[11]\,
I2 => \corner_reg_n_0_[11]\,
I3 => \corner_reg_n_0_[10]\,
I4 => \top_reg_n_0_[10]\,
I5 => \left_reg_n_0_[10]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D2882"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\,
I1 => \corner_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[14]\,
I4 => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\,
O => \Lyy_2_bottom_right0__0_carry__2_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_10_n_0\,
I2 => \left_reg_n_0_[13]\,
I3 => \top_reg_n_0_[13]\,
I4 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_11_n_0\,
I2 => \left_reg_n_0_[12]\,
I3 => \top_reg_n_0_[12]\,
I4 => \corner_reg_n_0_[12]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry__2_i_3_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry__2_i_12_n_0\,
I2 => \left_reg_n_0_[11]\,
I3 => \top_reg_n_0_[11]\,
I4 => \corner_reg_n_0_[11]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \left_reg_n_0_[13]\,
I1 => \top_reg_n_0_[13]\,
I2 => \corner_reg_n_0_[13]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry__2_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"D42B2BD42BD4D42B"
)
port map (
I0 => \corner_reg_n_0_[14]\,
I1 => \top_reg_n_0_[14]\,
I2 => \left_reg_n_0_[14]\,
I3 => \top_reg_n_0_[15]\,
I4 => \left_reg_n_0_[15]\,
I5 => \corner_reg_n_0_[15]\,
O => \Lyy_2_bottom_right0__0_carry__2_i_9_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE8E8E88"
)
port map (
I0 => last_value(2),
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => \corner_reg_n_0_[1]\,
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_1_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[3]\,
I1 => \left_reg_n_0_[3]\,
I2 => \top_reg_n_0_[3]\,
O => \Lyy_2_bottom_right0__0_carry_i_10_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \top_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_11_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"20BABA20BA2020BA"
)
port map (
I0 => last_value(1),
I1 => \corner_reg_n_0_[0]\,
I2 => last_value(0),
I3 => \top_reg_n_0_[1]\,
I4 => \left_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_2_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669966969969669"
)
port map (
I0 => \top_reg_n_0_[1]\,
I1 => \left_reg_n_0_[1]\,
I2 => \corner_reg_n_0_[1]\,
I3 => last_value(1),
I4 => last_value(0),
I5 => \corner_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_3_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_4_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_1_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_10_n_0\,
I2 => last_value(3),
I3 => \left_reg_n_0_[2]\,
I4 => \top_reg_n_0_[2]\,
I5 => \corner_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_5_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996969669696996"
)
port map (
I0 => \Lyy_2_bottom_right0__0_carry_i_2_n_0\,
I1 => \Lyy_2_bottom_right0__0_carry_i_9_n_0\,
I2 => last_value(2),
I3 => \left_reg_n_0_[1]\,
I4 => \top_reg_n_0_[1]\,
I5 => \corner_reg_n_0_[1]\,
O => \Lyy_2_bottom_right0__0_carry_i_6_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB44B4BB4"
)
port map (
I0 => \corner_reg_n_0_[0]\,
I1 => last_value(0),
I2 => last_value(1),
I3 => \Lyy_2_bottom_right0__0_carry_i_11_n_0\,
I4 => \left_reg_n_0_[0]\,
I5 => \top_reg_n_0_[0]\,
O => \Lyy_2_bottom_right0__0_carry_i_7_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \left_reg_n_0_[0]\,
I1 => \top_reg_n_0_[0]\,
I2 => \corner_reg_n_0_[0]\,
I3 => last_value(0),
O => \Lyy_2_bottom_right0__0_carry_i_8_n_0\
);
\Lyy_2_bottom_right0__0_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \corner_reg_n_0_[2]\,
I1 => \left_reg_n_0_[2]\,
I2 => \top_reg_n_0_[2]\,
O => \Lyy_2_bottom_right0__0_carry_i_9_n_0\
);
\Lyy_2_bottom_right[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => y5
);
\Lyy_2_bottom_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(0),
Q => Lyy_2_bottom_right(0),
R => '0'
);
\Lyy_2_bottom_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(10),
Q => Lyy_2_bottom_right(10),
R => '0'
);
\Lyy_2_bottom_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(11),
Q => Lyy_2_bottom_right(11),
R => '0'
);
\Lyy_2_bottom_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(12),
Q => Lyy_2_bottom_right(12),
R => '0'
);
\Lyy_2_bottom_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(13),
Q => Lyy_2_bottom_right(13),
R => '0'
);
\Lyy_2_bottom_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(14),
Q => Lyy_2_bottom_right(14),
R => '0'
);
\Lyy_2_bottom_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(15),
Q => Lyy_2_bottom_right(15),
R => '0'
);
\Lyy_2_bottom_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(1),
Q => Lyy_2_bottom_right(1),
R => '0'
);
\Lyy_2_bottom_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(2),
Q => Lyy_2_bottom_right(2),
R => '0'
);
\Lyy_2_bottom_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(3),
Q => Lyy_2_bottom_right(3),
R => '0'
);
\Lyy_2_bottom_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(4),
Q => Lyy_2_bottom_right(4),
R => '0'
);
\Lyy_2_bottom_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(5),
Q => Lyy_2_bottom_right(5),
R => '0'
);
\Lyy_2_bottom_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(6),
Q => Lyy_2_bottom_right(6),
R => '0'
);
\Lyy_2_bottom_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(7),
Q => Lyy_2_bottom_right(7),
R => '0'
);
\Lyy_2_bottom_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(8),
Q => Lyy_2_bottom_right(8),
R => '0'
);
\Lyy_2_bottom_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y5,
D => Lyy_2_bottom_right01_out(9),
Q => Lyy_2_bottom_right(9),
R => '0'
);
\Lyy_2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(0),
Q => \Lyy_2_reg_n_0_[0]\,
R => '0'
);
\Lyy_2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(10),
Q => \Lyy_2_reg_n_0_[10]\,
R => '0'
);
\Lyy_2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(11),
Q => \Lyy_2_reg_n_0_[11]\,
R => '0'
);
\Lyy_2_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(12),
Q => \Lyy_2_reg_n_0_[12]\,
R => '0'
);
\Lyy_2_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(13),
Q => \Lyy_2_reg_n_0_[13]\,
R => '0'
);
\Lyy_2_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(14),
Q => \Lyy_2_reg_n_0_[14]\,
R => '0'
);
\Lyy_2_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(15),
Q => \Lyy_2_reg_n_0_[15]\,
R => '0'
);
\Lyy_2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(1),
Q => \Lyy_2_reg_n_0_[1]\,
R => '0'
);
\Lyy_2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(2),
Q => \Lyy_2_reg_n_0_[2]\,
R => '0'
);
\Lyy_2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(3),
Q => \Lyy_2_reg_n_0_[3]\,
R => '0'
);
\Lyy_2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(4),
Q => \Lyy_2_reg_n_0_[4]\,
R => '0'
);
\Lyy_2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(5),
Q => \Lyy_2_reg_n_0_[5]\,
R => '0'
);
\Lyy_2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(6),
Q => \Lyy_2_reg_n_0_[6]\,
R => '0'
);
\Lyy_2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(7),
Q => \Lyy_2_reg_n_0_[7]\,
R => '0'
);
\Lyy_2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(8),
Q => \Lyy_2_reg_n_0_[8]\,
R => '0'
);
\Lyy_2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \Lyy_2[15]_i_1_n_0\,
D => Lyy_20(9),
Q => \Lyy_2_reg_n_0_[9]\,
R => '0'
);
\Lyy_2_top_left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(0),
Q => Lyy_2_top_left(0),
R => '0'
);
\Lyy_2_top_left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(10),
Q => Lyy_2_top_left(10),
R => '0'
);
\Lyy_2_top_left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(11),
Q => Lyy_2_top_left(11),
R => '0'
);
\Lyy_2_top_left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(12),
Q => Lyy_2_top_left(12),
R => '0'
);
\Lyy_2_top_left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(13),
Q => Lyy_2_top_left(13),
R => '0'
);
\Lyy_2_top_left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(14),
Q => Lyy_2_top_left(14),
R => '0'
);
\Lyy_2_top_left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(15),
Q => Lyy_2_top_left(15),
R => '0'
);
\Lyy_2_top_left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(1),
Q => Lyy_2_top_left(1),
R => '0'
);
\Lyy_2_top_left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(2),
Q => Lyy_2_top_left(2),
R => '0'
);
\Lyy_2_top_left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(3),
Q => Lyy_2_top_left(3),
R => '0'
);
\Lyy_2_top_left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(4),
Q => Lyy_2_top_left(4),
R => '0'
);
\Lyy_2_top_left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(5),
Q => Lyy_2_top_left(5),
R => '0'
);
\Lyy_2_top_left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(6),
Q => Lyy_2_top_left(6),
R => '0'
);
\Lyy_2_top_left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(7),
Q => Lyy_2_top_left(7),
R => '0'
);
\Lyy_2_top_left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(8),
Q => Lyy_2_top_left(8),
R => '0'
);
\Lyy_2_top_left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => bottom_left_1(9),
Q => Lyy_2_top_left(9),
R => '0'
);
\Lyy_2_top_right_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[0]\,
Q => Lyy_2_top_right(0),
R => '0'
);
\Lyy_2_top_right_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[10]\,
Q => Lyy_2_top_right(10),
R => '0'
);
\Lyy_2_top_right_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[11]\,
Q => Lyy_2_top_right(11),
R => '0'
);
\Lyy_2_top_right_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[12]\,
Q => Lyy_2_top_right(12),
R => '0'
);
\Lyy_2_top_right_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[13]\,
Q => Lyy_2_top_right(13),
R => '0'
);
\Lyy_2_top_right_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[14]\,
Q => Lyy_2_top_right(14),
R => '0'
);
\Lyy_2_top_right_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[15]\,
Q => Lyy_2_top_right(15),
R => '0'
);
\Lyy_2_top_right_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[1]\,
Q => Lyy_2_top_right(1),
R => '0'
);
\Lyy_2_top_right_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[2]\,
Q => Lyy_2_top_right(2),
R => '0'
);
\Lyy_2_top_right_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[3]\,
Q => Lyy_2_top_right(3),
R => '0'
);
\Lyy_2_top_right_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[4]\,
Q => Lyy_2_top_right(4),
R => '0'
);
\Lyy_2_top_right_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[5]\,
Q => Lyy_2_top_right(5),
R => '0'
);
\Lyy_2_top_right_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[6]\,
Q => Lyy_2_top_right(6),
R => '0'
);
\Lyy_2_top_right_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[7]\,
Q => Lyy_2_top_right(7),
R => '0'
);
\Lyy_2_top_right_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[8]\,
Q => Lyy_2_top_right(8),
R => '0'
);
\Lyy_2_top_right_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y1,
D => \bottom_right_1_reg_n_0_[9]\,
Q => Lyy_2_top_right(9),
R => '0'
);
\addr_0[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[0]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[0]\,
O => \addr_0[0]_i_1_n_0\
);
\addr_0[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[10]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[10]\,
O => \addr_0[10]_i_1_n_0\
);
\addr_0[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[11]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[11]\,
O => \addr_0[11]_i_1_n_0\
);
\addr_0[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[12]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[12]\,
O => \addr_0[12]_i_1_n_0\
);
\addr_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888808888"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => \cycle_reg[1]_rep_n_0\,
I5 => cycle(2),
O => addr_0
);
\addr_0[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[13]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[13]\,
O => \addr_0[13]_i_2_n_0\
);
\addr_0[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[1]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[1]\,
O => \addr_0[1]_i_1_n_0\
);
\addr_0[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[2]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[2]\,
O => \addr_0[2]_i_1_n_0\
);
\addr_0[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[3]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[3]\,
O => \addr_0[3]_i_1_n_0\
);
\addr_0[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[4]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[4]\,
O => \addr_0[4]_i_1_n_0\
);
\addr_0[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[5]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[5]\,
O => \addr_0[5]_i_1_n_0\
);
\addr_0[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[6]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[6]\,
O => \addr_0[6]_i_1_n_0\
);
\addr_0[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[7]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[7]\,
O => \addr_0[7]_i_1_n_0\
);
\addr_0[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[8]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[8]\,
O => \addr_0[8]_i_1_n_0\
);
\addr_0[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \compute_addr_0_reg_n_0_[9]\,
I1 => \cycle_reg[0]_rep_n_0\,
I2 => \compute_addr_2_reg_n_0_[9]\,
O => \addr_0[9]_i_1_n_0\
);
\addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[0]_i_1_n_0\,
Q => \addr_0_reg_n_0_[0]\,
R => '0'
);
\addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[10]_i_1_n_0\,
Q => \addr_0_reg_n_0_[10]\,
R => '0'
);
\addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[11]_i_1_n_0\,
Q => \addr_0_reg_n_0_[11]\,
R => '0'
);
\addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[12]_i_1_n_0\,
Q => \addr_0_reg_n_0_[12]\,
R => '0'
);
\addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[13]_i_2_n_0\,
Q => \addr_0_reg_n_0_[13]\,
R => '0'
);
\addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[1]_i_1_n_0\,
Q => \addr_0_reg_n_0_[1]\,
R => '0'
);
\addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[2]_i_1_n_0\,
Q => \addr_0_reg_n_0_[2]\,
R => '0'
);
\addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[3]_i_1_n_0\,
Q => \addr_0_reg_n_0_[3]\,
R => '0'
);
\addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[4]_i_1_n_0\,
Q => \addr_0_reg_n_0_[4]\,
R => '0'
);
\addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[5]_i_1_n_0\,
Q => \addr_0_reg_n_0_[5]\,
R => '0'
);
\addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[6]_i_1_n_0\,
Q => \addr_0_reg_n_0_[6]\,
R => '0'
);
\addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[7]_i_1_n_0\,
Q => \addr_0_reg_n_0_[7]\,
R => '0'
);
\addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[8]_i_1_n_0\,
Q => \addr_0_reg_n_0_[8]\,
R => '0'
);
\addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_0[9]_i_1_n_0\,
Q => \addr_0_reg_n_0_[9]\,
R => '0'
);
\addr_1[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(0),
O => \addr_1[0]_i_1_n_0\
);
\addr_1[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(10),
O => \addr_1[10]_i_1_n_0\
);
\addr_1[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(11),
O => \addr_1[11]_i_1_n_0\
);
\addr_1[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(12),
O => \addr_1[12]_i_1_n_0\
);
\addr_1[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(13),
O => \addr_1[13]_i_1_n_0\
);
\addr_1[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(1),
O => \addr_1[1]_i_1_n_0\
);
\addr_1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(2),
O => \addr_1[2]_i_1_n_0\
);
\addr_1[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(3),
O => \addr_1[3]_i_1_n_0\
);
\addr_1[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(4),
O => \addr_1[4]_i_1_n_0\
);
\addr_1[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(5),
O => \addr_1[5]_i_1_n_0\
);
\addr_1[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(6),
O => \addr_1[6]_i_1_n_0\
);
\addr_1[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(7),
O => \addr_1[7]_i_1_n_0\
);
\addr_1[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(8),
O => \addr_1[8]_i_1_n_0\
);
\addr_1[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => compute_addr_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => compute_addr_3(9),
O => \addr_1[9]_i_1_n_0\
);
\addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[0]_i_1_n_0\,
Q => addr_1(0),
R => '0'
);
\addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[10]_i_1_n_0\,
Q => addr_1(10),
R => '0'
);
\addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[11]_i_1_n_0\,
Q => addr_1(11),
R => '0'
);
\addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[12]_i_1_n_0\,
Q => addr_1(12),
R => '0'
);
\addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[13]_i_1_n_0\,
Q => addr_1(13),
R => '0'
);
\addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[1]_i_1_n_0\,
Q => addr_1(1),
R => '0'
);
\addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[2]_i_1_n_0\,
Q => addr_1(2),
R => '0'
);
\addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[3]_i_1_n_0\,
Q => addr_1(3),
R => '0'
);
\addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[4]_i_1_n_0\,
Q => addr_1(4),
R => '0'
);
\addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[5]_i_1_n_0\,
Q => addr_1(5),
R => '0'
);
\addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[6]_i_1_n_0\,
Q => addr_1(6),
R => '0'
);
\addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[7]_i_1_n_0\,
Q => addr_1(7),
R => '0'
);
\addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[8]_i_1_n_0\,
Q => addr_1(8),
R => '0'
);
\addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => addr_0,
D => \addr_1[9]_i_1_n_0\,
Q => addr_1(9),
R => '0'
);
\bottom_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8800880000000800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(2),
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => \cycle_reg[1]_rep_n_0\,
O => bottom_left_0
);
\bottom_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(0),
Q => \bottom_left_0_reg_n_0_[0]\,
R => '0'
);
\bottom_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(10),
Q => \bottom_left_0_reg_n_0_[10]\,
R => '0'
);
\bottom_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(11),
Q => \bottom_left_0_reg_n_0_[11]\,
R => '0'
);
\bottom_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(12),
Q => \bottom_left_0_reg_n_0_[12]\,
R => '0'
);
\bottom_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(13),
Q => \bottom_left_0_reg_n_0_[13]\,
R => '0'
);
\bottom_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(14),
Q => \bottom_left_0_reg_n_0_[14]\,
R => '0'
);
\bottom_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(15),
Q => \bottom_left_0_reg_n_0_[15]\,
R => '0'
);
\bottom_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(1),
Q => \bottom_left_0_reg_n_0_[1]\,
R => '0'
);
\bottom_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(2),
Q => \bottom_left_0_reg_n_0_[2]\,
R => '0'
);
\bottom_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(3),
Q => \bottom_left_0_reg_n_0_[3]\,
R => '0'
);
\bottom_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(4),
Q => \bottom_left_0_reg_n_0_[4]\,
R => '0'
);
\bottom_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(5),
Q => \bottom_left_0_reg_n_0_[5]\,
R => '0'
);
\bottom_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(6),
Q => \bottom_left_0_reg_n_0_[6]\,
R => '0'
);
\bottom_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(7),
Q => \bottom_left_0_reg_n_0_[7]\,
R => '0'
);
\bottom_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(8),
Q => \bottom_left_0_reg_n_0_[8]\,
R => '0'
);
\bottom_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_left_0,
D => dout_0(9),
Q => \bottom_left_0_reg_n_0_[9]\,
R => '0'
);
\bottom_left_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000040"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
O => top_right_1
);
\bottom_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(0),
Q => bottom_left_1(0),
R => '0'
);
\bottom_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(10),
Q => bottom_left_1(10),
R => '0'
);
\bottom_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(11),
Q => bottom_left_1(11),
R => '0'
);
\bottom_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(12),
Q => bottom_left_1(12),
R => '0'
);
\bottom_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(13),
Q => bottom_left_1(13),
R => '0'
);
\bottom_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(14),
Q => bottom_left_1(14),
R => '0'
);
\bottom_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(15),
Q => bottom_left_1(15),
R => '0'
);
\bottom_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(1),
Q => bottom_left_1(1),
R => '0'
);
\bottom_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(2),
Q => bottom_left_1(2),
R => '0'
);
\bottom_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(3),
Q => bottom_left_1(3),
R => '0'
);
\bottom_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(4),
Q => bottom_left_1(4),
R => '0'
);
\bottom_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(5),
Q => bottom_left_1(5),
R => '0'
);
\bottom_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(6),
Q => bottom_left_1(6),
R => '0'
);
\bottom_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(7),
Q => bottom_left_1(7),
R => '0'
);
\bottom_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(8),
Q => bottom_left_1(8),
R => '0'
);
\bottom_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => dout_0(9),
Q => bottom_left_1(9),
R => '0'
);
\bottom_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[0]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(0),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(0),
O => p_0_out(0)
);
\bottom_right_0[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(0),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[0]_i_2_n_0\
);
\bottom_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[10]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(10),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(10),
O => p_0_out(10)
);
\bottom_right_0[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(10),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(10),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[10]_i_2_n_0\
);
\bottom_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[11]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(11),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(11),
O => p_0_out(11)
);
\bottom_right_0[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(11),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(11),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[11]_i_2_n_0\
);
\bottom_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[12]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(12),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(12),
O => p_0_out(12)
);
\bottom_right_0[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(12),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(12),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[12]_i_2_n_0\
);
\bottom_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[13]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(13),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(13),
O => p_0_out(13)
);
\bottom_right_0[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(13),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(13),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[13]_i_2_n_0\
);
\bottom_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[14]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(14),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(14),
O => p_0_out(14)
);
\bottom_right_0[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(14),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(14),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[14]_i_2_n_0\
);
\bottom_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"444A000000000000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => rst,
I5 => active,
O => \bottom_right_0[15]_i_1_n_0\
);
\bottom_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[15]_i_4_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(15),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(15),
O => p_0_out(15)
);
\bottom_right_0[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => cycle(2),
O => \bottom_right_0[15]_i_3_n_0\
);
\bottom_right_0[15]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(15),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(15),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[15]_i_4_n_0\
);
\bottom_right_0[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(0),
O => \bottom_right_0[15]_i_5_n_0\
);
\bottom_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[1]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(1),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(1),
O => p_0_out(1)
);
\bottom_right_0[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(1),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[1]_i_2_n_0\
);
\bottom_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[2]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(2),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(2),
O => p_0_out(2)
);
\bottom_right_0[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(2),
I3 => cycle(2),
I4 => cycle(0),
O => \bottom_right_0[2]_i_2_n_0\
);
\bottom_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[3]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(3),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(3),
O => p_0_out(3)
);
\bottom_right_0[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(3),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[3]_i_2_n_0\
);
\bottom_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[4]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(4),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(4),
O => p_0_out(4)
);
\bottom_right_0[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(4),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[4]_i_2_n_0\
);
\bottom_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[5]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(5),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(5),
O => p_0_out(5)
);
\bottom_right_0[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(5),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[5]_i_2_n_0\
);
\bottom_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[6]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(6),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(6),
O => p_0_out(6)
);
\bottom_right_0[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(6),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[6]_i_2_n_0\
);
\bottom_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[7]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(7),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(7),
O => p_0_out(7)
);
\bottom_right_0[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(7),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[7]_i_2_n_0\
);
\bottom_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[8]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(8),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(8),
O => p_0_out(8)
);
\bottom_right_0[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(8),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[8]_i_2_n_0\
);
\bottom_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0CC880F00CC88"
)
port map (
I0 => \bottom_right_0[15]_i_3_n_0\,
I1 => \bottom_right_0[9]_i_2_n_0\,
I2 => \bottom_right_0[15]_i_5_n_0\,
I3 => dout_0(9),
I4 => cycle(3),
I5 => \cache_reg[8]_1\(9),
O => p_0_out(9)
);
\bottom_right_0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2FFFF"
)
port map (
I0 => bottom_left_1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => dout_1(9),
I3 => cycle(2),
I4 => \cycle_reg[0]_rep_n_0\,
O => \bottom_right_0[9]_i_2_n_0\
);
\bottom_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(0),
Q => \bottom_right_0_reg_n_0_[0]\,
R => '0'
);
\bottom_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(10),
Q => \bottom_right_0_reg_n_0_[10]\,
R => '0'
);
\bottom_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(11),
Q => \bottom_right_0_reg_n_0_[11]\,
R => '0'
);
\bottom_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(12),
Q => \bottom_right_0_reg_n_0_[12]\,
R => '0'
);
\bottom_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(13),
Q => \bottom_right_0_reg_n_0_[13]\,
R => '0'
);
\bottom_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(14),
Q => \bottom_right_0_reg_n_0_[14]\,
R => '0'
);
\bottom_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(15),
Q => \bottom_right_0_reg_n_0_[15]\,
R => '0'
);
\bottom_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(1),
Q => \bottom_right_0_reg_n_0_[1]\,
R => '0'
);
\bottom_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(2),
Q => \bottom_right_0_reg_n_0_[2]\,
R => '0'
);
\bottom_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(3),
Q => \bottom_right_0_reg_n_0_[3]\,
R => '0'
);
\bottom_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(4),
Q => \bottom_right_0_reg_n_0_[4]\,
R => '0'
);
\bottom_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(5),
Q => \bottom_right_0_reg_n_0_[5]\,
R => '0'
);
\bottom_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(6),
Q => \bottom_right_0_reg_n_0_[6]\,
R => '0'
);
\bottom_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(7),
Q => \bottom_right_0_reg_n_0_[7]\,
R => '0'
);
\bottom_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(8),
Q => \bottom_right_0_reg_n_0_[8]\,
R => '0'
);
\bottom_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \bottom_right_0[15]_i_1_n_0\,
D => p_0_out(9),
Q => \bottom_right_0_reg_n_0_[9]\,
R => '0'
);
\bottom_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[0]\,
O => \bottom_right_1[0]_i_1_n_0\
);
\bottom_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(10),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[10]\,
O => \bottom_right_1[10]_i_1_n_0\
);
\bottom_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(11),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[11]\,
O => \bottom_right_1[11]_i_1_n_0\
);
\bottom_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(12),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[12]\,
O => \bottom_right_1[12]_i_1_n_0\
);
\bottom_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(13),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[13]\,
O => \bottom_right_1[13]_i_1_n_0\
);
\bottom_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(14),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[14]\,
O => \bottom_right_1[14]_i_1_n_0\
);
\bottom_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(15),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[15]\,
O => \bottom_right_1[15]_i_1_n_0\
);
\bottom_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(1),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[1]\,
O => \bottom_right_1[1]_i_1_n_0\
);
\bottom_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(2),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[2]\,
O => \bottom_right_1[2]_i_1_n_0\
);
\bottom_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(3),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[3]\,
O => \bottom_right_1[3]_i_1_n_0\
);
\bottom_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(4),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[4]\,
O => \bottom_right_1[4]_i_1_n_0\
);
\bottom_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(5),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[5]\,
O => \bottom_right_1[5]_i_1_n_0\
);
\bottom_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(6),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[6]\,
O => \bottom_right_1[6]_i_1_n_0\
);
\bottom_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(7),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[7]\,
O => \bottom_right_1[7]_i_1_n_0\
);
\bottom_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[8]\,
O => \bottom_right_1[8]_i_1_n_0\
);
\bottom_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_0(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => dout_1(9),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \bottom_left_0_reg_n_0_[9]\,
O => \bottom_right_1[9]_i_1_n_0\
);
\bottom_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[0]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[0]\,
R => '0'
);
\bottom_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[10]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[10]\,
R => '0'
);
\bottom_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[11]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[11]\,
R => '0'
);
\bottom_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[12]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[12]\,
R => '0'
);
\bottom_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[13]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[13]\,
R => '0'
);
\bottom_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[14]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[14]\,
R => '0'
);
\bottom_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[15]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[15]\,
R => '0'
);
\bottom_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[1]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[1]\,
R => '0'
);
\bottom_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[2]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[2]\,
R => '0'
);
\bottom_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[3]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[3]\,
R => '0'
);
\bottom_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[4]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[4]\,
R => '0'
);
\bottom_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[5]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[5]\,
R => '0'
);
\bottom_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[6]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[6]\,
R => '0'
);
\bottom_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[7]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[7]\,
R => '0'
);
\bottom_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[8]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[8]\,
R => '0'
);
\bottom_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \bottom_right_1[9]_i_1_n_0\,
Q => \bottom_right_1_reg_n_0_[9]\,
R => '0'
);
bram_0: entity work.system_vga_hessian_1_0_blk_mem_gen_0
port map (
addra(13) => \addr_0_reg_n_0_[13]\,
addra(12) => \addr_0_reg_n_0_[12]\,
addra(11) => \addr_0_reg_n_0_[11]\,
addra(10) => \addr_0_reg_n_0_[10]\,
addra(9) => \addr_0_reg_n_0_[9]\,
addra(8) => \addr_0_reg_n_0_[8]\,
addra(7) => \addr_0_reg_n_0_[7]\,
addra(6) => \addr_0_reg_n_0_[6]\,
addra(5) => \addr_0_reg_n_0_[5]\,
addra(4) => \addr_0_reg_n_0_[4]\,
addra(3) => \addr_0_reg_n_0_[3]\,
addra(2) => \addr_0_reg_n_0_[2]\,
addra(1) => \addr_0_reg_n_0_[1]\,
addra(0) => \addr_0_reg_n_0_[0]\,
addrb(13 downto 0) => addr_1(13 downto 0),
clka => clk_x16,
clkb => clk_x16,
dina(15) => \din_reg_n_0_[15]\,
dina(14) => \din_reg_n_0_[14]\,
dina(13) => \din_reg_n_0_[13]\,
dina(12) => \din_reg_n_0_[12]\,
dina(11) => \din_reg_n_0_[11]\,
dina(10) => \din_reg_n_0_[10]\,
dina(9) => \din_reg_n_0_[9]\,
dina(8) => \din_reg_n_0_[8]\,
dina(7) => \din_reg_n_0_[7]\,
dina(6) => \din_reg_n_0_[6]\,
dina(5) => \din_reg_n_0_[5]\,
dina(4) => \din_reg_n_0_[4]\,
dina(3) => \din_reg_n_0_[3]\,
dina(2) => \din_reg_n_0_[2]\,
dina(1) => \din_reg_n_0_[1]\,
dina(0) => \din_reg_n_0_[0]\,
dinb(15 downto 0) => B"0000000000000000",
douta(15 downto 0) => dout_0(15 downto 0),
doutb(15 downto 0) => dout_1(15 downto 0),
ena => '1',
enb => '1',
wea(0) => wen_reg_n_0,
web(0) => '0'
);
\cache[9][15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => \cache[9][15]_i_1_n_0\
);
\cache[9][15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => active,
I1 => cycle(2),
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => \cycle_reg[0]_rep_n_0\,
O => \cache[10]_5\
);
\cache_reg[0][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(0),
Q => \cache_reg[0]_4\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(10),
Q => \cache_reg[0]_4\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(11),
Q => \cache_reg[0]_4\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(12),
Q => \cache_reg[0]_4\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(13),
Q => \cache_reg[0]_4\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(14),
Q => \cache_reg[0]_4\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(15),
Q => \cache_reg[0]_4\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(1),
Q => \cache_reg[0]_4\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(2),
Q => \cache_reg[0]_4\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(3),
Q => \cache_reg[0]_4\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(4),
Q => \cache_reg[0]_4\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(5),
Q => \cache_reg[0]_4\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(6),
Q => \cache_reg[0]_4\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(7),
Q => \cache_reg[0]_4\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(8),
Q => \cache_reg[0]_4\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[0][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => Lyy_2_bottom_right(9),
Q => \cache_reg[0]_4\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(0),
Q => \cache_reg[10]_3\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(10),
Q => \cache_reg[10]_3\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(11),
Q => \cache_reg[10]_3\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(12),
Q => \cache_reg[10]_3\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(13),
Q => \cache_reg[10]_3\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(14),
Q => \cache_reg[10]_3\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(15),
Q => \cache_reg[10]_3\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(1),
Q => \cache_reg[10]_3\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(2),
Q => \cache_reg[10]_3\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(3),
Q => \cache_reg[10]_3\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(4),
Q => \cache_reg[10]_3\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(5),
Q => \cache_reg[10]_3\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(6),
Q => \cache_reg[10]_3\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(7),
Q => \cache_reg[10]_3\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(8),
Q => \cache_reg[10]_3\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[10][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[9]_2\(9),
Q => \cache_reg[10]_3\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[2][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(0),
Q => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(10),
Q => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(11),
Q => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(12),
Q => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(13),
Q => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(14),
Q => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(15),
Q => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(1),
Q => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(2),
Q => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(3),
Q => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(4),
Q => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(5),
Q => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(6),
Q => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(7),
Q => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(8),
Q => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[2][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[0]_4\(9),
Q => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[3][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[3][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[4][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__14_n_0\,
Q => \cache_reg[4]_0\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__4_n_0\,
Q => \cache_reg[4]_0\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__3_n_0\,
Q => \cache_reg[4]_0\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__2_n_0\,
Q => \cache_reg[4]_0\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__1_n_0\,
Q => \cache_reg[4]_0\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__0_n_0\,
Q => \cache_reg[4]_0\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_gate_n_0,
Q => \cache_reg[4]_0\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__13_n_0\,
Q => \cache_reg[4]_0\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__12_n_0\,
Q => \cache_reg[4]_0\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__11_n_0\,
Q => \cache_reg[4]_0\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__10_n_0\,
Q => \cache_reg[4]_0\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__9_n_0\,
Q => \cache_reg[4]_0\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__8_n_0\,
Q => \cache_reg[4]_0\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__7_n_0\,
Q => \cache_reg[4]_0\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__6_n_0\,
Q => \cache_reg[4]_0\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[4][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__5_n_0\,
Q => \cache_reg[4]_0\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[6][0]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(0),
Q => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][10]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(10),
Q => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][11]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(11),
Q => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][12]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(12),
Q => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][13]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(13),
Q => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][14]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(14),
Q => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][15]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(15),
Q => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][1]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(1),
Q => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][2]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(2),
Q => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][3]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(3),
Q => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][4]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(4),
Q => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][5]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(5),
Q => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][6]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(6),
Q => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][7]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(7),
Q => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][8]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(8),
Q => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[6][9]_srl2___U0_cache_reg_r_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => \cache[10]_5\,
CLK => clk_x16,
D => \cache_reg[4]_0\(9),
Q => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\
);
\cache_reg[7][0]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][10]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][11]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][12]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][13]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][14]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][15]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][1]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][2]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][3]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][4]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][5]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][6]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][7]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][8]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[7][9]_U0_cache_reg_r_1\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0\,
Q => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
R => '0'
);
\cache_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__30_n_0\,
Q => \cache_reg[8]_1\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__20_n_0\,
Q => \cache_reg[8]_1\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__19_n_0\,
Q => \cache_reg[8]_1\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__18_n_0\,
Q => \cache_reg[8]_1\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__17_n_0\,
Q => \cache_reg[8]_1\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__16_n_0\,
Q => \cache_reg[8]_1\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__15_n_0\,
Q => \cache_reg[8]_1\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__29_n_0\,
Q => \cache_reg[8]_1\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__28_n_0\,
Q => \cache_reg[8]_1\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__27_n_0\,
Q => \cache_reg[8]_1\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__26_n_0\,
Q => \cache_reg[8]_1\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__25_n_0\,
Q => \cache_reg[8]_1\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__24_n_0\,
Q => \cache_reg[8]_1\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__23_n_0\,
Q => \cache_reg[8]_1\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__22_n_0\,
Q => \cache_reg[8]_1\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg_gate__21_n_0\,
Q => \cache_reg[8]_1\(9),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(0),
Q => \cache_reg[9]_2\(0),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(10),
Q => \cache_reg[9]_2\(10),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(11),
Q => \cache_reg[9]_2\(11),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(12),
Q => \cache_reg[9]_2\(12),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(13),
Q => \cache_reg[9]_2\(13),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(14),
Q => \cache_reg[9]_2\(14),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(15),
Q => \cache_reg[9]_2\(15),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(1),
Q => \cache_reg[9]_2\(1),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(2),
Q => \cache_reg[9]_2\(2),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(3),
Q => \cache_reg[9]_2\(3),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(4),
Q => \cache_reg[9]_2\(4),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(5),
Q => \cache_reg[9]_2\(5),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(6),
Q => \cache_reg[9]_2\(6),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(7),
Q => \cache_reg[9]_2\(7),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(8),
Q => \cache_reg[9]_2\(8),
R => \cache[9][15]_i_1_n_0\
);
\cache_reg[9][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => \cache_reg[8]_1\(9),
Q => \cache_reg[9]_2\(9),
R => \cache[9][15]_i_1_n_0\
);
cache_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => cache_reg_gate_n_0
);
\cache_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__0_n_0\
);
\cache_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__1_n_0\
);
\cache_reg_gate__10\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__10_n_0\
);
\cache_reg_gate__11\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__11_n_0\
);
\cache_reg_gate__12\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__12_n_0\
);
\cache_reg_gate__13\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__13_n_0\
);
\cache_reg_gate__14\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__14_n_0\
);
\cache_reg_gate__15\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][15]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__15_n_0\
);
\cache_reg_gate__16\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][14]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__16_n_0\
);
\cache_reg_gate__17\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][13]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__17_n_0\
);
\cache_reg_gate__18\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__18_n_0\
);
\cache_reg_gate__19\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__19_n_0\
);
\cache_reg_gate__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][12]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__2_n_0\
);
\cache_reg_gate__20\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__20_n_0\
);
\cache_reg_gate__21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__21_n_0\
);
\cache_reg_gate__22\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__22_n_0\
);
\cache_reg_gate__23\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__23_n_0\
);
\cache_reg_gate__24\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__24_n_0\
);
\cache_reg_gate__25\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__25_n_0\
);
\cache_reg_gate__26\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][4]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__26_n_0\
);
\cache_reg_gate__27\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][3]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__27_n_0\
);
\cache_reg_gate__28\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][2]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__28_n_0\
);
\cache_reg_gate__29\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][1]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__29_n_0\
);
\cache_reg_gate__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][11]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__3_n_0\
);
\cache_reg_gate__30\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[7][0]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__30_n_0\
);
\cache_reg_gate__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][10]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__4_n_0\
);
\cache_reg_gate__5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][9]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__5_n_0\
);
\cache_reg_gate__6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][8]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__6_n_0\
);
\cache_reg_gate__7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][7]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__7_n_0\
);
\cache_reg_gate__8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][6]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__8_n_0\
);
\cache_reg_gate__9\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cache_reg[3][5]_U0_cache_reg_r_1_n_0\,
I1 => cache_reg_r_1_n_0,
O => \cache_reg_gate__9_n_0\
);
cache_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => '1',
Q => cache_reg_r_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_n_0,
Q => cache_reg_r_0_n_0,
R => \cache[9][15]_i_1_n_0\
);
cache_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \cache[10]_5\,
D => cache_reg_r_0_n_0,
Q => cache_reg_r_1_n_0,
R => \cache[9][15]_i_1_n_0\
);
\compute_addr_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(0),
O => \compute_addr_0[0]_i_1_n_0\
);
\compute_addr_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[10]_i_2_n_0\,
O => \compute_addr_0[10]_i_1_n_0\
);
\compute_addr_0[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[0]\,
I1 => data5(10),
I2 => cycle(3),
I3 => \y1_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[10]_i_2_n_0\
);
\compute_addr_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDCDC88888"
)
port map (
I0 => cycle(0),
I1 => data5(11),
I2 => cycle(3),
I3 => \y1_reg_n_0_[1]\,
I4 => \compute_addr_0[11]_i_2_n_0\,
I5 => \compute_addr_0[11]_i_3_n_0\,
O => \compute_addr_0[11]_i_1_n_0\
);
\compute_addr_0[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle(2),
I1 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_2_n_0\
);
\compute_addr_0[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAAAAAACFC0"
)
port map (
I0 => \compute_addr_2[11]_i_2_n_0\,
I1 => \y1_reg_n_0_[1]\,
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[11]_i_3_n_0\
);
\compute_addr_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[12]_i_2_n_0\,
O => \compute_addr_0[12]_i_1_n_0\
);
\compute_addr_0[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[2]\,
I1 => data5(12),
I2 => cycle(3),
I3 => \y1_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[12]_i_2_n_0\
);
\compute_addr_0[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(0),
O => compute_addr_0
);
\compute_addr_0[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_0[13]_i_3_n_0\,
O => \compute_addr_0[13]_i_2_n_0\
);
\compute_addr_0[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => \y1_reg_n_0_[3]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_0[13]_i_3_n_0\
);
\compute_addr_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(1),
O => \compute_addr_0[1]_i_1_n_0\
);
\compute_addr_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \compute_addr_0[2]_i_1_n_0\
);
\compute_addr_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(3),
O => \compute_addr_0[3]_i_1_n_0\
);
\compute_addr_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(4),
O => \compute_addr_0[4]_i_1_n_0\
);
\compute_addr_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(5),
O => \compute_addr_0[5]_i_1_n_0\
);
\compute_addr_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(6),
O => \compute_addr_0[6]_i_1_n_0\
);
\compute_addr_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \compute_addr_0[7]_i_1_n_0\
);
\compute_addr_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(8),
O => \compute_addr_0[8]_i_1_n_0\
);
\compute_addr_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data1(9),
O => \compute_addr_0[9]_i_1_n_0\
);
\compute_addr_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[0]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[0]\,
R => '0'
);
\compute_addr_0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[10]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[10]\,
R => '0'
);
\compute_addr_0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[11]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[11]\,
R => '0'
);
\compute_addr_0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[12]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[12]\,
R => '0'
);
\compute_addr_0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[13]_i_2_n_0\,
Q => \compute_addr_0_reg_n_0_[13]\,
R => '0'
);
\compute_addr_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[1]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[1]\,
R => '0'
);
\compute_addr_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[2]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[2]\,
R => '0'
);
\compute_addr_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[3]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[3]\,
R => '0'
);
\compute_addr_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[4]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[4]\,
R => '0'
);
\compute_addr_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[5]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[5]\,
R => '0'
);
\compute_addr_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[6]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[6]\,
R => '0'
);
\compute_addr_0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[7]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[7]\,
R => '0'
);
\compute_addr_0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[8]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[8]\,
R => '0'
);
\compute_addr_0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_0[9]_i_1_n_0\,
Q => \compute_addr_0_reg_n_0_[9]\,
R => '0'
);
\compute_addr_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(0),
O => \compute_addr_1[0]_i_1_n_0\
);
\compute_addr_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(10),
I1 => cycle(0),
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[10]_i_2_n_0\,
O => \compute_addr_1[10]_i_1_n_0\
);
\compute_addr_1[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(10),
I1 => data2(10),
I2 => cycle(3),
I3 => \y3_reg_n_0_[0]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[10]_i_2_n_0\
);
\compute_addr_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(11),
I1 => cycle(0),
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[11]_i_2_n_0\,
O => \compute_addr_1[11]_i_1_n_0\
);
\compute_addr_1[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(11),
I1 => data2(11),
I2 => cycle(3),
I3 => \y3_reg_n_0_[1]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[11]_i_2_n_0\
);
\compute_addr_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(12),
I1 => cycle(0),
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[12]_i_2_n_0\,
O => \compute_addr_1[12]_i_1_n_0\
);
\compute_addr_1[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACAC00000000CFC0"
)
port map (
I0 => data5(12),
I1 => data2(12),
I2 => cycle(3),
I3 => \y3_reg_n_0_[2]\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[12]_i_2_n_0\
);
\compute_addr_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBB88B8B888"
)
port map (
I0 => data5(13),
I1 => cycle(0),
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \compute_addr_1[13]_i_2_n_0\,
O => \compute_addr_1[13]_i_1_n_0\
);
\compute_addr_1[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC000000000FA0A"
)
port map (
I0 => \y3_reg_n_0_[3]\,
I1 => data5(13),
I2 => cycle(3),
I3 => data2(13),
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \compute_addr_1[13]_i_2_n_0\
);
\compute_addr_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(1),
O => \compute_addr_1[1]_i_1_n_0\
);
\compute_addr_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(2),
O => \compute_addr_1[2]_i_1_n_0\
);
\compute_addr_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(3),
O => \compute_addr_1[3]_i_1_n_0\
);
\compute_addr_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(4),
O => \compute_addr_1[4]_i_1_n_0\
);
\compute_addr_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(5),
O => \compute_addr_1[5]_i_1_n_0\
);
\compute_addr_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(6),
O => \compute_addr_1[6]_i_1_n_0\
);
\compute_addr_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(7),
O => \compute_addr_1[7]_i_1_n_0\
);
\compute_addr_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(8),
O => \compute_addr_1[8]_i_1_n_0\
);
\compute_addr_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEBFF00002800"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[1]_rep_n_0\,
I2 => cycle(2),
I3 => cycle(3),
I4 => cycle(0),
I5 => data2(9),
O => \compute_addr_1[9]_i_1_n_0\
);
\compute_addr_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[0]_i_1_n_0\,
Q => compute_addr_1(0),
R => '0'
);
\compute_addr_1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[10]_i_1_n_0\,
Q => compute_addr_1(10),
R => '0'
);
\compute_addr_1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[11]_i_1_n_0\,
Q => compute_addr_1(11),
R => '0'
);
\compute_addr_1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[12]_i_1_n_0\,
Q => compute_addr_1(12),
R => '0'
);
\compute_addr_1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[13]_i_1_n_0\,
Q => compute_addr_1(13),
R => '0'
);
\compute_addr_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[1]_i_1_n_0\,
Q => compute_addr_1(1),
R => '0'
);
\compute_addr_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[2]_i_1_n_0\,
Q => compute_addr_1(2),
R => '0'
);
\compute_addr_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[3]_i_1_n_0\,
Q => compute_addr_1(3),
R => '0'
);
\compute_addr_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[4]_i_1_n_0\,
Q => compute_addr_1(4),
R => '0'
);
\compute_addr_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[5]_i_1_n_0\,
Q => compute_addr_1(5),
R => '0'
);
\compute_addr_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[6]_i_1_n_0\,
Q => compute_addr_1(6),
R => '0'
);
\compute_addr_1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[7]_i_1_n_0\,
Q => compute_addr_1(7),
R => '0'
);
\compute_addr_1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[8]_i_1_n_0\,
Q => compute_addr_1(8),
R => '0'
);
\compute_addr_1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_0,
D => \compute_addr_1[9]_i_1_n_0\,
Q => compute_addr_1(9),
R => '0'
);
\compute_addr_2[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[0]\,
O => \compute_addr_2[10]_i_1_n_0\
);
\compute_addr_2[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[0]\,
I1 => cycle(3),
I2 => data1(10),
O => \compute_addr_2[10]_i_2_n_0\
);
\compute_addr_2[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[1]\,
O => \compute_addr_2[11]_i_1_n_0\
);
\compute_addr_2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[1]\,
I1 => cycle(3),
I2 => data1(11),
O => \compute_addr_2[11]_i_2_n_0\
);
\compute_addr_2[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[2]\,
O => \compute_addr_2[12]_i_1_n_0\
);
\compute_addr_2[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[2]\,
I1 => cycle(3),
I2 => data1(12),
O => \compute_addr_2[12]_i_2_n_0\
);
\compute_addr_2[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080808080808000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => compute_addr_2
);
\compute_addr_2[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_2[13]_i_4_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => \y1_reg_n_0_[3]\,
O => \compute_addr_2[13]_i_2_n_0\
);
\compute_addr_2[13]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"81FF"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
O => \compute_addr_2[13]_i_3_n_0\
);
\compute_addr_2[13]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y2_reg_n_0_[3]\,
I1 => cycle(3),
I2 => data1(13),
O => \compute_addr_2[13]_i_4_n_0\
);
\compute_addr_2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(0),
Q => \compute_addr_2_reg_n_0_[0]\,
R => '0'
);
\compute_addr_2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[10]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[10]\,
R => '0'
);
\compute_addr_2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[11]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[11]\,
R => '0'
);
\compute_addr_2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[12]_i_1_n_0\,
Q => \compute_addr_2_reg_n_0_[12]\,
R => '0'
);
\compute_addr_2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_2[13]_i_2_n_0\,
Q => \compute_addr_2_reg_n_0_[13]\,
R => '0'
);
\compute_addr_2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(1),
Q => \compute_addr_2_reg_n_0_[1]\,
R => '0'
);
\compute_addr_2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(2),
Q => \compute_addr_2_reg_n_0_[2]\,
R => '0'
);
\compute_addr_2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(3),
Q => \compute_addr_2_reg_n_0_[3]\,
R => '0'
);
\compute_addr_2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(4),
Q => \compute_addr_2_reg_n_0_[4]\,
R => '0'
);
\compute_addr_2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(5),
Q => \compute_addr_2_reg_n_0_[5]\,
R => '0'
);
\compute_addr_2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(6),
Q => \compute_addr_2_reg_n_0_[6]\,
R => '0'
);
\compute_addr_2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(7),
Q => \compute_addr_2_reg_n_0_[7]\,
R => '0'
);
\compute_addr_2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(8),
Q => \compute_addr_2_reg_n_0_[8]\,
R => '0'
);
\compute_addr_2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => data1(9),
Q => \compute_addr_2_reg_n_0_[9]\,
R => '0'
);
\compute_addr_3[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(0),
O => \compute_addr_3[0]_i_1_n_0\
);
\compute_addr_3[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[0]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[10]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(10),
O => \compute_addr_3[10]_i_1_n_0\
);
\compute_addr_3[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(0),
I1 => cycle(3),
I2 => y8(0),
O => \compute_addr_3[10]_i_2_n_0\
);
\compute_addr_3[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[1]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[11]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(11),
O => \compute_addr_3[11]_i_1_n_0\
);
\compute_addr_3[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(1),
I1 => cycle(3),
I2 => y8(1),
O => \compute_addr_3[11]_i_2_n_0\
);
\compute_addr_3[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[2]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[12]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(12),
O => \compute_addr_3[12]_i_1_n_0\
);
\compute_addr_3[12]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(2),
I1 => cycle(3),
I2 => y8(2),
O => \compute_addr_3[12]_i_2_n_0\
);
\compute_addr_3[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8B8BB88B8B888"
)
port map (
I0 => \y6_reg_n_0_[3]\,
I1 => \compute_addr_2[13]_i_3_n_0\,
I2 => \compute_addr_3[13]_i_2_n_0\,
I3 => cycle(2),
I4 => \cycle_reg[1]_rep_n_0\,
I5 => data2(13),
O => \compute_addr_3[13]_i_1_n_0\
);
\compute_addr_3[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => y7(3),
I1 => cycle(3),
I2 => y8(3),
O => \compute_addr_3[13]_i_2_n_0\
);
\compute_addr_3[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(1),
O => \compute_addr_3[1]_i_1_n_0\
);
\compute_addr_3[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(2),
O => \compute_addr_3[2]_i_1_n_0\
);
\compute_addr_3[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(3),
O => \compute_addr_3[3]_i_1_n_0\
);
\compute_addr_3[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(4),
O => \compute_addr_3[4]_i_1_n_0\
);
\compute_addr_3[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(5),
O => \compute_addr_3[5]_i_1_n_0\
);
\compute_addr_3[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(6),
O => \compute_addr_3[6]_i_1_n_0\
);
\compute_addr_3[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(7),
O => \compute_addr_3[7]_i_1_n_0\
);
\compute_addr_3[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(8),
O => \compute_addr_3[8]_i_1_n_0\
);
\compute_addr_3[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFFF00808000"
)
port map (
I0 => data1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(2),
I5 => data2(9),
O => \compute_addr_3[9]_i_1_n_0\
);
\compute_addr_3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[0]_i_1_n_0\,
Q => compute_addr_3(0),
R => '0'
);
\compute_addr_3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[10]_i_1_n_0\,
Q => compute_addr_3(10),
R => '0'
);
\compute_addr_3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[11]_i_1_n_0\,
Q => compute_addr_3(11),
R => '0'
);
\compute_addr_3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[12]_i_1_n_0\,
Q => compute_addr_3(12),
R => '0'
);
\compute_addr_3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[13]_i_1_n_0\,
Q => compute_addr_3(13),
R => '0'
);
\compute_addr_3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[1]_i_1_n_0\,
Q => compute_addr_3(1),
R => '0'
);
\compute_addr_3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[2]_i_1_n_0\,
Q => compute_addr_3(2),
R => '0'
);
\compute_addr_3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[3]_i_1_n_0\,
Q => compute_addr_3(3),
R => '0'
);
\compute_addr_3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[4]_i_1_n_0\,
Q => compute_addr_3(4),
R => '0'
);
\compute_addr_3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[5]_i_1_n_0\,
Q => compute_addr_3(5),
R => '0'
);
\compute_addr_3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[6]_i_1_n_0\,
Q => compute_addr_3(6),
R => '0'
);
\compute_addr_3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[7]_i_1_n_0\,
Q => compute_addr_3(7),
R => '0'
);
\compute_addr_3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[8]_i_1_n_0\,
Q => compute_addr_3(8),
R => '0'
);
\compute_addr_3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => compute_addr_2,
D => \compute_addr_3[9]_i_1_n_0\,
Q => compute_addr_3(9),
R => '0'
);
\corner[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
I5 => top,
O => corner
);
\corner_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(0),
Q => \corner_reg_n_0_[0]\,
R => corner
);
\corner_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(10),
Q => \corner_reg_n_0_[10]\,
R => corner
);
\corner_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(11),
Q => \corner_reg_n_0_[11]\,
R => corner
);
\corner_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(12),
Q => \corner_reg_n_0_[12]\,
R => corner
);
\corner_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(13),
Q => \corner_reg_n_0_[13]\,
R => corner
);
\corner_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(14),
Q => \corner_reg_n_0_[14]\,
R => corner
);
\corner_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(15),
Q => \corner_reg_n_0_[15]\,
R => corner
);
\corner_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(1),
Q => \corner_reg_n_0_[1]\,
R => corner
);
\corner_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(2),
Q => \corner_reg_n_0_[2]\,
R => corner
);
\corner_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(3),
Q => \corner_reg_n_0_[3]\,
R => corner
);
\corner_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(4),
Q => \corner_reg_n_0_[4]\,
R => corner
);
\corner_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(5),
Q => \corner_reg_n_0_[5]\,
R => corner
);
\corner_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(6),
Q => \corner_reg_n_0_[6]\,
R => corner
);
\corner_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(7),
Q => \corner_reg_n_0_[7]\,
R => corner
);
\corner_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(8),
Q => \corner_reg_n_0_[8]\,
R => corner
);
\corner_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[10]_3\(9),
Q => \corner_reg_n_0_[9]\,
R => corner
);
\cycle[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_i_1_n_0\
);
\cycle[0]_rep_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle(0),
O => \cycle[0]_rep_i_1_n_0\
);
\cycle[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_i_1_n_0\
);
\cycle[1]_rep_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1_n_0\
);
\cycle[1]_rep_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => cycle(1),
I1 => cycle(0),
O => \cycle[1]_rep_i_1__0_n_0\
);
\cycle[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => cycle(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(2),
O => \cycle[2]_i_1_n_0\
);
\cycle[2]_rep_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \cycle_reg[1]_rep_n_0\,
I1 => cycle(0),
I2 => cycle(2),
O => \cycle[2]_rep_i_1_n_0\
);
\cycle[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rst,
I1 => active,
O => \cycle[3]_i_1_n_0\
);
\cycle[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cycle(3),
I1 => cycle(2),
I2 => cycle(1),
I3 => \cycle_reg[0]_rep_n_0\,
O => \cycle[3]_i_2_n_0\
);
\cycle_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_i_1_n_0\,
Q => cycle(0),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[0]_rep_i_1_n_0\,
Q => \cycle_reg[0]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_i_1_n_0\,
Q => cycle(1),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1_n_0\,
Q => \cycle_reg[1]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[1]_rep__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[1]_rep_i_1__0_n_0\,
Q => \cycle_reg[1]_rep__0_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_i_1_n_0\,
Q => cycle(2),
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[2]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[2]_rep_i_1_n_0\,
Q => \cycle_reg[2]_rep_n_0\,
R => \cycle[3]_i_1_n_0\
);
\cycle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => \cycle[3]_i_2_n_0\,
Q => cycle(3),
R => \cycle[3]_i_1_n_0\
);
det_0_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => A(15),
A(28) => A(15),
A(27) => A(15),
A(26) => A(15),
A(25) => A(15),
A(24) => A(15),
A(23) => A(15),
A(22) => A(15),
A(21) => A(15),
A(20) => A(15),
A(19) => A(15),
A(18) => A(15),
A(17) => A(15),
A(16) => A(15),
A(15 downto 0) => A(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_0_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => B(15),
B(16) => B(15),
B(15 downto 0) => B(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_0_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_0_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => Lxx,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => det_0_reg_i_2_n_0,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => det_0,
CEP => '0',
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_det_0_reg_OVERFLOW_UNCONNECTED,
P(47 downto 0) => NLW_det_0_reg_P_UNCONNECTED(47 downto 0),
PATTERNBDETECT => NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_0_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => det_0_reg_n_106,
PCOUT(46) => det_0_reg_n_107,
PCOUT(45) => det_0_reg_n_108,
PCOUT(44) => det_0_reg_n_109,
PCOUT(43) => det_0_reg_n_110,
PCOUT(42) => det_0_reg_n_111,
PCOUT(41) => det_0_reg_n_112,
PCOUT(40) => det_0_reg_n_113,
PCOUT(39) => det_0_reg_n_114,
PCOUT(38) => det_0_reg_n_115,
PCOUT(37) => det_0_reg_n_116,
PCOUT(36) => det_0_reg_n_117,
PCOUT(35) => det_0_reg_n_118,
PCOUT(34) => det_0_reg_n_119,
PCOUT(33) => det_0_reg_n_120,
PCOUT(32) => det_0_reg_n_121,
PCOUT(31) => det_0_reg_n_122,
PCOUT(30) => det_0_reg_n_123,
PCOUT(29) => det_0_reg_n_124,
PCOUT(28) => det_0_reg_n_125,
PCOUT(27) => det_0_reg_n_126,
PCOUT(26) => det_0_reg_n_127,
PCOUT(25) => det_0_reg_n_128,
PCOUT(24) => det_0_reg_n_129,
PCOUT(23) => det_0_reg_n_130,
PCOUT(22) => det_0_reg_n_131,
PCOUT(21) => det_0_reg_n_132,
PCOUT(20) => det_0_reg_n_133,
PCOUT(19) => det_0_reg_n_134,
PCOUT(18) => det_0_reg_n_135,
PCOUT(17) => det_0_reg_n_136,
PCOUT(16) => det_0_reg_n_137,
PCOUT(15) => det_0_reg_n_138,
PCOUT(14) => det_0_reg_n_139,
PCOUT(13) => det_0_reg_n_140,
PCOUT(12) => det_0_reg_n_141,
PCOUT(11) => det_0_reg_n_142,
PCOUT(10) => det_0_reg_n_143,
PCOUT(9) => det_0_reg_n_144,
PCOUT(8) => det_0_reg_n_145,
PCOUT(7) => det_0_reg_n_146,
PCOUT(6) => det_0_reg_n_147,
PCOUT(5) => det_0_reg_n_148,
PCOUT(4) => det_0_reg_n_149,
PCOUT(3) => det_0_reg_n_150,
PCOUT(2) => det_0_reg_n_151,
PCOUT(1) => det_0_reg_n_152,
PCOUT(0) => det_0_reg_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_0_reg_UNDERFLOW_UNCONNECTED
);
det_0_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => Lxx
);
det_0_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => rst,
I5 => active,
O => det_0_reg_i_2_n_0
);
det_0_reg_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => cycle(1),
I3 => rst,
I4 => active,
I5 => \cycle_reg[0]_rep_n_0\,
O => det_0
);
\det_abs[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(10),
I1 => det_reg_n_95,
I2 => det_reg_n_74,
O => \det_abs[10]_i_1_n_0\
);
\det_abs[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(11),
I1 => det_reg_n_94,
I2 => det_reg_n_74,
O => \det_abs[11]_i_1_n_0\
);
\det_abs[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(12),
I1 => det_reg_n_93,
I2 => det_reg_n_74,
O => \det_abs[12]_i_1_n_0\
);
\det_abs[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_93,
O => \det_abs[12]_i_3_n_0\
);
\det_abs[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_94,
O => \det_abs[12]_i_4_n_0\
);
\det_abs[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_95,
O => \det_abs[12]_i_5_n_0\
);
\det_abs[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_96,
O => \det_abs[12]_i_6_n_0\
);
\det_abs[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(13),
I1 => det_reg_n_92,
I2 => det_reg_n_74,
O => \det_abs[13]_i_1_n_0\
);
\det_abs[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(14),
I1 => det_reg_n_91,
I2 => det_reg_n_74,
O => \det_abs[14]_i_1_n_0\
);
\det_abs[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(15),
I1 => det_reg_n_90,
I2 => det_reg_n_74,
O => \det_abs[15]_i_1_n_0\
);
\det_abs[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(16),
I1 => det_reg_n_89,
I2 => det_reg_n_74,
O => \det_abs[16]_i_1_n_0\
);
\det_abs[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_89,
O => \det_abs[16]_i_3_n_0\
);
\det_abs[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_90,
O => \det_abs[16]_i_4_n_0\
);
\det_abs[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_91,
O => \det_abs[16]_i_5_n_0\
);
\det_abs[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_92,
O => \det_abs[16]_i_6_n_0\
);
\det_abs[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(17),
I1 => det_reg_n_88,
I2 => det_reg_n_74,
O => \det_abs[17]_i_1_n_0\
);
\det_abs[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(18),
I1 => det_reg_n_87,
I2 => det_reg_n_74,
O => \det_abs[18]_i_1_n_0\
);
\det_abs[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(19),
I1 => det_reg_n_86,
I2 => det_reg_n_74,
O => \det_abs[19]_i_1_n_0\
);
\det_abs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(1),
I1 => det_reg_n_104,
I2 => det_reg_n_74,
O => \det_abs[1]_i_1_n_0\
);
\det_abs[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(20),
I1 => det_reg_n_85,
I2 => det_reg_n_74,
O => \det_abs[20]_i_1_n_0\
);
\det_abs[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_85,
O => \det_abs[20]_i_3_n_0\
);
\det_abs[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_86,
O => \det_abs[20]_i_4_n_0\
);
\det_abs[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_87,
O => \det_abs[20]_i_5_n_0\
);
\det_abs[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_88,
O => \det_abs[20]_i_6_n_0\
);
\det_abs[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(21),
I1 => det_reg_n_84,
I2 => det_reg_n_74,
O => \det_abs[21]_i_1_n_0\
);
\det_abs[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(22),
I1 => det_reg_n_83,
I2 => det_reg_n_74,
O => \det_abs[22]_i_1_n_0\
);
\det_abs[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(23),
I1 => det_reg_n_82,
I2 => det_reg_n_74,
O => \det_abs[23]_i_1_n_0\
);
\det_abs[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(24),
I1 => det_reg_n_81,
I2 => det_reg_n_74,
O => \det_abs[24]_i_1_n_0\
);
\det_abs[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_81,
O => \det_abs[24]_i_3_n_0\
);
\det_abs[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_82,
O => \det_abs[24]_i_4_n_0\
);
\det_abs[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_83,
O => \det_abs[24]_i_5_n_0\
);
\det_abs[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_84,
O => \det_abs[24]_i_6_n_0\
);
\det_abs[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(25),
I1 => det_reg_n_80,
I2 => det_reg_n_74,
O => \det_abs[25]_i_1_n_0\
);
\det_abs[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(26),
I1 => det_reg_n_79,
I2 => det_reg_n_74,
O => \det_abs[26]_i_1_n_0\
);
\det_abs[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(27),
I1 => det_reg_n_78,
I2 => det_reg_n_74,
O => \det_abs[27]_i_1_n_0\
);
\det_abs[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(28),
I1 => det_reg_n_77,
I2 => det_reg_n_74,
O => \det_abs[28]_i_1_n_0\
);
\det_abs[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_77,
O => \det_abs[28]_i_3_n_0\
);
\det_abs[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_78,
O => \det_abs[28]_i_4_n_0\
);
\det_abs[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_79,
O => \det_abs[28]_i_5_n_0\
);
\det_abs[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_80,
O => \det_abs[28]_i_6_n_0\
);
\det_abs[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(29),
I1 => det_reg_n_76,
I2 => det_reg_n_74,
O => \det_abs[29]_i_1_n_0\
);
\det_abs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(2),
I1 => det_reg_n_103,
I2 => det_reg_n_74,
O => \det_abs[2]_i_1_n_0\
);
\det_abs[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(30),
I1 => det_reg_n_75,
I2 => det_reg_n_74,
O => \det_abs[30]_i_1_n_0\
);
\det_abs[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => det_abs0(31),
I1 => det_reg_n_74,
O => \det_abs[31]_i_1_n_0\
);
\det_abs[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_74,
O => \det_abs[31]_i_3_n_0\
);
\det_abs[31]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_75,
O => \det_abs[31]_i_4_n_0\
);
\det_abs[31]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_76,
O => \det_abs[31]_i_5_n_0\
);
\det_abs[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(3),
I1 => det_reg_n_102,
I2 => det_reg_n_74,
O => \det_abs[3]_i_1_n_0\
);
\det_abs[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(4),
I1 => det_reg_n_101,
I2 => det_reg_n_74,
O => \det_abs[4]_i_1_n_0\
);
\det_abs[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_105,
O => \det_abs[4]_i_3_n_0\
);
\det_abs[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_101,
O => \det_abs[4]_i_4_n_0\
);
\det_abs[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_102,
O => \det_abs[4]_i_5_n_0\
);
\det_abs[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_103,
O => \det_abs[4]_i_6_n_0\
);
\det_abs[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_104,
O => \det_abs[4]_i_7_n_0\
);
\det_abs[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(5),
I1 => det_reg_n_100,
I2 => det_reg_n_74,
O => \det_abs[5]_i_1_n_0\
);
\det_abs[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(6),
I1 => det_reg_n_99,
I2 => det_reg_n_74,
O => \det_abs[6]_i_1_n_0\
);
\det_abs[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(7),
I1 => det_reg_n_98,
I2 => det_reg_n_74,
O => \det_abs[7]_i_1_n_0\
);
\det_abs[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(8),
I1 => det_reg_n_97,
I2 => det_reg_n_74,
O => \det_abs[8]_i_1_n_0\
);
\det_abs[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_97,
O => \det_abs[8]_i_3_n_0\
);
\det_abs[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_98,
O => \det_abs[8]_i_4_n_0\
);
\det_abs[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_99,
O => \det_abs[8]_i_5_n_0\
);
\det_abs[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => det_reg_n_100,
O => \det_abs[8]_i_6_n_0\
);
\det_abs[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => det_abs0(9),
I1 => det_reg_n_96,
I2 => det_reg_n_74,
O => \det_abs[9]_i_1_n_0\
);
\det_abs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => det_reg_n_105,
Q => det_abs(0),
R => '0'
);
\det_abs_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[10]_i_1_n_0\,
Q => det_abs(10),
R => '0'
);
\det_abs_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[11]_i_1_n_0\,
Q => det_abs(11),
R => '0'
);
\det_abs_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[12]_i_1_n_0\,
Q => det_abs(12),
R => '0'
);
\det_abs_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[8]_i_2_n_0\,
CO(3) => \det_abs_reg[12]_i_2_n_0\,
CO(2) => \det_abs_reg[12]_i_2_n_1\,
CO(1) => \det_abs_reg[12]_i_2_n_2\,
CO(0) => \det_abs_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(12 downto 9),
S(3) => \det_abs[12]_i_3_n_0\,
S(2) => \det_abs[12]_i_4_n_0\,
S(1) => \det_abs[12]_i_5_n_0\,
S(0) => \det_abs[12]_i_6_n_0\
);
\det_abs_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[13]_i_1_n_0\,
Q => det_abs(13),
R => '0'
);
\det_abs_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[14]_i_1_n_0\,
Q => det_abs(14),
R => '0'
);
\det_abs_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[15]_i_1_n_0\,
Q => det_abs(15),
R => '0'
);
\det_abs_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[16]_i_1_n_0\,
Q => det_abs(16),
R => '0'
);
\det_abs_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[12]_i_2_n_0\,
CO(3) => \det_abs_reg[16]_i_2_n_0\,
CO(2) => \det_abs_reg[16]_i_2_n_1\,
CO(1) => \det_abs_reg[16]_i_2_n_2\,
CO(0) => \det_abs_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(16 downto 13),
S(3) => \det_abs[16]_i_3_n_0\,
S(2) => \det_abs[16]_i_4_n_0\,
S(1) => \det_abs[16]_i_5_n_0\,
S(0) => \det_abs[16]_i_6_n_0\
);
\det_abs_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[17]_i_1_n_0\,
Q => det_abs(17),
R => '0'
);
\det_abs_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[18]_i_1_n_0\,
Q => det_abs(18),
R => '0'
);
\det_abs_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[19]_i_1_n_0\,
Q => det_abs(19),
R => '0'
);
\det_abs_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[1]_i_1_n_0\,
Q => det_abs(1),
R => '0'
);
\det_abs_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[20]_i_1_n_0\,
Q => det_abs(20),
R => '0'
);
\det_abs_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[16]_i_2_n_0\,
CO(3) => \det_abs_reg[20]_i_2_n_0\,
CO(2) => \det_abs_reg[20]_i_2_n_1\,
CO(1) => \det_abs_reg[20]_i_2_n_2\,
CO(0) => \det_abs_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(20 downto 17),
S(3) => \det_abs[20]_i_3_n_0\,
S(2) => \det_abs[20]_i_4_n_0\,
S(1) => \det_abs[20]_i_5_n_0\,
S(0) => \det_abs[20]_i_6_n_0\
);
\det_abs_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[21]_i_1_n_0\,
Q => det_abs(21),
R => '0'
);
\det_abs_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[22]_i_1_n_0\,
Q => det_abs(22),
R => '0'
);
\det_abs_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[23]_i_1_n_0\,
Q => det_abs(23),
R => '0'
);
\det_abs_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[24]_i_1_n_0\,
Q => det_abs(24),
R => '0'
);
\det_abs_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[20]_i_2_n_0\,
CO(3) => \det_abs_reg[24]_i_2_n_0\,
CO(2) => \det_abs_reg[24]_i_2_n_1\,
CO(1) => \det_abs_reg[24]_i_2_n_2\,
CO(0) => \det_abs_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(24 downto 21),
S(3) => \det_abs[24]_i_3_n_0\,
S(2) => \det_abs[24]_i_4_n_0\,
S(1) => \det_abs[24]_i_5_n_0\,
S(0) => \det_abs[24]_i_6_n_0\
);
\det_abs_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[25]_i_1_n_0\,
Q => det_abs(25),
R => '0'
);
\det_abs_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[26]_i_1_n_0\,
Q => det_abs(26),
R => '0'
);
\det_abs_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[27]_i_1_n_0\,
Q => det_abs(27),
R => '0'
);
\det_abs_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[28]_i_1_n_0\,
Q => det_abs(28),
R => '0'
);
\det_abs_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[24]_i_2_n_0\,
CO(3) => \det_abs_reg[28]_i_2_n_0\,
CO(2) => \det_abs_reg[28]_i_2_n_1\,
CO(1) => \det_abs_reg[28]_i_2_n_2\,
CO(0) => \det_abs_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(28 downto 25),
S(3) => \det_abs[28]_i_3_n_0\,
S(2) => \det_abs[28]_i_4_n_0\,
S(1) => \det_abs[28]_i_5_n_0\,
S(0) => \det_abs[28]_i_6_n_0\
);
\det_abs_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[29]_i_1_n_0\,
Q => det_abs(29),
R => '0'
);
\det_abs_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[2]_i_1_n_0\,
Q => det_abs(2),
R => '0'
);
\det_abs_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[30]_i_1_n_0\,
Q => det_abs(30),
R => '0'
);
\det_abs_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[31]_i_1_n_0\,
Q => det_abs(31),
R => '0'
);
\det_abs_reg[31]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \det_abs_reg[31]_i_2_n_2\,
CO(0) => \det_abs_reg[31]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_det_abs_reg[31]_i_2_O_UNCONNECTED\(3),
O(2 downto 0) => det_abs0(31 downto 29),
S(3) => '0',
S(2) => \det_abs[31]_i_3_n_0\,
S(1) => \det_abs[31]_i_4_n_0\,
S(0) => \det_abs[31]_i_5_n_0\
);
\det_abs_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[3]_i_1_n_0\,
Q => det_abs(3),
R => '0'
);
\det_abs_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[4]_i_1_n_0\,
Q => det_abs(4),
R => '0'
);
\det_abs_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \det_abs_reg[4]_i_2_n_0\,
CO(2) => \det_abs_reg[4]_i_2_n_1\,
CO(1) => \det_abs_reg[4]_i_2_n_2\,
CO(0) => \det_abs_reg[4]_i_2_n_3\,
CYINIT => \det_abs[4]_i_3_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(4 downto 1),
S(3) => \det_abs[4]_i_4_n_0\,
S(2) => \det_abs[4]_i_5_n_0\,
S(1) => \det_abs[4]_i_6_n_0\,
S(0) => \det_abs[4]_i_7_n_0\
);
\det_abs_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[5]_i_1_n_0\,
Q => det_abs(5),
R => '0'
);
\det_abs_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[6]_i_1_n_0\,
Q => det_abs(6),
R => '0'
);
\det_abs_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[7]_i_1_n_0\,
Q => det_abs(7),
R => '0'
);
\det_abs_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[8]_i_1_n_0\,
Q => det_abs(8),
R => '0'
);
\det_abs_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \det_abs_reg[4]_i_2_n_0\,
CO(3) => \det_abs_reg[8]_i_2_n_0\,
CO(2) => \det_abs_reg[8]_i_2_n_1\,
CO(1) => \det_abs_reg[8]_i_2_n_2\,
CO(0) => \det_abs_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => det_abs0(8 downto 5),
S(3) => \det_abs[8]_i_3_n_0\,
S(2) => \det_abs[8]_i_4_n_0\,
S(1) => \det_abs[8]_i_5_n_0\,
S(0) => \det_abs[8]_i_6_n_0\
);
\det_abs_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => y6,
D => \det_abs[9]_i_1_n_0\,
Q => det_abs(9),
R => '0'
);
det_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 1,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \Lxy0__1_carry__2_n_4\,
A(28) => \Lxy0__1_carry__2_n_4\,
A(27) => \Lxy0__1_carry__2_n_4\,
A(26) => \Lxy0__1_carry__2_n_4\,
A(25) => \Lxy0__1_carry__2_n_4\,
A(24) => \Lxy0__1_carry__2_n_4\,
A(23) => \Lxy0__1_carry__2_n_4\,
A(22) => \Lxy0__1_carry__2_n_4\,
A(21) => \Lxy0__1_carry__2_n_4\,
A(20) => \Lxy0__1_carry__2_n_4\,
A(19) => \Lxy0__1_carry__2_n_4\,
A(18) => \Lxy0__1_carry__2_n_4\,
A(17) => \Lxy0__1_carry__2_n_4\,
A(16) => \Lxy0__1_carry__2_n_4\,
A(15) => \Lxy0__1_carry__2_n_4\,
A(14) => \Lxy0__1_carry__2_n_5\,
A(13) => \Lxy0__1_carry__2_n_6\,
A(12) => \Lxy0__1_carry__2_n_7\,
A(11) => \Lxy0__1_carry__1_n_4\,
A(10) => \Lxy0__1_carry__1_n_5\,
A(9) => \Lxy0__1_carry__1_n_6\,
A(8) => \Lxy0__1_carry__1_n_7\,
A(7) => \Lxy0__1_carry__0_n_4\,
A(6) => \Lxy0__1_carry__0_n_5\,
A(5) => \Lxy0__1_carry__0_n_6\,
A(4) => \Lxy0__1_carry__0_n_7\,
A(3) => \Lxy0__1_carry_n_4\,
A(2) => \Lxy0__1_carry_n_5\,
A(1) => \Lxy0__1_carry_n_6\,
A(0) => \Lxy0__1_carry_n_7\,
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_det_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0011",
B(17) => \Lxy0__1_carry__2_n_4\,
B(16) => \Lxy0__1_carry__2_n_4\,
B(15) => \Lxy0__1_carry__2_n_4\,
B(14) => \Lxy0__1_carry__2_n_5\,
B(13) => \Lxy0__1_carry__2_n_6\,
B(12) => \Lxy0__1_carry__2_n_7\,
B(11) => \Lxy0__1_carry__1_n_4\,
B(10) => \Lxy0__1_carry__1_n_5\,
B(9) => \Lxy0__1_carry__1_n_6\,
B(8) => \Lxy0__1_carry__1_n_7\,
B(7) => \Lxy0__1_carry__0_n_4\,
B(6) => \Lxy0__1_carry__0_n_5\,
B(5) => \Lxy0__1_carry__0_n_6\,
B(4) => \Lxy0__1_carry__0_n_7\,
B(3) => \Lxy0__1_carry_n_4\,
B(2) => \Lxy0__1_carry_n_5\,
B(1) => \Lxy0__1_carry_n_6\,
B(0) => \Lxy0__1_carry_n_7\,
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_det_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_det_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_det_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => y3,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => y3,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => y2,
CEP => y9,
CLK => clk_x16,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_det_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0010101",
OVERFLOW => NLW_det_reg_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_det_reg_P_UNCONNECTED(47 downto 32),
P(31) => det_reg_n_74,
P(30) => det_reg_n_75,
P(29) => det_reg_n_76,
P(28) => det_reg_n_77,
P(27) => det_reg_n_78,
P(26) => det_reg_n_79,
P(25) => det_reg_n_80,
P(24) => det_reg_n_81,
P(23) => det_reg_n_82,
P(22) => det_reg_n_83,
P(21) => det_reg_n_84,
P(20) => det_reg_n_85,
P(19) => det_reg_n_86,
P(18) => det_reg_n_87,
P(17) => det_reg_n_88,
P(16) => det_reg_n_89,
P(15) => det_reg_n_90,
P(14) => det_reg_n_91,
P(13) => det_reg_n_92,
P(12) => det_reg_n_93,
P(11) => det_reg_n_94,
P(10) => det_reg_n_95,
P(9) => det_reg_n_96,
P(8) => det_reg_n_97,
P(7) => det_reg_n_98,
P(6) => det_reg_n_99,
P(5) => det_reg_n_100,
P(4) => det_reg_n_101,
P(3) => det_reg_n_102,
P(2) => det_reg_n_103,
P(1) => det_reg_n_104,
P(0) => det_reg_n_105,
PATTERNBDETECT => NLW_det_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_det_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47) => det_0_reg_n_106,
PCIN(46) => det_0_reg_n_107,
PCIN(45) => det_0_reg_n_108,
PCIN(44) => det_0_reg_n_109,
PCIN(43) => det_0_reg_n_110,
PCIN(42) => det_0_reg_n_111,
PCIN(41) => det_0_reg_n_112,
PCIN(40) => det_0_reg_n_113,
PCIN(39) => det_0_reg_n_114,
PCIN(38) => det_0_reg_n_115,
PCIN(37) => det_0_reg_n_116,
PCIN(36) => det_0_reg_n_117,
PCIN(35) => det_0_reg_n_118,
PCIN(34) => det_0_reg_n_119,
PCIN(33) => det_0_reg_n_120,
PCIN(32) => det_0_reg_n_121,
PCIN(31) => det_0_reg_n_122,
PCIN(30) => det_0_reg_n_123,
PCIN(29) => det_0_reg_n_124,
PCIN(28) => det_0_reg_n_125,
PCIN(27) => det_0_reg_n_126,
PCIN(26) => det_0_reg_n_127,
PCIN(25) => det_0_reg_n_128,
PCIN(24) => det_0_reg_n_129,
PCIN(23) => det_0_reg_n_130,
PCIN(22) => det_0_reg_n_131,
PCIN(21) => det_0_reg_n_132,
PCIN(20) => det_0_reg_n_133,
PCIN(19) => det_0_reg_n_134,
PCIN(18) => det_0_reg_n_135,
PCIN(17) => det_0_reg_n_136,
PCIN(16) => det_0_reg_n_137,
PCIN(15) => det_0_reg_n_138,
PCIN(14) => det_0_reg_n_139,
PCIN(13) => det_0_reg_n_140,
PCIN(12) => det_0_reg_n_141,
PCIN(11) => det_0_reg_n_142,
PCIN(10) => det_0_reg_n_143,
PCIN(9) => det_0_reg_n_144,
PCIN(8) => det_0_reg_n_145,
PCIN(7) => det_0_reg_n_146,
PCIN(6) => det_0_reg_n_147,
PCIN(5) => det_0_reg_n_148,
PCIN(4) => det_0_reg_n_149,
PCIN(3) => det_0_reg_n_150,
PCIN(2) => det_0_reg_n_151,
PCIN(1) => det_0_reg_n_152,
PCIN(0) => det_0_reg_n_153,
PCOUT(47 downto 0) => NLW_det_reg_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_det_reg_UNDERFLOW_UNCONNECTED
);
det_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y2
);
det_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y9
);
\din_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(0),
Q => \din_reg_n_0_[0]\,
R => '0'
);
\din_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(10),
Q => \din_reg_n_0_[10]\,
R => '0'
);
\din_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(11),
Q => \din_reg_n_0_[11]\,
R => '0'
);
\din_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(12),
Q => \din_reg_n_0_[12]\,
R => '0'
);
\din_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(13),
Q => \din_reg_n_0_[13]\,
R => '0'
);
\din_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(14),
Q => \din_reg_n_0_[14]\,
R => '0'
);
\din_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(15),
Q => \din_reg_n_0_[15]\,
R => '0'
);
\din_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(1),
Q => \din_reg_n_0_[1]\,
R => '0'
);
\din_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(2),
Q => \din_reg_n_0_[2]\,
R => '0'
);
\din_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(3),
Q => \din_reg_n_0_[3]\,
R => '0'
);
\din_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(4),
Q => \din_reg_n_0_[4]\,
R => '0'
);
\din_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(5),
Q => \din_reg_n_0_[5]\,
R => '0'
);
\din_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(6),
Q => \din_reg_n_0_[6]\,
R => '0'
);
\din_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(7),
Q => \din_reg_n_0_[7]\,
R => '0'
);
\din_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(8),
Q => \din_reg_n_0_[8]\,
R => '0'
);
\din_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => det_0_reg_i_2_n_0,
D => \cache_reg[8]_1\(9),
Q => \din_reg_n_0_[9]\,
R => '0'
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => y3
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(0),
Q => hessian_out(0),
R => '0'
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(10),
Q => hessian_out(10),
R => '0'
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(11),
Q => hessian_out(11),
R => '0'
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(12),
Q => hessian_out(12),
R => '0'
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(13),
Q => hessian_out(13),
R => '0'
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(14),
Q => hessian_out(14),
R => '0'
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(15),
Q => hessian_out(15),
R => '0'
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(16),
Q => hessian_out(16),
R => '0'
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(17),
Q => hessian_out(17),
R => '0'
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(18),
Q => hessian_out(18),
R => '0'
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(19),
Q => hessian_out(19),
R => '0'
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(1),
Q => hessian_out(1),
R => '0'
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(20),
Q => hessian_out(20),
R => '0'
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(21),
Q => hessian_out(21),
R => '0'
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(22),
Q => hessian_out(22),
R => '0'
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(23),
Q => hessian_out(23),
R => '0'
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(24),
Q => hessian_out(24),
R => '0'
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(25),
Q => hessian_out(25),
R => '0'
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(26),
Q => hessian_out(26),
R => '0'
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(27),
Q => hessian_out(27),
R => '0'
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(28),
Q => hessian_out(28),
R => '0'
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(29),
Q => hessian_out(29),
R => '0'
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(2),
Q => hessian_out(2),
R => '0'
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(30),
Q => hessian_out(30),
R => '0'
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(31),
Q => hessian_out(31),
R => '0'
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(3),
Q => hessian_out(3),
R => '0'
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(4),
Q => hessian_out(4),
R => '0'
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(5),
Q => hessian_out(5),
R => '0'
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(6),
Q => hessian_out(6),
R => '0'
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(7),
Q => hessian_out(7),
R => '0'
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(8),
Q => hessian_out(8),
R => '0'
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => det_abs(9),
Q => hessian_out(9),
R => '0'
);
\i__carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(3),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[7]\,
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[6]\,
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[5]\,
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[4]\,
O => \i__carry__0_i_5_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[9]\,
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[8]\,
O => \i__carry__1_i_2_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0020FFDF"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[3]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => cycle(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55599555"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"5595"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
O => \i__carry_i_4_n_0\
);
\last_value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[0]\,
Q => last_value(0),
R => '0'
);
\last_value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[1]\,
Q => last_value(1),
R => '0'
);
\last_value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[2]\,
Q => last_value(2),
R => '0'
);
\last_value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[3]\,
Q => last_value(3),
R => '0'
);
\last_value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[4]\,
Q => last_value(4),
R => '0'
);
\last_value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[5]\,
Q => last_value(5),
R => '0'
);
\last_value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[6]\,
Q => last_value(6),
R => '0'
);
\last_value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \value_reg_n_0_[7]\,
Q => last_value(7),
R => '0'
);
\left[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \left[15]_i_2_n_0\,
I1 => x,
I2 => \x_reg_n_0_[0]\,
I3 => \x_reg_n_0_[9]\,
I4 => \x_reg_n_0_[8]\,
O => left
);
\left[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[6]\,
I3 => \left[15]_i_3_n_0\,
O => \left[15]_i_2_n_0\
);
\left[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \left[15]_i_3_n_0\
);
\left_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(0),
Q => \left_reg_n_0_[0]\,
R => left
);
\left_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(10),
Q => \left_reg_n_0_[10]\,
R => left
);
\left_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(11),
Q => \left_reg_n_0_[11]\,
R => left
);
\left_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(12),
Q => \left_reg_n_0_[12]\,
R => left
);
\left_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(13),
Q => \left_reg_n_0_[13]\,
R => left
);
\left_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(14),
Q => \left_reg_n_0_[14]\,
R => left
);
\left_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(15),
Q => \left_reg_n_0_[15]\,
R => left
);
\left_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(1),
Q => \left_reg_n_0_[1]\,
R => left
);
\left_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(2),
Q => \left_reg_n_0_[2]\,
R => left
);
\left_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(3),
Q => \left_reg_n_0_[3]\,
R => left
);
\left_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(4),
Q => \left_reg_n_0_[4]\,
R => left
);
\left_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(5),
Q => \left_reg_n_0_[5]\,
R => left
);
\left_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(6),
Q => \left_reg_n_0_[6]\,
R => left
);
\left_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(7),
Q => \left_reg_n_0_[7]\,
R => left
);
\left_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(8),
Q => \left_reg_n_0_[8]\,
R => left
);
\left_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[0]_4\(9),
Q => \left_reg_n_0_[9]\,
R => left
);
\plusOp_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \plusOp_inferred__0/i__carry_n_0\,
CO(2) => \plusOp_inferred__0/i__carry_n_1\,
CO(1) => \plusOp_inferred__0/i__carry_n_2\,
CO(0) => \plusOp_inferred__0/i__carry_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[3]\,
DI(2) => \x_reg_n_0_[2]\,
DI(1) => \x_reg_n_0_[1]\,
DI(0) => \x_reg_n_0_[0]\,
O(3) => \plusOp_inferred__0/i__carry_n_4\,
O(2) => \plusOp_inferred__0/i__carry_n_5\,
O(1) => \plusOp_inferred__0/i__carry_n_6\,
O(0) => \plusOp_inferred__0/i__carry_n_7\,
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\plusOp_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry_n_0\,
CO(3) => \plusOp_inferred__0/i__carry__0_n_0\,
CO(2) => \plusOp_inferred__0/i__carry__0_n_1\,
CO(1) => \plusOp_inferred__0/i__carry__0_n_2\,
CO(0) => \plusOp_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_reg_n_0_[6]\,
DI(2) => \x_reg_n_0_[5]\,
DI(1) => \x_reg_n_0_[4]\,
DI(0) => \i__carry__0_i_1_n_0\,
O(3) => \plusOp_inferred__0/i__carry__0_n_4\,
O(2) => \plusOp_inferred__0/i__carry__0_n_5\,
O(1) => \plusOp_inferred__0/i__carry__0_n_6\,
O(0) => \plusOp_inferred__0/i__carry__0_n_7\,
S(3) => \i__carry__0_i_2_n_0\,
S(2) => \i__carry__0_i_3_n_0\,
S(1) => \i__carry__0_i_4_n_0\,
S(0) => \i__carry__0_i_5_n_0\
);
\plusOp_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_inferred__0/i__carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_reg_n_0_[7]\,
O(3 downto 2) => \NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_inferred__0/i__carry__1_n_6\,
O(0) => \plusOp_inferred__0/i__carry__1_n_7\,
S(3 downto 2) => B"00",
S(1) => \i__carry__1_i_1_n_0\,
S(0) => \i__carry__1_i_2_n_0\
);
\top[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => x,
I1 => \top[15]_i_2_n_0\,
I2 => \y_actual_reg_n_0_[3]\,
I3 => \y_actual_reg_n_0_[0]\,
I4 => \y_actual_reg_n_0_[1]\,
I5 => \y_actual_reg_n_0_[2]\,
O => top
);
\top[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \y_actual_reg_n_0_[8]\,
I1 => \y_actual_reg_n_0_[9]\,
I2 => \y_actual_reg_n_0_[6]\,
I3 => \y_actual_reg_n_0_[7]\,
I4 => \y_actual_reg_n_0_[4]\,
I5 => \y_actual_reg_n_0_[5]\,
O => \top[15]_i_2_n_0\
);
\top_left_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(0),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_left_0[0]_i_1_n_0\
);
\top_left_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(10),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_left_0[10]_i_1_n_0\
);
\top_left_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(11),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_left_0[11]_i_1_n_0\
);
\top_left_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(12),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_left_0[12]_i_1_n_0\
);
\top_left_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(13),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_left_0[13]_i_1_n_0\
);
\top_left_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(14),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_left_0[14]_i_1_n_0\
);
\top_left_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000700010000000"
)
port map (
I0 => cycle(2),
I1 => cycle(3),
I2 => rst,
I3 => active,
I4 => \cycle_reg[0]_rep_n_0\,
I5 => \cycle_reg[1]_rep_n_0\,
O => top_left_0
);
\top_left_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(15),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_left_0[15]_i_2_n_0\
);
\top_left_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(1),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_left_0[1]_i_1_n_0\
);
\top_left_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(2),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_left_0[2]_i_1_n_0\
);
\top_left_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(3),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_left_0[3]_i_1_n_0\
);
\top_left_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(4),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_left_0[4]_i_1_n_0\
);
\top_left_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(5),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_left_0[5]_i_1_n_0\
);
\top_left_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(6),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_left_0[6]_i_1_n_0\
);
\top_left_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(7),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_left_0[7]_i_1_n_0\
);
\top_left_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(8),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_left_0[8]_i_1_n_0\
);
\top_left_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => dout_0(9),
I1 => cycle(2),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_left_0[9]_i_1_n_0\
);
\top_left_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[0]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[0]\,
R => '0'
);
\top_left_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[10]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[10]\,
R => '0'
);
\top_left_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[11]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[11]\,
R => '0'
);
\top_left_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[12]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[12]\,
R => '0'
);
\top_left_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[13]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[13]\,
R => '0'
);
\top_left_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[14]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[14]\,
R => '0'
);
\top_left_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[15]_i_2_n_0\,
Q => \top_left_0_reg_n_0_[15]\,
R => '0'
);
\top_left_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[1]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[1]\,
R => '0'
);
\top_left_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[2]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[2]\,
R => '0'
);
\top_left_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[3]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[3]\,
R => '0'
);
\top_left_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[4]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[4]\,
R => '0'
);
\top_left_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[5]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[5]\,
R => '0'
);
\top_left_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[6]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[6]\,
R => '0'
);
\top_left_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[7]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[7]\,
R => '0'
);
\top_left_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[8]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[8]\,
R => '0'
);
\top_left_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_left_0,
D => \top_left_0[9]_i_1_n_0\,
Q => \top_left_0_reg_n_0_[9]\,
R => '0'
);
\top_left_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(0),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[0]\,
O => \top_left_1[0]_i_1_n_0\
);
\top_left_1[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(10),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[10]\,
O => \top_left_1[10]_i_1_n_0\
);
\top_left_1[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(11),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[11]\,
O => \top_left_1[11]_i_1_n_0\
);
\top_left_1[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(12),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[12]\,
O => \top_left_1[12]_i_1_n_0\
);
\top_left_1[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(13),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[13]\,
O => \top_left_1[13]_i_1_n_0\
);
\top_left_1[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(14),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[14]\,
O => \top_left_1[14]_i_1_n_0\
);
\top_left_1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \cycle_reg[0]_rep_n_0\,
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep__0_n_0\,
O => bottom_right_1
);
\top_left_1[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(15),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \bottom_left_0_reg_n_0_[15]\,
O => \top_left_1[15]_i_2_n_0\
);
\top_left_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(1),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[1]\,
O => \top_left_1[1]_i_1_n_0\
);
\top_left_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(2),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[2]\,
O => \top_left_1[2]_i_1_n_0\
);
\top_left_1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(3),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[3]\,
O => \top_left_1[3]_i_1_n_0\
);
\top_left_1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(4),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[4]\,
O => \top_left_1[4]_i_1_n_0\
);
\top_left_1[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(5),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[5]\,
O => \top_left_1[5]_i_1_n_0\
);
\top_left_1[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(6),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[6]\,
O => \top_left_1[6]_i_1_n_0\
);
\top_left_1[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(7),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[7]\,
O => \top_left_1[7]_i_1_n_0\
);
\top_left_1[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(8),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[8]\,
O => \top_left_1[8]_i_1_n_0\
);
\top_left_1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAA8AAAA"
)
port map (
I0 => dout_1(9),
I1 => \cycle_reg[0]_rep_n_0\,
I2 => cycle(3),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(2),
I5 => \bottom_left_0_reg_n_0_[9]\,
O => \top_left_1[9]_i_1_n_0\
);
\top_left_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[0]_i_1_n_0\,
Q => top_left_1(0),
R => '0'
);
\top_left_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[10]_i_1_n_0\,
Q => top_left_1(10),
R => '0'
);
\top_left_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[11]_i_1_n_0\,
Q => top_left_1(11),
R => '0'
);
\top_left_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[12]_i_1_n_0\,
Q => top_left_1(12),
R => '0'
);
\top_left_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[13]_i_1_n_0\,
Q => top_left_1(13),
R => '0'
);
\top_left_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[14]_i_1_n_0\,
Q => top_left_1(14),
R => '0'
);
\top_left_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[15]_i_2_n_0\,
Q => top_left_1(15),
R => '0'
);
\top_left_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[1]_i_1_n_0\,
Q => top_left_1(1),
R => '0'
);
\top_left_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[2]_i_1_n_0\,
Q => top_left_1(2),
R => '0'
);
\top_left_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[3]_i_1_n_0\,
Q => top_left_1(3),
R => '0'
);
\top_left_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[4]_i_1_n_0\,
Q => top_left_1(4),
R => '0'
);
\top_left_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[5]_i_1_n_0\,
Q => top_left_1(5),
R => '0'
);
\top_left_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[6]_i_1_n_0\,
Q => top_left_1(6),
R => '0'
);
\top_left_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[7]_i_1_n_0\,
Q => top_left_1(7),
R => '0'
);
\top_left_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[8]_i_1_n_0\,
Q => top_left_1(8),
R => '0'
);
\top_left_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => bottom_right_1,
D => \top_left_1[9]_i_1_n_0\,
Q => top_left_1(9),
R => '0'
);
\top_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(0),
Q => \top_reg_n_0_[0]\,
R => top
);
\top_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(10),
Q => \top_reg_n_0_[10]\,
R => top
);
\top_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(11),
Q => \top_reg_n_0_[11]\,
R => top
);
\top_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(12),
Q => \top_reg_n_0_[12]\,
R => top
);
\top_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(13),
Q => \top_reg_n_0_[13]\,
R => top
);
\top_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(14),
Q => \top_reg_n_0_[14]\,
R => top
);
\top_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(15),
Q => \top_reg_n_0_[15]\,
R => top
);
\top_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(1),
Q => \top_reg_n_0_[1]\,
R => top
);
\top_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(2),
Q => \top_reg_n_0_[2]\,
R => top
);
\top_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(3),
Q => \top_reg_n_0_[3]\,
R => top
);
\top_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(4),
Q => \top_reg_n_0_[4]\,
R => top
);
\top_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(5),
Q => \top_reg_n_0_[5]\,
R => top
);
\top_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(6),
Q => \top_reg_n_0_[6]\,
R => top
);
\top_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(7),
Q => \top_reg_n_0_[7]\,
R => top
);
\top_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(8),
Q => \top_reg_n_0_[8]\,
R => top
);
\top_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => \cache_reg[9]_2\(9),
Q => \top_reg_n_0_[9]\,
R => top
);
\top_right_0[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(0),
O => \top_right_0[0]_i_1_n_0\
);
\top_right_0[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(10),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(10),
O => \top_right_0[10]_i_1_n_0\
);
\top_right_0[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(11),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(11),
O => \top_right_0[11]_i_1_n_0\
);
\top_right_0[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(12),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(12),
O => \top_right_0[12]_i_1_n_0\
);
\top_right_0[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(13),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(13),
O => \top_right_0[13]_i_1_n_0\
);
\top_right_0[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(14),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(14),
O => \top_right_0[14]_i_1_n_0\
);
\top_right_0[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0880000080080800"
)
port map (
I0 => rst,
I1 => active,
I2 => cycle(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => top_right_0
);
\top_right_0[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(15),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(15),
O => \top_right_0[15]_i_2_n_0\
);
\top_right_0[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(1),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(1),
O => \top_right_0[1]_i_1_n_0\
);
\top_right_0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(2),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(2),
O => \top_right_0[2]_i_1_n_0\
);
\top_right_0[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(3),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(3),
O => \top_right_0[3]_i_1_n_0\
);
\top_right_0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(4),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(4),
O => \top_right_0[4]_i_1_n_0\
);
\top_right_0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(5),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(5),
O => \top_right_0[5]_i_1_n_0\
);
\top_right_0[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(6),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(6),
O => \top_right_0[6]_i_1_n_0\
);
\top_right_0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(7),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(7),
O => \top_right_0[7]_i_1_n_0\
);
\top_right_0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(8),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(8),
O => \top_right_0[8]_i_1_n_0\
);
\top_right_0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEF00000020"
)
port map (
I0 => top_left_1(9),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(3),
I5 => dout_1(9),
O => \top_right_0[9]_i_1_n_0\
);
\top_right_0_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[0]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[0]\,
R => '0'
);
\top_right_0_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[10]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[10]\,
R => '0'
);
\top_right_0_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[11]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[11]\,
R => '0'
);
\top_right_0_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[12]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[12]\,
R => '0'
);
\top_right_0_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[13]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[13]\,
R => '0'
);
\top_right_0_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[14]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[14]\,
R => '0'
);
\top_right_0_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[15]_i_2_n_0\,
Q => \top_right_0_reg_n_0_[15]\,
R => '0'
);
\top_right_0_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[1]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[1]\,
R => '0'
);
\top_right_0_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[2]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[2]\,
R => '0'
);
\top_right_0_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[3]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[3]\,
R => '0'
);
\top_right_0_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[4]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[4]\,
R => '0'
);
\top_right_0_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[5]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[5]\,
R => '0'
);
\top_right_0_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[6]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[6]\,
R => '0'
);
\top_right_0_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[7]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[7]\,
R => '0'
);
\top_right_0_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[8]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[8]\,
R => '0'
);
\top_right_0_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_0,
D => \top_right_0[9]_i_1_n_0\,
Q => \top_right_0_reg_n_0_[9]\,
R => '0'
);
\top_right_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(0),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[0]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[0]\,
O => \top_right_1[0]_i_1_n_0\
);
\top_right_1[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(10),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[10]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[10]\,
O => \top_right_1[10]_i_1_n_0\
);
\top_right_1[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(11),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[11]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[11]\,
O => \top_right_1[11]_i_1_n_0\
);
\top_right_1[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(12),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[12]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[12]\,
O => \top_right_1[12]_i_1_n_0\
);
\top_right_1[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(13),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[13]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[13]\,
O => \top_right_1[13]_i_1_n_0\
);
\top_right_1[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(14),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[14]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[14]\,
O => \top_right_1[14]_i_1_n_0\
);
\top_right_1[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(15),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[15]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[15]\,
O => \top_right_1[15]_i_1_n_0\
);
\top_right_1[15]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => cycle(3),
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \top_right_1[15]_i_2_n_0\
);
\top_right_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(1),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[1]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[1]\,
O => \top_right_1[1]_i_1_n_0\
);
\top_right_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(2),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[2]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[2]\,
O => \top_right_1[2]_i_1_n_0\
);
\top_right_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(3),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[3]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[3]\,
O => \top_right_1[3]_i_1_n_0\
);
\top_right_1[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(4),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[4]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[4]\,
O => \top_right_1[4]_i_1_n_0\
);
\top_right_1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(5),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[5]\,
O => \top_right_1[5]_i_1_n_0\
);
\top_right_1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(6),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[6]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[6]\,
O => \top_right_1[6]_i_1_n_0\
);
\top_right_1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(7),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[7]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[7]\,
O => \top_right_1[7]_i_1_n_0\
);
\top_right_1[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(8),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[8]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[8]\,
O => \top_right_1[8]_i_1_n_0\
);
\top_right_1[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => dout_1(9),
I1 => \top_right_1[15]_i_2_n_0\,
I2 => \bottom_right_0_reg_n_0_[9]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \top_left_0_reg_n_0_[9]\,
O => \top_right_1[9]_i_1_n_0\
);
\top_right_1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[0]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[0]\,
R => '0'
);
\top_right_1_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[10]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[10]\,
R => '0'
);
\top_right_1_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[11]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[11]\,
R => '0'
);
\top_right_1_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[12]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[12]\,
R => '0'
);
\top_right_1_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[13]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[13]\,
R => '0'
);
\top_right_1_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[14]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[14]\,
R => '0'
);
\top_right_1_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[15]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[15]\,
R => '0'
);
\top_right_1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[1]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[1]\,
R => '0'
);
\top_right_1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[2]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[2]\,
R => '0'
);
\top_right_1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[3]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[3]\,
R => '0'
);
\top_right_1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[4]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[4]\,
R => '0'
);
\top_right_1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[5]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[5]\,
R => '0'
);
\top_right_1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[6]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[6]\,
R => '0'
);
\top_right_1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[7]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[7]\,
R => '0'
);
\top_right_1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[8]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[8]\,
R => '0'
);
\top_right_1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => top_right_1,
D => \top_right_1[9]_i_1_n_0\,
Q => \top_right_1_reg_n_0_[9]\,
R => '0'
);
\value_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(0),
Q => \value_reg_n_0_[0]\,
R => '0'
);
\value_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(1),
Q => \value_reg_n_0_[1]\,
R => '0'
);
\value_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(2),
Q => \value_reg_n_0_[2]\,
R => '0'
);
\value_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(3),
Q => \value_reg_n_0_[3]\,
R => '0'
);
\value_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(4),
Q => \value_reg_n_0_[4]\,
R => '0'
);
\value_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(5),
Q => \value_reg_n_0_[5]\,
R => '0'
);
\value_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(6),
Q => \value_reg_n_0_[6]\,
R => '0'
);
\value_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => x,
D => g_in(7),
Q => \value_reg_n_0_[7]\,
R => '0'
);
wen_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAAA2AAAA"
)
port map (
I0 => wen_reg_n_0,
I1 => wen_i_2_n_0,
I2 => \cycle_reg[0]_rep_n_0\,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => wen_i_1_n_0
);
wen_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => active,
I1 => rst,
O => wen_i_2_n_0
);
wen_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x16,
CE => '1',
D => wen_i_1_n_0,
Q => wen_reg_n_0,
R => '0'
);
\x0[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3B01FFC53A00FEC4"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => data2(0),
I4 => \x_reg_n_0_[0]\,
I5 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_2_n_0\
);
\x0[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(0),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_7\,
O => \x0[0]_i_3_n_0\
);
\x0[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCEECCEEEEEECCFC"
)
port map (
I0 => data2(1),
I1 => \x0[1]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_6\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_2_n_0\
);
\x0[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(1),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_6\,
O => \x0[1]_i_3_n_0\
);
\x0[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"60600060"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[0]\,
I2 => cycle(0),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[1]_i_4_n_0\
);
\x0[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBBBFBBBFFBBBBBB"
)
port map (
I0 => \x0[2]_i_2_n_0\,
I1 => \x0[2]_i_3_n_0\,
I2 => data2(2),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry_n_5\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[2]_i_1_n_0\
);
\x0[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88AA22A0880022A0"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x0[2]_i_4_n_0\,
I2 => \plusOp_inferred__0/i__carry_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(2),
O => \x0[2]_i_2_n_0\
);
\x0[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FF3F3F377777777"
)
port map (
I0 => data2(2),
I1 => \x0[2]_i_5_n_0\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
I5 => \x1[6]_i_8_n_0\,
O => \x0[2]_i_3_n_0\
);
\x0[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[2]_i_4_n_0\
);
\x0[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
O => \x0[2]_i_5_n_0\
);
\x0[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x0[3]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[3]_i_3_n_0\,
I3 => cycle(3),
I4 => \x0[3]_i_4_n_0\,
O => \x0[3]_i_1_n_0\
);
\x0[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"660FFF00660FFFFF"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_5_n_0\,
I2 => data2(3),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_2_n_0\
);
\x0[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F9F090000900"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x0[3]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(3),
O => \x0[3]_i_3_n_0\
);
\x0[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data2(3),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \plusOp_inferred__0/i__carry_n_4\,
O => \x0[3]_i_4_n_0\
);
\x0[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_5_n_0\
);
\x0[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[2]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[0]\,
O => \x0[3]_i_6_n_0\
);
\x0[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[4]_i_2_n_0\,
I1 => \x0[4]_i_3_n_0\,
I2 => data2(4),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[4]_i_1_n_0\
);
\x0[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x0[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[4]_i_2_n_0\
);
\x0[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"008A0080A08AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data2(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \plusOp_inferred__0/i__carry__0_n_7\,
I5 => \x0[4]_i_5_n_0\,
O => \x0[4]_i_3_n_0\
);
\x0[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
O => \x0[4]_i_4_n_0\
);
\x0[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"95555555"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[0]\,
O => \x0[4]_i_5_n_0\
);
\x0[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x0[5]_i_2_n_0\,
I1 => \x0[5]_i_3_n_0\,
I2 => data2(5),
I3 => cycle(3),
I4 => \plusOp_inferred__0/i__carry__0_n_6\,
I5 => \x1[5]_i_3_n_0\,
O => \x0[5]_i_1_n_0\
);
\x0[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data2(5),
I1 => \x_reg_n_0_[5]\,
I2 => \x0[8]_i_7_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x0[5]_i_2_n_0\
);
\x0[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A80008AAAAAAAA"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \plusOp_inferred__0/i__carry__0_n_6\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => data2(5),
I5 => \x0[5]_i_4_n_0\,
O => \x0[5]_i_3_n_0\
);
\x0[5]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x0[5]_i_5_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => cycle(0),
O => \x0[5]_i_4_n_0\
);
\x0[5]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \x_reg_n_0_[0]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x0[5]_i_5_n_0\
);
\x0[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0507"
)
port map (
I0 => \x0[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(3),
I3 => \x0[6]_i_3_n_0\,
I4 => \x0[6]_i_4_n_0\,
O => \x0[6]_i_1_n_0\
);
\x0[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0707077077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data2(6),
I2 => \x_reg_n_0_[6]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x0[8]_i_5_n_0\,
O => \x0[6]_i_2_n_0\
);
\x0[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6600FF0F66FFFF0F"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x0[6]_i_5_n_0\,
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data2(6),
O => \x0[6]_i_3_n_0\
);
\x0[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0C0C0C0C0C0C088"
)
port map (
I0 => data2(6),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__0_n_5\,
I3 => cycle(0),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[6]_i_4_n_0\
);
\x0[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[0]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x0[6]_i_5_n_0\
);
\x0[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF020000"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x0[7]_i_2_n_0\,
I3 => \x0[7]_i_3_n_0\,
I4 => \x0[7]_i_4_n_0\,
I5 => \x0[7]_i_5_n_0\,
O => \x0[7]_i_1_n_0\
);
\x0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[8]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \x_reg_n_0_[6]\,
O => \x0[7]_i_2_n_0\
);
\x0[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99F000FF99F00000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x0[7]_i_6_n_0\,
I2 => data2(7),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_3_n_0\
);
\x0[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
O => \x0[7]_i_4_n_0\
);
\x0[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x0[7]_i_7_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data2(7),
I4 => cycle(3),
I5 => \plusOp_inferred__0/i__carry__0_n_4\,
O => \x0[7]_i_5_n_0\
);
\x0[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \x0[6]_i_5_n_0\,
I1 => \x_reg_n_0_[6]\,
O => \x0[7]_i_6_n_0\
);
\x0[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x_reg_n_0_[6]\,
I3 => \x_reg_n_0_[5]\,
I4 => \x0[8]_i_7_n_0\,
I5 => \x_reg_n_0_[7]\,
O => \x0[7]_i_7_n_0\
);
\x0[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0FFF1F1F1"
)
port map (
I0 => \x0[8]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x0[8]_i_3_n_0\,
I3 => \x0[8]_i_4_n_0\,
I4 => \x0[8]_i_5_n_0\,
I5 => cycle(3),
O => \x0[8]_i_1_n_0\
);
\x0[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"990FFF00990FFFFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x0[8]_i_6_n_0\,
I2 => data2(8),
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \plusOp_inferred__0/i__carry__1_n_7\,
O => \x0[8]_i_2_n_0\
);
\x0[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888B888B888B8C0"
)
port map (
I0 => \plusOp_inferred__0/i__carry__1_n_7\,
I1 => cycle(3),
I2 => data2(8),
I3 => \cycle_reg[2]_rep_n_0\,
I4 => cycle(0),
I5 => \cycle_reg[1]_rep__0_n_0\,
O => \x0[8]_i_3_n_0\
);
\x0[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x0[8]_i_4_n_0\
);
\x0[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x0[8]_i_5_n_0\
);
\x0[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x0[6]_i_5_n_0\,
O => \x0[8]_i_6_n_0\
);
\x0[8]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEEE"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[0]\,
I4 => \x_reg_n_0_[3]\,
O => \x0[8]_i_7_n_0\
);
\x0[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"77FE000000000000"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(3),
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => active,
I5 => rst,
O => \x0[9]_i_1_n_0\
);
\x0[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0101"
)
port map (
I0 => \x0[9]_i_3_n_0\,
I1 => cycle(3),
I2 => cycle(2),
I3 => \x0[9]_i_4_n_0\,
I4 => \x0[9]_i_5_n_0\,
O => \x0[9]_i_2_n_0\
);
\x0[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF03AFF3A003A0F3"
)
port map (
I0 => \x0[9]_i_6_n_0\,
I1 => \plusOp_inferred__0/i__carry__1_n_6\,
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => data2(9),
I5 => \x0[9]_i_7_n_0\,
O => \x0[9]_i_3_n_0\
);
\x0[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C0C0C0C0C44"
)
port map (
I0 => data2(9),
I1 => cycle(3),
I2 => \plusOp_inferred__0/i__carry__1_n_6\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => \cycle_reg[1]_rep_n_0\,
O => \x0[9]_i_4_n_0\
);
\x0[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5CCC0000"
)
port map (
I0 => \x0[9]_i_7_n_0\,
I1 => data2(9),
I2 => \cycle_reg[1]_rep_n_0\,
I3 => \cycle_reg[0]_rep_n_0\,
I4 => cycle(2),
I5 => cycle(3),
O => \x0[9]_i_5_n_0\
);
\x0[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"55559555"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x_reg_n_0_[6]\,
I4 => \x0[6]_i_5_n_0\,
O => \x0[9]_i_6_n_0\
);
\x0[9]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[9]\,
I1 => \x_reg_n_0_[8]\,
I2 => \x_reg_n_0_[7]\,
I3 => \x0[8]_i_7_n_0\,
I4 => \x_reg_n_0_[5]\,
I5 => \x_reg_n_0_[6]\,
O => \x0[9]_i_7_n_0\
);
\x0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[0]_i_1_n_0\,
Q => data1(0),
R => '0'
);
\x0_reg[0]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[0]_i_2_n_0\,
I1 => \x0[0]_i_3_n_0\,
O => \x0_reg[0]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0_reg[1]_i_1_n_0\,
Q => data1(1),
R => '0'
);
\x0_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \x0[1]_i_2_n_0\,
I1 => \x0[1]_i_3_n_0\,
O => \x0_reg[1]_i_1_n_0\,
S => cycle(3)
);
\x0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[2]_i_1_n_0\,
Q => data1(2),
R => '0'
);
\x0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[3]_i_1_n_0\,
Q => data1(3),
R => '0'
);
\x0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[4]_i_1_n_0\,
Q => data1(4),
R => '0'
);
\x0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[5]_i_1_n_0\,
Q => data1(5),
R => '0'
);
\x0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[6]_i_1_n_0\,
Q => data1(6),
R => '0'
);
\x0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[7]_i_1_n_0\,
Q => data1(7),
R => '0'
);
\x0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[8]_i_1_n_0\,
Q => data1(8),
R => '0'
);
\x0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => \x0[9]_i_1_n_0\,
D => \x0[9]_i_2_n_0\,
Q => data1(9),
R => '0'
);
\x1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF01FF4EFE00B100"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \x_reg_n_0_[0]\,
I4 => cycle(3),
I5 => data1(0),
O => \x1[0]_i_1_n_0\
);
\x1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFEFAAA955565010"
)
port map (
I0 => cycle(3),
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => data1(1),
I5 => \x_reg_n_0_[1]\,
O => \x1[1]_i_1_n_0\
);
\x1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEAEAEAEFEAE"
)
port map (
I0 => \x1[2]_i_2_n_0\,
I1 => \x1[2]_i_3_n_0\,
I2 => cycle(3),
I3 => \x_reg_n_0_[2]\,
I4 => \x1[5]_i_3_n_0\,
I5 => data1(2),
O => \x1[2]_i_1_n_0\
);
\x1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A2A288880202888"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => \x_reg_n_0_[2]\,
I2 => cycle(0),
I3 => \x_reg_n_0_[1]\,
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(2),
O => \x1[2]_i_2_n_0\
);
\x1[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3CAAAAAA00000000"
)
port map (
I0 => data1(2),
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[2]_i_3_n_0\
);
\x1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[3]_i_2_n_0\,
I1 => \x1[3]_i_3_n_0\,
I2 => data1(3),
I3 => cycle(3),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[3]_i_1_n_0\
);
\x1[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0770707077777777"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => data1(3),
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x0[8]_i_5_n_0\,
O => \x1[3]_i_2_n_0\
);
\x1[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(3),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[3]\,
I5 => \x1[3]_i_4_n_0\,
O => \x1[3]_i_3_n_0\
);
\x1[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \x_reg_n_0_[1]\,
I1 => \x_reg_n_0_[2]\,
O => \x1[3]_i_4_n_0\
);
\x1[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCDDFCDDFFDDCCDD"
)
port map (
I0 => \x1[4]_i_2_n_0\,
I1 => \x1[4]_i_3_n_0\,
I2 => data1(4),
I3 => cycle(3),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[5]_i_3_n_0\,
O => \x1[4]_i_1_n_0\
);
\x1[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3C555555FFFF3CFF"
)
port map (
I0 => data1(4),
I1 => \x_reg_n_0_[4]\,
I2 => \x1[4]_i_4_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => \cycle_reg[2]_rep_n_0\,
O => \x1[4]_i_2_n_0\
);
\x1[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A08A0080008AA080"
)
port map (
I0 => \x0[7]_i_4_n_0\,
I1 => data1(4),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[4]\,
I5 => \x1[4]_i_5_n_0\,
O => \x1[4]_i_3_n_0\
);
\x1[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_4_n_0\
);
\x1[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
O => \x1[4]_i_5_n_0\
);
\x1[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => \x1[5]_i_2_n_0\,
I1 => data1(5),
I2 => \x1[5]_i_3_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => cycle(3),
O => \x1[5]_i_1_n_0\
);
\x1[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDFDCDCDFDFDFDCD"
)
port map (
I0 => \x1[5]_i_4_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[6]_i_8_n_0\,
I4 => data1(5),
I5 => \x1[5]_i_5_n_0\,
O => \x1[5]_i_2_n_0\
);
\x1[5]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => cycle(0),
O => \x1[5]_i_3_n_0\
);
\x1[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0530FA3FF5300A3F"
)
port map (
I0 => \x1[6]_i_7_n_0\,
I1 => data1(5),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[5]\,
I5 => \left[15]_i_3_n_0\,
O => \x1[5]_i_4_n_0\
);
\x1[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555666"
)
port map (
I0 => \x_reg_n_0_[5]\,
I1 => \x_reg_n_0_[3]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[1]\,
I4 => \x_reg_n_0_[4]\,
O => \x1[5]_i_5_n_0\
);
\x1[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[6]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[6]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[6]_i_4_n_0\,
O => \x1[6]_i_1_n_0\
);
\x1[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05050CFC05F5F"
)
port map (
I0 => data1(6),
I1 => \x1[6]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[6]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[6]\,
O => \x1[6]_i_2_n_0\
);
\x1[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A900FF00A9000000"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x1[6]_i_7_n_0\,
I2 => \x_reg_n_0_[5]\,
I3 => \cycle_reg[2]_rep_n_0\,
I4 => \x1[6]_i_8_n_0\,
I5 => data1(6),
O => \x1[6]_i_3_n_0\
);
\x1[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(6),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[6]\,
O => \x1[6]_i_4_n_0\
);
\x1[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_5_n_0\
);
\x1[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555666"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[4]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[3]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[6]_i_6_n_0\
);
\x1[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEA"
)
port map (
I0 => \x_reg_n_0_[4]\,
I1 => \x_reg_n_0_[1]\,
I2 => \x_reg_n_0_[2]\,
I3 => \x_reg_n_0_[3]\,
O => \x1[6]_i_7_n_0\
);
\x1[6]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cycle_reg[1]_rep__0_n_0\,
I1 => cycle(0),
O => \x1[6]_i_8_n_0\
);
\x1[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF100F1"
)
port map (
I0 => \x1[7]_i_2_n_0\,
I1 => \cycle_reg[2]_rep_n_0\,
I2 => \x1[7]_i_3_n_0\,
I3 => cycle(3),
I4 => \x1[7]_i_4_n_0\,
O => \x1[7]_i_1_n_0\
);
\x1[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"303F5050CFC05F5F"
)
port map (
I0 => data1(7),
I1 => \x1[7]_i_5_n_0\,
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => \x1[9]_i_6_n_0\,
I4 => cycle(0),
I5 => \x_reg_n_0_[7]\,
O => \x1[7]_i_2_n_0\
);
\x1[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F0F0F090000000"
)
port map (
I0 => \x_reg_n_0_[7]\,
I1 => \x1[9]_i_6_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
I3 => cycle(0),
I4 => \cycle_reg[1]_rep__0_n_0\,
I5 => data1(7),
O => \x1[7]_i_3_n_0\
);
\x1[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => data1(7),
I1 => cycle(0),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \cycle_reg[1]_rep__0_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[7]_i_4_n_0\
);
\x1[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \x_reg_n_0_[3]\,
I1 => \x_reg_n_0_[2]\,
I2 => \x_reg_n_0_[1]\,
I3 => \x_reg_n_0_[4]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[5]\,
O => \x1[7]_i_5_n_0\
);
\x1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => \x1[8]_i_2_n_0\,
I1 => cycle(3),
I2 => \cycle_reg[2]_rep_n_0\,
I3 => \x1[8]_i_3_n_0\,
O => \x1[8]_i_1_n_0\
);
\x1[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA300A3F0A30FA3F"
)
port map (
I0 => \x1[8]_i_4_n_0\,
I1 => data1(8),
I2 => \cycle_reg[1]_rep__0_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[8]\,
I5 => \left[15]_i_2_n_0\,
O => \x1[8]_i_2_n_0\
);
\x1[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[8]_i_5_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(8),
I4 => cycle(3),
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_3_n_0\
);
\x1[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555556"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[6]\,
I2 => \x_reg_n_0_[5]\,
I3 => \x1[6]_i_7_n_0\,
I4 => \x_reg_n_0_[7]\,
O => \x1[8]_i_4_n_0\
);
\x1[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000002"
)
port map (
I0 => \x1[8]_i_6_n_0\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[6]_i_7_n_0\,
I3 => \x_reg_n_0_[5]\,
I4 => \x_reg_n_0_[6]\,
I5 => \x_reg_n_0_[8]\,
O => \x1[8]_i_5_n_0\
);
\x1[8]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cycle(0),
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \cycle_reg[2]_rep_n_0\,
O => \x1[8]_i_6_n_0\
);
\x1[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088008880880880"
)
port map (
I0 => active,
I1 => rst,
I2 => cycle(0),
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \cycle_reg[1]_rep__0_n_0\,
O => x1
);
\x1[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000047"
)
port map (
I0 => \x1[9]_i_3_n_0\,
I1 => \cycle_reg[1]_rep__0_n_0\,
I2 => \x1[9]_i_4_n_0\,
I3 => cycle(3),
I4 => \cycle_reg[2]_rep_n_0\,
I5 => \x1[9]_i_5_n_0\,
O => \x1[9]_i_2_n_0\
);
\x1[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C335555"
)
port map (
I0 => data1(9),
I1 => \x_reg_n_0_[9]\,
I2 => \x_reg_n_0_[8]\,
I3 => \left[15]_i_2_n_0\,
I4 => cycle(0),
O => \x1[9]_i_3_n_0\
);
\x1[9]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0100FEFF"
)
port map (
I0 => \x_reg_n_0_[8]\,
I1 => \x_reg_n_0_[7]\,
I2 => \x1[9]_i_6_n_0\,
I3 => cycle(0),
I4 => \x_reg_n_0_[9]\,
O => \x1[9]_i_4_n_0\
);
\x1[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FEECCF000EECC"
)
port map (
I0 => \x1[9]_i_7_n_0\,
I1 => \x1[9]_i_8_n_0\,
I2 => \x1[5]_i_3_n_0\,
I3 => data1(9),
I4 => cycle(3),
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_5_n_0\
);
\x1[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFEFE"
)
port map (
I0 => \x_reg_n_0_[6]\,
I1 => \x_reg_n_0_[5]\,
I2 => \x_reg_n_0_[3]\,
I3 => \x_reg_n_0_[2]\,
I4 => \x_reg_n_0_[1]\,
I5 => \x_reg_n_0_[4]\,
O => \x1[9]_i_6_n_0\
);
\x1[9]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => cycle(0),
I2 => \cycle_reg[1]_rep__0_n_0\,
O => \x1[9]_i_7_n_0\
);
\x1[9]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888000000008"
)
port map (
I0 => \cycle_reg[2]_rep_n_0\,
I1 => \x1[6]_i_8_n_0\,
I2 => \x1[9]_i_6_n_0\,
I3 => \x_reg_n_0_[7]\,
I4 => \x_reg_n_0_[8]\,
I5 => \x_reg_n_0_[9]\,
O => \x1[9]_i_8_n_0\
);
\x1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[0]_i_1_n_0\,
Q => data2(0),
R => '0'
);
\x1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[1]_i_1_n_0\,
Q => data2(1),
R => '0'
);
\x1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[2]_i_1_n_0\,
Q => data2(2),
R => '0'
);
\x1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[3]_i_1_n_0\,
Q => data2(3),
R => '0'
);
\x1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[4]_i_1_n_0\,
Q => data2(4),
R => '0'
);
\x1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[5]_i_1_n_0\,
Q => data2(5),
R => '0'
);
\x1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[6]_i_1_n_0\,
Q => data2(6),
R => '0'
);
\x1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[7]_i_1_n_0\,
Q => data2(7),
R => '0'
);
\x1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[8]_i_1_n_0\,
Q => data2(8),
R => '0'
);
\x1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x1,
D => \x1[9]_i_2_n_0\,
Q => data2(9),
R => '0'
);
\x[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => cycle(0),
I1 => active,
I2 => rst,
I3 => \cycle_reg[1]_rep_n_0\,
I4 => cycle(3),
I5 => cycle(2),
O => x
);
\x_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(0),
Q => \x_reg_n_0_[0]\,
R => '0'
);
\x_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(1),
Q => \x_reg_n_0_[1]\,
R => '0'
);
\x_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(2),
Q => \x_reg_n_0_[2]\,
R => '0'
);
\x_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(3),
Q => \x_reg_n_0_[3]\,
R => '0'
);
\x_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(4),
Q => \x_reg_n_0_[4]\,
R => '0'
);
\x_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(5),
Q => \x_reg_n_0_[5]\,
R => '0'
);
\x_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(6),
Q => \x_reg_n_0_[6]\,
R => '0'
);
\x_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(7),
Q => \x_reg_n_0_[7]\,
R => '0'
);
\x_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(8),
Q => \x_reg_n_0_[8]\,
R => '0'
);
\x_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => x_addr(9),
Q => \x_reg_n_0_[9]\,
R => '0'
);
\y1[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y1[2]_i_1_n_0\
);
\y1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
I3 => \y_actual_reg_n_0_[3]\,
O => \y1[3]_i_1_n_0\
);
\y1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[0]_i_1_n_0\,
Q => \y1_reg_n_0_[0]\,
R => '0'
);
\y1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y5[1]_i_1_n_0\,
Q => \y1_reg_n_0_[1]\,
R => '0'
);
\y1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[2]_i_1_n_0\,
Q => \y1_reg_n_0_[2]\,
R => '0'
);
\y1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y1[3]_i_1_n_0\,
Q => \y1_reg_n_0_[3]\,
R => '0'
);
\y2[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
O => \y2[1]_i_1_n_0\
);
\y2[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y2[2]_i_1_n_0\
);
\y2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y2[3]_i_1_n_0\
);
\y2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y_actual_reg_n_0_[0]\,
Q => \y2_reg_n_0_[0]\,
R => '0'
);
\y2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[1]_i_1_n_0\,
Q => \y2_reg_n_0_[1]\,
R => '0'
);
\y2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[2]_i_1_n_0\,
Q => \y2_reg_n_0_[2]\,
R => '0'
);
\y2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y2[3]_i_1_n_0\,
Q => \y2_reg_n_0_[3]\,
R => '0'
);
\y3[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
O => \y3[1]_i_1_n_0\
);
\y3[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"87"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[2]\,
O => \y3[2]_i_1_n_0\
);
\y3[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y3[3]_i_1_n_0\
);
\y3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y5[0]_i_1_n_0\,
Q => \y3_reg_n_0_[0]\,
R => '0'
);
\y3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[1]_i_1_n_0\,
Q => \y3_reg_n_0_[1]\,
R => '0'
);
\y3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[2]_i_1_n_0\,
Q => \y3_reg_n_0_[2]\,
R => '0'
);
\y3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y3,
D => \y3[3]_i_1_n_0\,
Q => \y3_reg_n_0_[3]\,
R => '0'
);
\y4[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
O => \y4[2]_i_1_n_0\
);
\y4[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y4[3]_i_1_n_0\
);
\y4_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[0]\,
Q => data2(10),
R => '0'
);
\y4_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y_actual_reg_n_0_[1]\,
Q => data2(11),
R => '0'
);
\y4_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[2]_i_1_n_0\,
Q => data2(12),
R => '0'
);
\y4_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y1,
D => \y4[3]_i_1_n_0\,
Q => data2(13),
R => '0'
);
\y5[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[0]\,
O => \y5[0]_i_1_n_0\
);
\y5[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[0]\,
O => \y5[1]_i_1_n_0\
);
\y5[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y5[2]_i_1_n_0\
);
\y5[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A955"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y5[3]_i_1_n_0\
);
\y5_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[0]_i_1_n_0\,
Q => data1(10),
R => '0'
);
\y5_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[1]_i_1_n_0\,
Q => data1(11),
R => '0'
);
\y5_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[2]_i_1_n_0\,
Q => data1(12),
R => '0'
);
\y5_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y5[3]_i_1_n_0\,
Q => data1(13),
R => '0'
);
\y6[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_actual_reg_n_0_[1]\,
I1 => \y_actual_reg_n_0_[2]\,
O => \y6[2]_i_1_n_0\
);
\y6[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[2]\,
I2 => \y_actual_reg_n_0_[1]\,
O => \y6[3]_i_1_n_0\
);
\y6_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y_actual_reg_n_0_[0]\,
Q => \y6_reg_n_0_[0]\,
R => '0'
);
\y6_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y2[1]_i_1_n_0\,
Q => \y6_reg_n_0_[1]\,
R => '0'
);
\y6_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[2]_i_1_n_0\,
Q => \y6_reg_n_0_[2]\,
R => '0'
);
\y6_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y6,
D => \y6[3]_i_1_n_0\,
Q => \y6_reg_n_0_[3]\,
R => '0'
);
\y7[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \y_actual_reg_n_0_[2]\,
I1 => \y_actual_reg_n_0_[1]\,
I2 => \y_actual_reg_n_0_[0]\,
O => \y7[2]_i_1_n_0\
);
\y7[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y7[3]_i_1_n_0\
);
\y7_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y5[0]_i_1_n_0\,
Q => y7(0),
R => '0'
);
\y7_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y3[1]_i_1_n_0\,
Q => y7(1),
R => '0'
);
\y7_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[2]_i_1_n_0\,
Q => y7(2),
R => '0'
);
\y7_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y2,
D => \y7[3]_i_1_n_0\,
Q => y7(3),
R => '0'
);
\y8[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
O => \y8[3]_i_1_n_0\
);
\y8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[0]\,
Q => y8(0),
R => '0'
);
\y8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[1]\,
Q => y8(1),
R => '0'
);
\y8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y_actual_reg_n_0_[2]\,
Q => y8(2),
R => '0'
);
\y8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y5,
D => \y8[3]_i_1_n_0\,
Q => y8(3),
R => '0'
);
\y9[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \y_actual_reg_n_0_[3]\,
I1 => \y_actual_reg_n_0_[0]\,
I2 => \y_actual_reg_n_0_[1]\,
I3 => \y_actual_reg_n_0_[2]\,
O => \y9[3]_i_1_n_0\
);
\y9_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[0]_i_1_n_0\,
Q => data5(10),
R => '0'
);
\y9_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y5[1]_i_1_n_0\,
Q => data5(11),
R => '0'
);
\y9_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y1[2]_i_1_n_0\,
Q => data5(12),
R => '0'
);
\y9_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => y9,
D => \y9[3]_i_1_n_0\,
Q => data5(13),
R => '0'
);
\y_actual_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(0),
Q => \y_actual_reg_n_0_[0]\,
R => '0'
);
\y_actual_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(1),
Q => \y_actual_reg_n_0_[1]\,
R => '0'
);
\y_actual_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(2),
Q => \y_actual_reg_n_0_[2]\,
R => '0'
);
\y_actual_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(3),
Q => \y_actual_reg_n_0_[3]\,
R => '0'
);
\y_actual_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(4),
Q => \y_actual_reg_n_0_[4]\,
R => '0'
);
\y_actual_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(5),
Q => \y_actual_reg_n_0_[5]\,
R => '0'
);
\y_actual_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(6),
Q => \y_actual_reg_n_0_[6]\,
R => '0'
);
\y_actual_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(7),
Q => \y_actual_reg_n_0_[7]\,
R => '0'
);
\y_actual_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(8),
Q => \y_actual_reg_n_0_[8]\,
R => '0'
);
\y_actual_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x16,
CE => x,
D => y_addr(9),
Q => \y_actual_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_hessian_1_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_hessian_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_hessian_1_0 : entity is "system_vga_hessian_1_0,vga_hessian,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_hessian_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_hessian_1_0 : entity is "vga_hessian,Vivado 2016.4";
end system_vga_hessian_1_0;
architecture STRUCTURE of system_vga_hessian_1_0 is
begin
U0: entity work.system_vga_hessian_1_0_vga_hessian
port map (
active => active,
clk_x16 => clk_x16,
g_in(7 downto 0) => g_in(7 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
rst => rst,
x_addr(9 downto 0) => x_addr(9 downto 0),
y_addr(9 downto 0) => y_addr(9 downto 0)
);
end STRUCTURE;
| mit | 07fa81677b4910f139eb4815203ae54c | 0.546372 | 2.727797 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/data/cpu_l1mem_data_types_pkg.vhdl | 1 | 3,444 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package cpu_l1mem_data_types_pkg is
type cpu_l1mem_data_request_code_index_type is (
cpu_l1mem_data_request_code_index_none,
cpu_l1mem_data_request_code_index_load,
cpu_l1mem_data_request_code_index_store,
cpu_l1mem_data_request_code_index_invalidate,
cpu_l1mem_data_request_code_index_flush,
cpu_l1mem_data_request_code_index_writeback,
cpu_l1mem_data_request_code_index_sync
);
type cpu_l1mem_data_request_code_type is
array (cpu_l1mem_data_request_code_index_type range
cpu_l1mem_data_request_code_index_type'high downto
cpu_l1mem_data_request_code_index_type'low) of std_ulogic;
constant cpu_l1mem_data_request_code_none : cpu_l1mem_data_request_code_type := "0000001";
constant cpu_l1mem_data_request_code_load : cpu_l1mem_data_request_code_type := "0000010";
constant cpu_l1mem_data_request_code_store : cpu_l1mem_data_request_code_type := "0000100";
constant cpu_l1mem_data_request_code_invalidate : cpu_l1mem_data_request_code_type := "0001000";
constant cpu_l1mem_data_request_code_flush : cpu_l1mem_data_request_code_type := "0010000";
constant cpu_l1mem_data_request_code_writeback : cpu_l1mem_data_request_code_type := "0100000";
constant cpu_l1mem_data_request_code_sync : cpu_l1mem_data_request_code_type := "1000000";
type cpu_l1mem_data_result_code_index_type is (
cpu_l1mem_data_result_code_index_valid,
cpu_l1mem_data_result_code_index_error,
cpu_l1mem_data_result_code_index_tlbmiss,
cpu_l1mem_data_result_code_index_pf
);
type cpu_l1mem_data_result_code_type is
array (cpu_l1mem_data_result_code_index_type range
cpu_l1mem_data_result_code_index_type'high downto
cpu_l1mem_data_result_code_index_type'low) of std_ulogic;
constant cpu_l1mem_data_result_code_valid : cpu_l1mem_data_result_code_type := "0001";
constant cpu_l1mem_data_result_code_error : cpu_l1mem_data_result_code_type := "0010";
constant cpu_l1mem_data_result_code_tlbmiss : cpu_l1mem_data_result_code_type := "0100";
constant cpu_l1mem_data_result_code_pf : cpu_l1mem_data_result_code_type := "1000";
end package;
| apache-2.0 | 6a2740fec58089736241927d2e474975 | 0.625436 | 3.457831 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/synth/system_vga_hessian_0_0.vhd | 1 | 4,405 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 40
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_0_0_arch : ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=40,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=640}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
| mit | d80fd9f73d09540829b4f85b61922f48 | 0.719637 | 3.680033 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s6.vhd | 2 | 3,965 | library ieee;
use ieee.std_logic_1164.all;
entity s6 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s6;
architecture behaviour of s6 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"c"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"f"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"a"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"b"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"e"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"d"));
end case;
end process;
end; | mit | d04d9c6cb5628482dd5d0d0a0f93f40c | 0.675914 | 3.019802 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zed_vga/zed_vga.srcs/sources_1/new/zed_vga.vhd | 2 | 1,413 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: zed_vga - Structural
-- Description: Output rgb-565 pixel data to zedboard vga
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity zed_vga is
port(
clk: in std_logic;
active: in std_logic;
rgb565: in std_logic_vector(15 downto 0);
vga_r: out std_logic_vector(3 downto 0);
vga_g: out std_logic_vector(3 downto 0);
vga_b: out std_logic_vector(3 downto 0)
);
end zed_vga;
architecture Structural of zed_vga is
signal red: std_logic_vector(4 downto 0);
signal green: std_logic_vector(5 downto 0);
signal blue: std_logic_vector(4 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if active = '1' then
red <= rgb565(15 downto 11);
green <= rgb565(10 downto 5);
blue <= rgb565(4 downto 0);
else
red <= (others => '0');
green <= (others => '0');
blue <= (others => '0');
end if;
end if;
end process;
vga_r <= red(4 downto 1);
vga_g <= green(5 downto 2);
vga_b <= blue(4 downto 1);
end Structural;
| mit | 49d19a2936af369ce9df462427b585c0 | 0.491154 | 3.980282 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/madd_pipe_inferred-rtl.vhdl | 1 | 3,565 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of madd_pipe_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
prod_tmp1 : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
prod_tmp2 : std_ulogic_vector(src1_bits+src2_bits downto 0);
acc_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_msb_carryin : std_ulogic;
result_msb : std_ulogic;
carryout : std_ulogic;
end record;
type stage_type is record
overflow : std_ulogic;
result : std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
end record;
type reg_type is array(0 to stages-1) of stage_type;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.prod_tmp1 <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
c.prod_tmp2 <= (('0' & c.prod_tmp1(src1_bits+src2_bits-2 downto 0) & '0') xor
(src1_bits+src2_bits downto 0 => sub));
c.acc_tmp <= '0' & acc(src1_bits+src2_bits-2 downto 0) & '1';
c.result_tmp <= std_ulogic_vector(signed(c.acc_tmp) +
signed(c.prod_tmp2));
c.result_msb_carryin <= c.result_tmp(src1_bits+src2_bits);
c.result_msb <= (acc(src1_bits+src2_bits-1) xor
c.prod_tmp1(src1_bits+src2_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor acc(src1_bits+src2_bits-1)) and (c.prod_tmp1(src1_bits+src2_bits-1) or c.result_msb_carryin)) or
(c.prod_tmp1(src1_bits+src2_bits-1) and c.result_msb_carryin));
r_next(0).overflow <= c.carryout xor (not unsgnd and c.result_msb_carryin);
r_next(0).result <= c.result_msb & c.result_tmp(src1_bits+src2_bits-1 downto 1);
stages_gt_1 : if stages > 1 generate
pipeline_loop : for n in 1 to stages-1 generate
r_next(n) <= r(n-1);
end generate;
end generate;
overflow <= r(stages-1).overflow;
result <= r(stages-1).result;
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | 2658e4247d0546f6c3c1a78ce5b53e3e | 0.567461 | 3.457808 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/sim/system_zybo_hdmi_0_0.vhd | 2 | 3,819 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
| mit | ae70f158153bd36362569ea092f159bc | 0.69966 | 3.834337 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/timestamp_generator.vhd | 2 | 2,565 | -------------------------------------------------------------------------------
-- Title : Timestamp Generator module
-- Project :
-------------------------------------------------------------------------------
-- File : timestamp_generator.vhd
-- Author : strongly-typed
-- Created : 2011-09-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A fast, wide counter for keeping a timestamp for events like
-- samples.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity timestamp_generator is
port (
timestamp_o_p : out timestamp_type;
clk : in std_logic
);
end timestamp_generator;
-------------------------------------------------------------------------------
architecture behavioural of timestamp_generator is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal cnt : timestamp_type := (others => '0'); --unsigned(WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
timestamp_o_p <= cnt;
----------------------------------------------------------------------------
-- Sequential process
----------------------------------------------------------------------------
cnt_proc : process(clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process cnt_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | a7346c28786232d76bdbd368be9ee10e | 0.299805 | 7.478134 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_sim_netlist.vhdl | 1 | 5,064 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 23:35:06 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_sim_netlist.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_vga_0_0_zed_vga is
port (
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
rgb565 : in STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
active : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_vga_0_0_zed_vga : entity is "zed_vga";
end system_zed_vga_0_0_zed_vga;
architecture STRUCTURE of system_zed_vga_0_0_zed_vga is
signal \red[4]_i_1_n_0\ : STD_LOGIC;
begin
\blue_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(0),
Q => vga_b(0),
R => \red[4]_i_1_n_0\
);
\blue_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(1),
Q => vga_b(1),
R => \red[4]_i_1_n_0\
);
\blue_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(2),
Q => vga_b(2),
R => \red[4]_i_1_n_0\
);
\blue_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(3),
Q => vga_b(3),
R => \red[4]_i_1_n_0\
);
\green_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(4),
Q => vga_g(0),
R => \red[4]_i_1_n_0\
);
\green_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(5),
Q => vga_g(1),
R => \red[4]_i_1_n_0\
);
\green_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(6),
Q => vga_g(2),
R => \red[4]_i_1_n_0\
);
\green_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(7),
Q => vga_g(3),
R => \red[4]_i_1_n_0\
);
\red[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \red[4]_i_1_n_0\
);
\red_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(8),
Q => vga_r(0),
R => \red[4]_i_1_n_0\
);
\red_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(9),
Q => vga_r(1),
R => \red[4]_i_1_n_0\
);
\red_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(10),
Q => vga_r(2),
R => \red[4]_i_1_n_0\
);
\red_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb565(11),
Q => vga_r(3),
R => \red[4]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_vga_0_0 is
port (
clk : in STD_LOGIC;
active : in STD_LOGIC;
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_vga_0_0 : entity is "system_zed_vga_0_0,zed_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_vga_0_0 : entity is "zed_vga,Vivado 2016.4";
end system_zed_vga_0_0;
architecture STRUCTURE of system_zed_vga_0_0 is
begin
U0: entity work.system_zed_vga_0_0_zed_vga
port map (
active => active,
clk => clk,
rgb565(11 downto 8) => rgb565(15 downto 12),
rgb565(7 downto 4) => rgb565(10 downto 7),
rgb565(3 downto 0) => rgb565(4 downto 1),
vga_b(3 downto 0) => vga_b(3 downto 0),
vga_g(3 downto 0) => vga_g(3 downto 0),
vga_r(3 downto 0) => vga_r(3 downto 0)
);
end STRUCTURE;
| mit | 03153cc2d54b5ad5794a66f66de10be4 | 0.535742 | 3 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0_1/system_vga_sync_0_0_sim_netlist.vhdl | 1 | 17,563 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 09:37:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_sync_0_0 -prefix
-- system_vga_sync_0_0_ system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
active : out STD_LOGIC;
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC
);
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active_INST_0_i_1_n_0 : STD_LOGIC;
signal h_count_next : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \h_count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[5]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal h_sync_next : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal v_sync_next : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair0";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"000002AA"
)
port map (
I0 => active_INST_0_i_1_n_0,
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
I3 => \^xaddr\(9),
I4 => \^yaddr\(9),
O => active
);
active_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
O => active_INST_0_i_1_n_0
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => h_count_next(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => h_count_next(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
I2 => \^xaddr\(2),
O => h_count_next(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(2),
O => h_count_next(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(1),
I3 => \^xaddr\(0),
I4 => \^xaddr\(3),
O => \h_count_reg[4]_i_1_n_0\
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00000000FFBF"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(8),
I2 => \^xaddr\(9),
I3 => \^xaddr\(7),
I4 => \h_count_reg[5]_i_2_n_0\,
I5 => \^xaddr\(5),
O => h_count_next(5)
);
\h_count_reg[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(3),
I4 => \^xaddr\(4),
O => \h_count_reg[5]_i_2_n_0\
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(4),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
O => h_count_next(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
I4 => \^xaddr\(6),
O => h_count_next(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0B00B0"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(4),
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => h_count_next(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FBFBFB0B000000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(4),
I2 => \h_count_reg[9]_i_3_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \^xaddr\(8),
I5 => \^xaddr\(9),
O => h_count_next(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFEFFF"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(2),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => \h_count_reg[4]_i_1_n_0\,
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(8),
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(9),
Q => \^xaddr\(9)
);
h_sync_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00002AA800000000"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
I4 => \^xaddr\(8),
I5 => \^xaddr\(9),
O => h_sync_next
);
h_sync_reg_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => h_sync_next,
PRE => rst,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => p_0_in(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55AA55AA45AA55AA"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFAA0045FFAA00"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(3)
);
\v_count_reg[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \v_count_reg[3]_i_2_n_0\
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => p_0_in(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => p_0_in(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_5_n_0\,
I2 => \^yaddr\(5),
O => \v_count_reg[6]_i_1_n_0\
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(6),
O => p_0_in(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(5),
I4 => \^yaddr\(7),
O => p_0_in(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[5]_i_2_n_0\,
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"D0D00DD0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => active_INST_0_i_1_n_0,
O => p_0_in(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(7),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
I4 => \^yaddr\(4),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => \v_count_reg[6]_i_1_n_0\,
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(9),
Q => \^yaddr\(9)
);
v_sync_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(3),
I2 => \^yaddr\(4),
I3 => \^yaddr\(2),
I4 => \^yaddr\(1),
I5 => active_INST_0_i_1_n_0,
O => v_sync_next
);
v_sync_reg_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => v_sync_next,
PRE => rst,
Q => vsync
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk_25 => clk_25,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | e67d65abb7d81e10f91a0fed2312c703 | 0.48699 | 2.753685 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/synth/affine_block_ieee754_fp_multiplier_0_0.vhd | 2 | 4,008 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_0_0;
ARCHITECTURE affine_block_ieee754_fp_multiplier_0_0_arch OF affine_block_ieee754_fp_multiplier_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "ieee754_fp_multiplier,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_multiplier_0_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_multiplier_0_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_multiplier,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_0_0_arch;
| mit | 4e3e387b46366e75c27fc710e5791900 | 0.749251 | 3.802657 | false | false | false | false |
loa-org/loa-hdl | modules/hdlc/hdl/hdlc_busmaster_with_support.vhd | 1 | 5,409 | -------------------------------------------------------------------------------
-- Title : HDLC Busmaster with support
-- Project :
-------------------------------------------------------------------------------
-- File : hdlc_busmaster_with_support.vhd
-- Author :
-- Company :
-- Created : 2015-09-15
-- Last update: 2015-09-15
-- Platform :
-------------------------------------------------------------------------------
-- Description:
--
--
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.hdlc_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
use work.fifo_sync_pkg.all;
use work.utils_pkg.all;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_busmaster_with_support is
generic (
DIV_RX : positive := 87;
DIV_TX : positive := 434;
RESET_IMPL : reset_type := sync
);
port (
rx : in std_logic;
tx : out std_logic;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
reset : in std_logic;
clk : in std_logic
);
end entity hdlc_busmaster_with_support;
-------------------------------------------------------------------------------
architecture str of hdlc_busmaster_with_support is
type fifo_link_8bit_type is record
data : std_logic_vector(7 downto 0);
enable : std_logic;
empty : std_logic;
end record;
-- Connections components used for HDLC link
signal rx_to_dec : hdlc_dec_in_type := (data => (others => '0'), enable => '0');
signal dec_to_busmaster : hdlc_dec_out_type := (data => (others => '0'), enable => '0');
signal master_to_enc : hdlc_enc_in_type := (data => (others => '0'), enable => '0');
signal enc_to_fifo : hdlc_enc_out_type := (data => (others => '0'), enable => '0');
signal fifo_to_uart_tx : fifo_link_8bit_type := (data => (others => '0'), enable => '0', empty => '0');
signal enc_busy : std_logic := '0';
signal clk_rx_en, clk_tx_en : std_logic;
begin -- architecture str
-----------------------------------------------------------------------------
-- Baudrate Generator
-----------------------------------------------------------------------------
baudrate_rx_gen_inst : entity work.clock_divider
generic map(DIV => DIV_RX)
port map(
clk => clk,
clk_out_p => clk_rx_en);
baudrate_tx_gen_inst : entity work.clock_divider
generic map(DIV => DIV_TX)
port map(
clk => clk,
clk_out_p => clk_tx_en);
-----------------------------------------------------------------------------
-- UART RX
-----------------------------------------------------------------------------
uart_rx_inst : entity work.uart_rx
generic map (RESET_IMPL => RESET_IMPL)
port map(
rxd_p => rx,
disable_p => '0',
data_p => rx_to_dec.data,
we_p => rx_to_dec.enable,
error_p => open,
full_p => '0',
clk_rx_en => clk_rx_en,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Decoder
-----------------------------------------------------------------------------
hdlc_dec_inst : entity work.hdlc_dec
port map(
din_p => rx_to_dec,
dout_p => dec_to_busmaster,
clk => clk);
-----------------------------------------------------------------------------
-- Busmaster
-----------------------------------------------------------------------------
bus_master_inst : entity work.hdlc_busmaster
port map(
din_p => dec_to_busmaster,
dout_p => master_to_enc,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-----------------------------------------------------------------------------
-- Encoder
-----------------------------------------------------------------------------
hdlc_enc_inst : entity work.hdlc_enc
port map(
din_p => master_to_enc,
dout_p => enc_to_fifo,
busy_p => open,
clk => clk);
-----------------------------------------------------------------------------
-- Transmit FIFO
-----------------------------------------------------------------------------
tx_fifo_inst : entity work.fifo_sync
generic map(
data_width => 8,
address_width => 5)
port map(
di => enc_to_fifo.data,
wr => enc_to_fifo.enable,
full => open,
do => fifo_to_uart_tx.data,
rd => fifo_to_uart_tx.enable,
empty => fifo_to_uart_tx.empty,
valid => open,
clk => clk);
-----------------------------------------------------------------------------
-- UART TX
-----------------------------------------------------------------------------
uart_tx_inst : entity work.uart_tx
generic map (RESET_IMPL => RESET_IMPL)
port map(
txd_p => tx,
busy_p => open,
data_p => fifo_to_uart_tx.data,
empty_p => fifo_to_uart_tx.empty,
re_p => fifo_to_uart_tx.enable,
clk_tx_en => clk_tx_en,
reset => reset,
clk => clk);
end architecture str;
| bsd-3-clause | 6dd9012ad78afff478ece61f6a7cb91e | 0.373082 | 4.30996 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_sync/vga_sync.srcs/sources_1/new/vga_sync.vhd | 1 | 2,947 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture Structural of vga_sync is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk, rst)
begin
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
if rising_edge(clk) then
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
| mit | eb8b74b37d320cb4419dae653f5ec4f1 | 0.437055 | 4.048077 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_1/affine_block_ieee754_fp_multiplier_1_1_sim_netlist.vhdl | 1 | 200,504 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top affine_block_ieee754_fp_multiplier_1_1 -prefix
-- affine_block_ieee754_fp_multiplier_1_1_ affine_block_ieee754_fp_multiplier_0_0_sim_netlist.vhdl
-- Design : affine_block_ieee754_fp_multiplier_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_1_ieee754_fp_multiplier is
port (
z : out STD_LOGIC_VECTOR ( 7 downto 0 );
z_mantissa : out STD_LOGIC_VECTOR ( 22 downto 0 );
x : in STD_LOGIC_VECTOR ( 30 downto 0 );
y : in STD_LOGIC_VECTOR ( 30 downto 0 );
\y_11__s_port_\ : in STD_LOGIC
);
end affine_block_ieee754_fp_multiplier_1_1_ieee754_fp_multiplier;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_1_ieee754_fp_multiplier is
signal L1 : STD_LOGIC;
signal \L1_carry__0_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__0_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_0\ : STD_LOGIC;
signal \L1_carry__0_n_1\ : STD_LOGIC;
signal \L1_carry__0_n_2\ : STD_LOGIC;
signal \L1_carry__0_n_3\ : STD_LOGIC;
signal \L1_carry__1_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__1_i_8_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_0\ : STD_LOGIC;
signal \L1_carry__1_n_1\ : STD_LOGIC;
signal \L1_carry__1_n_2\ : STD_LOGIC;
signal \L1_carry__1_n_3\ : STD_LOGIC;
signal \L1_carry__2_i_1_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_2_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_3_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_4_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_5_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_6_n_0\ : STD_LOGIC;
signal \L1_carry__2_i_7_n_0\ : STD_LOGIC;
signal \L1_carry__2_n_1\ : STD_LOGIC;
signal \L1_carry__2_n_2\ : STD_LOGIC;
signal \L1_carry__2_n_3\ : STD_LOGIC;
signal L1_carry_i_10_n_0 : STD_LOGIC;
signal L1_carry_i_11_n_0 : STD_LOGIC;
signal L1_carry_i_12_n_0 : STD_LOGIC;
signal L1_carry_i_13_n_0 : STD_LOGIC;
signal L1_carry_i_14_n_0 : STD_LOGIC;
signal L1_carry_i_15_n_0 : STD_LOGIC;
signal L1_carry_i_16_n_0 : STD_LOGIC;
signal L1_carry_i_17_n_0 : STD_LOGIC;
signal L1_carry_i_18_n_0 : STD_LOGIC;
signal L1_carry_i_19_n_0 : STD_LOGIC;
signal L1_carry_i_1_n_0 : STD_LOGIC;
signal L1_carry_i_20_n_0 : STD_LOGIC;
signal L1_carry_i_21_n_0 : STD_LOGIC;
signal L1_carry_i_22_n_0 : STD_LOGIC;
signal L1_carry_i_23_n_0 : STD_LOGIC;
signal L1_carry_i_24_n_0 : STD_LOGIC;
signal L1_carry_i_25_n_0 : STD_LOGIC;
signal L1_carry_i_26_n_0 : STD_LOGIC;
signal L1_carry_i_27_n_0 : STD_LOGIC;
signal L1_carry_i_28_n_0 : STD_LOGIC;
signal L1_carry_i_29_n_0 : STD_LOGIC;
signal L1_carry_i_2_n_0 : STD_LOGIC;
signal L1_carry_i_30_n_0 : STD_LOGIC;
signal L1_carry_i_31_n_0 : STD_LOGIC;
signal L1_carry_i_32_n_0 : STD_LOGIC;
signal L1_carry_i_33_n_0 : STD_LOGIC;
signal L1_carry_i_34_n_0 : STD_LOGIC;
signal L1_carry_i_35_n_0 : STD_LOGIC;
signal L1_carry_i_36_n_0 : STD_LOGIC;
signal L1_carry_i_37_n_0 : STD_LOGIC;
signal L1_carry_i_38_n_0 : STD_LOGIC;
signal L1_carry_i_39_n_0 : STD_LOGIC;
signal L1_carry_i_3_n_0 : STD_LOGIC;
signal L1_carry_i_40_n_0 : STD_LOGIC;
signal L1_carry_i_41_n_0 : STD_LOGIC;
signal L1_carry_i_42_n_0 : STD_LOGIC;
signal L1_carry_i_43_n_0 : STD_LOGIC;
signal L1_carry_i_44_n_0 : STD_LOGIC;
signal L1_carry_i_45_n_0 : STD_LOGIC;
signal L1_carry_i_46_n_0 : STD_LOGIC;
signal L1_carry_i_47_n_0 : STD_LOGIC;
signal L1_carry_i_48_n_0 : STD_LOGIC;
signal L1_carry_i_49_n_0 : STD_LOGIC;
signal L1_carry_i_4_n_0 : STD_LOGIC;
signal L1_carry_i_50_n_0 : STD_LOGIC;
signal L1_carry_i_51_n_0 : STD_LOGIC;
signal L1_carry_i_52_n_0 : STD_LOGIC;
signal L1_carry_i_53_n_0 : STD_LOGIC;
signal L1_carry_i_54_n_0 : STD_LOGIC;
signal L1_carry_i_5_n_0 : STD_LOGIC;
signal L1_carry_i_6_n_0 : STD_LOGIC;
signal L1_carry_i_7_n_0 : STD_LOGIC;
signal L1_carry_i_8_n_0 : STD_LOGIC;
signal L1_carry_i_9_n_0 : STD_LOGIC;
signal L1_carry_n_0 : STD_LOGIC;
signal L1_carry_n_1 : STD_LOGIC;
signal L1_carry_n_2 : STD_LOGIC;
signal L1_carry_n_3 : STD_LOGIC;
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__0_n_4\ : STD_LOGIC;
signal \_carry__0_n_5\ : STD_LOGIC;
signal \_carry__0_n_6\ : STD_LOGIC;
signal \_carry__0_n_7\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_i_2_n_0\ : STD_LOGIC;
signal \_carry__1_i_3_n_0\ : STD_LOGIC;
signal \_carry__1_i_4_n_0\ : STD_LOGIC;
signal \_carry__1_n_0\ : STD_LOGIC;
signal \_carry__1_n_1\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry__1_n_3\ : STD_LOGIC;
signal \_carry__1_n_4\ : STD_LOGIC;
signal \_carry__1_n_5\ : STD_LOGIC;
signal \_carry__1_n_6\ : STD_LOGIC;
signal \_carry__1_n_7\ : STD_LOGIC;
signal \_carry__2_i_1_n_0\ : STD_LOGIC;
signal \_carry__2_i_2_n_0\ : STD_LOGIC;
signal \_carry__2_i_3_n_0\ : STD_LOGIC;
signal \_carry__2_i_4_n_0\ : STD_LOGIC;
signal \_carry__2_n_0\ : STD_LOGIC;
signal \_carry__2_n_1\ : STD_LOGIC;
signal \_carry__2_n_2\ : STD_LOGIC;
signal \_carry__2_n_3\ : STD_LOGIC;
signal \_carry__2_n_4\ : STD_LOGIC;
signal \_carry__2_n_5\ : STD_LOGIC;
signal \_carry__2_n_6\ : STD_LOGIC;
signal \_carry__2_n_7\ : STD_LOGIC;
signal \_carry__3_i_1_n_0\ : STD_LOGIC;
signal \_carry__3_i_2_n_0\ : STD_LOGIC;
signal \_carry__3_i_3_n_0\ : STD_LOGIC;
signal \_carry__3_i_4_n_0\ : STD_LOGIC;
signal \_carry__3_n_0\ : STD_LOGIC;
signal \_carry__3_n_1\ : STD_LOGIC;
signal \_carry__3_n_2\ : STD_LOGIC;
signal \_carry__3_n_3\ : STD_LOGIC;
signal \_carry__3_n_4\ : STD_LOGIC;
signal \_carry__3_n_5\ : STD_LOGIC;
signal \_carry__3_n_6\ : STD_LOGIC;
signal \_carry__3_n_7\ : STD_LOGIC;
signal \_carry__4_i_1_n_0\ : STD_LOGIC;
signal \_carry__4_i_2_n_0\ : STD_LOGIC;
signal \_carry__4_i_3_n_0\ : STD_LOGIC;
signal \_carry__4_i_4_n_0\ : STD_LOGIC;
signal \_carry__4_n_0\ : STD_LOGIC;
signal \_carry__4_n_1\ : STD_LOGIC;
signal \_carry__4_n_2\ : STD_LOGIC;
signal \_carry__4_n_3\ : STD_LOGIC;
signal \_carry__4_n_4\ : STD_LOGIC;
signal \_carry__4_n_5\ : STD_LOGIC;
signal \_carry__4_n_6\ : STD_LOGIC;
signal \_carry__4_n_7\ : STD_LOGIC;
signal \_carry__5_i_1_n_0\ : STD_LOGIC;
signal \_carry__5_i_2_n_0\ : STD_LOGIC;
signal \_carry__5_i_3_n_0\ : STD_LOGIC;
signal \_carry__5_i_4_n_0\ : STD_LOGIC;
signal \_carry__5_n_0\ : STD_LOGIC;
signal \_carry__5_n_1\ : STD_LOGIC;
signal \_carry__5_n_2\ : STD_LOGIC;
signal \_carry__5_n_3\ : STD_LOGIC;
signal \_carry__5_n_4\ : STD_LOGIC;
signal \_carry__5_n_5\ : STD_LOGIC;
signal \_carry__5_n_6\ : STD_LOGIC;
signal \_carry__5_n_7\ : STD_LOGIC;
signal \_carry__6_i_1_n_0\ : STD_LOGIC;
signal \_carry__6_i_2_n_0\ : STD_LOGIC;
signal \_carry__6_n_3\ : STD_LOGIC;
signal \_carry__6_n_6\ : STD_LOGIC;
signal \_carry__6_n_7\ : STD_LOGIC;
signal \_carry_i_10_n_0\ : STD_LOGIC;
signal \_carry_i_11_n_0\ : STD_LOGIC;
signal \_carry_i_12_n_0\ : STD_LOGIC;
signal \_carry_i_13_n_0\ : STD_LOGIC;
signal \_carry_i_14_n_0\ : STD_LOGIC;
signal \_carry_i_15_n_0\ : STD_LOGIC;
signal \_carry_i_16_n_0\ : STD_LOGIC;
signal \_carry_i_17_n_0\ : STD_LOGIC;
signal \_carry_i_18_n_0\ : STD_LOGIC;
signal \_carry_i_19_n_0\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_20_n_0\ : STD_LOGIC;
signal \_carry_i_21_n_0\ : STD_LOGIC;
signal \_carry_i_22_n_0\ : STD_LOGIC;
signal \_carry_i_23_n_0\ : STD_LOGIC;
signal \_carry_i_24_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_6_n_0\ : STD_LOGIC;
signal \_carry_i_7_n_0\ : STD_LOGIC;
signal \_carry_i_8_n_0\ : STD_LOGIC;
signal \_carry_i_9_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal \_carry_n_4\ : STD_LOGIC;
signal \_carry_n_5\ : STD_LOGIC;
signal \_carry_n_6\ : STD_LOGIC;
signal \_carry_n_7\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \msb1__1\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal msb1_n_106 : STD_LOGIC;
signal msb1_n_107 : STD_LOGIC;
signal msb1_n_108 : STD_LOGIC;
signal msb1_n_109 : STD_LOGIC;
signal msb1_n_110 : STD_LOGIC;
signal msb1_n_111 : STD_LOGIC;
signal msb1_n_112 : STD_LOGIC;
signal msb1_n_113 : STD_LOGIC;
signal msb1_n_114 : STD_LOGIC;
signal msb1_n_115 : STD_LOGIC;
signal msb1_n_116 : STD_LOGIC;
signal msb1_n_117 : STD_LOGIC;
signal msb1_n_118 : STD_LOGIC;
signal msb1_n_119 : STD_LOGIC;
signal msb1_n_120 : STD_LOGIC;
signal msb1_n_121 : STD_LOGIC;
signal msb1_n_122 : STD_LOGIC;
signal msb1_n_123 : STD_LOGIC;
signal msb1_n_124 : STD_LOGIC;
signal msb1_n_125 : STD_LOGIC;
signal msb1_n_126 : STD_LOGIC;
signal msb1_n_127 : STD_LOGIC;
signal msb1_n_128 : STD_LOGIC;
signal msb1_n_129 : STD_LOGIC;
signal msb1_n_130 : STD_LOGIC;
signal msb1_n_131 : STD_LOGIC;
signal msb1_n_132 : STD_LOGIC;
signal msb1_n_133 : STD_LOGIC;
signal msb1_n_134 : STD_LOGIC;
signal msb1_n_135 : STD_LOGIC;
signal msb1_n_136 : STD_LOGIC;
signal msb1_n_137 : STD_LOGIC;
signal msb1_n_138 : STD_LOGIC;
signal msb1_n_139 : STD_LOGIC;
signal msb1_n_140 : STD_LOGIC;
signal msb1_n_141 : STD_LOGIC;
signal msb1_n_142 : STD_LOGIC;
signal msb1_n_143 : STD_LOGIC;
signal msb1_n_144 : STD_LOGIC;
signal msb1_n_145 : STD_LOGIC;
signal msb1_n_146 : STD_LOGIC;
signal msb1_n_147 : STD_LOGIC;
signal msb1_n_148 : STD_LOGIC;
signal msb1_n_149 : STD_LOGIC;
signal msb1_n_150 : STD_LOGIC;
signal msb1_n_151 : STD_LOGIC;
signal msb1_n_152 : STD_LOGIC;
signal msb1_n_153 : STD_LOGIC;
signal msb1_n_58 : STD_LOGIC;
signal msb1_n_59 : STD_LOGIC;
signal msb1_n_60 : STD_LOGIC;
signal msb1_n_61 : STD_LOGIC;
signal msb1_n_62 : STD_LOGIC;
signal msb1_n_63 : STD_LOGIC;
signal msb1_n_64 : STD_LOGIC;
signal msb1_n_65 : STD_LOGIC;
signal msb1_n_66 : STD_LOGIC;
signal msb1_n_67 : STD_LOGIC;
signal msb1_n_68 : STD_LOGIC;
signal msb1_n_69 : STD_LOGIC;
signal msb1_n_70 : STD_LOGIC;
signal msb1_n_71 : STD_LOGIC;
signal msb1_n_72 : STD_LOGIC;
signal msb1_n_73 : STD_LOGIC;
signal msb1_n_74 : STD_LOGIC;
signal msb1_n_75 : STD_LOGIC;
signal msb1_n_76 : STD_LOGIC;
signal msb1_n_77 : STD_LOGIC;
signal msb1_n_78 : STD_LOGIC;
signal msb1_n_79 : STD_LOGIC;
signal msb1_n_80 : STD_LOGIC;
signal msb1_n_81 : STD_LOGIC;
signal msb1_n_82 : STD_LOGIC;
signal msb1_n_83 : STD_LOGIC;
signal msb1_n_84 : STD_LOGIC;
signal msb1_n_85 : STD_LOGIC;
signal msb1_n_86 : STD_LOGIC;
signal msb1_n_87 : STD_LOGIC;
signal msb1_n_88 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal sel0 : STD_LOGIC_VECTOR ( 22 downto 0 );
signal \y_11__s_net_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[11]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[11]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[15]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[15]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[15]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[19]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[22]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[22]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_100_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_101_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_102_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_103_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_104_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_105_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_106_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_107_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_108_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_109_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_110_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_111_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_112_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_113_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_114_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_115_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_116_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_117_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_118_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_119_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_120_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_121_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_122_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_123_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_124_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_125_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_126_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_127_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_128_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_129_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_130_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_131_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_132_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_133_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_134_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_135_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_136_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_137_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_138_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_139_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_140_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_141_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_142_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_143_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_144_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_145_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_146_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_147_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_148_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_149_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_150_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_151_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_152_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_153_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_154_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_155_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_156_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_157_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_158_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_159_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_15_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_160_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_161_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_162_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_163_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_164_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_165_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_166_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_167_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_168_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_169_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_16_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_170_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_171_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_172_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_173_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_174_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_175_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_176_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_177_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_178_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_179_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_17_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_180_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_181_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_182_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_183_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_184_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_185_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_186_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_187_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_188_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_189_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_18_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_190_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_191_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_192_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_193_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_194_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_195_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_196_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_197_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_198_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_199_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_19_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_200_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_201_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_202_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_203_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_204_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_205_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_206_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_207_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_208_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_209_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_20_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_210_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_211_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_212_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_213_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_214_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_215_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_216_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_217_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_218_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_219_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_21_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_220_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_221_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_222_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_223_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_224_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_225_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_226_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_227_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_228_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_229_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_22_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_230_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_231_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_232_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_233_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_234_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_235_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_236_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_237_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_238_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_239_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_240_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_241_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_242_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_243_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_244_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_245_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_246_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_29_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_30_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_31_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_32_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_33_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_34_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_35_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_36_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_37_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_38_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_39_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_40_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_41_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_42_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_43_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_44_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_45_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_46_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_47_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_48_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_49_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_50_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_51_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_52_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_53_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_54_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_55_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_56_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_57_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_58_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_59_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_60_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_61_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_62_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_63_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_64_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_65_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_66_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_67_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_68_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_69_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_70_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_71_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_72_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_73_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_74_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_75_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_76_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_77_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_78_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_79_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_80_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_81_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_82_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_83_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_94_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_95_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_96_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_97_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_98_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_99_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[3]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[3]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_1\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_2\ : STD_LOGIC;
signal \z[7]_INST_0_i_1_n_3\ : STD_LOGIC;
signal \z[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \z[7]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_1_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_2_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_3_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_4_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_5_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_6_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_i_7_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_0\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_1\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_2\ : STD_LOGIC;
signal \z_exponent0__0_carry_n_3\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_1\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_2\ : STD_LOGIC;
signal \z_exponent1_carry__0_n_3\ : STD_LOGIC;
signal \z_exponent1_carry_i_1__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_1_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_2__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_2_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_3__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_3_n_0 : STD_LOGIC;
signal \z_exponent1_carry_i_4__0_n_0\ : STD_LOGIC;
signal z_exponent1_carry_i_4_n_0 : STD_LOGIC;
signal z_exponent1_carry_i_5_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_0 : STD_LOGIC;
signal z_exponent1_carry_n_1 : STD_LOGIC;
signal z_exponent1_carry_n_2 : STD_LOGIC;
signal z_exponent1_carry_n_3 : STD_LOGIC;
signal NLW_L1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_L1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW__carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_msb1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_msb1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_msb1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_msb1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_msb1__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_msb1__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_msb1__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_msb1__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 31 );
signal \NLW_msb1__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_z_exponent1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of L1_carry_i_18 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_19 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_22 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_23 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_27 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of L1_carry_i_30 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of L1_carry_i_31 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of L1_carry_i_33 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of L1_carry_i_34 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of L1_carry_i_36 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_39 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_46 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of L1_carry_i_47 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of L1_carry_i_49 : label is "soft_lutpair24";
attribute SOFT_HLUTNM of L1_carry_i_52 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of L1_carry_i_53 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of L1_carry_i_54 : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \_carry_i_11\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \_carry_i_18\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \_carry_i_19\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \_carry_i_20\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \_carry_i_22\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_carry_i_24\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \_carry_i_6\ : label is "soft_lutpair27";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of msb1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \msb1__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_8\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[11]_INST_0_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[15]_INST_0_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_102\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_111\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_112\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_113\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_114\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_173\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_174\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_175\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_176\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_177\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_178\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_179\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_180\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_181\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_182\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_183\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_184\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_185\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_186\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_187\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_188\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_191\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_192\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_197\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_198\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_202\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_203\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_204\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_205\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_212\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_213\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_214\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_215\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_216\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_217\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_220\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_231\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_246\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_31\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_37\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_38\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_39\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_43\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_44\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_47\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_48\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_49\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_50\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_51\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_52\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_57\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_59\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_62\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_63\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_65\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_68\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_70\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_72\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_77\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_79\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_95\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \z[30]_INST_0_i_97\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_10\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \z[7]_INST_0_i_12\ : label is "soft_lutpair32";
attribute HLUTNM : string;
attribute HLUTNM of \z_exponent0__0_carry__0_i_2\ : label is "lutpair3";
attribute SOFT_HLUTNM of \z_exponent0__0_carry__0_i_8\ : label is "soft_lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \z_exponent0__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \z_exponent0__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \z_exponent0__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \z_exponent1_carry_i_1__0\ : label is "lutpair4";
attribute HLUTNM of \z_exponent1_carry_i_3__0\ : label is "lutpair2";
attribute HLUTNM of z_exponent1_carry_i_4 : label is "lutpair1";
attribute HLUTNM of \z_exponent1_carry_i_4__0\ : label is "lutpair3";
attribute HLUTNM of z_exponent1_carry_i_5 : label is "lutpair4";
begin
\y_11__s_net_1\ <= \y_11__s_port_\;
L1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => L1_carry_n_0,
CO(2) => L1_carry_n_1,
CO(1) => L1_carry_n_2,
CO(0) => L1_carry_n_3,
CYINIT => '1',
DI(3) => L1_carry_i_1_n_0,
DI(2) => L1_carry_i_2_n_0,
DI(1) => L1_carry_i_3_n_0,
DI(0) => L1_carry_i_4_n_0,
O(3 downto 0) => NLW_L1_carry_O_UNCONNECTED(3 downto 0),
S(3) => L1_carry_i_5_n_0,
S(2) => L1_carry_i_6_n_0,
S(1) => L1_carry_i_7_n_0,
S(0) => L1_carry_i_8_n_0
);
\L1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => L1_carry_n_0,
CO(3) => \L1_carry__0_n_0\,
CO(2) => \L1_carry__0_n_1\,
CO(1) => \L1_carry__0_n_2\,
CO(0) => \L1_carry__0_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__0_i_1_n_0\,
DI(2) => \L1_carry__0_i_2_n_0\,
DI(1) => \L1_carry__0_i_3_n_0\,
DI(0) => \L1_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__0_i_5_n_0\,
S(2) => \L1_carry__0_i_6_n_0\,
S(1) => \L1_carry__0_i_7_n_0\,
S(0) => \L1_carry__0_i_8_n_0\
);
\L1_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_1_n_0\
);
\L1_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_2_n_0\
);
\L1_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_3_n_0\
);
\L1_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_4_n_0\
);
\L1_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_5_n_0\
);
\L1_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_6_n_0\
);
\L1_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_7_n_0\
);
\L1_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__0_i_8_n_0\
);
\L1_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__0_n_0\,
CO(3) => \L1_carry__1_n_0\,
CO(2) => \L1_carry__1_n_1\,
CO(1) => \L1_carry__1_n_2\,
CO(0) => \L1_carry__1_n_3\,
CYINIT => '0',
DI(3) => \L1_carry__1_i_1_n_0\,
DI(2) => \L1_carry__1_i_2_n_0\,
DI(1) => \L1_carry__1_i_3_n_0\,
DI(0) => \L1_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_L1_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__1_i_5_n_0\,
S(2) => \L1_carry__1_i_6_n_0\,
S(1) => \L1_carry__1_i_7_n_0\,
S(0) => \L1_carry__1_i_8_n_0\
);
\L1_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_1_n_0\
);
\L1_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_2_n_0\
);
\L1_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_3_n_0\
);
\L1_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_4_n_0\
);
\L1_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_5_n_0\
);
\L1_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_6_n_0\
);
\L1_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_7_n_0\
);
\L1_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__1_i_8_n_0\
);
\L1_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \L1_carry__1_n_0\,
CO(3) => L1,
CO(2) => \L1_carry__2_n_1\,
CO(1) => \L1_carry__2_n_2\,
CO(0) => \L1_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \L1_carry__2_i_1_n_0\,
DI(1) => \L1_carry__2_i_2_n_0\,
DI(0) => \L1_carry__2_i_3_n_0\,
O(3 downto 0) => \NLW_L1_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \L1_carry__2_i_4_n_0\,
S(2) => \L1_carry__2_i_5_n_0\,
S(1) => \L1_carry__2_i_6_n_0\,
S(0) => \L1_carry__2_i_7_n_0\
);
\L1_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_1_n_0\
);
\L1_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_2_n_0\
);
\L1_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_3_n_0\
);
\L1_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_4_n_0\
);
\L1_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_5_n_0\
);
\L1_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_6_n_0\
);
\L1_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \L1_carry__2_i_7_n_0\
);
L1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2FFFF00000000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_1_n_0
);
L1_carry_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"4555FFFF45554555"
)
port map (
I0 => L1_carry_i_24_n_0,
I1 => L1_carry_i_25_n_0,
I2 => L1_carry_i_26_n_0,
I3 => L1_carry_i_27_n_0,
I4 => L1_carry_i_28_n_0,
I5 => L1_carry_i_29_n_0,
O => L1_carry_i_10_n_0
);
L1_carry_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF7550000"
)
port map (
I0 => L1_carry_i_30_n_0,
I1 => L1_carry_i_31_n_0,
I2 => L1_carry_i_32_n_0,
I3 => L1_carry_i_33_n_0,
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_35_n_0,
O => L1_carry_i_11_n_0
);
L1_carry_i_12: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_22_n_0,
I2 => L1_carry_i_19_n_0,
O => L1_carry_i_12_n_0
);
L1_carry_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
I4 => L1_carry_i_34_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_13_n_0
);
L1_carry_i_14: unisim.vcomponents.LUT5
generic map(
INIT => X"A9AA5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
O => L1_carry_i_14_n_0
);
L1_carry_i_15: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_15_n_0
);
L1_carry_i_16: unisim.vcomponents.LUT3
generic map(
INIT => X"65"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
O => L1_carry_i_16_n_0
);
L1_carry_i_17: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => L1_carry_i_17_n_0
);
L1_carry_i_18: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_34_n_0,
I1 => \msb1__1\(42),
I2 => \msb1__1\(43),
I3 => \msb1__1\(41),
I4 => \msb1__1\(40),
O => L1_carry_i_18_n_0
);
L1_carry_i_19: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => \msb1__1\(26),
I2 => \msb1__1\(27),
I3 => \msb1__1\(25),
I4 => \msb1__1\(24),
O => L1_carry_i_19_n_0
);
L1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_14_n_0,
I1 => L1_carry_i_15_n_0,
O => L1_carry_i_2_n_0
);
L1_carry_i_20: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(10),
I1 => \msb1__1\(11),
I2 => \msb1__1\(9),
I3 => \msb1__1\(8),
O => L1_carry_i_20_n_0
);
L1_carry_i_21: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(14),
I1 => \msb1__1\(15),
I2 => \msb1__1\(13),
I3 => \msb1__1\(12),
O => L1_carry_i_21_n_0
);
L1_carry_i_22: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_37_n_0,
I1 => \msb1__1\(16),
I2 => \msb1__1\(17),
I3 => \msb1__1\(19),
I4 => \msb1__1\(18),
O => L1_carry_i_22_n_0
);
L1_carry_i_23: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => L1_carry_i_33_n_0,
I1 => \msb1__1\(32),
I2 => \msb1__1\(33),
I3 => \msb1__1\(35),
I4 => \msb1__1\(34),
O => L1_carry_i_23_n_0
);
L1_carry_i_24: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000EFFFF"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
I2 => \msb1__1\(41),
I3 => \msb1__1\(40),
I4 => L1_carry_i_29_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_24_n_0
);
L1_carry_i_25: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F100"
)
port map (
I0 => L1_carry_i_39_n_0,
I1 => L1_carry_i_40_n_0,
I2 => L1_carry_i_41_n_0,
I3 => L1_carry_i_42_n_0,
I4 => \msb1__1\(35),
I5 => \msb1__1\(34),
O => L1_carry_i_25_n_0
);
L1_carry_i_26: unisim.vcomponents.LUT6
generic map(
INIT => X"1111110011111101"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(33),
I3 => \msb1__1\(34),
I4 => \msb1__1\(35),
I5 => \msb1__1\(32),
O => L1_carry_i_26_n_0
);
L1_carry_i_27: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(41),
I1 => \msb1__1\(40),
O => L1_carry_i_27_n_0
);
L1_carry_i_28: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111011111111"
)
port map (
I0 => \msb1__1\(45),
I1 => \msb1__1\(44),
I2 => L1_carry_i_43_n_0,
I3 => L1_carry_i_44_n_0,
I4 => L1_carry_i_39_n_0,
I5 => L1_carry_i_45_n_0,
O => L1_carry_i_28_n_0
);
L1_carry_i_29: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(47),
O => L1_carry_i_29_n_0
);
L1_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => L1_carry_i_16_n_0,
I1 => L1_carry_i_17_n_0,
O => L1_carry_i_3_n_0
);
L1_carry_i_30: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(41),
I2 => \msb1__1\(43),
I3 => \msb1__1\(42),
O => L1_carry_i_30_n_0
);
L1_carry_i_31: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(33),
I3 => \msb1__1\(32),
O => L1_carry_i_31_n_0
);
L1_carry_i_32: unisim.vcomponents.LUT6
generic map(
INIT => X"8A888A888A88AA88"
)
port map (
I0 => L1_carry_i_36_n_0,
I1 => L1_carry_i_46_n_0,
I2 => L1_carry_i_47_n_0,
I3 => L1_carry_i_37_n_0,
I4 => L1_carry_i_20_n_0,
I5 => L1_carry_i_21_n_0,
O => L1_carry_i_32_n_0
);
L1_carry_i_33: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(36),
I2 => \msb1__1\(38),
I3 => \msb1__1\(39),
O => L1_carry_i_33_n_0
);
L1_carry_i_34: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(47),
I1 => \msb1__1\(46),
I2 => \msb1__1\(45),
I3 => \msb1__1\(44),
O => L1_carry_i_34_n_0
);
L1_carry_i_35: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => L1_carry_i_48_n_0,
I1 => L1_carry_i_49_n_0,
I2 => L1_carry_i_34_n_0,
I3 => L1_carry_i_36_n_0,
I4 => L1_carry_i_21_n_0,
I5 => L1_carry_i_37_n_0,
O => L1_carry_i_35_n_0
);
L1_carry_i_36: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(29),
I2 => \msb1__1\(30),
I3 => \msb1__1\(31),
O => L1_carry_i_36_n_0
);
L1_carry_i_37: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(20),
I3 => \msb1__1\(21),
O => L1_carry_i_37_n_0
);
L1_carry_i_38: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(43),
O => L1_carry_i_38_n_0
);
L1_carry_i_39: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(23),
I1 => \msb1__1\(22),
I2 => \msb1__1\(18),
I3 => \msb1__1\(19),
O => L1_carry_i_39_n_0
);
L1_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"D"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_4_n_0
);
L1_carry_i_40: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFF2"
)
port map (
I0 => L1_carry_i_50_n_0,
I1 => L1_carry_i_51_n_0,
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(17),
I5 => \msb1__1\(16),
O => L1_carry_i_40_n_0
);
L1_carry_i_41: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFE0FF"
)
port map (
I0 => \msb1__1\(21),
I1 => \msb1__1\(20),
I2 => L1_carry_i_52_n_0,
I3 => L1_carry_i_53_n_0,
I4 => \msb1__1\(25),
I5 => \msb1__1\(24),
O => L1_carry_i_41_n_0
);
L1_carry_i_42: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111110001"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(31),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => \msb1__1\(29),
I5 => \msb1__1\(28),
O => L1_carry_i_42_n_0
);
L1_carry_i_43: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => \msb1__1\(3),
I2 => \msb1__1\(26),
I3 => \msb1__1\(27),
I4 => L1_carry_i_54_n_0,
I5 => L1_carry_i_38_n_0,
O => L1_carry_i_43_n_0
);
L1_carry_i_44: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(10),
I3 => \msb1__1\(11),
O => L1_carry_i_44_n_0
);
L1_carry_i_45: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \msb1__1\(34),
I1 => \msb1__1\(35),
I2 => \msb1__1\(15),
I3 => \msb1__1\(14),
I4 => \msb1__1\(31),
I5 => \msb1__1\(30),
O => L1_carry_i_45_n_0
);
L1_carry_i_46: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(25),
I2 => \msb1__1\(27),
I3 => \msb1__1\(26),
O => L1_carry_i_46_n_0
);
L1_carry_i_47: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \msb1__1\(18),
I1 => \msb1__1\(19),
I2 => \msb1__1\(17),
I3 => \msb1__1\(16),
O => L1_carry_i_47_n_0
);
L1_carry_i_48: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(39),
I3 => \msb1__1\(38),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => L1_carry_i_48_n_0
);
L1_carry_i_49: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(5),
I1 => \msb1__1\(4),
O => L1_carry_i_49_n_0
);
L1_carry_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => L1_carry_i_5_n_0
);
L1_carry_i_50: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF1"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(5),
I2 => \msb1__1\(11),
I3 => \msb1__1\(10),
I4 => \msb1__1\(6),
I5 => \msb1__1\(7),
O => L1_carry_i_50_n_0
);
L1_carry_i_51: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFFFE"
)
port map (
I0 => \msb1__1\(13),
I1 => \msb1__1\(12),
I2 => \msb1__1\(8),
I3 => \msb1__1\(9),
I4 => \msb1__1\(11),
I5 => \msb1__1\(10),
O => L1_carry_i_51_n_0
);
L1_carry_i_52: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(23),
O => L1_carry_i_52_n_0
);
L1_carry_i_53: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(28),
O => L1_carry_i_53_n_0
);
L1_carry_i_54: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(39),
I1 => \msb1__1\(38),
O => L1_carry_i_54_n_0
);
L1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => L1_carry_i_14_n_0,
O => L1_carry_i_6_n_0
);
L1_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => L1_carry_i_17_n_0,
I1 => L1_carry_i_16_n_0,
O => L1_carry_i_7_n_0
);
L1_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => L1_carry_i_8_n_0
);
L1_carry_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"00808888AAAAAAAA"
)
port map (
I0 => L1_carry_i_18_n_0,
I1 => L1_carry_i_19_n_0,
I2 => L1_carry_i_20_n_0,
I3 => L1_carry_i_21_n_0,
I4 => L1_carry_i_22_n_0,
I5 => L1_carry_i_23_n_0,
O => L1_carry_i_9_n_0
);
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \_carry_n_4\,
O(2) => \_carry_n_5\,
O(1) => \_carry_n_6\,
O(0) => \_carry_n_7\,
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => p_0_in(1)
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__0_n_4\,
O(2) => \_carry__0_n_5\,
O(1) => \_carry__0_n_6\,
O(0) => \_carry__0_n_7\,
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200AAAAFDFF5555"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3) => \_carry__1_n_0\,
CO(2) => \_carry__1_n_1\,
CO(1) => \_carry__1_n_2\,
CO(0) => \_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__1_n_4\,
O(2) => \_carry__1_n_5\,
O(1) => \_carry__1_n_6\,
O(0) => \_carry__1_n_7\,
S(3) => \_carry__1_i_1_n_0\,
S(2) => \_carry__1_i_2_n_0\,
S(1) => \_carry__1_i_3_n_0\,
S(0) => \_carry__1_i_4_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_1_n_0\
);
\_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_2_n_0\
);
\_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_3_n_0\
);
\_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__1_i_4_n_0\
);
\_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__1_n_0\,
CO(3) => \_carry__2_n_0\,
CO(2) => \_carry__2_n_1\,
CO(1) => \_carry__2_n_2\,
CO(0) => \_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__2_n_4\,
O(2) => \_carry__2_n_5\,
O(1) => \_carry__2_n_6\,
O(0) => \_carry__2_n_7\,
S(3) => \_carry__2_i_1_n_0\,
S(2) => \_carry__2_i_2_n_0\,
S(1) => \_carry__2_i_3_n_0\,
S(0) => \_carry__2_i_4_n_0\
);
\_carry__2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_1_n_0\
);
\_carry__2_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_2_n_0\
);
\_carry__2_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_3_n_0\
);
\_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__2_i_4_n_0\
);
\_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__2_n_0\,
CO(3) => \_carry__3_n_0\,
CO(2) => \_carry__3_n_1\,
CO(1) => \_carry__3_n_2\,
CO(0) => \_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__3_n_4\,
O(2) => \_carry__3_n_5\,
O(1) => \_carry__3_n_6\,
O(0) => \_carry__3_n_7\,
S(3) => \_carry__3_i_1_n_0\,
S(2) => \_carry__3_i_2_n_0\,
S(1) => \_carry__3_i_3_n_0\,
S(0) => \_carry__3_i_4_n_0\
);
\_carry__3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_1_n_0\
);
\_carry__3_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_2_n_0\
);
\_carry__3_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_3_n_0\
);
\_carry__3_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__3_i_4_n_0\
);
\_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__3_n_0\,
CO(3) => \_carry__4_n_0\,
CO(2) => \_carry__4_n_1\,
CO(1) => \_carry__4_n_2\,
CO(0) => \_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__4_n_4\,
O(2) => \_carry__4_n_5\,
O(1) => \_carry__4_n_6\,
O(0) => \_carry__4_n_7\,
S(3) => \_carry__4_i_1_n_0\,
S(2) => \_carry__4_i_2_n_0\,
S(1) => \_carry__4_i_3_n_0\,
S(0) => \_carry__4_i_4_n_0\
);
\_carry__4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_1_n_0\
);
\_carry__4_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_2_n_0\
);
\_carry__4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_3_n_0\
);
\_carry__4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__4_i_4_n_0\
);
\_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__4_n_0\,
CO(3) => \_carry__5_n_0\,
CO(2) => \_carry__5_n_1\,
CO(1) => \_carry__5_n_2\,
CO(0) => \_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \_carry__5_n_4\,
O(2) => \_carry__5_n_5\,
O(1) => \_carry__5_n_6\,
O(0) => \_carry__5_n_7\,
S(3) => \_carry__5_i_1_n_0\,
S(2) => \_carry__5_i_2_n_0\,
S(1) => \_carry__5_i_3_n_0\,
S(0) => \_carry__5_i_4_n_0\
);
\_carry__5_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_1_n_0\
);
\_carry__5_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_2_n_0\
);
\_carry__5_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_3_n_0\
);
\_carry__5_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__5_i_4_n_0\
);
\_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__5_n_0\,
CO(3 downto 1) => \NLW__carry__6_CO_UNCONNECTED\(3 downto 1),
CO(0) => \_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW__carry__6_O_UNCONNECTED\(3 downto 2),
O(1) => \_carry__6_n_6\,
O(0) => \_carry__6_n_7\,
S(3 downto 2) => B"00",
S(1) => \_carry__6_i_1_n_0\,
S(0) => \_carry__6_i_2_n_0\
);
\_carry__6_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_1_n_0\
);
\_carry__6_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555D0000FFFFFFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
I5 => L1_carry_i_13_n_0,
O => \_carry__6_i_2_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBABAA"
)
port map (
I0 => \msb1__1\(47),
I1 => \_carry_i_6_n_0\,
I2 => \_carry_i_7_n_0\,
I3 => \_carry_i_8_n_0\,
I4 => \_carry_i_9_n_0\,
O => \_carry_i_1_n_0\
);
\_carry_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => L1_carry_i_10_n_0,
O => \_carry_i_10_n_0\
);
\_carry_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(42),
I1 => \msb1__1\(40),
O => \_carry_i_11_n_0\
);
\_carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(24),
I2 => \msb1__1\(28),
I3 => \_carry_i_18_n_0\,
I4 => \msb1__1\(26),
I5 => \msb1__1\(27),
O => \_carry_i_12_n_0\
);
\_carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(14),
I2 => \msb1__1\(18),
I3 => \_carry_i_19_n_0\,
I4 => \msb1__1\(16),
I5 => \msb1__1\(17),
O => \_carry_i_13_n_0\
);
\_carry_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EFEE"
)
port map (
I0 => \_carry_i_20_n_0\,
I1 => \msb1__1\(7),
I2 => \msb1__1\(6),
I3 => \msb1__1\(5),
I4 => \_carry_i_21_n_0\,
O => \_carry_i_14_n_0\
);
\_carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00BA"
)
port map (
I0 => \msb1__1\(11),
I1 => \msb1__1\(10),
I2 => \msb1__1\(9),
I3 => \msb1__1\(12),
I4 => \_carry_i_22_n_0\,
I5 => \msb1__1\(13),
O => \_carry_i_15_n_0\
);
\_carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(20),
I1 => \msb1__1\(19),
I2 => \msb1__1\(23),
I3 => \_carry_i_23_n_0\,
I4 => \msb1__1\(21),
I5 => \msb1__1\(22),
O => \_carry_i_16_n_0\
);
\_carry_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(30),
I1 => \msb1__1\(29),
I2 => \msb1__1\(33),
I3 => \_carry_i_24_n_0\,
I4 => \msb1__1\(31),
I5 => \msb1__1\(32),
O => \_carry_i_17_n_0\
);
\_carry_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(32),
I1 => \msb1__1\(30),
O => \_carry_i_18_n_0\
);
\_carry_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(22),
I1 => \msb1__1\(20),
O => \_carry_i_19_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \_carry_i_2_n_0\
);
\_carry_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"5504"
)
port map (
I0 => \msb1__1\(4),
I1 => \msb1__1\(1),
I2 => \msb1__1\(2),
I3 => \msb1__1\(3),
O => \_carry_i_20_n_0\
);
\_carry_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF4"
)
port map (
I0 => \msb1__1\(7),
I1 => \msb1__1\(6),
I2 => \msb1__1\(12),
I3 => \msb1__1\(10),
I4 => \msb1__1\(8),
O => \_carry_i_21_n_0\
);
\_carry_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(17),
I1 => \msb1__1\(15),
O => \_carry_i_22_n_0\
);
\_carry_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(25),
O => \_carry_i_23_n_0\
);
\_carry_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \msb1__1\(37),
I1 => \msb1__1\(35),
O => \_carry_i_24_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => L1_carry_i_16_n_0,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_10_n_0\,
O => p_0_in(1)
);
\_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \msb1__1\(46),
I1 => \msb1__1\(45),
I2 => \msb1__1\(44),
O => \_carry_i_6_n_0\
);
\_carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0FFFFFFF4"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
I2 => \msb1__1\(38),
I3 => \_carry_i_11_n_0\,
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \_carry_i_7_n_0\
);
\_carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55551110"
)
port map (
I0 => \_carry_i_12_n_0\,
I1 => \_carry_i_13_n_0\,
I2 => \_carry_i_14_n_0\,
I3 => \_carry_i_15_n_0\,
I4 => \_carry_i_16_n_0\,
I5 => \_carry_i_17_n_0\,
O => \_carry_i_8_n_0\
);
\_carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF00F4"
)
port map (
I0 => \msb1__1\(40),
I1 => \msb1__1\(39),
I2 => \msb1__1\(41),
I3 => \msb1__1\(42),
I4 => \msb1__1\(45),
I5 => \msb1__1\(43),
O => \_carry_i_9_n_0\
);
msb1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_msb1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => '0',
B(16 downto 0) => x(16 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_msb1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_msb1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_msb1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_msb1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_msb1_OVERFLOW_UNCONNECTED,
P(47) => msb1_n_58,
P(46) => msb1_n_59,
P(45) => msb1_n_60,
P(44) => msb1_n_61,
P(43) => msb1_n_62,
P(42) => msb1_n_63,
P(41) => msb1_n_64,
P(40) => msb1_n_65,
P(39) => msb1_n_66,
P(38) => msb1_n_67,
P(37) => msb1_n_68,
P(36) => msb1_n_69,
P(35) => msb1_n_70,
P(34) => msb1_n_71,
P(33) => msb1_n_72,
P(32) => msb1_n_73,
P(31) => msb1_n_74,
P(30) => msb1_n_75,
P(29) => msb1_n_76,
P(28) => msb1_n_77,
P(27) => msb1_n_78,
P(26) => msb1_n_79,
P(25) => msb1_n_80,
P(24) => msb1_n_81,
P(23) => msb1_n_82,
P(22) => msb1_n_83,
P(21) => msb1_n_84,
P(20) => msb1_n_85,
P(19) => msb1_n_86,
P(18) => msb1_n_87,
P(17) => msb1_n_88,
P(16 downto 0) => \msb1__1\(16 downto 0),
PATTERNBDETECT => NLW_msb1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_msb1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => msb1_n_106,
PCOUT(46) => msb1_n_107,
PCOUT(45) => msb1_n_108,
PCOUT(44) => msb1_n_109,
PCOUT(43) => msb1_n_110,
PCOUT(42) => msb1_n_111,
PCOUT(41) => msb1_n_112,
PCOUT(40) => msb1_n_113,
PCOUT(39) => msb1_n_114,
PCOUT(38) => msb1_n_115,
PCOUT(37) => msb1_n_116,
PCOUT(36) => msb1_n_117,
PCOUT(35) => msb1_n_118,
PCOUT(34) => msb1_n_119,
PCOUT(33) => msb1_n_120,
PCOUT(32) => msb1_n_121,
PCOUT(31) => msb1_n_122,
PCOUT(30) => msb1_n_123,
PCOUT(29) => msb1_n_124,
PCOUT(28) => msb1_n_125,
PCOUT(27) => msb1_n_126,
PCOUT(26) => msb1_n_127,
PCOUT(25) => msb1_n_128,
PCOUT(24) => msb1_n_129,
PCOUT(23) => msb1_n_130,
PCOUT(22) => msb1_n_131,
PCOUT(21) => msb1_n_132,
PCOUT(20) => msb1_n_133,
PCOUT(19) => msb1_n_134,
PCOUT(18) => msb1_n_135,
PCOUT(17) => msb1_n_136,
PCOUT(16) => msb1_n_137,
PCOUT(15) => msb1_n_138,
PCOUT(14) => msb1_n_139,
PCOUT(13) => msb1_n_140,
PCOUT(12) => msb1_n_141,
PCOUT(11) => msb1_n_142,
PCOUT(10) => msb1_n_143,
PCOUT(9) => msb1_n_144,
PCOUT(8) => msb1_n_145,
PCOUT(7) => msb1_n_146,
PCOUT(6) => msb1_n_147,
PCOUT(5) => msb1_n_148,
PCOUT(4) => msb1_n_149,
PCOUT(3) => msb1_n_150,
PCOUT(2) => msb1_n_151,
PCOUT(1) => msb1_n_152,
PCOUT(0) => msb1_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_msb1_UNDERFLOW_UNCONNECTED
);
\msb1__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 23) => B"0000001",
A(22 downto 0) => y(22 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_msb1__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 6) => B"000000000001",
B(5 downto 0) => x(22 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_msb1__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_msb1__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_msb1__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_msb1__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_msb1__0_OVERFLOW_UNCONNECTED\,
P(47 downto 31) => \NLW_msb1__0_P_UNCONNECTED\(47 downto 31),
P(30 downto 0) => \msb1__1\(47 downto 17),
PATTERNBDETECT => \NLW_msb1__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_msb1__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => msb1_n_106,
PCIN(46) => msb1_n_107,
PCIN(45) => msb1_n_108,
PCIN(44) => msb1_n_109,
PCIN(43) => msb1_n_110,
PCIN(42) => msb1_n_111,
PCIN(41) => msb1_n_112,
PCIN(40) => msb1_n_113,
PCIN(39) => msb1_n_114,
PCIN(38) => msb1_n_115,
PCIN(37) => msb1_n_116,
PCIN(36) => msb1_n_117,
PCIN(35) => msb1_n_118,
PCIN(34) => msb1_n_119,
PCIN(33) => msb1_n_120,
PCIN(32) => msb1_n_121,
PCIN(31) => msb1_n_122,
PCIN(30) => msb1_n_123,
PCIN(29) => msb1_n_124,
PCIN(28) => msb1_n_125,
PCIN(27) => msb1_n_126,
PCIN(26) => msb1_n_127,
PCIN(25) => msb1_n_128,
PCIN(24) => msb1_n_129,
PCIN(23) => msb1_n_130,
PCIN(22) => msb1_n_131,
PCIN(21) => msb1_n_132,
PCIN(20) => msb1_n_133,
PCIN(19) => msb1_n_134,
PCIN(18) => msb1_n_135,
PCIN(17) => msb1_n_136,
PCIN(16) => msb1_n_137,
PCIN(15) => msb1_n_138,
PCIN(14) => msb1_n_139,
PCIN(13) => msb1_n_140,
PCIN(12) => msb1_n_141,
PCIN(11) => msb1_n_142,
PCIN(10) => msb1_n_143,
PCIN(9) => msb1_n_144,
PCIN(8) => msb1_n_145,
PCIN(7) => msb1_n_146,
PCIN(6) => msb1_n_147,
PCIN(5) => msb1_n_148,
PCIN(4) => msb1_n_149,
PCIN(3) => msb1_n_150,
PCIN(2) => msb1_n_151,
PCIN(1) => msb1_n_152,
PCIN(0) => msb1_n_153,
PCOUT(47 downto 0) => \NLW_msb1__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_msb1__0_UNDERFLOW_UNCONNECTED\
);
\z[11]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[7]_INST_0_i_1_n_0\,
CO(3) => \z[11]_INST_0_i_1_n_0\,
CO(2) => \z[11]_INST_0_i_1_n_1\,
CO(1) => \z[11]_INST_0_i_1_n_2\,
CO(0) => \z[11]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(11 downto 8),
S(3) => sel0(11),
S(2) => \z[11]_INST_0_i_3_n_0\,
S(1 downto 0) => sel0(9 downto 8)
);
\z[11]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
O => sel0(11)
);
\z[11]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => \z[11]_INST_0_i_3_n_0\
);
\z[11]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_6_n_0\,
O => sel0(9)
);
\z[11]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[11]_INST_0_i_7_n_0\,
O => sel0(8)
);
\z[11]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_50_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_52_n_0\,
O => \z[11]_INST_0_i_6_n_0\
);
\z[11]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[11]_INST_0_i_9_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_54_n_0\,
O => \z[11]_INST_0_i_7_n_0\
);
\z[11]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_98_n_0\,
O => \z[11]_INST_0_i_8_n_0\
);
\z[11]_INST_0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_101_n_0\,
O => \z[11]_INST_0_i_9_n_0\
);
\z[15]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[11]_INST_0_i_1_n_0\,
CO(3) => \z[15]_INST_0_i_1_n_0\,
CO(2) => \z[15]_INST_0_i_1_n_1\,
CO(1) => \z[15]_INST_0_i_1_n_2\,
CO(0) => \z[15]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(15 downto 12),
S(3 downto 0) => sel0(15 downto 12)
);
\z[15]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_14_n_0\,
O => sel0(15)
);
\z[15]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_15_n_0\,
O => sel0(14)
);
\z[15]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_6_n_0\,
O => sel0(13)
);
\z[15]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
O => sel0(12)
);
\z[15]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[15]_INST_0_i_8_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_60_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_63_n_0\,
O => \z[15]_INST_0_i_6_n_0\
);
\z[15]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_48_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[15]_INST_0_i_8_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_65_n_0\,
O => \z[15]_INST_0_i_7_n_0\
);
\z[15]_INST_0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_120_n_0\,
O => \z[15]_INST_0_i_8_n_0\
);
\z[19]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[15]_INST_0_i_1_n_0\,
CO(3) => \z[19]_INST_0_i_1_n_0\,
CO(2) => \z[19]_INST_0_i_1_n_1\,
CO(1) => \z[19]_INST_0_i_1_n_2\,
CO(0) => \z[19]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(19 downto 16),
S(3 downto 0) => sel0(19 downto 16)
);
\z[19]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
O => sel0(19)
);
\z[19]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_18_n_0\,
O => sel0(18)
);
\z[19]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_19_n_0\,
O => sel0(17)
);
\z[19]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_20_n_0\,
O => sel0(16)
);
\z[22]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[19]_INST_0_i_1_n_0\,
CO(3 downto 2) => \NLW_z[22]_INST_0_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \z[22]_INST_0_i_1_n_2\,
CO(0) => \z[22]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_z[22]_INST_0_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => z_mantissa(22 downto 20),
S(3) => '0',
S(2 downto 0) => sel0(22 downto 20)
);
\z[22]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F2F2FFF2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_76_n_0\,
I3 => L1,
I4 => \z[22]_INST_0_i_5_n_0\,
O => sel0(22)
);
\z[22]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_22_n_0\,
O => sel0(21)
);
\z[22]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_82_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_67_n_0\,
I4 => L1,
I5 => \z[22]_INST_0_i_6_n_0\,
O => sel0(20)
);
\z[22]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_168_n_0\,
I1 => \z[30]_INST_0_i_154_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_158_n_0\,
O => \z[22]_INST_0_i_5_n_0\
);
\z[22]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_154_n_0\,
I1 => \z[30]_INST_0_i_155_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_158_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_152_n_0\,
O => \z[22]_INST_0_i_6_n_0\
);
\z[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(0),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(0),
I5 => \y_11__s_net_1\,
O => z(0)
);
\z[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(1),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(1),
I5 => \y_11__s_net_1\,
O => z(1)
);
\z[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(2),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(2),
I5 => \y_11__s_net_1\,
O => z(2)
);
\z[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(3),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(3),
I5 => \y_11__s_net_1\,
O => z(3)
);
\z[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(4),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(4),
I5 => \y_11__s_net_1\,
O => z(4)
);
\z[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(5),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(5),
I5 => \y_11__s_net_1\,
O => z(5)
);
\z[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(6),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(6),
I5 => \y_11__s_net_1\,
O => z(6)
);
\z[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0002"
)
port map (
I0 => data0(7),
I1 => \z[30]_INST_0_i_1_n_0\,
I2 => \z[30]_INST_0_i_2_n_0\,
I3 => \z[30]_INST_0_i_3_n_0\,
I4 => data1(7),
I5 => \y_11__s_net_1\,
O => z(7)
);
\z[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \z[30]_INST_0_i_5_n_0\,
I1 => \z[30]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => sel0(0),
I4 => \z[30]_INST_0_i_9_n_0\,
I5 => sel0(2),
O => \z[30]_INST_0_i_1_n_0\
);
\z[30]_INST_0_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => sel0(2)
);
\z[30]_INST_0_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_181_n_0\,
I1 => \z[30]_INST_0_i_182_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_183_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_184_n_0\,
O => \z[30]_INST_0_i_100_n_0\
);
\z[30]_INST_0_i_101\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_185_n_0\,
I1 => \z[30]_INST_0_i_186_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_187_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_188_n_0\,
O => \z[30]_INST_0_i_101_n_0\
);
\z[30]_INST_0_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_189_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_171_n_0\,
O => \z[30]_INST_0_i_102_n_0\
);
\z[30]_INST_0_i_103\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF4FFF7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_103_n_0\
);
\z[30]_INST_0_i_104\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_183_n_0\,
I1 => \z[30]_INST_0_i_184_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_190_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_181_n_0\,
O => \z[30]_INST_0_i_104_n_0\
);
\z[30]_INST_0_i_105\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_187_n_0\,
I1 => \z[30]_INST_0_i_188_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_191_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_105_n_0\
);
\z[30]_INST_0_i_106\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_175_n_0\,
I1 => \z[30]_INST_0_i_176_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_192_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_106_n_0\
);
\z[30]_INST_0_i_107\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(3),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_107_n_0\
);
\z[30]_INST_0_i_108\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_179_n_0\,
I1 => \z[30]_INST_0_i_180_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_193_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_177_n_0\,
O => \z[30]_INST_0_i_108_n_0\
);
\z[30]_INST_0_i_109\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4F7FFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \msb1__1\(2),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_109_n_0\
);
\z[30]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_47_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_48_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_49_n_0\,
O => \z[30]_INST_0_i_11_n_0\
);
\z[30]_INST_0_i_110\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_190_n_0\,
I1 => \z[30]_INST_0_i_181_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_195_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_183_n_0\,
O => \z[30]_INST_0_i_110_n_0\
);
\z[30]_INST_0_i_111\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_191_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_185_n_0\,
O => \z[30]_INST_0_i_111_n_0\
);
\z[30]_INST_0_i_112\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_196_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_187_n_0\,
O => \z[30]_INST_0_i_112_n_0\
);
\z[30]_INST_0_i_113\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_192_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_173_n_0\,
O => \z[30]_INST_0_i_113_n_0\
);
\z[30]_INST_0_i_114\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_197_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_175_n_0\,
O => \z[30]_INST_0_i_114_n_0\
);
\z[30]_INST_0_i_115\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFF3FAAFFFFFFFF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \z[30]_INST_0_i_198_n_0\,
I3 => L1,
I4 => \_carry_n_4\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_115_n_0\
);
\z[30]_INST_0_i_116\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_199_n_0\,
I1 => \_carry__0_n_6\,
I2 => \_carry__5_n_6\,
I3 => \_carry__0_n_5\,
I4 => \z[30]_INST_0_i_200_n_0\,
I5 => \z[30]_INST_0_i_201_n_0\,
O => \z[30]_INST_0_i_116_n_0\
);
\z[30]_INST_0_i_117\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_117_n_0\
);
\z[30]_INST_0_i_118\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C33AAAA"
)
port map (
I0 => \_carry_n_6\,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_10_n_0,
I3 => \_carry_i_1_n_0\,
I4 => L1,
O => \z[30]_INST_0_i_118_n_0\
);
\z[30]_INST_0_i_119\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEAEFFFF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \_carry_n_4\,
I2 => L1,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(1),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_119_n_0\
);
\z[30]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_50_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_47_n_0\,
I4 => \z[30]_INST_0_i_51_n_0\,
O => sel0(10)
);
\z[30]_INST_0_i_120\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_176_n_0\,
I1 => \z[30]_INST_0_i_202_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_173_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_174_n_0\,
O => \z[30]_INST_0_i_120_n_0\
);
\z[30]_INST_0_i_121\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_180_n_0\,
I1 => \z[30]_INST_0_i_203_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_177_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_178_n_0\,
O => \z[30]_INST_0_i_121_n_0\
);
\z[30]_INST_0_i_122\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_184_n_0\,
I1 => \z[30]_INST_0_i_204_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_181_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_182_n_0\,
O => \z[30]_INST_0_i_122_n_0\
);
\z[30]_INST_0_i_123\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => \z[30]_INST_0_i_205_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_185_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_186_n_0\,
O => \z[30]_INST_0_i_123_n_0\
);
\z[30]_INST_0_i_124\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_206_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_208_n_0\,
O => \z[30]_INST_0_i_124_n_0\
);
\z[30]_INST_0_i_125\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_209_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_95_n_0\,
I4 => \z[30]_INST_0_i_210_n_0\,
O => \z[30]_INST_0_i_125_n_0\
);
\z[30]_INST_0_i_126\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_96_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_206_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_207_n_0\,
O => \z[30]_INST_0_i_126_n_0\
);
\z[30]_INST_0_i_127\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_172_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_209_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_132_n_0\,
O => \z[30]_INST_0_i_127_n_0\
);
\z[30]_INST_0_i_128\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA03030AFA03F3F"
)
port map (
I0 => \z[30]_INST_0_i_211_n_0\,
I1 => \z[30]_INST_0_i_212_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_213_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_128_n_0\
);
\z[30]_INST_0_i_129\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_129_n_0\
);
\z[30]_INST_0_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_52_n_0\,
I1 => \z[30]_INST_0_i_53_n_0\,
I2 => \z[30]_INST_0_i_54_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_55_n_0\,
O => \z[30]_INST_0_i_13_n_0\
);
\z[30]_INST_0_i_130\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_182_n_0\,
I1 => \z[30]_INST_0_i_215_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_184_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_204_n_0\,
O => \z[30]_INST_0_i_130_n_0\
);
\z[30]_INST_0_i_131\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0AF3030A0AF3F3F"
)
port map (
I0 => \z[30]_INST_0_i_216_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_131_n_0\
);
\z[30]_INST_0_i_132\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(0),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(8),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_132_n_0\
);
\z[30]_INST_0_i_133\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(4),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(12),
O => \z[30]_INST_0_i_133_n_0\
);
\z[30]_INST_0_i_134\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(2),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_134_n_0\
);
\z[30]_INST_0_i_135\: unisim.vcomponents.LUT6
generic map(
INIT => X"1510D5DFFFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => L1_carry_i_17_n_0,
I2 => L1,
I3 => \_carry_n_5\,
I4 => \msb1__1\(14),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_135_n_0\
);
\z[30]_INST_0_i_136\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_207_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_136_n_0\
);
\z[30]_INST_0_i_137\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_218_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_148_n_0\,
O => \z[30]_INST_0_i_137_n_0\
);
\z[30]_INST_0_i_138\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_138_n_0\
);
\z[30]_INST_0_i_139\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8B88888"
)
port map (
I0 => \z[30]_INST_0_i_188_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(40),
I3 => L1_carry_i_14_n_0,
I4 => L1_carry_i_15_n_0,
I5 => \msb1__1\(24),
O => \z[30]_INST_0_i_139_n_0\
);
\z[30]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_56_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_58_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_59_n_0\,
O => \z[30]_INST_0_i_14_n_0\
);
\z[30]_INST_0_i_140\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_140_n_0\
);
\z[30]_INST_0_i_141\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_202_n_0\,
O => \z[30]_INST_0_i_141_n_0\
);
\z[30]_INST_0_i_142\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_178_n_0\,
I1 => \z[30]_INST_0_i_214_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_180_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_203_n_0\,
O => \z[30]_INST_0_i_142_n_0\
);
\z[30]_INST_0_i_143\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_208_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_207_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_146_n_0\,
O => \z[30]_INST_0_i_143_n_0\
);
\z[30]_INST_0_i_144\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_210_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_132_n_0\,
I3 => \z[30]_INST_0_i_118_n_0\,
I4 => \z[30]_INST_0_i_133_n_0\,
O => \z[30]_INST_0_i_144_n_0\
);
\z[30]_INST_0_i_145\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_186_n_0\,
I1 => \z[30]_INST_0_i_217_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_188_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_205_n_0\,
O => \z[30]_INST_0_i_145_n_0\
);
\z[30]_INST_0_i_146\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(5),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(13),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_146_n_0\
);
\z[30]_INST_0_i_147\: unisim.vcomponents.LUT6
generic map(
INIT => X"77CF44CC77CF77CF"
)
port map (
I0 => \msb1__1\(9),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(1),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(17),
O => \z[30]_INST_0_i_147_n_0\
);
\z[30]_INST_0_i_148\: unisim.vcomponents.LUT6
generic map(
INIT => X"7757555777F7FFF7"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(15),
I2 => \_carry_n_5\,
I3 => L1,
I4 => L1_carry_i_17_n_0,
I5 => \msb1__1\(7),
O => \z[30]_INST_0_i_148_n_0\
);
\z[30]_INST_0_i_149\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF47474747"
)
port map (
I0 => \msb1__1\(19),
I1 => \z[30]_INST_0_i_194_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(11),
I5 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_149_n_0\
);
\z[30]_INST_0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_60_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_61_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_62_n_0\,
O => \z[30]_INST_0_i_15_n_0\
);
\z[30]_INST_0_i_150\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_133_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_166_n_0\,
O => \z[30]_INST_0_i_150_n_0\
);
\z[30]_INST_0_i_151\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5DD0511"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_151_n_0\
);
\z[30]_INST_0_i_152\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_219_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_211_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_212_n_0\,
O => \z[30]_INST_0_i_152_n_0\
);
\z[30]_INST_0_i_153\: unisim.vcomponents.LUT6
generic map(
INIT => X"505FC0C0505FCFCF"
)
port map (
I0 => \z[30]_INST_0_i_203_n_0\,
I1 => \z[30]_INST_0_i_220_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_178_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_214_n_0\,
O => \z[30]_INST_0_i_153_n_0\
);
\z[30]_INST_0_i_154\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_221_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_182_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_215_n_0\,
O => \z[30]_INST_0_i_154_n_0\
);
\z[30]_INST_0_i_155\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_222_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_216_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_217_n_0\,
O => \z[30]_INST_0_i_155_n_0\
);
\z[30]_INST_0_i_156\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_147_n_0\,
O => \z[30]_INST_0_i_156_n_0\
);
\z[30]_INST_0_i_157\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFBBA088"
)
port map (
I0 => \z[30]_INST_0_i_134_n_0\,
I1 => \_carry_n_6\,
I2 => L1_carry_i_16_n_0,
I3 => L1,
I4 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_157_n_0\
);
\z[30]_INST_0_i_158\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_203_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => \z[30]_INST_0_i_220_n_0\,
O => \z[30]_INST_0_i_158_n_0\
);
\z[30]_INST_0_i_159\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_224_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_219_n_0\,
O => \z[30]_INST_0_i_159_n_0\
);
\z[30]_INST_0_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_63_n_0\,
I1 => \z[30]_INST_0_i_64_n_0\,
I2 => \z[30]_INST_0_i_65_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_66_n_0\,
O => \z[30]_INST_0_i_16_n_0\
);
\z[30]_INST_0_i_160\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_225_n_0\,
I1 => \z[30]_INST_0_i_222_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_221_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_226_n_0\,
O => \z[30]_INST_0_i_160_n_0\
);
\z[30]_INST_0_i_161\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \z[30]_INST_0_i_166_n_0\,
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_227_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_228_n_0\,
O => \z[30]_INST_0_i_161_n_0\
);
\z[30]_INST_0_i_162\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(14),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(6),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(22),
O => \z[30]_INST_0_i_162_n_0\
);
\z[30]_INST_0_i_163\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \msb1__1\(10),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_170_n_0\,
I4 => \msb1__1\(18),
O => \z[30]_INST_0_i_163_n_0\
);
\z[30]_INST_0_i_164\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_223_n_0\,
I1 => \z[30]_INST_0_i_229_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_219_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_230_n_0\,
O => \z[30]_INST_0_i_164_n_0\
);
\z[30]_INST_0_i_165\: unisim.vcomponents.LUT5
generic map(
INIT => X"47CC47FF"
)
port map (
I0 => \msb1__1\(13),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(21),
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(5),
O => \z[30]_INST_0_i_165_n_0\
);
\z[30]_INST_0_i_166\: unisim.vcomponents.LUT6
generic map(
INIT => X"4447CCCF4447FFFF"
)
port map (
I0 => \msb1__1\(8),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(16),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(0),
O => \z[30]_INST_0_i_166_n_0\
);
\z[30]_INST_0_i_167\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BFB0B0B0BFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_170_n_0\,
I1 => \msb1__1\(12),
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(20),
I4 => \z[30]_INST_0_i_194_n_0\,
I5 => \msb1__1\(4),
O => \z[30]_INST_0_i_167_n_0\
);
\z[30]_INST_0_i_168\: unisim.vcomponents.LUT6
generic map(
INIT => X"7477FFFF74770000"
)
port map (
I0 => \z[30]_INST_0_i_217_n_0\,
I1 => L1_carry_i_17_n_0,
I2 => L1_carry_i_14_n_0,
I3 => \z[30]_INST_0_i_231_n_0\,
I4 => L1_carry_i_16_n_0,
I5 => \z[30]_INST_0_i_222_n_0\,
O => \z[30]_INST_0_i_168_n_0\
);
\z[30]_INST_0_i_169\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6FFFFAAA60000"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_169_n_0\
);
\z[30]_INST_0_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_68_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_69_n_0\,
O => \z[30]_INST_0_i_17_n_0\
);
\z[30]_INST_0_i_170\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A55FFFF9A550000"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z[30]_INST_0_i_232_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => L1_carry_i_9_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_170_n_0\
);
\z[30]_INST_0_i_171\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFF7FFF70FF7F"
)
port map (
I0 => \z[30]_INST_0_i_194_n_0\,
I1 => \msb1__1\(0),
I2 => \z[30]_INST_0_i_118_n_0\,
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(4),
I5 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_171_n_0\
);
\z[30]_INST_0_i_172\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FFF7FF"
)
port map (
I0 => \msb1__1\(2),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \z[30]_INST_0_i_194_n_0\,
I4 => \msb1__1\(6),
O => \z[30]_INST_0_i_172_n_0\
);
\z[30]_INST_0_i_173\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(29),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(13),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(45),
O => \z[30]_INST_0_i_173_n_0\
);
\z[30]_INST_0_i_174\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(37),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(21),
O => \z[30]_INST_0_i_174_n_0\
);
\z[30]_INST_0_i_175\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(25),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(9),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(41),
O => \z[30]_INST_0_i_175_n_0\
);
\z[30]_INST_0_i_176\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(33),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(17),
O => \z[30]_INST_0_i_176_n_0\
);
\z[30]_INST_0_i_177\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(27),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(11),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(43),
O => \z[30]_INST_0_i_177_n_0\
);
\z[30]_INST_0_i_178\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(35),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_178_n_0\
);
\z[30]_INST_0_i_179\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(7),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(39),
O => \z[30]_INST_0_i_179_n_0\
);
\z[30]_INST_0_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_68_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_71_n_0\,
O => \z[30]_INST_0_i_18_n_0\
);
\z[30]_INST_0_i_180\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACACF000"
)
port map (
I0 => \msb1__1\(15),
I1 => \msb1__1\(47),
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(31),
I4 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_180_n_0\
);
\z[30]_INST_0_i_181\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(14),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(46),
O => \z[30]_INST_0_i_181_n_0\
);
\z[30]_INST_0_i_182\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(38),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_182_n_0\
);
\z[30]_INST_0_i_183\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(26),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(10),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(42),
O => \z[30]_INST_0_i_183_n_0\
);
\z[30]_INST_0_i_184\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(34),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_184_n_0\
);
\z[30]_INST_0_i_185\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(28),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(12),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(44),
O => \z[30]_INST_0_i_185_n_0\
);
\z[30]_INST_0_i_186\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => \msb1__1\(36),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(20),
O => \z[30]_INST_0_i_186_n_0\
);
\z[30]_INST_0_i_187\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(24),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(8),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(40),
O => \z[30]_INST_0_i_187_n_0\
);
\z[30]_INST_0_i_188\: unisim.vcomponents.LUT4
generic map(
INIT => X"88C0"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(32),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_188_n_0\
);
\z[30]_INST_0_i_189\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFFBFFFBFBF"
)
port map (
I0 => \z[30]_INST_0_i_118_n_0\,
I1 => \msb1__1\(2),
I2 => \z[30]_INST_0_i_194_n_0\,
I3 => L1_carry_i_17_n_0,
I4 => L1,
I5 => \_carry_n_5\,
O => \z[30]_INST_0_i_189_n_0\
);
\z[30]_INST_0_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_43_n_0\,
I3 => \z[30]_INST_0_i_70_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_73_n_0\,
O => \z[30]_INST_0_i_19_n_0\
);
\z[30]_INST_0_i_190\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(6),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(38),
O => \z[30]_INST_0_i_190_n_0\
);
\z[30]_INST_0_i_191\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(36),
O => \z[30]_INST_0_i_191_n_0\
);
\z[30]_INST_0_i_192\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(37),
O => \z[30]_INST_0_i_192_n_0\
);
\z[30]_INST_0_i_193\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(19),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(3),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(35),
O => \z[30]_INST_0_i_193_n_0\
);
\z[30]_INST_0_i_194\: unisim.vcomponents.LUT6
generic map(
INIT => X"5DA200005DA2FFFF"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => L1_carry_i_12_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_194_n_0\
);
\z[30]_INST_0_i_195\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(18),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(2),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(34),
O => \z[30]_INST_0_i_195_n_0\
);
\z[30]_INST_0_i_196\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(16),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(0),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(32),
O => \z[30]_INST_0_i_196_n_0\
);
\z[30]_INST_0_i_197\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_14_n_0,
I2 => \msb1__1\(1),
I3 => L1_carry_i_15_n_0,
I4 => \msb1__1\(33),
O => \z[30]_INST_0_i_197_n_0\
);
\z[30]_INST_0_i_198\: unisim.vcomponents.LUT5
generic map(
INIT => X"555DAAA2"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => \_carry_i_1_n_0\,
I2 => L1_carry_i_10_n_0,
I3 => L1_carry_i_11_n_0,
I4 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_198_n_0\
);
\z[30]_INST_0_i_199\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_4\,
I1 => \_carry__3_n_4\,
I2 => \_carry__4_n_4\,
I3 => \_carry__5_n_5\,
I4 => \z[30]_INST_0_i_233_n_0\,
O => \z[30]_INST_0_i_199_n_0\
);
\z[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \z[30]_INST_0_i_11_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_13_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
I4 => \z[30]_INST_0_i_15_n_0\,
I5 => \z[30]_INST_0_i_16_n_0\,
O => \z[30]_INST_0_i_2_n_0\
);
\z[30]_INST_0_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_72_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_59_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_74_n_0\,
O => \z[30]_INST_0_i_20_n_0\
);
\z[30]_INST_0_i_200\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__1_n_4\,
I1 => \_carry__6_n_6\,
I2 => \_carry__0_n_7\,
I3 => \_carry__4_n_5\,
I4 => \z[30]_INST_0_i_234_n_0\,
O => \z[30]_INST_0_i_200_n_0\
);
\z[30]_INST_0_i_201\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \_carry__2_n_5\,
I1 => \_carry__6_n_7\,
I2 => \_carry__0_n_4\,
I3 => \_carry__5_n_7\,
I4 => \z[30]_INST_0_i_235_n_0\,
O => \z[30]_INST_0_i_201_n_0\
);
\z[30]_INST_0_i_202\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(41),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(25),
O => \z[30]_INST_0_i_202_n_0\
);
\z[30]_INST_0_i_203\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(39),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(23),
O => \z[30]_INST_0_i_203_n_0\
);
\z[30]_INST_0_i_204\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(42),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(26),
O => \z[30]_INST_0_i_204_n_0\
);
\z[30]_INST_0_i_205\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(40),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(24),
O => \z[30]_INST_0_i_205_n_0\
);
\z[30]_INST_0_i_206\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(5),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_206_n_0\
);
\z[30]_INST_0_i_207\: unisim.vcomponents.LUT6
generic map(
INIT => X"4747FF47FFFFFF47"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \msb1__1\(9),
I3 => \_carry_n_4\,
I4 => L1,
I5 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_207_n_0\
);
\z[30]_INST_0_i_208\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCF44FFFFCF77"
)
port map (
I0 => \msb1__1\(7),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(3),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \z[30]_INST_0_i_170_n_0\,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_208_n_0\
);
\z[30]_INST_0_i_209\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FFFFFFF3FAFAF"
)
port map (
I0 => \_carry_n_5\,
I1 => L1_carry_i_17_n_0,
I2 => \msb1__1\(4),
I3 => L1_carry_i_14_n_0,
I4 => L1,
I5 => \_carry_n_4\,
O => \z[30]_INST_0_i_209_n_0\
);
\z[30]_INST_0_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_75_n_0\,
I1 => \z[30]_INST_0_i_76_n_0\,
I2 => \z[30]_INST_0_i_77_n_0\,
I3 => \z[30]_INST_0_i_78_n_0\,
I4 => \z[30]_INST_0_i_79_n_0\,
I5 => \z[30]_INST_0_i_80_n_0\,
O => \z[30]_INST_0_i_21_n_0\
);
\z[30]_INST_0_i_210\: unisim.vcomponents.LUT6
generic map(
INIT => X"CF44CF77FFFFFFFF"
)
port map (
I0 => \msb1__1\(6),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \msb1__1\(2),
I3 => \z[30]_INST_0_i_169_n_0\,
I4 => \msb1__1\(10),
I5 => \z[30]_INST_0_i_194_n_0\,
O => \z[30]_INST_0_i_210_n_0\
);
\z[30]_INST_0_i_211\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(21),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(37),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_211_n_0\
);
\z[30]_INST_0_i_212\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(45),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(29),
O => \z[30]_INST_0_i_212_n_0\
);
\z[30]_INST_0_i_213\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(17),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(33),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_213_n_0\
);
\z[30]_INST_0_i_214\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(43),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(27),
O => \z[30]_INST_0_i_214_n_0\
);
\z[30]_INST_0_i_215\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F5F"
)
port map (
I0 => \msb1__1\(46),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(30),
O => \z[30]_INST_0_i_215_n_0\
);
\z[30]_INST_0_i_216\: unisim.vcomponents.LUT4
generic map(
INIT => X"773F"
)
port map (
I0 => \msb1__1\(20),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(36),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_216_n_0\
);
\z[30]_INST_0_i_217\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0A0"
)
port map (
I0 => \msb1__1\(44),
I1 => L1_carry_i_14_n_0,
I2 => L1_carry_i_15_n_0,
I3 => \msb1__1\(28),
O => \z[30]_INST_0_i_217_n_0\
);
\z[30]_INST_0_i_218\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF444F4FFF777F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_169_n_0\,
I2 => \_carry_n_4\,
I3 => L1,
I4 => L1_carry_i_14_n_0,
I5 => \msb1__1\(11),
O => \z[30]_INST_0_i_218_n_0\
);
\z[30]_INST_0_i_219\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(25),
I1 => \msb1__1\(41),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(33),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_219_n_0\
);
\z[30]_INST_0_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0DDD0D0000DD0D"
)
port map (
I0 => \z[30]_INST_0_i_43_n_0\,
I1 => \z[30]_INST_0_i_81_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_82_n_0\,
I4 => L1,
I5 => \z[30]_INST_0_i_83_n_0\,
O => \z[30]_INST_0_i_22_n_0\
);
\z[30]_INST_0_i_220\: unisim.vcomponents.LUT4
generic map(
INIT => X"3777"
)
port map (
I0 => \msb1__1\(47),
I1 => L1_carry_i_15_n_0,
I2 => \msb1__1\(31),
I3 => \z[30]_INST_0_i_198_n_0\,
O => \z[30]_INST_0_i_220_n_0\
);
\z[30]_INST_0_i_221\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(26),
I1 => \msb1__1\(42),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(34),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_221_n_0\
);
\z[30]_INST_0_i_222\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(24),
I1 => \msb1__1\(40),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(32),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_222_n_0\
);
\z[30]_INST_0_i_223\: unisim.vcomponents.LUT6
generic map(
INIT => X"103F1F3FFFFFFFFF"
)
port map (
I0 => \msb1__1\(27),
I1 => \msb1__1\(43),
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_198_n_0\,
I4 => \msb1__1\(35),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_223_n_0\
);
\z[30]_INST_0_i_224\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(29),
I1 => \msb1__1\(45),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(37),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_224_n_0\
);
\z[30]_INST_0_i_225\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F103F1FFFFFFFFF"
)
port map (
I0 => \msb1__1\(28),
I1 => \msb1__1\(44),
I2 => L1_carry_i_17_n_0,
I3 => L1_carry_i_14_n_0,
I4 => \msb1__1\(36),
I5 => L1_carry_i_15_n_0,
O => \z[30]_INST_0_i_225_n_0\
);
\z[30]_INST_0_i_226\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0EFEFEF"
)
port map (
I0 => \z[30]_INST_0_i_236_n_0\,
I1 => \z[30]_INST_0_i_237_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(46),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_238_n_0\,
O => \z[30]_INST_0_i_226_n_0\
);
\z[30]_INST_0_i_227\: unisim.vcomponents.LUT4
generic map(
INIT => X"E2FF"
)
port map (
I0 => \_carry_n_4\,
I1 => L1,
I2 => L1_carry_i_14_n_0,
I3 => \msb1__1\(12),
O => \z[30]_INST_0_i_227_n_0\
);
\z[30]_INST_0_i_228\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBA808A"
)
port map (
I0 => \msb1__1\(20),
I1 => \z[30]_INST_0_i_198_n_0\,
I2 => L1,
I3 => \_carry_n_4\,
I4 => \msb1__1\(4),
O => \z[30]_INST_0_i_228_n_0\
);
\z[30]_INST_0_i_229\: unisim.vcomponents.LUT6
generic map(
INIT => X"10105050101F5F5F"
)
port map (
I0 => \z[30]_INST_0_i_239_n_0\,
I1 => \msb1__1\(39),
I2 => L1_carry_i_17_n_0,
I3 => \msb1__1\(47),
I4 => L1_carry_i_15_n_0,
I5 => \z[30]_INST_0_i_240_n_0\,
O => \z[30]_INST_0_i_229_n_0\
);
\z[30]_INST_0_i_230\: unisim.vcomponents.LUT6
generic map(
INIT => X"50503030505F3F3F"
)
port map (
I0 => \z[30]_INST_0_i_241_n_0\,
I1 => \z[30]_INST_0_i_242_n_0\,
I2 => L1_carry_i_17_n_0,
I3 => \z[30]_INST_0_i_243_n_0\,
I4 => \z[30]_INST_0_i_198_n_0\,
I5 => \z[30]_INST_0_i_244_n_0\,
O => \z[30]_INST_0_i_230_n_0\
);
\z[30]_INST_0_i_231\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => L1_carry_i_15_n_0,
I1 => \msb1__1\(36),
O => \z[30]_INST_0_i_231_n_0\
);
\z[30]_INST_0_i_232\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAEAEAEFFFFFFAE"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_29_n_0,
I2 => L1_carry_i_28_n_0,
I3 => \z[30]_INST_0_i_245_n_0\,
I4 => L1_carry_i_25_n_0,
I5 => L1_carry_i_24_n_0,
O => \z[30]_INST_0_i_232_n_0\
);
\z[30]_INST_0_i_233\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_6\,
I1 => \_carry__1_n_6\,
I2 => \_carry__3_n_6\,
I3 => \_carry__1_n_7\,
O => \z[30]_INST_0_i_233_n_0\
);
\z[30]_INST_0_i_234\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__2_n_7\,
I1 => L1,
I2 => \_carry__3_n_5\,
I3 => \_carry__1_n_5\,
O => \z[30]_INST_0_i_234_n_0\
);
\z[30]_INST_0_i_235\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \_carry__5_n_4\,
I1 => \_carry__3_n_7\,
I2 => \_carry__4_n_6\,
I3 => \_carry__4_n_7\,
O => \z[30]_INST_0_i_235_n_0\
);
\z[30]_INST_0_i_236\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3CC333341441111"
)
port map (
I0 => \msb1__1\(38),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_236_n_0\
);
\z[30]_INST_0_i_237\: unisim.vcomponents.LUT6
generic map(
INIT => X"343344441C11CCCC"
)
port map (
I0 => \msb1__1\(22),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_237_n_0\
);
\z[30]_INST_0_i_238\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(30),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_238_n_0\
);
\z[30]_INST_0_i_239\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808880820200020"
)
port map (
I0 => \msb1__1\(23),
I1 => L1_carry_i_13_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \_carry_i_1_n_0\,
I4 => \z[30]_INST_0_i_232_n_0\,
I5 => L1_carry_i_12_n_0,
O => \z[30]_INST_0_i_239_n_0\
);
\z[30]_INST_0_i_240\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800888820220000"
)
port map (
I0 => \msb1__1\(31),
I1 => L1_carry_i_12_n_0,
I2 => \z[30]_INST_0_i_232_n_0\,
I3 => \_carry_i_1_n_0\,
I4 => L1_carry_i_9_n_0,
I5 => L1_carry_i_13_n_0,
O => \z[30]_INST_0_i_240_n_0\
);
\z[30]_INST_0_i_241\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(21),
O => \z[30]_INST_0_i_241_n_0\
);
\z[30]_INST_0_i_242\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_242_n_0\
);
\z[30]_INST_0_i_243\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(29),
O => \z[30]_INST_0_i_243_n_0\
);
\z[30]_INST_0_i_244\: unisim.vcomponents.LUT6
generic map(
INIT => X"66A6555500000000"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => L1_carry_i_9_n_0,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_232_n_0\,
I4 => L1_carry_i_12_n_0,
I5 => \msb1__1\(45),
O => \z[30]_INST_0_i_244_n_0\
);
\z[30]_INST_0_i_245\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF5D5"
)
port map (
I0 => L1_carry_i_27_n_0,
I1 => \msb1__1\(32),
I2 => \z[30]_INST_0_i_246_n_0\,
I3 => \msb1__1\(33),
I4 => \msb1__1\(36),
I5 => \msb1__1\(37),
O => \z[30]_INST_0_i_245_n_0\
);
\z[30]_INST_0_i_246\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \msb1__1\(35),
I1 => \msb1__1\(34),
O => \z[30]_INST_0_i_246_n_0\
);
\z[30]_INST_0_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_97_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_29_n_0\
);
\z[30]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \z[30]_INST_0_i_17_n_0\,
I1 => \z[30]_INST_0_i_18_n_0\,
I2 => \z[30]_INST_0_i_19_n_0\,
I3 => \z[30]_INST_0_i_20_n_0\,
I4 => \z[30]_INST_0_i_21_n_0\,
I5 => \z[30]_INST_0_i_22_n_0\,
O => \z[30]_INST_0_i_3_n_0\
);
\z[30]_INST_0_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \z[30]_INST_0_i_99_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_100_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_101_n_0\,
O => \z[30]_INST_0_i_30_n_0\
);
\z[30]_INST_0_i_31\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_102_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_103_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_31_n_0\
);
\z[30]_INST_0_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \z[30]_INST_0_i_105_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_99_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_106_n_0\,
O => \z[30]_INST_0_i_32_n_0\
);
\z[30]_INST_0_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_97_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_33_n_0\
);
\z[30]_INST_0_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \z[30]_INST_0_i_104_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_98_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_99_n_0\,
O => \z[30]_INST_0_i_34_n_0\
);
\z[30]_INST_0_i_35\: unisim.vcomponents.LUT6
generic map(
INIT => X"4700FFFF47004700"
)
port map (
I0 => \z[30]_INST_0_i_107_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_94_n_0\,
I3 => \z[30]_INST_0_i_43_n_0\,
I4 => \z[30]_INST_0_i_102_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_35_n_0\
);
\z[30]_INST_0_i_36\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \z[30]_INST_0_i_106_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_101_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_104_n_0\,
O => \z[30]_INST_0_i_36_n_0\
);
\z[30]_INST_0_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_106_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_108_n_0\,
O => \z[30]_INST_0_i_37_n_0\
);
\z[30]_INST_0_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_104_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_105_n_0\,
O => \z[30]_INST_0_i_38_n_0\
);
\z[30]_INST_0_i_39\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_103_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_109_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_39_n_0\
);
\z[30]_INST_0_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_110_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_111_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_112_n_0\,
O => \z[30]_INST_0_i_40_n_0\
);
\z[30]_INST_0_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \z[30]_INST_0_i_108_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_113_n_0\,
I3 => L1_carry_i_16_n_0,
I4 => \z[30]_INST_0_i_114_n_0\,
O => \z[30]_INST_0_i_41_n_0\
);
\z[30]_INST_0_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFD8"
)
port map (
I0 => L1,
I1 => L1_carry_i_16_n_0,
I2 => \_carry_n_6\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_95_n_0\,
O => \z[30]_INST_0_i_42_n_0\
);
\z[30]_INST_0_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_43_n_0\
);
\z[30]_INST_0_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_105_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_110_n_0\,
O => \z[30]_INST_0_i_44_n_0\
);
\z[30]_INST_0_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040F00000404"
)
port map (
I0 => \z[30]_INST_0_i_117_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_115_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_45_n_0\
);
\z[30]_INST_0_i_46\: unisim.vcomponents.LUT5
generic map(
INIT => X"10FF1010"
)
port map (
I0 => \z[30]_INST_0_i_95_n_0\,
I1 => \z[30]_INST_0_i_119_n_0\,
I2 => \z[30]_INST_0_i_57_n_0\,
I3 => \z[30]_INST_0_i_109_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_46_n_0\
);
\z[30]_INST_0_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_120_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_121_n_0\,
O => \z[30]_INST_0_i_47_n_0\
);
\z[30]_INST_0_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_123_n_0\,
O => \z[30]_INST_0_i_48_n_0\
);
\z[30]_INST_0_i_49\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_124_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_125_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_49_n_0\
);
\z[30]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_29_n_0\,
I1 => \z[30]_INST_0_i_30_n_0\,
I2 => \z[30]_INST_0_i_31_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_32_n_0\,
O => \z[30]_INST_0_i_5_n_0\
);
\z[30]_INST_0_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_123_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_50_n_0\
);
\z[30]_INST_0_i_51\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_125_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_126_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_51_n_0\
);
\z[30]_INST_0_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_126_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_127_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_52_n_0\
);
\z[30]_INST_0_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_121_n_0\,
I1 => \z[30]_INST_0_i_98_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_123_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_100_n_0\,
O => \z[30]_INST_0_i_53_n_0\
);
\z[30]_INST_0_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"47FF474700FF0000"
)
port map (
I0 => \z[30]_INST_0_i_94_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_96_n_0\,
I3 => \z[30]_INST_0_i_127_n_0\,
I4 => \z[30]_INST_0_i_43_n_0\,
I5 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_54_n_0\
);
\z[30]_INST_0_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_100_n_0\,
I1 => \z[30]_INST_0_i_101_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_121_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_98_n_0\,
O => \z[30]_INST_0_i_55_n_0\
);
\z[30]_INST_0_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_128_n_0\,
I1 => \z[30]_INST_0_i_129_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_130_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_131_n_0\,
O => \z[30]_INST_0_i_56_n_0\
);
\z[30]_INST_0_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry_i_1_n_0\,
I1 => \z[30]_INST_0_i_116_n_0\,
O => \z[30]_INST_0_i_57_n_0\
);
\z[30]_INST_0_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_132_n_0\,
I1 => \z[30]_INST_0_i_133_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_134_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_135_n_0\,
O => \z[30]_INST_0_i_58_n_0\
);
\z[30]_INST_0_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_136_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_137_n_0\,
O => \z[30]_INST_0_i_59_n_0\
);
\z[30]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"115F1F5F"
)
port map (
I0 => \z[30]_INST_0_i_33_n_0\,
I1 => \z[30]_INST_0_i_34_n_0\,
I2 => \z[30]_INST_0_i_35_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_36_n_0\,
O => \z[30]_INST_0_i_6_n_0\
);
\z[30]_INST_0_i_60\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_138_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_139_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_60_n_0\
);
\z[30]_INST_0_i_61\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \z[30]_INST_0_i_140_n_0\,
I1 => L1_carry_i_16_n_0,
I2 => \z[30]_INST_0_i_141_n_0\,
I3 => \_carry_i_10_n_0\,
I4 => \z[30]_INST_0_i_142_n_0\,
O => \z[30]_INST_0_i_61_n_0\
);
\z[30]_INST_0_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_58_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_143_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_62_n_0\
);
\z[30]_INST_0_i_63\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_143_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_144_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_63_n_0\
);
\z[30]_INST_0_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_142_n_0\,
I1 => \z[30]_INST_0_i_120_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_145_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_122_n_0\,
O => \z[30]_INST_0_i_64_n_0\
);
\z[30]_INST_0_i_65\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \z[30]_INST_0_i_144_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_124_n_0\,
I3 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_65_n_0\
);
\z[30]_INST_0_i_66\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_122_n_0\,
I1 => \z[30]_INST_0_i_123_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_142_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_120_n_0\,
O => \z[30]_INST_0_i_66_n_0\
);
\z[30]_INST_0_i_67\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_146_n_0\,
I1 => \z[30]_INST_0_i_147_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_148_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_149_n_0\,
O => \z[30]_INST_0_i_67_n_0\
);
\z[30]_INST_0_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_150_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_151_n_0\,
O => \z[30]_INST_0_i_68_n_0\
);
\z[30]_INST_0_i_69\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_152_n_0\,
I1 => \z[30]_INST_0_i_153_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_154_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_155_n_0\,
O => \z[30]_INST_0_i_69_n_0\
);
\z[30]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => sel0(3)
);
\z[30]_INST_0_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_137_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_156_n_0\,
O => \z[30]_INST_0_i_70_n_0\
);
\z[30]_INST_0_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_155_n_0\,
I1 => \z[30]_INST_0_i_130_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_152_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_153_n_0\,
O => \z[30]_INST_0_i_71_n_0\
);
\z[30]_INST_0_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_157_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_150_n_0\,
O => \z[30]_INST_0_i_72_n_0\
);
\z[30]_INST_0_i_73\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_153_n_0\,
I1 => \z[30]_INST_0_i_128_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_130_n_0\,
O => \z[30]_INST_0_i_73_n_0\
);
\z[30]_INST_0_i_74\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_130_n_0\,
I1 => \z[30]_INST_0_i_131_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_153_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_128_n_0\,
O => \z[30]_INST_0_i_74_n_0\
);
\z[30]_INST_0_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"000002A2AAAA02A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_158_n_0\,
I2 => \_carry_i_10_n_0\,
I3 => \z[30]_INST_0_i_159_n_0\,
I4 => \_carry_i_1_n_0\,
I5 => \z[30]_INST_0_i_160_n_0\,
O => \z[30]_INST_0_i_75_n_0\
);
\z[30]_INST_0_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"4C4C4C4040404C40"
)
port map (
I0 => \z[30]_INST_0_i_161_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_162_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_163_n_0\,
O => \z[30]_INST_0_i_76_n_0\
);
\z[30]_INST_0_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_81_n_0\,
I1 => \z[30]_INST_0_i_57_n_0\,
O => \z[30]_INST_0_i_77_n_0\
);
\z[30]_INST_0_i_78\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_164_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_155_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_78_n_0\
);
\z[30]_INST_0_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \z[30]_INST_0_i_57_n_0\,
I1 => \z[30]_INST_0_i_67_n_0\,
O => \z[30]_INST_0_i_79_n_0\
);
\z[30]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A80FFFF8A808A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_40_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_41_n_0\,
I4 => \z[30]_INST_0_i_42_n_0\,
I5 => \z[30]_INST_0_i_43_n_0\,
O => sel0(0)
);
\z[30]_INST_0_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \z[30]_INST_0_i_82_n_0\,
I1 => \z[30]_INST_0_i_43_n_0\,
O => \z[30]_INST_0_i_80_n_0\
);
\z[30]_INST_0_i_81\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_148_n_0\,
I1 => \z[30]_INST_0_i_149_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_147_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_165_n_0\,
O => \z[30]_INST_0_i_81_n_0\
);
\z[30]_INST_0_i_82\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFC05F5FCFC05050"
)
port map (
I0 => \z[30]_INST_0_i_163_n_0\,
I1 => \z[30]_INST_0_i_135_n_0\,
I2 => \z[30]_INST_0_i_95_n_0\,
I3 => \z[30]_INST_0_i_166_n_0\,
I4 => \z[30]_INST_0_i_118_n_0\,
I5 => \z[30]_INST_0_i_167_n_0\,
O => \z[30]_INST_0_i_82_n_0\
);
\z[30]_INST_0_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_158_n_0\,
I1 => \z[30]_INST_0_i_152_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_168_n_0\,
I4 => \_carry_i_10_n_0\,
I5 => \z[30]_INST_0_i_154_n_0\,
O => \z[30]_INST_0_i_83_n_0\
);
\z[30]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_41_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[30]_INST_0_i_44_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_45_n_0\,
O => \z[30]_INST_0_i_9_n_0\
);
\z[30]_INST_0_i_94\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(1),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_169_n_0\,
I3 => \msb1__1\(5),
I4 => \z[30]_INST_0_i_170_n_0\,
O => \z[30]_INST_0_i_94_n_0\
);
\z[30]_INST_0_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => \_carry_n_7\,
I1 => \_carry_i_10_n_0\,
I2 => L1,
O => \z[30]_INST_0_i_95_n_0\
);
\z[30]_INST_0_i_96\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF4F7"
)
port map (
I0 => \msb1__1\(3),
I1 => \z[30]_INST_0_i_118_n_0\,
I2 => \z[30]_INST_0_i_170_n_0\,
I3 => \msb1__1\(7),
I4 => \z[30]_INST_0_i_169_n_0\,
O => \z[30]_INST_0_i_96_n_0\
);
\z[30]_INST_0_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_171_n_0\,
I1 => \z[30]_INST_0_i_95_n_0\,
I2 => \z[30]_INST_0_i_172_n_0\,
O => \z[30]_INST_0_i_97_n_0\
);
\z[30]_INST_0_i_98\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_173_n_0\,
I1 => \z[30]_INST_0_i_174_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_175_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_176_n_0\,
O => \z[30]_INST_0_i_98_n_0\
);
\z[30]_INST_0_i_99\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \z[30]_INST_0_i_177_n_0\,
I1 => \z[30]_INST_0_i_178_n_0\,
I2 => L1_carry_i_16_n_0,
I3 => \z[30]_INST_0_i_179_n_0\,
I4 => L1_carry_i_17_n_0,
I5 => \z[30]_INST_0_i_180_n_0\,
O => \z[30]_INST_0_i_99_n_0\
);
\z[3]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z[3]_INST_0_i_1_n_0\,
CO(2) => \z[3]_INST_0_i_1_n_1\,
CO(1) => \z[3]_INST_0_i_1_n_2\,
CO(0) => \z[3]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => sel0(0),
O(3 downto 0) => z_mantissa(3 downto 0),
S(3) => \z[3]_INST_0_i_2_n_0\,
S(2) => \z[3]_INST_0_i_3_n_0\,
S(1) => sel0(1),
S(0) => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_37_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_38_n_0\,
I4 => \z[30]_INST_0_i_39_n_0\,
O => \z[3]_INST_0_i_2_n_0\
);
\z[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8A80"
)
port map (
I0 => L1,
I1 => \z[30]_INST_0_i_44_n_0\,
I2 => \_carry_i_1_n_0\,
I3 => \z[30]_INST_0_i_37_n_0\,
I4 => \z[30]_INST_0_i_46_n_0\,
O => \z[3]_INST_0_i_3_n_0\
);
\z[3]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
O => sel0(1)
);
\z[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAA9AA"
)
port map (
I0 => sel0(0),
I1 => \z[30]_INST_0_i_3_n_0\,
I2 => \z[3]_INST_0_i_6_n_0\,
I3 => \z[3]_INST_0_i_7_n_0\,
I4 => \z[3]_INST_0_i_8_n_0\,
I5 => \z[3]_INST_0_i_9_n_0\,
O => \z[3]_INST_0_i_5_n_0\
);
\z[3]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => sel0(0),
I1 => sel0(2),
I2 => \z[7]_INST_0_i_8_n_0\,
I3 => \z[7]_INST_0_i_6_n_0\,
O => \z[3]_INST_0_i_6_n_0\
);
\z[3]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
I1 => sel0(10),
I2 => \z[30]_INST_0_i_11_n_0\,
I3 => \z[30]_INST_0_i_15_n_0\,
O => \z[3]_INST_0_i_7_n_0\
);
\z[3]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \z[15]_INST_0_i_7_n_0\,
I1 => \z[15]_INST_0_i_6_n_0\,
I2 => sel0(3),
I3 => \z[7]_INST_0_i_7_n_0\,
O => \z[3]_INST_0_i_8_n_0\
);
\z[3]_INST_0_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \z[30]_INST_0_i_9_n_0\,
I1 => \z[11]_INST_0_i_6_n_0\,
I2 => \z[11]_INST_0_i_7_n_0\,
I3 => \z[30]_INST_0_i_14_n_0\,
O => \z[3]_INST_0_i_9_n_0\
);
\z[7]_INST_0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \z[3]_INST_0_i_1_n_0\,
CO(3) => \z[7]_INST_0_i_1_n_0\,
CO(2) => \z[7]_INST_0_i_1_n_1\,
CO(1) => \z[7]_INST_0_i_1_n_2\,
CO(0) => \z[7]_INST_0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => z_mantissa(7 downto 4),
S(3 downto 0) => sel0(7 downto 4)
);
\z[7]_INST_0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_98_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_99_n_0\,
O => \z[7]_INST_0_i_10_n_0\
);
\z[7]_INST_0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_101_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_104_n_0\,
O => \z[7]_INST_0_i_11_n_0\
);
\z[7]_INST_0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \z[30]_INST_0_i_99_n_0\,
I1 => \_carry_i_10_n_0\,
I2 => \z[30]_INST_0_i_106_n_0\,
O => \z[7]_INST_0_i_12_n_0\
);
\z[7]_INST_0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_6_n_0\,
O => sel0(7)
);
\z[7]_INST_0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_7_n_0\,
O => sel0(6)
);
\z[7]_INST_0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_8_n_0\,
O => sel0(5)
);
\z[7]_INST_0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \z[7]_INST_0_i_9_n_0\,
O => sel0(4)
);
\z[7]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_10_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[11]_INST_0_i_9_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_29_n_0\,
O => \z[7]_INST_0_i_6_n_0\
);
\z[7]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_11_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_10_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_33_n_0\,
O => \z[7]_INST_0_i_7_n_0\
);
\z[7]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[7]_INST_0_i_12_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_11_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_35_n_0\,
O => \z[7]_INST_0_i_8_n_0\
);
\z[7]_INST_0_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"000047FF"
)
port map (
I0 => \z[30]_INST_0_i_38_n_0\,
I1 => \_carry_i_1_n_0\,
I2 => \z[7]_INST_0_i_12_n_0\,
I3 => L1,
I4 => \z[30]_INST_0_i_31_n_0\,
O => \z[7]_INST_0_i_9_n_0\
);
\z_exponent0__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \z_exponent0__0_carry_n_0\,
CO(2) => \z_exponent0__0_carry_n_1\,
CO(1) => \z_exponent0__0_carry_n_2\,
CO(0) => \z_exponent0__0_carry_n_3\,
CYINIT => '1',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent0__0_carry_i_3_n_0\,
DI(0) => '1',
O(3 downto 0) => data0(3 downto 0),
S(3) => \z_exponent0__0_carry_i_4_n_0\,
S(2) => \z_exponent0__0_carry_i_5_n_0\,
S(1) => \z_exponent0__0_carry_i_6_n_0\,
S(0) => \z_exponent0__0_carry_i_7_n_0\
);
\z_exponent0__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \z_exponent0__0_carry_n_0\,
CO(3) => \NLW_z_exponent0__0_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent0__0_carry__0_n_1\,
CO(1) => \z_exponent0__0_carry__0_n_2\,
CO(0) => \z_exponent0__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data0(7 downto 4),
S(3) => \z_exponent0__0_carry__0_i_4_n_0\,
S(2) => \z_exponent0__0_carry__0_i_5_n_0\,
S(1) => \z_exponent0__0_carry__0_i_6_n_0\,
S(0) => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA9A900"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => y(28),
I4 => x(28),
O => \z_exponent0__0_carry__0_i_1_n_0\
);
\z_exponent0__0_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F990"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
O => \z_exponent0__0_carry__0_i_2_n_0\
);
\z_exponent0__0_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1E1E00"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => y(26),
I4 => x(26),
O => \z_exponent0__0_carry__0_i_3_n_0\
);
\z_exponent0__0_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => \z_exponent0__0_carry__0_i_4_n_0\
);
\z_exponent0__0_carry__0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => \z_exponent0__0_carry__0_i_5_n_0\
);
\z_exponent0__0_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => \z_exponent0__0_carry__0_i_6_n_0\
);
\z_exponent0__0_carry__0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => \z_exponent0__0_carry__0_i_3_n_0\,
I3 => x(27),
I4 => y(27),
O => \z_exponent0__0_carry__0_i_7_n_0\
);
\z_exponent0__0_carry__0_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => L1_carry_i_9_n_0,
I1 => L1_carry_i_10_n_0,
I2 => L1_carry_i_11_n_0,
O => \z_exponent0__0_carry__0_i_8_n_0\
);
\z_exponent0__0_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F660"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
O => \z_exponent0__0_carry_i_1_n_0\
);
\z_exponent0__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
O => \z_exponent0__0_carry_i_2_n_0\
);
\z_exponent0__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_3_n_0\
);
\z_exponent0__0_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent0__0_carry_i_4_n_0\
);
\z_exponent0__0_carry_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => \z_exponent0__0_carry_i_2_n_0\,
I3 => y(25),
I4 => x(25),
O => \z_exponent0__0_carry_i_5_n_0\
);
\z_exponent0__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => L1_carry_i_10_n_0,
I2 => x(24),
I3 => \z_exponent0__0_carry_i_3_n_0\,
O => \z_exponent0__0_carry_i_6_n_0\
);
\z_exponent0__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => x(23),
I1 => y(23),
I2 => \_carry_i_1_n_0\,
O => \z_exponent0__0_carry_i_7_n_0\
);
z_exponent1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => z_exponent1_carry_n_0,
CO(2) => z_exponent1_carry_n_1,
CO(1) => z_exponent1_carry_n_2,
CO(0) => z_exponent1_carry_n_3,
CYINIT => '0',
DI(3) => \z_exponent0__0_carry_i_1_n_0\,
DI(2) => \z_exponent0__0_carry_i_2_n_0\,
DI(1) => \z_exponent1_carry_i_1__0_n_0\,
DI(0) => x(23),
O(3 downto 0) => data1(3 downto 0),
S(3) => \z_exponent1_carry_i_2__0_n_0\,
S(2) => \z_exponent1_carry_i_3__0_n_0\,
S(1) => z_exponent1_carry_i_4_n_0,
S(0) => z_exponent1_carry_i_5_n_0
);
\z_exponent1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => z_exponent1_carry_n_0,
CO(3) => \NLW_z_exponent1_carry__0_CO_UNCONNECTED\(3),
CO(2) => \z_exponent1_carry__0_n_1\,
CO(1) => \z_exponent1_carry__0_n_2\,
CO(0) => \z_exponent1_carry__0_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \z_exponent0__0_carry__0_i_1_n_0\,
DI(1) => \z_exponent0__0_carry__0_i_2_n_0\,
DI(0) => \z_exponent0__0_carry__0_i_3_n_0\,
O(3 downto 0) => data1(7 downto 4),
S(3) => z_exponent1_carry_i_1_n_0,
S(2) => z_exponent1_carry_i_2_n_0,
S(1) => z_exponent1_carry_i_3_n_0,
S(0) => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"6999699969999996"
)
port map (
I0 => x(30),
I1 => y(30),
I2 => x(29),
I3 => y(29),
I4 => \msb1__1\(47),
I5 => \msb1__1\(46),
O => z_exponent1_carry_i_1_n_0
);
\z_exponent1_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
O => \z_exponent1_carry_i_1__0_n_0\
);
z_exponent1_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"96969669"
)
port map (
I0 => \z_exponent0__0_carry__0_i_1_n_0\,
I1 => y(29),
I2 => x(29),
I3 => \msb1__1\(46),
I4 => \msb1__1\(47),
O => z_exponent1_carry_i_2_n_0
);
\z_exponent1_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"E11E1EE11EE1E11E"
)
port map (
I0 => L1_carry_i_10_n_0,
I1 => L1_carry_i_11_n_0,
I2 => L1_carry_i_9_n_0,
I3 => \z_exponent0__0_carry_i_1_n_0\,
I4 => y(26),
I5 => x(26),
O => \z_exponent1_carry_i_2__0_n_0\
);
z_exponent1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"56A9A956A95656A9"
)
port map (
I0 => L1_carry_i_13_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => L1_carry_i_12_n_0,
I3 => \z_exponent0__0_carry__0_i_2_n_0\,
I4 => y(28),
I5 => x(28),
O => z_exponent1_carry_i_3_n_0
);
\z_exponent1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => L1_carry_i_11_n_0,
I1 => L1_carry_i_10_n_0,
I2 => y(25),
I3 => x(25),
I4 => \z_exponent0__0_carry_i_2_n_0\,
O => \z_exponent1_carry_i_3__0_n_0\
);
z_exponent1_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y(24),
I1 => x(24),
I2 => L1_carry_i_10_n_0,
I3 => \z_exponent1_carry_i_1__0_n_0\,
O => z_exponent1_carry_i_4_n_0
);
\z_exponent1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => L1_carry_i_12_n_0,
I1 => \z_exponent0__0_carry__0_i_8_n_0\,
I2 => y(27),
I3 => x(27),
I4 => \z_exponent0__0_carry__0_i_3_n_0\,
O => \z_exponent1_carry_i_4__0_n_0\
);
z_exponent1_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => y(23),
I1 => \_carry_i_1_n_0\,
I2 => x(23),
O => z_exponent1_carry_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_ieee754_fp_multiplier_1_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_ieee754_fp_multiplier_1_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_ieee754_fp_multiplier_1_1 : entity is "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_ieee754_fp_multiplier_1_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_ieee754_fp_multiplier_1_1 : entity is "ieee754_fp_multiplier,Vivado 2016.4";
end affine_block_ieee754_fp_multiplier_1_1;
architecture STRUCTURE of affine_block_ieee754_fp_multiplier_1_1 is
signal \z[30]_INST_0_i_23_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_24_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_25_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_26_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_27_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_28_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_84_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_85_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_86_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_87_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_88_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_89_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_90_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_91_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_92_n_0\ : STD_LOGIC;
signal \z[30]_INST_0_i_93_n_0\ : STD_LOGIC;
signal z_mantissa : STD_LOGIC_VECTOR ( 22 downto 0 );
begin
U0: entity work.affine_block_ieee754_fp_multiplier_1_1_ieee754_fp_multiplier
port map (
x(30 downto 0) => x(30 downto 0),
y(30 downto 0) => y(30 downto 0),
\y_11__s_port_\ => \z[30]_INST_0_i_4_n_0\,
z(7 downto 0) => z(30 downto 23),
z_mantissa(22 downto 0) => z_mantissa(22 downto 0)
);
\z[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(0),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(0)
);
\z[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(10),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(10)
);
\z[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(11),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(11)
);
\z[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(12),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(12)
);
\z[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(13),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(13)
);
\z[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(14),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(14)
);
\z[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(15),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(15)
);
\z[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(16),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(16)
);
\z[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(17),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(17)
);
\z[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(18),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(18)
);
\z[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(19),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(19)
);
\z[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(1),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(1)
);
\z[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(20),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(20)
);
\z[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(21),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(21)
);
\z[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(22),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(22)
);
\z[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(2),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(2)
);
\z[30]_INST_0_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(29),
I1 => x(4),
I2 => x(11),
I3 => x(13),
I4 => \z[30]_INST_0_i_84_n_0\,
O => \z[30]_INST_0_i_23_n_0\
);
\z[30]_INST_0_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => x(25),
I1 => x(20),
I2 => x(15),
I3 => x(22),
I4 => \z[30]_INST_0_i_85_n_0\,
O => \z[30]_INST_0_i_24_n_0\
);
\z[30]_INST_0_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_86_n_0\,
I1 => \z[30]_INST_0_i_87_n_0\,
I2 => \z[30]_INST_0_i_88_n_0\,
I3 => x(24),
I4 => x(10),
I5 => x(2),
O => \z[30]_INST_0_i_25_n_0\
);
\z[30]_INST_0_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(30),
I1 => y(5),
I2 => y(0),
I3 => y(1),
I4 => \z[30]_INST_0_i_89_n_0\,
O => \z[30]_INST_0_i_26_n_0\
);
\z[30]_INST_0_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => y(29),
I1 => y(18),
I2 => y(2),
I3 => y(10),
I4 => \z[30]_INST_0_i_90_n_0\,
O => \z[30]_INST_0_i_27_n_0\
);
\z[30]_INST_0_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \z[30]_INST_0_i_91_n_0\,
I1 => \z[30]_INST_0_i_92_n_0\,
I2 => \z[30]_INST_0_i_93_n_0\,
I3 => y(12),
I4 => y(20),
I5 => y(4),
O => \z[30]_INST_0_i_28_n_0\
);
\z[30]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"101010FF10101010"
)
port map (
I0 => \z[30]_INST_0_i_23_n_0\,
I1 => \z[30]_INST_0_i_24_n_0\,
I2 => \z[30]_INST_0_i_25_n_0\,
I3 => \z[30]_INST_0_i_26_n_0\,
I4 => \z[30]_INST_0_i_27_n_0\,
I5 => \z[30]_INST_0_i_28_n_0\,
O => \z[30]_INST_0_i_4_n_0\
);
\z[30]_INST_0_i_84\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(9),
I1 => x(3),
I2 => x(17),
I3 => x(7),
O => \z[30]_INST_0_i_84_n_0\
);
\z[30]_INST_0_i_85\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(18),
I1 => x(30),
I2 => x(21),
I3 => x(6),
O => \z[30]_INST_0_i_85_n_0\
);
\z[30]_INST_0_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(14),
I1 => x(12),
I2 => x(8),
I3 => x(27),
O => \z[30]_INST_0_i_86_n_0\
);
\z[30]_INST_0_i_87\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => x(28),
I1 => x(23),
I2 => x(19),
I3 => x(1),
O => \z[30]_INST_0_i_87_n_0\
);
\z[30]_INST_0_i_88\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(0),
I1 => x(26),
I2 => x(16),
I3 => x(5),
O => \z[30]_INST_0_i_88_n_0\
);
\z[30]_INST_0_i_89\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(14),
I1 => y(8),
I2 => y(24),
I3 => y(27),
O => \z[30]_INST_0_i_89_n_0\
);
\z[30]_INST_0_i_90\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(7),
I1 => y(26),
I2 => y(17),
I3 => y(6),
O => \z[30]_INST_0_i_90_n_0\
);
\z[30]_INST_0_i_91\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(21),
I1 => y(15),
I2 => y(22),
I3 => y(23),
O => \z[30]_INST_0_i_91_n_0\
);
\z[30]_INST_0_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => y(19),
I1 => y(28),
I2 => y(9),
I3 => y(3),
O => \z[30]_INST_0_i_92_n_0\
);
\z[30]_INST_0_i_93\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => y(16),
I1 => y(25),
I2 => y(13),
I3 => y(11),
O => \z[30]_INST_0_i_93_n_0\
);
\z[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y(31),
I1 => x(31),
O => z(31)
);
\z[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(3),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(3)
);
\z[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(4),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(4)
);
\z[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(5),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(5)
);
\z[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(6),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(6)
);
\z[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(7),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(7)
);
\z[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(8),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(8)
);
\z[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => z_mantissa(9),
I1 => \z[30]_INST_0_i_4_n_0\,
O => z(9)
);
end STRUCTURE;
| mit | 5da33066d1144afb438ae9870cd2f262 | 0.486968 | 2.258208 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/cpu_or1knd_i5_pkg.vhdl | 1 | 2,335 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library isa;
use isa.or1k_pkg.all;
library util;
use util.types_pkg.all;
use util.numeric_pkg.all;
use work.cpu_or1knd_i5_config_pkg.all;
package cpu_or1knd_i5_pkg is
constant cpu_or1knd_i5_spr_sys_vr_ver : std_ulogic_vector(31 downto 24) := "00010000";
constant cpu_or1knd_i5_spr_sys_vr_cfg : std_ulogic_vector(23 downto 16) := "00000000";
constant cpu_or1knd_i5_spr_sys_vr_rev : std_ulogic_vector(5 downto 0) := "000000";
constant cpu_or1knd_i5_spr_sys_vr : or1k_spr_data_type := (cpu_or1knd_i5_spr_sys_vr_ver &
cpu_or1knd_i5_spr_sys_vr_cfg &
(15 downto 6 => '0') &
cpu_or1knd_i5_spr_sys_vr_rev);
constant cpu_or1knd_i5_data_size_bits : natural := bitsize(or1k_log2_word_bytes);
subtype cpu_or1knd_i5_data_size_type is std_ulogic_vector(cpu_or1knd_i5_data_size_bits-1 downto 0);
end package;
| apache-2.0 | 30964707ea668a41cd4d988c0c64388c | 0.505353 | 4.089317 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.vhdl | 1 | 5,724 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:41:32 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb565_to_rgb888_0_0 -prefix
-- system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
port (
rgb_888 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC
);
end system_rgb565_to_rgb888_0_0_rgb565_to_rgb888;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 is
begin
\rgb_888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(5),
Q => rgb_888(5),
R => '0'
);
\rgb_888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(6),
Q => rgb_888(6),
R => '0'
);
\rgb_888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(7),
Q => rgb_888(7),
R => '0'
);
\rgb_888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(8),
Q => rgb_888(8),
R => '0'
);
\rgb_888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(9),
Q => rgb_888(9),
R => '0'
);
\rgb_888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(10),
Q => rgb_888(10),
R => '0'
);
\rgb_888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(11),
Q => rgb_888(11),
R => '0'
);
\rgb_888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(12),
Q => rgb_888(12),
R => '0'
);
\rgb_888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(13),
Q => rgb_888(13),
R => '0'
);
\rgb_888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(14),
Q => rgb_888(14),
R => '0'
);
\rgb_888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(15),
Q => rgb_888(15),
R => '0'
);
\rgb_888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(0),
Q => rgb_888(0),
R => '0'
);
\rgb_888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(1),
Q => rgb_888(1),
R => '0'
);
\rgb_888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(2),
Q => rgb_888(2),
R => '0'
);
\rgb_888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(3),
Q => rgb_888(3),
R => '0'
);
\rgb_888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(4),
Q => rgb_888(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_0_0 : entity is "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_0_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_0_0;
architecture STRUCTURE of system_rgb565_to_rgb888_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 20 downto 3 );
begin
rgb_888(23 downto 21) <= \^rgb_888\(18 downto 16);
rgb_888(20 downto 16) <= \^rgb_888\(20 downto 16);
rgb_888(15 downto 14) <= \^rgb_888\(9 downto 8);
rgb_888(13 downto 3) <= \^rgb_888\(13 downto 3);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
port map (
clk => clk,
rgb_565(15 downto 0) => rgb_565(15 downto 0),
rgb_888(15 downto 13) => \^rgb_888\(18 downto 16),
rgb_888(12 downto 11) => \^rgb_888\(20 downto 19),
rgb_888(10 downto 9) => \^rgb_888\(9 downto 8),
rgb_888(8 downto 5) => \^rgb_888\(13 downto 10),
rgb_888(4 downto 0) => \^rgb_888\(7 downto 3)
);
end STRUCTURE;
| mit | 85eb807844a193bedcb3e12d3c1c0148 | 0.532669 | 3.05606 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_overlay/vga_overlay.srcs/sources_1/new/vga_overlay.vhd | 4 | 1,070 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_overlay is
port (
clk : in std_logic;
rgb_0 : in std_logic_vector(23 downto 0);
rgb_1 : in std_logic_vector(23 downto 0);
rgb : out std_logic_vector(23 downto 0)
);
end vga_overlay;
architecture Behavioral of vga_overlay is
signal r_0, g_0, b_0, r_1, g_1, b_1 : unsigned(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
r_0 <= unsigned(rgb_0(23 downto 16)) srl 1;
g_0 <= unsigned(rgb_0(15 downto 8)) srl 1;
b_0 <= unsigned(rgb_0(7 downto 0)) srl 1;
r_1 <= unsigned(rgb_1(23 downto 16)) srl 1;
g_1 <= unsigned(rgb_1(15 downto 8)) srl 1;
b_1 <= unsigned(rgb_1(7 downto 0)) srl 1;
rgb(23 downto 16) <= std_logic_vector(r_0 + r_1);
rgb(15 downto 8) <= std_logic_vector(g_0 + g_1);
rgb(7 downto 0) <= std_logic_vector(b_0 + b_1);
end if;
end process;
end Behavioral;
| mit | 8561891c2504ca47d12b82c7726aa1c9 | 0.539252 | 3.092486 | false | false | false | false |
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